1 //===-- llvm/CallingConvLower.h - Calling Conventions -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the CCState and CCValAssign classes, used for lowering
11 // and implementing calling conventions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
16 #define LLVM_CODEGEN_CALLINGCONVLOWER_H
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Target/TargetCallingConv.h"
29 class TargetRegisterInfo;
31 /// CCValAssign - Represent assignment of one arg/retval to a location.
35 Full, // The value fills the full location.
36 SExt, // The value is sign extended in the location.
37 ZExt, // The value is zero extended in the location.
38 AExt, // The value is extended with undefined upper bits.
39 SExtUpper, // The value is in the upper bits of the location and should be
40 // sign extended when retrieved.
41 ZExtUpper, // The value is in the upper bits of the location and should be
42 // zero extended when retrieved.
43 AExtUpper, // The value is in the upper bits of the location and should be
44 // extended with undefined upper bits when retrieved.
45 BCvt, // The value is bit-converted in the location.
46 VExt, // The value is vector-widened in the location.
47 // FIXME: Not implemented yet. Code that uses AExt to mean
48 // vector-widen should be fixed to use VExt instead.
49 FPExt, // The floating-point value is fp-extended in the location.
50 Indirect // The location contains pointer to the value.
51 // TODO: a subset of the value is in the location.
55 /// ValNo - This is the value number begin assigned (e.g. an argument number).
58 /// Loc is either a stack offset or a register number.
61 /// isMem - True if this is a memory loc, false if it is a register loc.
64 /// isCustom - True if this arg/retval requires special handling.
65 unsigned isCustom : 1;
67 /// Information about how the value is assigned.
70 /// ValVT - The type of the value being assigned.
73 /// LocVT - The type of the location being assigned to.
77 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
78 unsigned RegNo, MVT LocVT,
91 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
92 unsigned RegNo, MVT LocVT,
95 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
100 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
101 unsigned Offset, MVT LocVT,
107 Ret.isCustom = false;
114 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
115 unsigned Offset, MVT LocVT,
118 Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
123 // There is no need to differentiate between a pending CCValAssign and other
124 // kinds, as they are stored in a different list.
125 static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
126 LocInfo HTP, unsigned ExtraInfo = 0) {
127 return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
130 void convertToReg(unsigned RegNo) {
135 void convertToMem(unsigned Offset) {
140 unsigned getValNo() const { return ValNo; }
141 MVT getValVT() const { return ValVT; }
143 bool isRegLoc() const { return !isMem; }
144 bool isMemLoc() const { return isMem; }
146 bool needsCustom() const { return isCustom; }
148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
149 unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
150 unsigned getExtraInfo() const { return Loc; }
151 MVT getLocVT() const { return LocVT; }
153 LocInfo getLocInfo() const { return HTP; }
154 bool isExtInLoc() const {
155 return (HTP == AExt || HTP == SExt || HTP == ZExt);
158 bool isUpperBitsInLoc() const {
159 return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
163 /// Describes a register that needs to be forwarded from the prologue to a
165 struct ForwardedRegister {
166 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
167 : VReg(VReg), PReg(PReg), VT(VT) {}
173 /// CCAssignFn - This function assigns a location for Val, updating State to
174 /// reflect the change. It returns 'true' if it failed to handle Val.
175 typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
176 MVT LocVT, CCValAssign::LocInfo LocInfo,
177 ISD::ArgFlagsTy ArgFlags, CCState &State);
179 /// CCCustomFn - This function assigns a location for Val, possibly updating
180 /// all args to reflect changes and indicates if it handled it. It must set
181 /// isCustom if it handles the arg and returns true.
182 typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
183 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
184 ISD::ArgFlagsTy &ArgFlags, CCState &State);
186 /// CCState - This class holds information needed while lowering arguments and
187 /// return values. It captures which registers are already assigned and which
188 /// stack slots are used. It provides accessors to allocate these values.
191 CallingConv::ID CallingConv;
193 bool AnalyzingMustTailForwardedRegs = false;
195 const TargetRegisterInfo &TRI;
196 SmallVectorImpl<CCValAssign> &Locs;
197 LLVMContext &Context;
199 unsigned StackOffset;
200 unsigned MaxStackArgAlign;
201 SmallVector<uint32_t, 16> UsedRegs;
202 SmallVector<CCValAssign, 4> PendingLocs;
204 // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
206 // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
208 // Or, in another words it tracks byval parameters that are stored in
209 // general purpose registers.
211 // For 4 byte stack alignment,
212 // instance index means byval parameter number in formal
213 // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
214 // then, for function "foo":
216 // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
218 // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
219 // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
221 // In case of 8 bytes stack alignment,
222 // ByValRegs may also contain information about wasted registers.
223 // In function shown above, r3 would be wasted according to AAPCS rules.
224 // And in that case ByValRegs[1].Waste would be "true".
225 // ByValRegs vector size still would be 2,
226 // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
228 // Supposed use-case for this collection:
229 // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
230 // 2. HandleByVal fillups ByValRegs.
231 // 3. Argument analysis (LowerFormatArguments, for example). After
232 // some byval argument was analyzed, InRegsParamsProcessed is increased.
234 ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
235 Begin(B), End(E), Waste(IsWaste) {}
236 // First register allocated for current parameter.
239 // First after last register allocated for current parameter.
242 // Means that current range of registers doesn't belong to any
243 // parameters. It was wasted due to stack alignment rules.
244 // For more information see:
245 // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
248 SmallVector<ByValInfo, 4 > ByValRegs;
250 // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
251 // during argument analysis.
252 unsigned InRegsParamsProcessed;
255 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
256 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
258 void addLoc(const CCValAssign &V) {
262 LLVMContext &getContext() const { return Context; }
263 MachineFunction &getMachineFunction() const { return MF; }
264 CallingConv::ID getCallingConv() const { return CallingConv; }
265 bool isVarArg() const { return IsVarArg; }
267 /// getNextStackOffset - Return the next stack offset such that all stack
268 /// slots satisfy their alignment requirements.
269 unsigned getNextStackOffset() const {
273 /// getAlignedCallFrameSize - Return the size of the call frame needed to
274 /// be able to store all arguments and such that the alignment requirement
275 /// of each of the arguments is satisfied.
276 unsigned getAlignedCallFrameSize() const {
277 return alignTo(StackOffset, MaxStackArgAlign);
280 /// isAllocated - Return true if the specified register (or an alias) is
282 bool isAllocated(unsigned Reg) const {
283 return UsedRegs[Reg/32] & (1 << (Reg&31));
286 /// AnalyzeFormalArguments - Analyze an array of argument values,
287 /// incorporating info about the formals into this state.
288 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
291 /// The function will invoke AnalyzeFormalArguments.
292 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
294 AnalyzeFormalArguments(Ins, Fn);
297 /// AnalyzeReturn - Analyze the returned values of a return,
298 /// incorporating info about the result values into this state.
299 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
302 /// CheckReturn - Analyze the return values of a function, returning
303 /// true if the return can be performed without sret-demotion, and
305 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
308 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
309 /// incorporating info about the passed values into this state.
310 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
313 /// AnalyzeCallOperands - Same as above except it takes vectors of types
314 /// and argument flags.
315 void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
316 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
319 /// The function will invoke AnalyzeCallOperands.
320 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
322 AnalyzeCallOperands(Outs, Fn);
325 /// AnalyzeCallResult - Analyze the return values of a call,
326 /// incorporating info about the passed values into this state.
327 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
330 /// A shadow allocated register is a register that was allocated
331 /// but wasn't added to the location list (Locs).
332 /// \returns true if the register was allocated as shadow or false otherwise.
333 bool IsShadowAllocatedReg(unsigned Reg) const;
335 /// AnalyzeCallResult - Same as above except it's specialized for calls which
336 /// produce a single value.
337 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
339 /// getFirstUnallocated - Return the index of the first unallocated register
340 /// in the set, or Regs.size() if they are all allocated.
341 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
342 for (unsigned i = 0; i < Regs.size(); ++i)
343 if (!isAllocated(Regs[i]))
348 /// AllocateReg - Attempt to allocate one register. If it is not available,
349 /// return zero. Otherwise, return the register, marking it and any aliases
351 unsigned AllocateReg(unsigned Reg) {
352 if (isAllocated(Reg)) return 0;
357 /// Version of AllocateReg with extra register to be shadowed.
358 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
359 if (isAllocated(Reg)) return 0;
361 MarkAllocated(ShadowReg);
365 /// AllocateReg - Attempt to allocate one of the specified registers. If none
366 /// are available, return zero. Otherwise, return the first one available,
367 /// marking it and any aliases as allocated.
368 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
369 unsigned FirstUnalloc = getFirstUnallocated(Regs);
370 if (FirstUnalloc == Regs.size())
371 return 0; // Didn't find the reg.
373 // Mark the register and any aliases as allocated.
374 unsigned Reg = Regs[FirstUnalloc];
379 /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
380 /// registers. If this is not possible, return zero. Otherwise, return the first
381 /// register of the block that were allocated, marking the entire block as allocated.
382 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
383 if (RegsRequired > Regs.size())
386 for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
388 bool BlockAvailable = true;
389 // Check for already-allocated regs in this block
390 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
391 if (isAllocated(Regs[StartIdx + BlockIdx])) {
392 BlockAvailable = false;
396 if (BlockAvailable) {
397 // Mark the entire block as allocated
398 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
399 MarkAllocated(Regs[StartIdx + BlockIdx]);
401 return Regs[StartIdx];
404 // No block was available
408 /// Version of AllocateReg with list of registers to be shadowed.
409 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
410 unsigned FirstUnalloc = getFirstUnallocated(Regs);
411 if (FirstUnalloc == Regs.size())
412 return 0; // Didn't find the reg.
414 // Mark the register and any aliases as allocated.
415 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
417 MarkAllocated(ShadowReg);
421 /// AllocateStack - Allocate a chunk of stack space with the specified size
423 unsigned AllocateStack(unsigned Size, unsigned Align) {
424 assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
425 StackOffset = alignTo(StackOffset, Align);
426 unsigned Result = StackOffset;
428 MaxStackArgAlign = std::max(Align, MaxStackArgAlign);
429 ensureMaxAlignment(Align);
433 void ensureMaxAlignment(unsigned Align) {
434 if (!AnalyzingMustTailForwardedRegs)
435 MF.getFrameInfo().ensureMaxAlignment(Align);
438 /// Version of AllocateStack with extra register to be shadowed.
439 unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
440 MarkAllocated(ShadowReg);
441 return AllocateStack(Size, Align);
444 /// Version of AllocateStack with list of extra registers to be shadowed.
445 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
446 unsigned AllocateStack(unsigned Size, unsigned Align,
447 ArrayRef<MCPhysReg> ShadowRegs) {
448 for (unsigned i = 0; i < ShadowRegs.size(); ++i)
449 MarkAllocated(ShadowRegs[i]);
450 return AllocateStack(Size, Align);
453 // HandleByVal - Allocate a stack slot large enough to pass an argument by
454 // value. The size and alignment information of the argument is encoded in its
455 // parameter attribute.
456 void HandleByVal(unsigned ValNo, MVT ValVT,
457 MVT LocVT, CCValAssign::LocInfo LocInfo,
458 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
460 // Returns count of byval arguments that are to be stored (even partly)
462 unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
464 // Returns count of byval in-regs arguments proceed.
465 unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
467 // Get information about N-th byval parameter that is stored in registers.
468 // Here "ByValParamIndex" is N.
469 void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
470 unsigned& BeginReg, unsigned& EndReg) const {
471 assert(InRegsParamRecordIndex < ByValRegs.size() &&
472 "Wrong ByVal parameter index");
474 const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
475 BeginReg = info.Begin;
479 // Add information about parameter that is kept in registers.
480 void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
481 ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
484 // Goes either to next byval parameter (excluding "waste" record), or
485 // to the end of collection.
486 // Returns false, if end is reached.
487 bool nextInRegsParam() {
488 unsigned e = ByValRegs.size();
489 if (InRegsParamsProcessed < e)
490 ++InRegsParamsProcessed;
491 return InRegsParamsProcessed < e;
494 // Clear byval registers tracking info.
495 void clearByValRegsInfo() {
496 InRegsParamsProcessed = 0;
500 // Rewind byval registers tracking info.
501 void rewindByValRegsInfo() {
502 InRegsParamsProcessed = 0;
505 // Get list of pending assignments
506 SmallVectorImpl<llvm::CCValAssign> &getPendingLocs() {
510 /// Compute the remaining unused register parameters that would be used for
511 /// the given value type. This is useful when varargs are passed in the
512 /// registers that normal prototyped parameters would be passed in, or for
513 /// implementing perfect forwarding.
514 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
517 /// Compute the set of registers that need to be preserved and forwarded to
518 /// any musttail calls.
519 void analyzeMustTailForwardedRegisters(
520 SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
523 /// Returns true if the results of the two calling conventions are compatible.
524 /// This is usually part of the check for tailcall eligibility.
525 static bool resultsCompatible(CallingConv::ID CalleeCC,
526 CallingConv::ID CallerCC, MachineFunction &MF,
528 const SmallVectorImpl<ISD::InputArg> &Ins,
529 CCAssignFn CalleeFn, CCAssignFn CallerFn);
531 /// The function runs an additional analysis pass over function arguments.
532 /// It will mark each argument with the attribute flag SecArgPass.
533 /// After running, it will sort the locs list.
535 void AnalyzeArgumentsSecondPass(const SmallVectorImpl<T> &Args,
537 unsigned NumFirstPassLocs = Locs.size();
539 /// Creates similar argument list to \p Args in which each argument is
540 /// marked using SecArgPass flag.
541 SmallVector<T, 16> SecPassArg;
542 // SmallVector<ISD::InputArg, 16> SecPassArg;
543 for (auto Arg : Args) {
544 Arg.Flags.setSecArgPass();
545 SecPassArg.push_back(Arg);
548 // Run the second argument pass
549 AnalyzeArguments(SecPassArg, Fn);
551 // Sort the locations of the arguments according to their original position.
552 SmallVector<CCValAssign, 16> TmpArgLocs;
553 std::swap(TmpArgLocs, Locs);
554 auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
555 std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
556 std::back_inserter(Locs),
557 [](const CCValAssign &A, const CCValAssign &B) -> bool {
558 return A.getValNo() < B.getValNo();
563 /// MarkAllocated - Mark a register and all of its aliases as allocated.
564 void MarkAllocated(unsigned Reg);
569 } // end namespace llvm