1 //===- llvm/CallingConvLower.h - Calling Conventions ------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares the CCState and CCValAssign classes, used for lowering
10 // and implementing calling conventions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
15 #define LLVM_CODEGEN_CALLINGCONVLOWER_H
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/TargetCallingConv.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/MC/MCRegisterInfo.h"
29 class TargetRegisterInfo;
31 /// CCValAssign - Represent assignment of one arg/retval to a location.
35 Full, // The value fills the full location.
36 SExt, // The value is sign extended in the location.
37 ZExt, // The value is zero extended in the location.
38 AExt, // The value is extended with undefined upper bits.
39 SExtUpper, // The value is in the upper bits of the location and should be
40 // sign extended when retrieved.
41 ZExtUpper, // The value is in the upper bits of the location and should be
42 // zero extended when retrieved.
43 AExtUpper, // The value is in the upper bits of the location and should be
44 // extended with undefined upper bits when retrieved.
45 BCvt, // The value is bit-converted in the location.
46 VExt, // The value is vector-widened in the location.
47 // FIXME: Not implemented yet. Code that uses AExt to mean
48 // vector-widen should be fixed to use VExt instead.
49 FPExt, // The floating-point value is fp-extended in the location.
50 Indirect // The location contains pointer to the value.
51 // TODO: a subset of the value is in the location.
55 /// ValNo - This is the value number begin assigned (e.g. an argument number).
58 /// Loc is either a stack offset or a register number.
61 /// isMem - True if this is a memory loc, false if it is a register loc.
64 /// isCustom - True if this arg/retval requires special handling.
65 unsigned isCustom : 1;
67 /// Information about how the value is assigned.
70 /// ValVT - The type of the value being assigned.
73 /// LocVT - The type of the location being assigned to.
77 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
78 unsigned RegNo, MVT LocVT,
91 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
92 unsigned RegNo, MVT LocVT,
95 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
100 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
101 unsigned Offset, MVT LocVT,
107 Ret.isCustom = false;
114 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
115 unsigned Offset, MVT LocVT,
118 Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
123 // There is no need to differentiate between a pending CCValAssign and other
124 // kinds, as they are stored in a different list.
125 static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
126 LocInfo HTP, unsigned ExtraInfo = 0) {
127 return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
130 void convertToReg(unsigned RegNo) {
135 void convertToMem(unsigned Offset) {
140 unsigned getValNo() const { return ValNo; }
141 MVT getValVT() const { return ValVT; }
143 bool isRegLoc() const { return !isMem; }
144 bool isMemLoc() const { return isMem; }
146 bool needsCustom() const { return isCustom; }
148 Register getLocReg() const { assert(isRegLoc()); return Loc; }
149 unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
150 unsigned getExtraInfo() const { return Loc; }
151 MVT getLocVT() const { return LocVT; }
153 LocInfo getLocInfo() const { return HTP; }
154 bool isExtInLoc() const {
155 return (HTP == AExt || HTP == SExt || HTP == ZExt);
158 bool isUpperBitsInLoc() const {
159 return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
163 /// Describes a register that needs to be forwarded from the prologue to a
165 struct ForwardedRegister {
166 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
167 : VReg(VReg), PReg(PReg), VT(VT) {}
173 /// CCAssignFn - This function assigns a location for Val, updating State to
174 /// reflect the change. It returns 'true' if it failed to handle Val.
175 typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
176 MVT LocVT, CCValAssign::LocInfo LocInfo,
177 ISD::ArgFlagsTy ArgFlags, CCState &State);
179 /// CCCustomFn - This function assigns a location for Val, possibly updating
180 /// all args to reflect changes and indicates if it handled it. It must set
181 /// isCustom if it handles the arg and returns true.
182 typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
183 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
184 ISD::ArgFlagsTy &ArgFlags, CCState &State);
186 /// CCState - This class holds information needed while lowering arguments and
187 /// return values. It captures which registers are already assigned and which
188 /// stack slots are used. It provides accessors to allocate these values.
191 CallingConv::ID CallingConv;
193 bool AnalyzingMustTailForwardedRegs = false;
195 const TargetRegisterInfo &TRI;
196 SmallVectorImpl<CCValAssign> &Locs;
197 LLVMContext &Context;
199 unsigned StackOffset;
200 unsigned MaxStackArgAlign;
201 SmallVector<uint32_t, 16> UsedRegs;
202 SmallVector<CCValAssign, 4> PendingLocs;
203 SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
205 // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
207 // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
209 // Or, in another words it tracks byval parameters that are stored in
210 // general purpose registers.
212 // For 4 byte stack alignment,
213 // instance index means byval parameter number in formal
214 // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
215 // then, for function "foo":
217 // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
219 // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
220 // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
222 // In case of 8 bytes stack alignment,
223 // ByValRegs may also contain information about wasted registers.
224 // In function shown above, r3 would be wasted according to AAPCS rules.
225 // And in that case ByValRegs[1].Waste would be "true".
226 // ByValRegs vector size still would be 2,
227 // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
229 // Supposed use-case for this collection:
230 // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
231 // 2. HandleByVal fillups ByValRegs.
232 // 3. Argument analysis (LowerFormatArguments, for example). After
233 // some byval argument was analyzed, InRegsParamsProcessed is increased.
235 ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
236 Begin(B), End(E), Waste(IsWaste) {}
237 // First register allocated for current parameter.
240 // First after last register allocated for current parameter.
243 // Means that current range of registers doesn't belong to any
244 // parameters. It was wasted due to stack alignment rules.
245 // For more information see:
246 // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
249 SmallVector<ByValInfo, 4 > ByValRegs;
251 // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
252 // during argument analysis.
253 unsigned InRegsParamsProcessed;
256 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
257 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
259 void addLoc(const CCValAssign &V) {
263 LLVMContext &getContext() const { return Context; }
264 MachineFunction &getMachineFunction() const { return MF; }
265 CallingConv::ID getCallingConv() const { return CallingConv; }
266 bool isVarArg() const { return IsVarArg; }
268 /// getNextStackOffset - Return the next stack offset such that all stack
269 /// slots satisfy their alignment requirements.
270 unsigned getNextStackOffset() const {
274 /// getAlignedCallFrameSize - Return the size of the call frame needed to
275 /// be able to store all arguments and such that the alignment requirement
276 /// of each of the arguments is satisfied.
277 unsigned getAlignedCallFrameSize() const {
278 return alignTo(StackOffset, MaxStackArgAlign);
281 /// isAllocated - Return true if the specified register (or an alias) is
283 bool isAllocated(unsigned Reg) const {
284 return UsedRegs[Reg/32] & (1 << (Reg&31));
287 /// AnalyzeFormalArguments - Analyze an array of argument values,
288 /// incorporating info about the formals into this state.
289 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
292 /// The function will invoke AnalyzeFormalArguments.
293 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
295 AnalyzeFormalArguments(Ins, Fn);
298 /// AnalyzeReturn - Analyze the returned values of a return,
299 /// incorporating info about the result values into this state.
300 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
303 /// CheckReturn - Analyze the return values of a function, returning
304 /// true if the return can be performed without sret-demotion, and
306 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
309 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
310 /// incorporating info about the passed values into this state.
311 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
314 /// AnalyzeCallOperands - Same as above except it takes vectors of types
315 /// and argument flags.
316 void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
317 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
320 /// The function will invoke AnalyzeCallOperands.
321 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
323 AnalyzeCallOperands(Outs, Fn);
326 /// AnalyzeCallResult - Analyze the return values of a call,
327 /// incorporating info about the passed values into this state.
328 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
331 /// A shadow allocated register is a register that was allocated
332 /// but wasn't added to the location list (Locs).
333 /// \returns true if the register was allocated as shadow or false otherwise.
334 bool IsShadowAllocatedReg(unsigned Reg) const;
336 /// AnalyzeCallResult - Same as above except it's specialized for calls which
337 /// produce a single value.
338 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
340 /// getFirstUnallocated - Return the index of the first unallocated register
341 /// in the set, or Regs.size() if they are all allocated.
342 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
343 for (unsigned i = 0; i < Regs.size(); ++i)
344 if (!isAllocated(Regs[i]))
349 /// AllocateReg - Attempt to allocate one register. If it is not available,
350 /// return zero. Otherwise, return the register, marking it and any aliases
352 unsigned AllocateReg(unsigned Reg) {
353 if (isAllocated(Reg)) return 0;
358 /// Version of AllocateReg with extra register to be shadowed.
359 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
360 if (isAllocated(Reg)) return 0;
362 MarkAllocated(ShadowReg);
366 /// AllocateReg - Attempt to allocate one of the specified registers. If none
367 /// are available, return zero. Otherwise, return the first one available,
368 /// marking it and any aliases as allocated.
369 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
370 unsigned FirstUnalloc = getFirstUnallocated(Regs);
371 if (FirstUnalloc == Regs.size())
372 return 0; // Didn't find the reg.
374 // Mark the register and any aliases as allocated.
375 unsigned Reg = Regs[FirstUnalloc];
380 /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
381 /// registers. If this is not possible, return zero. Otherwise, return the first
382 /// register of the block that were allocated, marking the entire block as allocated.
383 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
384 if (RegsRequired > Regs.size())
387 for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
389 bool BlockAvailable = true;
390 // Check for already-allocated regs in this block
391 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
392 if (isAllocated(Regs[StartIdx + BlockIdx])) {
393 BlockAvailable = false;
397 if (BlockAvailable) {
398 // Mark the entire block as allocated
399 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
400 MarkAllocated(Regs[StartIdx + BlockIdx]);
402 return Regs[StartIdx];
405 // No block was available
409 /// Version of AllocateReg with list of registers to be shadowed.
410 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
411 unsigned FirstUnalloc = getFirstUnallocated(Regs);
412 if (FirstUnalloc == Regs.size())
413 return 0; // Didn't find the reg.
415 // Mark the register and any aliases as allocated.
416 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
418 MarkAllocated(ShadowReg);
422 /// AllocateStack - Allocate a chunk of stack space with the specified size
424 unsigned AllocateStack(unsigned Size, unsigned Align) {
425 assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
426 StackOffset = alignTo(StackOffset, Align);
427 unsigned Result = StackOffset;
429 MaxStackArgAlign = std::max(Align, MaxStackArgAlign);
430 ensureMaxAlignment(Align);
434 void ensureMaxAlignment(unsigned Align) {
435 if (!AnalyzingMustTailForwardedRegs)
436 MF.getFrameInfo().ensureMaxAlignment(Align);
439 /// Version of AllocateStack with extra register to be shadowed.
440 unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
441 MarkAllocated(ShadowReg);
442 return AllocateStack(Size, Align);
445 /// Version of AllocateStack with list of extra registers to be shadowed.
446 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
447 unsigned AllocateStack(unsigned Size, unsigned Align,
448 ArrayRef<MCPhysReg> ShadowRegs) {
449 for (unsigned i = 0; i < ShadowRegs.size(); ++i)
450 MarkAllocated(ShadowRegs[i]);
451 return AllocateStack(Size, Align);
454 // HandleByVal - Allocate a stack slot large enough to pass an argument by
455 // value. The size and alignment information of the argument is encoded in its
456 // parameter attribute.
457 void HandleByVal(unsigned ValNo, MVT ValVT,
458 MVT LocVT, CCValAssign::LocInfo LocInfo,
459 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
461 // Returns count of byval arguments that are to be stored (even partly)
463 unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
465 // Returns count of byval in-regs arguments proceed.
466 unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
468 // Get information about N-th byval parameter that is stored in registers.
469 // Here "ByValParamIndex" is N.
470 void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
471 unsigned& BeginReg, unsigned& EndReg) const {
472 assert(InRegsParamRecordIndex < ByValRegs.size() &&
473 "Wrong ByVal parameter index");
475 const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
476 BeginReg = info.Begin;
480 // Add information about parameter that is kept in registers.
481 void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
482 ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
485 // Goes either to next byval parameter (excluding "waste" record), or
486 // to the end of collection.
487 // Returns false, if end is reached.
488 bool nextInRegsParam() {
489 unsigned e = ByValRegs.size();
490 if (InRegsParamsProcessed < e)
491 ++InRegsParamsProcessed;
492 return InRegsParamsProcessed < e;
495 // Clear byval registers tracking info.
496 void clearByValRegsInfo() {
497 InRegsParamsProcessed = 0;
501 // Rewind byval registers tracking info.
502 void rewindByValRegsInfo() {
503 InRegsParamsProcessed = 0;
506 // Get list of pending assignments
507 SmallVectorImpl<CCValAssign> &getPendingLocs() {
511 // Get a list of argflags for pending assignments.
512 SmallVectorImpl<ISD::ArgFlagsTy> &getPendingArgFlags() {
513 return PendingArgFlags;
516 /// Compute the remaining unused register parameters that would be used for
517 /// the given value type. This is useful when varargs are passed in the
518 /// registers that normal prototyped parameters would be passed in, or for
519 /// implementing perfect forwarding.
520 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
523 /// Compute the set of registers that need to be preserved and forwarded to
524 /// any musttail calls.
525 void analyzeMustTailForwardedRegisters(
526 SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
529 /// Returns true if the results of the two calling conventions are compatible.
530 /// This is usually part of the check for tailcall eligibility.
531 static bool resultsCompatible(CallingConv::ID CalleeCC,
532 CallingConv::ID CallerCC, MachineFunction &MF,
534 const SmallVectorImpl<ISD::InputArg> &Ins,
535 CCAssignFn CalleeFn, CCAssignFn CallerFn);
537 /// The function runs an additional analysis pass over function arguments.
538 /// It will mark each argument with the attribute flag SecArgPass.
539 /// After running, it will sort the locs list.
541 void AnalyzeArgumentsSecondPass(const SmallVectorImpl<T> &Args,
543 unsigned NumFirstPassLocs = Locs.size();
545 /// Creates similar argument list to \p Args in which each argument is
546 /// marked using SecArgPass flag.
547 SmallVector<T, 16> SecPassArg;
548 // SmallVector<ISD::InputArg, 16> SecPassArg;
549 for (auto Arg : Args) {
550 Arg.Flags.setSecArgPass();
551 SecPassArg.push_back(Arg);
554 // Run the second argument pass
555 AnalyzeArguments(SecPassArg, Fn);
557 // Sort the locations of the arguments according to their original position.
558 SmallVector<CCValAssign, 16> TmpArgLocs;
559 TmpArgLocs.swap(Locs);
560 auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
561 std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
562 std::back_inserter(Locs),
563 [](const CCValAssign &A, const CCValAssign &B) -> bool {
564 return A.getValNo() < B.getValNo();
569 /// MarkAllocated - Mark a register and all of its aliases as allocated.
570 void MarkAllocated(unsigned Reg);
573 } // end namespace llvm
575 #endif // LLVM_CODEGEN_CALLINGCONVLOWER_H