1 //===- llvm/CallingConvLower.h - Calling Conventions ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the CCState and CCValAssign classes, used for lowering
11 // and implementing calling conventions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
16 #define LLVM_CODEGEN_CALLINGCONVLOWER_H
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/TargetCallingConv.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/MC/MCRegisterInfo.h"
30 class TargetRegisterInfo;
32 /// CCValAssign - Represent assignment of one arg/retval to a location.
36 Full, // The value fills the full location.
37 SExt, // The value is sign extended in the location.
38 ZExt, // The value is zero extended in the location.
39 AExt, // The value is extended with undefined upper bits.
40 SExtUpper, // The value is in the upper bits of the location and should be
41 // sign extended when retrieved.
42 ZExtUpper, // The value is in the upper bits of the location and should be
43 // zero extended when retrieved.
44 AExtUpper, // The value is in the upper bits of the location and should be
45 // extended with undefined upper bits when retrieved.
46 BCvt, // The value is bit-converted in the location.
47 VExt, // The value is vector-widened in the location.
48 // FIXME: Not implemented yet. Code that uses AExt to mean
49 // vector-widen should be fixed to use VExt instead.
50 FPExt, // The floating-point value is fp-extended in the location.
51 Indirect // The location contains pointer to the value.
52 // TODO: a subset of the value is in the location.
56 /// ValNo - This is the value number begin assigned (e.g. an argument number).
59 /// Loc is either a stack offset or a register number.
62 /// isMem - True if this is a memory loc, false if it is a register loc.
65 /// isCustom - True if this arg/retval requires special handling.
66 unsigned isCustom : 1;
68 /// Information about how the value is assigned.
71 /// ValVT - The type of the value being assigned.
74 /// LocVT - The type of the location being assigned to.
78 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
79 unsigned RegNo, MVT LocVT,
92 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
93 unsigned RegNo, MVT LocVT,
96 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
101 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
102 unsigned Offset, MVT LocVT,
108 Ret.isCustom = false;
115 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
116 unsigned Offset, MVT LocVT,
119 Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
124 // There is no need to differentiate between a pending CCValAssign and other
125 // kinds, as they are stored in a different list.
126 static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
127 LocInfo HTP, unsigned ExtraInfo = 0) {
128 return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
131 void convertToReg(unsigned RegNo) {
136 void convertToMem(unsigned Offset) {
141 unsigned getValNo() const { return ValNo; }
142 MVT getValVT() const { return ValVT; }
144 bool isRegLoc() const { return !isMem; }
145 bool isMemLoc() const { return isMem; }
147 bool needsCustom() const { return isCustom; }
149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
150 unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
151 unsigned getExtraInfo() const { return Loc; }
152 MVT getLocVT() const { return LocVT; }
154 LocInfo getLocInfo() const { return HTP; }
155 bool isExtInLoc() const {
156 return (HTP == AExt || HTP == SExt || HTP == ZExt);
159 bool isUpperBitsInLoc() const {
160 return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
164 /// Describes a register that needs to be forwarded from the prologue to a
166 struct ForwardedRegister {
167 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
168 : VReg(VReg), PReg(PReg), VT(VT) {}
174 /// CCAssignFn - This function assigns a location for Val, updating State to
175 /// reflect the change. It returns 'true' if it failed to handle Val.
176 typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
177 MVT LocVT, CCValAssign::LocInfo LocInfo,
178 ISD::ArgFlagsTy ArgFlags, CCState &State);
180 /// CCCustomFn - This function assigns a location for Val, possibly updating
181 /// all args to reflect changes and indicates if it handled it. It must set
182 /// isCustom if it handles the arg and returns true.
183 typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
184 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
185 ISD::ArgFlagsTy &ArgFlags, CCState &State);
187 /// CCState - This class holds information needed while lowering arguments and
188 /// return values. It captures which registers are already assigned and which
189 /// stack slots are used. It provides accessors to allocate these values.
192 CallingConv::ID CallingConv;
194 bool AnalyzingMustTailForwardedRegs = false;
196 const TargetRegisterInfo &TRI;
197 SmallVectorImpl<CCValAssign> &Locs;
198 LLVMContext &Context;
200 unsigned StackOffset;
201 unsigned MaxStackArgAlign;
202 SmallVector<uint32_t, 16> UsedRegs;
203 SmallVector<CCValAssign, 4> PendingLocs;
204 SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
206 // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
208 // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
210 // Or, in another words it tracks byval parameters that are stored in
211 // general purpose registers.
213 // For 4 byte stack alignment,
214 // instance index means byval parameter number in formal
215 // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
216 // then, for function "foo":
218 // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
220 // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
221 // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
223 // In case of 8 bytes stack alignment,
224 // ByValRegs may also contain information about wasted registers.
225 // In function shown above, r3 would be wasted according to AAPCS rules.
226 // And in that case ByValRegs[1].Waste would be "true".
227 // ByValRegs vector size still would be 2,
228 // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
230 // Supposed use-case for this collection:
231 // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
232 // 2. HandleByVal fillups ByValRegs.
233 // 3. Argument analysis (LowerFormatArguments, for example). After
234 // some byval argument was analyzed, InRegsParamsProcessed is increased.
236 ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
237 Begin(B), End(E), Waste(IsWaste) {}
238 // First register allocated for current parameter.
241 // First after last register allocated for current parameter.
244 // Means that current range of registers doesn't belong to any
245 // parameters. It was wasted due to stack alignment rules.
246 // For more information see:
247 // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
250 SmallVector<ByValInfo, 4 > ByValRegs;
252 // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
253 // during argument analysis.
254 unsigned InRegsParamsProcessed;
257 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
258 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
260 void addLoc(const CCValAssign &V) {
264 LLVMContext &getContext() const { return Context; }
265 MachineFunction &getMachineFunction() const { return MF; }
266 CallingConv::ID getCallingConv() const { return CallingConv; }
267 bool isVarArg() const { return IsVarArg; }
269 /// getNextStackOffset - Return the next stack offset such that all stack
270 /// slots satisfy their alignment requirements.
271 unsigned getNextStackOffset() const {
275 /// getAlignedCallFrameSize - Return the size of the call frame needed to
276 /// be able to store all arguments and such that the alignment requirement
277 /// of each of the arguments is satisfied.
278 unsigned getAlignedCallFrameSize() const {
279 return alignTo(StackOffset, MaxStackArgAlign);
282 /// isAllocated - Return true if the specified register (or an alias) is
284 bool isAllocated(unsigned Reg) const {
285 return UsedRegs[Reg/32] & (1 << (Reg&31));
288 /// AnalyzeFormalArguments - Analyze an array of argument values,
289 /// incorporating info about the formals into this state.
290 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
293 /// The function will invoke AnalyzeFormalArguments.
294 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
296 AnalyzeFormalArguments(Ins, Fn);
299 /// AnalyzeReturn - Analyze the returned values of a return,
300 /// incorporating info about the result values into this state.
301 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
304 /// CheckReturn - Analyze the return values of a function, returning
305 /// true if the return can be performed without sret-demotion, and
307 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
310 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
311 /// incorporating info about the passed values into this state.
312 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
315 /// AnalyzeCallOperands - Same as above except it takes vectors of types
316 /// and argument flags.
317 void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
318 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
321 /// The function will invoke AnalyzeCallOperands.
322 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
324 AnalyzeCallOperands(Outs, Fn);
327 /// AnalyzeCallResult - Analyze the return values of a call,
328 /// incorporating info about the passed values into this state.
329 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
332 /// A shadow allocated register is a register that was allocated
333 /// but wasn't added to the location list (Locs).
334 /// \returns true if the register was allocated as shadow or false otherwise.
335 bool IsShadowAllocatedReg(unsigned Reg) const;
337 /// AnalyzeCallResult - Same as above except it's specialized for calls which
338 /// produce a single value.
339 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
341 /// getFirstUnallocated - Return the index of the first unallocated register
342 /// in the set, or Regs.size() if they are all allocated.
343 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
344 for (unsigned i = 0; i < Regs.size(); ++i)
345 if (!isAllocated(Regs[i]))
350 /// AllocateReg - Attempt to allocate one register. If it is not available,
351 /// return zero. Otherwise, return the register, marking it and any aliases
353 unsigned AllocateReg(unsigned Reg) {
354 if (isAllocated(Reg)) return 0;
359 /// Version of AllocateReg with extra register to be shadowed.
360 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
361 if (isAllocated(Reg)) return 0;
363 MarkAllocated(ShadowReg);
367 /// AllocateReg - Attempt to allocate one of the specified registers. If none
368 /// are available, return zero. Otherwise, return the first one available,
369 /// marking it and any aliases as allocated.
370 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
371 unsigned FirstUnalloc = getFirstUnallocated(Regs);
372 if (FirstUnalloc == Regs.size())
373 return 0; // Didn't find the reg.
375 // Mark the register and any aliases as allocated.
376 unsigned Reg = Regs[FirstUnalloc];
381 /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
382 /// registers. If this is not possible, return zero. Otherwise, return the first
383 /// register of the block that were allocated, marking the entire block as allocated.
384 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
385 if (RegsRequired > Regs.size())
388 for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
390 bool BlockAvailable = true;
391 // Check for already-allocated regs in this block
392 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
393 if (isAllocated(Regs[StartIdx + BlockIdx])) {
394 BlockAvailable = false;
398 if (BlockAvailable) {
399 // Mark the entire block as allocated
400 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
401 MarkAllocated(Regs[StartIdx + BlockIdx]);
403 return Regs[StartIdx];
406 // No block was available
410 /// Version of AllocateReg with list of registers to be shadowed.
411 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
412 unsigned FirstUnalloc = getFirstUnallocated(Regs);
413 if (FirstUnalloc == Regs.size())
414 return 0; // Didn't find the reg.
416 // Mark the register and any aliases as allocated.
417 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
419 MarkAllocated(ShadowReg);
423 /// AllocateStack - Allocate a chunk of stack space with the specified size
425 unsigned AllocateStack(unsigned Size, unsigned Align) {
426 assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
427 StackOffset = alignTo(StackOffset, Align);
428 unsigned Result = StackOffset;
430 MaxStackArgAlign = std::max(Align, MaxStackArgAlign);
431 ensureMaxAlignment(Align);
435 void ensureMaxAlignment(unsigned Align) {
436 if (!AnalyzingMustTailForwardedRegs)
437 MF.getFrameInfo().ensureMaxAlignment(Align);
440 /// Version of AllocateStack with extra register to be shadowed.
441 unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
442 MarkAllocated(ShadowReg);
443 return AllocateStack(Size, Align);
446 /// Version of AllocateStack with list of extra registers to be shadowed.
447 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
448 unsigned AllocateStack(unsigned Size, unsigned Align,
449 ArrayRef<MCPhysReg> ShadowRegs) {
450 for (unsigned i = 0; i < ShadowRegs.size(); ++i)
451 MarkAllocated(ShadowRegs[i]);
452 return AllocateStack(Size, Align);
455 // HandleByVal - Allocate a stack slot large enough to pass an argument by
456 // value. The size and alignment information of the argument is encoded in its
457 // parameter attribute.
458 void HandleByVal(unsigned ValNo, MVT ValVT,
459 MVT LocVT, CCValAssign::LocInfo LocInfo,
460 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
462 // Returns count of byval arguments that are to be stored (even partly)
464 unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
466 // Returns count of byval in-regs arguments proceed.
467 unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
469 // Get information about N-th byval parameter that is stored in registers.
470 // Here "ByValParamIndex" is N.
471 void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
472 unsigned& BeginReg, unsigned& EndReg) const {
473 assert(InRegsParamRecordIndex < ByValRegs.size() &&
474 "Wrong ByVal parameter index");
476 const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
477 BeginReg = info.Begin;
481 // Add information about parameter that is kept in registers.
482 void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
483 ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
486 // Goes either to next byval parameter (excluding "waste" record), or
487 // to the end of collection.
488 // Returns false, if end is reached.
489 bool nextInRegsParam() {
490 unsigned e = ByValRegs.size();
491 if (InRegsParamsProcessed < e)
492 ++InRegsParamsProcessed;
493 return InRegsParamsProcessed < e;
496 // Clear byval registers tracking info.
497 void clearByValRegsInfo() {
498 InRegsParamsProcessed = 0;
502 // Rewind byval registers tracking info.
503 void rewindByValRegsInfo() {
504 InRegsParamsProcessed = 0;
507 // Get list of pending assignments
508 SmallVectorImpl<CCValAssign> &getPendingLocs() {
512 // Get a list of argflags for pending assignments.
513 SmallVectorImpl<ISD::ArgFlagsTy> &getPendingArgFlags() {
514 return PendingArgFlags;
517 /// Compute the remaining unused register parameters that would be used for
518 /// the given value type. This is useful when varargs are passed in the
519 /// registers that normal prototyped parameters would be passed in, or for
520 /// implementing perfect forwarding.
521 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
524 /// Compute the set of registers that need to be preserved and forwarded to
525 /// any musttail calls.
526 void analyzeMustTailForwardedRegisters(
527 SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
530 /// Returns true if the results of the two calling conventions are compatible.
531 /// This is usually part of the check for tailcall eligibility.
532 static bool resultsCompatible(CallingConv::ID CalleeCC,
533 CallingConv::ID CallerCC, MachineFunction &MF,
535 const SmallVectorImpl<ISD::InputArg> &Ins,
536 CCAssignFn CalleeFn, CCAssignFn CallerFn);
538 /// The function runs an additional analysis pass over function arguments.
539 /// It will mark each argument with the attribute flag SecArgPass.
540 /// After running, it will sort the locs list.
542 void AnalyzeArgumentsSecondPass(const SmallVectorImpl<T> &Args,
544 unsigned NumFirstPassLocs = Locs.size();
546 /// Creates similar argument list to \p Args in which each argument is
547 /// marked using SecArgPass flag.
548 SmallVector<T, 16> SecPassArg;
549 // SmallVector<ISD::InputArg, 16> SecPassArg;
550 for (auto Arg : Args) {
551 Arg.Flags.setSecArgPass();
552 SecPassArg.push_back(Arg);
555 // Run the second argument pass
556 AnalyzeArguments(SecPassArg, Fn);
558 // Sort the locations of the arguments according to their original position.
559 SmallVector<CCValAssign, 16> TmpArgLocs;
560 std::swap(TmpArgLocs, Locs);
561 auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
562 std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
563 std::back_inserter(Locs),
564 [](const CCValAssign &A, const CCValAssign &B) -> bool {
565 return A.getValNo() < B.getValNo();
570 /// MarkAllocated - Mark a register and all of its aliases as allocated.
571 void MarkAllocated(unsigned Reg);
574 } // end namespace llvm
576 #endif // LLVM_CODEGEN_CALLINGCONVLOWER_H