1 //===-- llvm/CallingConvLower.h - Calling Conventions -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the CCState and CCValAssign classes, used for lowering
11 // and implementing calling conventions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
16 #define LLVM_CODEGEN_CALLINGCONVLOWER_H
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/Target/TargetCallingConv.h"
28 class TargetRegisterInfo;
30 /// CCValAssign - Represent assignment of one arg/retval to a location.
34 Full, // The value fills the full location.
35 SExt, // The value is sign extended in the location.
36 ZExt, // The value is zero extended in the location.
37 AExt, // The value is extended with undefined upper bits.
38 SExtUpper, // The value is in the upper bits of the location and should be
39 // sign extended when retrieved.
40 ZExtUpper, // The value is in the upper bits of the location and should be
41 // zero extended when retrieved.
42 AExtUpper, // The value is in the upper bits of the location and should be
43 // extended with undefined upper bits when retrieved.
44 BCvt, // The value is bit-converted in the location.
45 VExt, // The value is vector-widened in the location.
46 // FIXME: Not implemented yet. Code that uses AExt to mean
47 // vector-widen should be fixed to use VExt instead.
48 FPExt, // The floating-point value is fp-extended in the location.
49 Indirect // The location contains pointer to the value.
50 // TODO: a subset of the value is in the location.
54 /// ValNo - This is the value number begin assigned (e.g. an argument number).
57 /// Loc is either a stack offset or a register number.
60 /// isMem - True if this is a memory loc, false if it is a register loc.
63 /// isCustom - True if this arg/retval requires special handling.
64 unsigned isCustom : 1;
66 /// Information about how the value is assigned.
69 /// ValVT - The type of the value being assigned.
72 /// LocVT - The type of the location being assigned to.
76 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
77 unsigned RegNo, MVT LocVT,
90 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
91 unsigned RegNo, MVT LocVT,
94 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
99 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
100 unsigned Offset, MVT LocVT,
106 Ret.isCustom = false;
113 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
114 unsigned Offset, MVT LocVT,
117 Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
122 // There is no need to differentiate between a pending CCValAssign and other
123 // kinds, as they are stored in a different list.
124 static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
125 LocInfo HTP, unsigned ExtraInfo = 0) {
126 return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
129 void convertToReg(unsigned RegNo) {
134 void convertToMem(unsigned Offset) {
139 unsigned getValNo() const { return ValNo; }
140 MVT getValVT() const { return ValVT; }
142 bool isRegLoc() const { return !isMem; }
143 bool isMemLoc() const { return isMem; }
145 bool needsCustom() const { return isCustom; }
147 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
148 unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
149 unsigned getExtraInfo() const { return Loc; }
150 MVT getLocVT() const { return LocVT; }
152 LocInfo getLocInfo() const { return HTP; }
153 bool isExtInLoc() const {
154 return (HTP == AExt || HTP == SExt || HTP == ZExt);
157 bool isUpperBitsInLoc() const {
158 return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
162 /// Describes a register that needs to be forwarded from the prologue to a
164 struct ForwardedRegister {
165 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
166 : VReg(VReg), PReg(PReg), VT(VT) {}
172 /// CCAssignFn - This function assigns a location for Val, updating State to
173 /// reflect the change. It returns 'true' if it failed to handle Val.
174 typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
175 MVT LocVT, CCValAssign::LocInfo LocInfo,
176 ISD::ArgFlagsTy ArgFlags, CCState &State);
178 /// CCCustomFn - This function assigns a location for Val, possibly updating
179 /// all args to reflect changes and indicates if it handled it. It must set
180 /// isCustom if it handles the arg and returns true.
181 typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
182 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
183 ISD::ArgFlagsTy &ArgFlags, CCState &State);
185 /// ParmContext - This enum tracks whether calling convention lowering is in
186 /// the context of prologue or call generation. Not all backends make use of
187 /// this information.
188 typedef enum { Unknown, Prologue, Call } ParmContext;
190 /// CCState - This class holds information needed while lowering arguments and
191 /// return values. It captures which registers are already assigned and which
192 /// stack slots are used. It provides accessors to allocate these values.
195 CallingConv::ID CallingConv;
198 const TargetRegisterInfo &TRI;
199 SmallVectorImpl<CCValAssign> &Locs;
200 LLVMContext &Context;
202 unsigned StackOffset;
203 SmallVector<uint32_t, 16> UsedRegs;
204 SmallVector<CCValAssign, 4> PendingLocs;
206 // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
208 // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
210 // Or, in another words it tracks byval parameters that are stored in
211 // general purpose registers.
213 // For 4 byte stack alignment,
214 // instance index means byval parameter number in formal
215 // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
216 // then, for function "foo":
218 // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
220 // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
221 // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
223 // In case of 8 bytes stack alignment,
224 // ByValRegs may also contain information about wasted registers.
225 // In function shown above, r3 would be wasted according to AAPCS rules.
226 // And in that case ByValRegs[1].Waste would be "true".
227 // ByValRegs vector size still would be 2,
228 // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
230 // Supposed use-case for this collection:
231 // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
232 // 2. HandleByVal fillups ByValRegs.
233 // 3. Argument analysis (LowerFormatArguments, for example). After
234 // some byval argument was analyzed, InRegsParamsProcessed is increased.
236 ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
237 Begin(B), End(E), Waste(IsWaste) {}
238 // First register allocated for current parameter.
241 // First after last register allocated for current parameter.
244 // Means that current range of registers doesn't belong to any
245 // parameters. It was wasted due to stack alignment rules.
246 // For more information see:
247 // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
250 SmallVector<ByValInfo, 4 > ByValRegs;
252 // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
253 // during argument analysis.
254 unsigned InRegsParamsProcessed;
257 ParmContext CallOrPrologue;
260 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
261 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
263 void addLoc(const CCValAssign &V) {
267 LLVMContext &getContext() const { return Context; }
268 MachineFunction &getMachineFunction() const { return MF; }
269 CallingConv::ID getCallingConv() const { return CallingConv; }
270 bool isVarArg() const { return IsVarArg; }
272 unsigned getNextStackOffset() const { return StackOffset; }
274 /// isAllocated - Return true if the specified register (or an alias) is
276 bool isAllocated(unsigned Reg) const {
277 return UsedRegs[Reg/32] & (1 << (Reg&31));
280 /// AnalyzeFormalArguments - Analyze an array of argument values,
281 /// incorporating info about the formals into this state.
282 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
285 /// AnalyzeReturn - Analyze the returned values of a return,
286 /// incorporating info about the result values into this state.
287 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
290 /// CheckReturn - Analyze the return values of a function, returning
291 /// true if the return can be performed without sret-demotion, and
293 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
296 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
297 /// incorporating info about the passed values into this state.
298 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
301 /// AnalyzeCallOperands - Same as above except it takes vectors of types
302 /// and argument flags.
303 void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
304 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
307 /// AnalyzeCallResult - Analyze the return values of a call,
308 /// incorporating info about the passed values into this state.
309 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
312 /// AnalyzeCallResult - Same as above except it's specialized for calls which
313 /// produce a single value.
314 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
316 /// getFirstUnallocated - Return the first unallocated register in the set, or
317 /// NumRegs if they are all allocated.
318 unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const {
319 for (unsigned i = 0; i != NumRegs; ++i)
320 if (!isAllocated(Regs[i]))
325 /// AllocateReg - Attempt to allocate one register. If it is not available,
326 /// return zero. Otherwise, return the register, marking it and any aliases
328 unsigned AllocateReg(unsigned Reg) {
329 if (isAllocated(Reg)) return 0;
334 /// Version of AllocateReg with extra register to be shadowed.
335 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
336 if (isAllocated(Reg)) return 0;
338 MarkAllocated(ShadowReg);
342 /// AllocateReg - Attempt to allocate one of the specified registers. If none
343 /// are available, return zero. Otherwise, return the first one available,
344 /// marking it and any aliases as allocated.
345 unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) {
346 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
347 if (FirstUnalloc == NumRegs)
348 return 0; // Didn't find the reg.
350 // Mark the register and any aliases as allocated.
351 unsigned Reg = Regs[FirstUnalloc];
356 /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
357 /// registers. If this is not possible, return zero. Otherwise, return the first
358 /// register of the block that were allocated, marking the entire block as allocated.
359 unsigned AllocateRegBlock(ArrayRef<uint16_t> Regs, unsigned RegsRequired) {
360 if (RegsRequired > Regs.size())
363 for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
365 bool BlockAvailable = true;
366 // Check for already-allocated regs in this block
367 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
368 if (isAllocated(Regs[StartIdx + BlockIdx])) {
369 BlockAvailable = false;
373 if (BlockAvailable) {
374 // Mark the entire block as allocated
375 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
376 MarkAllocated(Regs[StartIdx + BlockIdx]);
378 return Regs[StartIdx];
381 // No block was available
385 /// Version of AllocateReg with list of registers to be shadowed.
386 unsigned AllocateReg(const MCPhysReg *Regs, const MCPhysReg *ShadowRegs,
388 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
389 if (FirstUnalloc == NumRegs)
390 return 0; // Didn't find the reg.
392 // Mark the register and any aliases as allocated.
393 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
395 MarkAllocated(ShadowReg);
399 /// AllocateStack - Allocate a chunk of stack space with the specified size
401 unsigned AllocateStack(unsigned Size, unsigned Align) {
402 assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
403 StackOffset = ((StackOffset + Align - 1) & ~(Align - 1));
404 unsigned Result = StackOffset;
406 MF.getFrameInfo()->ensureMaxAlignment(Align);
410 /// Version of AllocateStack with extra register to be shadowed.
411 unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
412 MarkAllocated(ShadowReg);
413 return AllocateStack(Size, Align);
416 /// Version of AllocateStack with list of extra registers to be shadowed.
417 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
418 unsigned AllocateStack(unsigned Size, unsigned Align,
419 const MCPhysReg *ShadowRegs, unsigned NumShadowRegs) {
420 for (unsigned i = 0; i < NumShadowRegs; ++i)
421 MarkAllocated(ShadowRegs[i]);
422 return AllocateStack(Size, Align);
425 // HandleByVal - Allocate a stack slot large enough to pass an argument by
426 // value. The size and alignment information of the argument is encoded in its
427 // parameter attribute.
428 void HandleByVal(unsigned ValNo, MVT ValVT,
429 MVT LocVT, CCValAssign::LocInfo LocInfo,
430 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
432 // Returns count of byval arguments that are to be stored (even partly)
434 unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
436 // Returns count of byval in-regs arguments proceed.
437 unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
439 // Get information about N-th byval parameter that is stored in registers.
440 // Here "ByValParamIndex" is N.
441 void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
442 unsigned& BeginReg, unsigned& EndReg) const {
443 assert(InRegsParamRecordIndex < ByValRegs.size() &&
444 "Wrong ByVal parameter index");
446 const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
447 BeginReg = info.Begin;
451 // Add information about parameter that is kept in registers.
452 void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
453 ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
456 // Goes either to next byval parameter (excluding "waste" record), or
457 // to the end of collection.
458 // Returns false, if end is reached.
459 bool nextInRegsParam() {
460 unsigned e = ByValRegs.size();
461 if (InRegsParamsProcessed < e)
462 ++InRegsParamsProcessed;
463 return InRegsParamsProcessed < e;
466 // Clear byval registers tracking info.
467 void clearByValRegsInfo() {
468 InRegsParamsProcessed = 0;
472 // Rewind byval registers tracking info.
473 void rewindByValRegsInfo() {
474 InRegsParamsProcessed = 0;
477 ParmContext getCallOrPrologue() const { return CallOrPrologue; }
479 // Get list of pending assignments
480 SmallVectorImpl<llvm::CCValAssign> &getPendingLocs() {
484 /// Compute the remaining unused register parameters that would be used for
485 /// the given value type. This is useful when varargs are passed in the
486 /// registers that normal prototyped parameters would be passed in, or for
487 /// implementing perfect forwarding.
488 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
491 /// Compute the set of registers that need to be preserved and forwarded to
492 /// any musttail calls.
493 void analyzeMustTailForwardedRegisters(
494 SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
498 /// MarkAllocated - Mark a register and all of its aliases as allocated.
499 void MarkAllocated(unsigned Reg);
504 } // end namespace llvm