1 //===-- FastISel.h - Definition of the FastISel class ---*- C++ -*---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file defines the FastISel class.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_FASTISEL_H
16 #define LLVM_CODEGEN_FASTISEL_H
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/IR/IntrinsicInst.h"
22 #include "llvm/Target/TargetLowering.h"
26 class MachineConstantPool;
28 /// \brief This is a fast-path instruction selection class that generates poor
29 /// code and doesn't support illegal types or non-trivial lowering, but runs
45 bool IsSwiftError : 1;
49 : Val(nullptr), Ty(nullptr), IsSExt(false), IsZExt(false),
50 IsInReg(false), IsSRet(false), IsNest(false), IsByVal(false),
51 IsInAlloca(false), IsReturned(false), IsSwiftSelf(false),
52 IsSwiftError(false), Alignment(0) {}
54 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
55 /// and called function attributes.
56 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
58 typedef std::vector<ArgListEntry> ArgListTy;
60 struct CallLoweringInfo {
66 bool DoesNotReturn : 1;
67 bool IsReturnValueUsed : 1;
69 // \brief IsTailCall Should be modified by implementations of FastLowerCall
70 // that perform tail call conversions.
73 unsigned NumFixedArgs;
74 CallingConv::ID CallConv;
78 ImmutableCallSite *CS;
81 unsigned NumResultRegs;
85 SmallVector<Value *, 16> OutVals;
86 SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
87 SmallVector<unsigned, 16> OutRegs;
88 SmallVector<ISD::InputArg, 4> Ins;
89 SmallVector<unsigned, 4> InRegs;
92 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
93 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
94 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
95 Callee(nullptr), Symbol(nullptr), CS(nullptr), Call(nullptr),
96 ResultReg(0), NumResultRegs(0), IsPatchPoint(false) {}
98 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
99 const Value *Target, ArgListTy &&ArgsList,
100 ImmutableCallSite &Call) {
104 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
105 DoesNotReturn = Call.doesNotReturn();
106 IsVarArg = FuncTy->isVarArg();
107 IsReturnValueUsed = !Call.getInstruction()->use_empty();
108 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
109 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
111 CallConv = Call.getCallingConv();
112 Args = std::move(ArgsList);
113 NumFixedArgs = FuncTy->getNumParams();
120 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
121 MCSymbol *Target, ArgListTy &&ArgsList,
122 ImmutableCallSite &Call,
123 unsigned FixedArgs = ~0U) {
125 Callee = Call.getCalledValue();
128 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
129 DoesNotReturn = Call.doesNotReturn();
130 IsVarArg = FuncTy->isVarArg();
131 IsReturnValueUsed = !Call.getInstruction()->use_empty();
132 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
133 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
135 CallConv = Call.getCallingConv();
136 Args = std::move(ArgsList);
137 NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
144 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
145 const Value *Target, ArgListTy &&ArgsList,
146 unsigned FixedArgs = ~0U) {
150 Args = std::move(ArgsList);
151 NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
155 CallLoweringInfo &setCallee(const DataLayout &DL, MCContext &Ctx,
156 CallingConv::ID CC, Type *ResultTy,
157 StringRef Target, ArgListTy &&ArgsList,
158 unsigned FixedArgs = ~0U);
160 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
161 MCSymbol *Target, ArgListTy &&ArgsList,
162 unsigned FixedArgs = ~0U) {
166 Args = std::move(ArgsList);
167 NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
171 CallLoweringInfo &setTailCall(bool Value = true) {
176 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
177 IsPatchPoint = Value;
181 ArgListTy &getArgs() { return Args; }
196 DenseMap<const Value *, unsigned> LocalValueMap;
197 FunctionLoweringInfo &FuncInfo;
199 MachineRegisterInfo &MRI;
200 MachineFrameInfo &MFI;
201 MachineConstantPool &MCP;
203 const TargetMachine &TM;
204 const DataLayout &DL;
205 const TargetInstrInfo &TII;
206 const TargetLowering &TLI;
207 const TargetRegisterInfo &TRI;
208 const TargetLibraryInfo *LibInfo;
209 bool SkipTargetIndependentISel;
211 /// \brief The position of the last instruction for materializing constants
212 /// for use in the current block. It resets to EmitStartPt when it makes sense
213 /// (for example, it's usually profitable to avoid function calls between the
214 /// definition and the use)
215 MachineInstr *LastLocalValue;
217 /// \brief The top most instruction in the current block that is allowed for
218 /// emitting local variables. LastLocalValue resets to EmitStartPt when it
219 /// makes sense (for example, on function calls)
220 MachineInstr *EmitStartPt;
223 /// \brief Return the position of the last instruction emitted for
224 /// materializing constants for use in the current block.
225 MachineInstr *getLastLocalValue() { return LastLocalValue; }
227 /// \brief Update the position of the last instruction emitted for
228 /// materializing constants for use in the current block.
229 void setLastLocalValue(MachineInstr *I) {
234 /// \brief Set the current block to which generated machine instructions will
235 /// be appended, and clear the local CSE map.
236 void startNewBlock();
238 /// \brief Return current debug location information.
239 DebugLoc getCurDebugLoc() const { return DbgLoc; }
241 /// \brief Do "fast" instruction selection for function arguments and append
242 /// the machine instructions to the current block. Returns true when
244 bool lowerArguments();
246 /// \brief Do "fast" instruction selection for the given LLVM IR instruction
247 /// and append the generated machine instructions to the current block.
248 /// Returns true if selection was successful.
249 bool selectInstruction(const Instruction *I);
251 /// \brief Do "fast" instruction selection for the given LLVM IR operator
252 /// (Instruction or ConstantExpr), and append generated machine instructions
253 /// to the current block. Return true if selection was successful.
254 bool selectOperator(const User *I, unsigned Opcode);
256 /// \brief Create a virtual register and arrange for it to be assigned the
257 /// value for the given LLVM value.
258 unsigned getRegForValue(const Value *V);
260 /// \brief Look up the value to see if its value is already cached in a
261 /// register. It may be defined by instructions across blocks or defined
263 unsigned lookUpRegForValue(const Value *V);
265 /// \brief This is a wrapper around getRegForValue that also takes care of
266 /// truncating or sign-extending the given getelementptr index value.
267 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
269 /// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note
270 /// that we could have a sequence where multiple LLVM IR instructions are
271 /// folded into the same machineinstr. For example we could have:
273 /// A: x = load i32 *P
274 /// B: y = icmp A, 42
277 /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B"
278 /// (and any other folded instructions) because it is between A and C.
280 /// If we succeed folding, return true.
281 bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
283 /// \brief The specified machine instr operand is a vreg, and that vreg is
284 /// being provided by the specified load instruction. If possible, try to
285 /// fold the load as an operand to the instruction, returning true if
288 /// This method should be implemented by targets.
289 virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
290 const LoadInst * /*LI*/) {
294 /// \brief Reset InsertPt to prepare for inserting instructions into the
296 void recomputeInsertPt();
298 /// \brief Remove all dead instructions between the I and E.
299 void removeDeadCode(MachineBasicBlock::iterator I,
300 MachineBasicBlock::iterator E);
303 MachineBasicBlock::iterator InsertPt;
307 /// \brief Prepare InsertPt to begin inserting instructions into the local
308 /// value area and return the old insert position.
309 SavePoint enterLocalValueArea();
311 /// \brief Reset InsertPt to the given old insert position.
312 void leaveLocalValueArea(SavePoint Old);
317 explicit FastISel(FunctionLoweringInfo &FuncInfo,
318 const TargetLibraryInfo *LibInfo,
319 bool SkipTargetIndependentISel = false);
321 /// \brief This method is called by target-independent code when the normal
322 /// FastISel process fails to select an instruction. This gives targets a
323 /// chance to emit code for anything that doesn't fit into FastISel's
324 /// framework. It returns true if it was successful.
325 virtual bool fastSelectInstruction(const Instruction *I) = 0;
327 /// \brief This method is called by target-independent code to do target-
328 /// specific argument lowering. It returns true if it was successful.
329 virtual bool fastLowerArguments();
331 /// \brief This method is called by target-independent code to do target-
332 /// specific call lowering. It returns true if it was successful.
333 virtual bool fastLowerCall(CallLoweringInfo &CLI);
335 /// \brief This method is called by target-independent code to do target-
336 /// specific intrinsic lowering. It returns true if it was successful.
337 virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II);
339 /// \brief This method is called by target-independent code to request that an
340 /// instruction with the given type and opcode be emitted.
341 virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
343 /// \brief This method is called by target-independent code to request that an
344 /// instruction with the given type, opcode, and register operand be emitted.
345 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
348 /// \brief This method is called by target-independent code to request that an
349 /// instruction with the given type, opcode, and register operands be emitted.
350 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
351 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
353 /// \brief This method is called by target-independent code to request that an
354 /// instruction with the given type, opcode, and register and immediate
355 // operands be emitted.
356 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
357 bool Op0IsKill, uint64_t Imm);
359 /// \brief This method is a wrapper of fastEmit_ri.
361 /// It first tries to emit an instruction with an immediate operand using
362 /// fastEmit_ri. If that fails, it materializes the immediate into a register
363 /// and try fastEmit_rr instead.
364 unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
365 uint64_t Imm, MVT ImmType);
367 /// \brief This method is called by target-independent code to request that an
368 /// instruction with the given type, opcode, and immediate operand be emitted.
369 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
371 /// \brief This method is called by target-independent code to request that an
372 /// instruction with the given type, opcode, and floating-point immediate
373 /// operand be emitted.
374 virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
375 const ConstantFP *FPImm);
377 /// \brief Emit a MachineInstr with no operands and a result register in the
378 /// given register class.
379 unsigned fastEmitInst_(unsigned MachineInstOpcode,
380 const TargetRegisterClass *RC);
382 /// \brief Emit a MachineInstr with one register operand and a result register
383 /// in the given register class.
384 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
385 const TargetRegisterClass *RC, unsigned Op0,
388 /// \brief Emit a MachineInstr with two register operands and a result
389 /// register in the given register class.
390 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
391 const TargetRegisterClass *RC, unsigned Op0,
392 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
394 /// \brief Emit a MachineInstr with three register operands and a result
395 /// register in the given register class.
396 unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
397 const TargetRegisterClass *RC, unsigned Op0,
398 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
399 unsigned Op2, bool Op2IsKill);
401 /// \brief Emit a MachineInstr with a register operand, an immediate, and a
402 /// result register in the given register class.
403 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
404 const TargetRegisterClass *RC, unsigned Op0,
405 bool Op0IsKill, uint64_t Imm);
407 /// \brief Emit a MachineInstr with one register operand and two immediate
409 unsigned fastEmitInst_rii(unsigned MachineInstOpcode,
410 const TargetRegisterClass *RC, unsigned Op0,
411 bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
413 /// \brief Emit a MachineInstr with a floating point immediate, and a result
414 /// register in the given register class.
415 unsigned fastEmitInst_f(unsigned MachineInstOpcode,
416 const TargetRegisterClass *RC,
417 const ConstantFP *FPImm);
419 /// \brief Emit a MachineInstr with two register operands, an immediate, and a
420 /// result register in the given register class.
421 unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
422 const TargetRegisterClass *RC, unsigned Op0,
423 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
426 /// \brief Emit a MachineInstr with a single immediate operand, and a result
427 /// register in the given register class.
428 unsigned fastEmitInst_i(unsigned MachineInstrOpcode,
429 const TargetRegisterClass *RC, uint64_t Imm);
431 /// \brief Emit a MachineInstr for an extract_subreg from a specified index of
432 /// a superregister to a specified type.
433 unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
436 /// \brief Emit MachineInstrs to compute the value of Op with all but the
437 /// least significant bit set to zero.
438 unsigned fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill);
440 /// \brief Emit an unconditional branch to the given block, unless it is the
441 /// immediate (fall-through) successor, and update the CFG.
442 void fastEmitBranch(MachineBasicBlock *MBB, const DebugLoc &DL);
444 /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
445 /// and adds TrueMBB and FalseMBB to the successor list.
446 void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB,
447 MachineBasicBlock *FalseMBB);
449 /// \brief Update the value map to include the new mapping for this
450 /// instruction, or insert an extra copy to get the result in a previous
451 /// determined register.
453 /// NOTE: This is only necessary because we might select a block that uses a
454 /// value before we select the block that defines the value. It might be
455 /// possible to fix this by selecting blocks in reverse postorder.
456 void updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs = 1);
458 unsigned createResultReg(const TargetRegisterClass *RC);
460 /// \brief Try to constrain Op so that it is usable by argument OpNum of the
461 /// provided MCInstrDesc. If this fails, create a new virtual register in the
462 /// correct class and COPY the value there.
463 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
466 /// \brief Emit a constant in a register using target-specific logic, such as
467 /// constant pool loads.
468 virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; }
470 /// \brief Emit an alloca address in a register using target-specific logic.
471 virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
473 /// \brief Emit the floating-point constant +0.0 in a register using target-
475 virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
479 /// \brief Check if \c Add is an add that can be safely folded into \c GEP.
481 /// \c Add can be folded into \c GEP if:
482 /// - \c Add is an add,
483 /// - \c Add's size matches \c GEP's,
484 /// - \c Add is in the same basic block as \c GEP, and
485 /// - \c Add has a constant operand.
486 bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
488 /// \brief Test whether the given value has exactly one use.
489 bool hasTrivialKill(const Value *V);
491 /// \brief Create a machine mem operand from the given instruction.
492 MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
494 CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
496 bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
497 bool lowerCallTo(const CallInst *CI, const char *SymbolName,
499 bool lowerCallTo(CallLoweringInfo &CLI);
501 bool isCommutativeIntrinsic(IntrinsicInst const *II) {
502 switch (II->getIntrinsicID()) {
503 case Intrinsic::sadd_with_overflow:
504 case Intrinsic::uadd_with_overflow:
505 case Intrinsic::smul_with_overflow:
506 case Intrinsic::umul_with_overflow:
514 bool lowerCall(const CallInst *I);
515 /// \brief Select and emit code for a binary operator instruction, which has
516 /// an opcode which directly corresponds to the given ISD opcode.
517 bool selectBinaryOp(const User *I, unsigned ISDOpcode);
518 bool selectFNeg(const User *I);
519 bool selectGetElementPtr(const User *I);
520 bool selectStackmap(const CallInst *I);
521 bool selectPatchpoint(const CallInst *I);
522 bool selectCall(const User *Call);
523 bool selectIntrinsicCall(const IntrinsicInst *II);
524 bool selectBitCast(const User *I);
525 bool selectCast(const User *I, unsigned Opcode);
526 bool selectExtractValue(const User *I);
527 bool selectInsertValue(const User *I);
530 /// \brief Handle PHI nodes in successor blocks.
532 /// Emit code to ensure constants are copied into registers when needed.
533 /// Remember the virtual registers that need to be added to the Machine PHI
534 /// nodes as input. We cannot just directly add them, because expansion might
535 /// result in multiple MBB's for one BB. As such, the start of the BB might
536 /// correspond to a different MBB than the end.
537 bool handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
539 /// \brief Helper for materializeRegForValue to materialize a constant in a
540 /// target-independent way.
541 unsigned materializeConstant(const Value *V, MVT VT);
543 /// \brief Helper for getRegForVale. This function is called when the value
544 /// isn't already available in a register and must be materialized with new
546 unsigned materializeRegForValue(const Value *V, MVT VT);
548 /// \brief Clears LocalValueMap and moves the area for the new local variables
549 /// to the beginning of the block. It helps to avoid spilling cached variables
550 /// across heavy instructions like calls.
551 void flushLocalValueMap();
553 /// \brief Removes dead local value instructions after SavedLastLocalvalue.
554 void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue);
556 /// \brief Insertion point before trying to select the current instruction.
557 MachineBasicBlock::iterator SavedInsertPt;
559 /// \brief Add a stackmap or patchpoint intrinsic call's live variable
560 /// operands to a stackmap or patchpoint machine instruction.
561 bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
562 const CallInst *CI, unsigned StartIdx);
563 bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
564 const Value *Callee, bool ForceRetVoidTy,
565 CallLoweringInfo &CLI);
568 } // end namespace llvm