1 //===- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating functions from LLVM IR into
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
16 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/IndexedMap.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/ISDOpcodes.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/TargetRegisterInfo.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/IR/Value.h"
30 #include "llvm/Support/KnownBits.h"
39 class BranchProbabilityInfo;
42 class MachineFunction;
44 class MachineRegisterInfo;
49 //===--------------------------------------------------------------------===//
50 /// FunctionLoweringInfo - This contains information that is global to a
51 /// function that is used when lowering a region of the function.
53 class FunctionLoweringInfo {
57 const TargetLowering *TLI;
58 MachineRegisterInfo *RegInfo;
59 BranchProbabilityInfo *BPI;
60 /// CanLowerReturn - true iff the function's return value can be lowered to
64 /// True if part of the CSRs will be handled via explicit copies.
67 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
68 /// allocated to hold a pointer to the hidden sret parameter.
69 unsigned DemoteRegister;
71 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
72 DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
74 /// A map from swifterror value in a basic block to the virtual register it is
75 /// currently represented by.
76 DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
79 /// A list of upward exposed vreg uses that need to be satisfied by either a
80 /// copy def or a phi node at the beginning of the basic block representing
81 /// the predecessor(s) swifterror value.
82 DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
83 SwiftErrorVRegUpwardsUse;
85 /// A map from instructions that define/use a swifterror value to the virtual
86 /// register that represents that def/use.
87 llvm::DenseMap<PointerIntPair<const Instruction *, 1, bool>, unsigned>
88 SwiftErrorVRegDefUses;
90 /// The swifterror argument of the current function.
91 const Value *SwiftErrorArg;
93 using SwiftErrorValues = SmallVector<const Value*, 1>;
94 /// A function can only have a single swifterror argument. And if it does
95 /// have a swifterror argument, it must be the first entry in
97 SwiftErrorValues SwiftErrorVals;
99 /// Get or create the swifterror value virtual register in
100 /// SwiftErrorVRegDefMap for this basic block.
101 unsigned getOrCreateSwiftErrorVReg(const MachineBasicBlock *,
104 /// Set the swifterror virtual register in the SwiftErrorVRegDefMap for this
106 void setCurrentSwiftErrorVReg(const MachineBasicBlock *MBB, const Value *,
109 /// Get or create the swifterror value virtual register for a def of a
110 /// swifterror by an instruction.
111 std::pair<unsigned, bool> getOrCreateSwiftErrorVRegDefAt(const Instruction *);
112 std::pair<unsigned, bool>
113 getOrCreateSwiftErrorVRegUseAt(const Instruction *, const MachineBasicBlock *,
116 /// ValueMap - Since we emit code for the function a basic block at a time,
117 /// we must remember which virtual registers hold the values for
118 /// cross-basic-block values.
119 DenseMap<const Value *, unsigned> ValueMap;
121 /// VirtReg2Value map is needed by the Divergence Analysis driven
122 /// instruction selection. It is reverted ValueMap. It is computed
123 /// in lazy style - on demand. It is used to get the Value corresponding
124 /// to the live in virtual register and is called from the
125 /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
126 DenseMap<unsigned, const Value*> VirtReg2Value;
128 /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
129 /// to get the Value corresponding to the live-in virtual register.
130 const Value * getValueFromVirtualReg(unsigned Vreg);
132 /// Track virtual registers created for exception pointers.
133 DenseMap<const Value *, unsigned> CatchPadExceptionPointers;
135 /// Keep track of frame indices allocated for statepoints as they could be
136 /// used across basic block boundaries. This struct is more complex than a
137 /// simple map because the stateopint lowering code de-duplicates gc pointers
138 /// based on their SDValue (so %p and (bitcast %p to T) will get the same
139 /// slot), and we track that here.
141 struct StatepointSpillMap {
142 using SlotMapTy = DenseMap<const Value *, Optional<int>>;
144 /// Maps uniqued llvm IR values to the slots they were spilled in. If a
145 /// value is mapped to None it means we visited the value but didn't spill
146 /// it (because it was a constant, for instance).
149 /// Maps llvm IR values to the values they were de-duplicated to.
150 DenseMap<const Value *, const Value *> DuplicateMap;
152 SlotMapTy::const_iterator find(const Value *V) const {
153 auto DuplIt = DuplicateMap.find(V);
154 if (DuplIt != DuplicateMap.end())
156 return SlotMap.find(V);
159 SlotMapTy::const_iterator end() const { return SlotMap.end(); }
162 /// Maps gc.statepoint instructions to their corresponding StatepointSpillMap
164 DenseMap<const Instruction *, StatepointSpillMap> StatepointSpillMaps;
166 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
167 /// the entry block. This allows the allocas to be efficiently referenced
168 /// anywhere in the function.
169 DenseMap<const AllocaInst*, int> StaticAllocaMap;
171 /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
172 DenseMap<const Argument*, int> ByValArgFrameIndexMap;
174 /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
175 /// function arguments that are inserted after scheduling is completed.
176 SmallVector<MachineInstr*, 8> ArgDbgValues;
178 /// RegFixups - Registers which need to be replaced after isel is done.
179 DenseMap<unsigned, unsigned> RegFixups;
181 DenseSet<unsigned> RegsWithFixups;
183 /// StatepointStackSlots - A list of temporary stack slots (frame indices)
184 /// used to spill values at a statepoint. We store them here to enable
185 /// reuse of the same stack slots across different statepoints in different
187 SmallVector<unsigned, 50> StatepointStackSlots;
189 /// MBB - The current block.
190 MachineBasicBlock *MBB;
192 /// MBB - The current insert position inside the current block.
193 MachineBasicBlock::iterator InsertPt;
196 unsigned NumSignBits : 31;
197 unsigned IsValid : 1;
200 LiveOutInfo() : NumSignBits(0), IsValid(true) {}
203 /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
205 DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
207 /// VisitedBBs - The set of basic blocks visited thus far by instruction
209 SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
211 /// PHINodesToUpdate - A list of phi instructions whose operand list will
212 /// be updated after processing the current basic block.
213 /// TODO: This isn't per-function state, it's per-basic-block state. But
214 /// there's no other convenient place for it to live right now.
215 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
216 unsigned OrigNumPHINodesToUpdate;
218 /// If the current MBB is a landing pad, the exception pointer and exception
219 /// selector registers are copied into these virtual registers by
220 /// SelectionDAGISel::PrepareEHLandingPad().
221 unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
223 /// set - Initialize this FunctionLoweringInfo with the given Function
224 /// and its associated MachineFunction.
226 void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
228 /// clear - Clear out all the function-specific state. This returns this
229 /// FunctionLoweringInfo to an empty state, ready to be used for a
230 /// different function.
233 /// isExportedInst - Return true if the specified value is an instruction
234 /// exported from its block.
235 bool isExportedInst(const Value *V) {
236 return ValueMap.count(V);
239 unsigned CreateReg(MVT VT);
241 unsigned CreateRegs(Type *Ty);
243 unsigned InitializeRegForValue(const Value *V) {
244 // Tokens never live in vregs.
245 if (V->getType()->isTokenTy())
247 unsigned &R = ValueMap[V];
248 assert(R == 0 && "Already initialized this value register!");
249 return R = CreateRegs(V->getType());
252 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
253 /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
254 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
255 if (!LiveOutRegInfo.inBounds(Reg))
258 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
265 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
266 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
267 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
268 /// the larger bit width by zero extension. The bit width must be no smaller
269 /// than the LiveOutInfo's existing bit width.
270 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
272 /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
273 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
274 const KnownBits &Known) {
275 // Only install this information if it tells us something.
276 if (NumSignBits == 1 && Known.isUnknown())
279 LiveOutRegInfo.grow(Reg);
280 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
281 LOI.NumSignBits = NumSignBits;
282 LOI.Known.One = Known.One;
283 LOI.Known.Zero = Known.Zero;
286 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
287 /// register based on the LiveOutInfo of its operands.
288 void ComputePHILiveOutRegInfo(const PHINode*);
290 /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
291 /// called when a block is visited before all of its predecessors.
292 void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
293 // PHIs with no uses have no ValueMap entry.
294 DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
295 if (It == ValueMap.end())
298 unsigned Reg = It->second;
302 LiveOutRegInfo.grow(Reg);
303 LiveOutRegInfo[Reg].IsValid = false;
306 /// setArgumentFrameIndex - Record frame index for the byval
308 void setArgumentFrameIndex(const Argument *A, int FI);
310 /// getArgumentFrameIndex - Get frame index for the byval argument.
311 int getArgumentFrameIndex(const Argument *A);
313 unsigned getCatchPadExceptionPointerVReg(const Value *CPI,
314 const TargetRegisterClass *RC);
317 void addSEHHandlersForLPads(ArrayRef<const LandingPadInst *> LPads);
319 /// LiveOutRegInfo - Information about live out vregs.
320 IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
323 } // end namespace llvm
325 #endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H