1 //==-- llvm/CodeGen/GlobalISel/InstructionSelector.h -------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file This file declares the API for the instruction selector.
11 /// This class is responsible for selecting machine instructions.
12 /// It's implemented by the target. It's used by the InstructionSelect pass.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
17 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
19 #include "llvm/ADT/Optional.h"
25 class MachineRegisterInfo;
26 class RegisterBankInfo;
27 class TargetInstrInfo;
28 class TargetRegisterInfo;
30 /// Provides the logic to select generic machine instructions.
31 class InstructionSelector {
33 virtual ~InstructionSelector() {}
35 /// Select the (possibly generic) instruction \p I to only use target-specific
36 /// opcodes. It is OK to insert multiple instructions, but they cannot be
37 /// generic pre-isel instructions.
39 /// \returns whether selection succeeded.
40 /// \pre I.getParent() && I.getParent()->getParent()
43 /// for I in all mutated/inserted instructions:
44 /// !isPreISelGenericOpcode(I.getOpcode())
46 virtual bool select(MachineInstr &I) const = 0;
49 InstructionSelector();
51 /// Mutate the newly-selected instruction \p I to constrain its (possibly
52 /// generic) virtual register operands to the instruction's register class.
53 /// This could involve inserting COPYs before (for uses) or after (for defs).
54 /// This requires the number of operands to match the instruction description.
55 /// \returns whether operand regclass constraining succeeded.
57 // FIXME: Not all instructions have the same number of operands. We should
58 // probably expose a constrain helper per operand and let the target selector
59 // constrain individual registers, like fast-isel.
60 bool constrainSelectedInstRegOperands(MachineInstr &I,
61 const TargetInstrInfo &TII,
62 const TargetRegisterInfo &TRI,
63 const RegisterBankInfo &RBI) const;
65 bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
66 const MachineRegisterInfo &MRI) const;
68 bool isObviouslySafeToFold(MachineInstr &MI) const;
71 } // End namespace llvm.