1 //==-- llvm/CodeGen/GlobalISel/InstructionSelector.h -------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file This file declares the API for the instruction selector.
11 /// This class is responsible for selecting machine instructions.
12 /// It's implemented by the target. It's used by the InstructionSelect pass.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
17 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
21 class RegisterBankInfo;
22 class TargetInstrInfo;
23 class TargetRegisterInfo;
25 /// Provides the logic to select generic machine instructions.
26 class InstructionSelector {
28 virtual ~InstructionSelector() {}
30 /// Select the (possibly generic) instruction \p I to only use target-specific
31 /// opcodes. It is OK to insert multiple instructions, but they cannot be
32 /// generic pre-isel instructions.
34 /// \returns whether selection succeeded.
35 /// \pre I.getParent() && I.getParent()->getParent()
38 /// for I in all mutated/inserted instructions:
39 /// !isPreISelGenericOpcode(I.getOpcode())
41 virtual bool select(MachineInstr &I) const = 0;
44 InstructionSelector();
46 /// Mutate the newly-selected instruction \p I to constrain its (possibly
47 /// generic) virtual register operands to the instruction's register class.
48 /// This could involve inserting COPYs before (for uses) or after (for defs).
49 /// This requires the number of operands to match the instruction description.
50 /// \returns whether operand regclass constraining succeeded.
52 // FIXME: Not all instructions have the same number of operands. We should
53 // probably expose a constrain helper per operand and let the target selector
54 // constrain individual registers, like fast-isel.
55 bool constrainSelectedInstRegOperands(MachineInstr &I,
56 const TargetInstrInfo &TII,
57 const TargetRegisterInfo &TRI,
58 const RegisterBankInfo &RBI) const;
61 } // End namespace llvm.