1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the MachineIRBuilder class.
11 /// This is a helper class to build MachineInstr.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
17 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
18 #include "llvm/CodeGen/GlobalISel/Types.h"
20 #include "llvm/CodeGen/LowLevelType.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DebugLoc.h"
30 // Forward declarations.
31 class MachineFunction;
33 class TargetInstrInfo;
34 class GISelChangeObserver;
36 /// Class which stores all the state required in a MachineIRBuilder.
37 /// Since MachineIRBuilders will only store state in this object, it allows
38 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39 struct MachineIRBuilderState {
40 /// MachineFunction under construction.
42 /// Information used to access the description of the opcodes.
43 const TargetInstrInfo *TII;
44 /// Information used to verify types are consistent and to create virtual registers.
45 MachineRegisterInfo *MRI;
46 /// Debug location to be set to any instruction we create.
49 /// \name Fields describing the insertion point.
51 MachineBasicBlock *MBB;
52 MachineBasicBlock::iterator II;
55 GISelChangeObserver *Observer;
57 GISelCSEInfo *CSEInfo;
64 const TargetRegisterClass *RC;
68 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
69 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
70 DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
73 void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {
79 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
82 MIB.addDef(MRI.createVirtualRegister(RC));
87 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
94 return MRI.getType(Reg);
96 llvm_unreachable("Unrecognised DstOp::DstType enum");
99 unsigned getReg() const {
100 assert(Ty == DstType::Ty_Reg && "Not a register");
104 const TargetRegisterClass *getRegClass() const {
109 llvm_unreachable("Not a RC Operand");
113 DstType getDstOpKind() const { return Ty; }
121 MachineInstrBuilder SrcMIB;
123 CmpInst::Predicate Pred;
127 enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
128 SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}
129 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
130 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
132 void addSrcToMIB(MachineInstrBuilder &MIB) const {
134 case SrcType::Ty_Predicate:
135 MIB.addPredicate(Pred);
137 case SrcType::Ty_Reg:
140 case SrcType::Ty_MIB:
141 MIB.addUse(SrcMIB->getOperand(0).getReg());
146 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
148 case SrcType::Ty_Predicate:
149 llvm_unreachable("Not a register operand");
150 case SrcType::Ty_Reg:
151 return MRI.getType(Reg);
152 case SrcType::Ty_MIB:
153 return MRI.getType(SrcMIB->getOperand(0).getReg());
155 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
158 unsigned getReg() const {
160 case SrcType::Ty_Predicate:
161 llvm_unreachable("Not a register operand");
162 case SrcType::Ty_Reg:
164 case SrcType::Ty_MIB:
165 return SrcMIB->getOperand(0).getReg();
167 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
170 CmpInst::Predicate getPredicate() const {
172 case SrcType::Ty_Predicate:
175 llvm_unreachable("Not a register operand");
179 SrcType getSrcOpKind() const { return Ty; }
186 Optional<unsigned> Flags;
189 explicit FlagsOp(unsigned F) : Flags(F) {}
190 FlagsOp() : Flags(None) {}
191 Optional<unsigned> getFlags() const { return Flags; }
193 /// Helper class to build MachineInstr.
194 /// It keeps internally the insertion point and debug location for all
195 /// the new instructions we want to create.
196 /// This information can be modify via the related setters.
197 class MachineIRBuilder {
199 MachineIRBuilderState State;
202 void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
204 void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
206 void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
208 void recordInsertion(MachineInstr *MI) const;
211 /// Some constructors for easy use.
212 MachineIRBuilder() = default;
213 MachineIRBuilder(MachineFunction &MF) { setMF(MF); }
214 MachineIRBuilder(MachineInstr &MI) : MachineIRBuilder(*MI.getMF()) {
218 virtual ~MachineIRBuilder() = default;
220 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
222 const TargetInstrInfo &getTII() {
223 assert(State.TII && "TargetInstrInfo is not set");
227 /// Getter for the function we currently build.
228 MachineFunction &getMF() {
229 assert(State.MF && "MachineFunction is not set");
233 /// Getter for DebugLoc
234 const DebugLoc &getDL() { return State.DL; }
237 MachineRegisterInfo *getMRI() { return State.MRI; }
238 const MachineRegisterInfo *getMRI() const { return State.MRI; }
240 /// Getter for the State
241 MachineIRBuilderState &getState() { return State; }
243 /// Getter for the basic block we currently build.
244 const MachineBasicBlock &getMBB() const {
245 assert(State.MBB && "MachineBasicBlock is not set");
249 MachineBasicBlock &getMBB() {
250 return const_cast<MachineBasicBlock &>(
251 const_cast<const MachineIRBuilder *>(this)->getMBB());
254 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
255 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
257 /// Current insertion point for new instructions.
258 MachineBasicBlock::iterator getInsertPt() { return State.II; }
260 /// Set the insertion point before the specified position.
261 /// \pre MBB must be in getMF().
262 /// \pre II must be a valid iterator in MBB.
263 void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II);
266 void setCSEInfo(GISelCSEInfo *Info);
268 /// \name Setters for the insertion point.
270 /// Set the MachineFunction where to build instructions.
271 void setMF(MachineFunction &MF);
273 /// Set the insertion point to the end of \p MBB.
274 /// \pre \p MBB must be contained by getMF().
275 void setMBB(MachineBasicBlock &MBB);
277 /// Set the insertion point to before MI.
278 /// \pre MI must be in getMF().
279 void setInstr(MachineInstr &MI);
282 void setChangeObserver(GISelChangeObserver &Observer);
283 void stopObservingChanges();
286 /// Set the debug location to \p DL for all the next build instructions.
287 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
289 /// Get the current instruction's debug location.
290 DebugLoc getDebugLoc() { return State.DL; }
292 /// Build and insert <empty> = \p Opcode <empty>.
293 /// The insertion point is the one set by the last call of either
294 /// setBasicBlock or setMI.
296 /// \pre setBasicBlock or setMI must have been called.
298 /// \return a MachineInstrBuilder for the newly created instruction.
299 MachineInstrBuilder buildInstr(unsigned Opcode);
301 /// Build but don't insert <empty> = \p Opcode <empty>.
303 /// \pre setMF, setBasicBlock or setMI must have been called.
305 /// \return a MachineInstrBuilder for the newly created instruction.
306 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
308 /// Insert an existing instruction at the insertion point.
309 MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
311 /// Build and insert a DBG_VALUE instruction expressing the fact that the
312 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
313 MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
316 /// Build and insert a DBG_VALUE instruction expressing the fact that the
317 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
319 MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
320 const MDNode *Variable,
323 /// Build and insert a DBG_VALUE instruction expressing the fact that the
324 /// associated \p Variable lives in the stack slot specified by \p FI
325 /// (suitably modified by \p Expr).
326 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
329 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
330 /// given by \p C (suitably modified by \p Expr).
331 MachineInstrBuilder buildConstDbgValue(const Constant &C,
332 const MDNode *Variable,
335 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
336 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
337 MachineInstrBuilder buildDbgLabel(const MDNode *Label);
339 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
341 /// G_FRAME_INDEX materializes the address of an alloca value or other
342 /// stack-based object.
344 /// \pre setBasicBlock or setMI must have been called.
345 /// \pre \p Res must be a generic virtual register with pointer type.
347 /// \return a MachineInstrBuilder for the newly created instruction.
348 MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
350 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
352 /// G_GLOBAL_VALUE materializes the address of the specified global
355 /// \pre setBasicBlock or setMI must have been called.
356 /// \pre \p Res must be a generic virtual register with pointer type
357 /// in the same address space as \p GV.
359 /// \return a MachineInstrBuilder for the newly created instruction.
360 MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
363 /// Build and insert \p Res = G_GEP \p Op0, \p Op1
365 /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
366 /// storing the resulting pointer in \p Res.
368 /// \pre setBasicBlock or setMI must have been called.
369 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
371 /// \pre \p Op1 must be a generic virtual register with scalar type.
373 /// \return a MachineInstrBuilder for the newly created instruction.
374 MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
377 /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
379 /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
380 /// storing the resulting pointer in \p Res. If \p Value is zero then no
381 /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
384 /// \pre setBasicBlock or setMI must have been called.
385 /// \pre \p Op0 must be a generic virtual register with pointer type.
386 /// \pre \p ValueTy must be a scalar type.
387 /// \pre \p Res must be 0. This is to detect confusion between
388 /// materializeGEP() and buildGEP().
389 /// \post \p Res will either be a new generic virtual register of the same
390 /// type as \p Op0 or \p Op0 itself.
392 /// \return a MachineInstrBuilder for the newly created instruction.
393 Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
397 /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
399 /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
400 /// pointer properties. This has the effect of rounding the address *down* to
401 /// a specified alignment in bits.
403 /// \pre setBasicBlock or setMI must have been called.
404 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
406 /// \pre \p NumBits must be an integer representing the number of low bits to
407 /// be cleared in \p Op0.
409 /// \return a MachineInstrBuilder for the newly created instruction.
410 MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
413 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
414 /// \p Op1, \p CarryIn
416 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
417 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
420 /// \pre setBasicBlock or setMI must have been called.
421 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
422 /// with the same scalar type.
423 /// \pre \p CarryOut and \p CarryIn must be generic virtual
424 /// registers with the same scalar type (typically s1)
426 /// \return The newly created instruction.
427 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
428 const SrcOp &Op0, const SrcOp &Op1,
429 const SrcOp &CarryIn);
431 /// Build and insert \p Res = G_ANYEXT \p Op0
433 /// G_ANYEXT produces a register of the specified width, with bits 0 to
434 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
435 /// (i.e. this is neither zero nor sign-extension). For a vector register,
436 /// each element is extended individually.
438 /// \pre setBasicBlock or setMI must have been called.
439 /// \pre \p Res must be a generic virtual register with scalar or vector type.
440 /// \pre \p Op must be a generic virtual register with scalar or vector type.
441 /// \pre \p Op must be smaller than \p Res
443 /// \return The newly created instruction.
445 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
447 /// Build and insert \p Res = G_SEXT \p Op
449 /// G_SEXT produces a register of the specified width, with bits 0 to
450 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
451 /// high bit of \p Op (i.e. 2s-complement sign extended).
453 /// \pre setBasicBlock or setMI must have been called.
454 /// \pre \p Res must be a generic virtual register with scalar or vector type.
455 /// \pre \p Op must be a generic virtual register with scalar or vector type.
456 /// \pre \p Op must be smaller than \p Res
458 /// \return The newly created instruction.
459 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
461 /// Build and insert \p Res = G_ZEXT \p Op
463 /// G_ZEXT produces a register of the specified width, with bits 0 to
464 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
465 /// register, each element is extended individually.
467 /// \pre setBasicBlock or setMI must have been called.
468 /// \pre \p Res must be a generic virtual register with scalar or vector type.
469 /// \pre \p Op must be a generic virtual register with scalar or vector type.
470 /// \pre \p Op must be smaller than \p Res
472 /// \return The newly created instruction.
473 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
475 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
476 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
478 /// \pre setBasicBlock or setMI must have been called.
479 /// \pre \p Res must be a generic virtual register with scalar or vector type.
480 /// \pre \p Op must be a generic virtual register with scalar or vector type.
482 /// \return The newly created instruction.
483 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
485 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
486 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
488 /// \pre setBasicBlock or setMI must have been called.
489 /// \pre \p Res must be a generic virtual register with scalar or vector type.
490 /// \pre \p Op must be a generic virtual register with scalar or vector type.
492 /// \return The newly created instruction.
493 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
495 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
496 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
498 /// \pre setBasicBlock or setMI must have been called.
499 /// \pre \p Res must be a generic virtual register with scalar or vector type.
500 /// \pre \p Op must be a generic virtual register with scalar or vector type.
502 /// \return The newly created instruction.
503 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
505 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
506 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
509 /// \pre setBasicBlock or setMI must have been called.
510 /// \pre \p Res must be a generic virtual register with scalar or vector type.
511 /// \pre \p Op must be a generic virtual register with scalar or vector type.
513 /// \return The newly created instruction.
514 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
517 /// Build and insert an appropriate cast between two registers of equal size.
518 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
520 /// Build and insert G_BR \p Dest
522 /// G_BR is an unconditional branch to \p Dest.
524 /// \pre setBasicBlock or setMI must have been called.
526 /// \return a MachineInstrBuilder for the newly created instruction.
527 MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
529 /// Build and insert G_BRCOND \p Tst, \p Dest
531 /// G_BRCOND is a conditional branch to \p Dest.
533 /// \pre setBasicBlock or setMI must have been called.
534 /// \pre \p Tst must be a generic virtual register with scalar
535 /// type. At the beginning of legalization, this will be a single
536 /// bit (s1). Targets with interesting flags registers may change
537 /// this. For a wider type, whether the branch is taken must only
538 /// depend on bit 0 (for now).
540 /// \return The newly created instruction.
541 MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
543 /// Build and insert G_BRINDIRECT \p Tgt
545 /// G_BRINDIRECT is an indirect branch to \p Tgt.
547 /// \pre setBasicBlock or setMI must have been called.
548 /// \pre \p Tgt must be a generic virtual register with pointer type.
550 /// \return a MachineInstrBuilder for the newly created instruction.
551 MachineInstrBuilder buildBrIndirect(unsigned Tgt);
553 /// Build and insert \p Res = G_CONSTANT \p Val
555 /// G_CONSTANT is an integer constant with the specified size and value. \p
556 /// Val will be extended or truncated to the size of \p Reg.
558 /// \pre setBasicBlock or setMI must have been called.
559 /// \pre \p Res must be a generic virtual register with scalar or pointer
562 /// \return The newly created instruction.
563 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
564 const ConstantInt &Val);
566 /// Build and insert \p Res = G_CONSTANT \p Val
568 /// G_CONSTANT is an integer constant with the specified size and value.
570 /// \pre setBasicBlock or setMI must have been called.
571 /// \pre \p Res must be a generic virtual register with scalar type.
573 /// \return The newly created instruction.
574 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
576 /// Build and insert \p Res = G_FCONSTANT \p Val
578 /// G_FCONSTANT is a floating-point constant with the specified size and
581 /// \pre setBasicBlock or setMI must have been called.
582 /// \pre \p Res must be a generic virtual register with scalar type.
584 /// \return The newly created instruction.
585 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
586 const ConstantFP &Val);
588 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
590 /// Build and insert \p Res = COPY Op
592 /// Register-to-register COPY sets \p Res to \p Op.
594 /// \pre setBasicBlock or setMI must have been called.
596 /// \return a MachineInstrBuilder for the newly created instruction.
597 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
599 /// Build and insert `Res = G_LOAD Addr, MMO`.
601 /// Loads the value stored at \p Addr. Puts the result in \p Res.
603 /// \pre setBasicBlock or setMI must have been called.
604 /// \pre \p Res must be a generic virtual register.
605 /// \pre \p Addr must be a generic virtual register with pointer type.
607 /// \return a MachineInstrBuilder for the newly created instruction.
608 MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
609 MachineMemOperand &MMO);
611 /// Build and insert `Res = <opcode> Addr, MMO`.
613 /// Loads the value stored at \p Addr. Puts the result in \p Res.
615 /// \pre setBasicBlock or setMI must have been called.
616 /// \pre \p Res must be a generic virtual register.
617 /// \pre \p Addr must be a generic virtual register with pointer type.
619 /// \return a MachineInstrBuilder for the newly created instruction.
620 MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
621 unsigned Addr, MachineMemOperand &MMO);
623 /// Build and insert `G_STORE Val, Addr, MMO`.
625 /// Stores the value \p Val to \p Addr.
627 /// \pre setBasicBlock or setMI must have been called.
628 /// \pre \p Val must be a generic virtual register.
629 /// \pre \p Addr must be a generic virtual register with pointer type.
631 /// \return a MachineInstrBuilder for the newly created instruction.
632 MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
633 MachineMemOperand &MMO);
635 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
637 /// \pre setBasicBlock or setMI must have been called.
638 /// \pre \p Res and \p Src must be generic virtual registers.
640 /// \return a MachineInstrBuilder for the newly created instruction.
641 MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index);
643 /// Build and insert \p Res = IMPLICIT_DEF.
644 MachineInstrBuilder buildUndef(const DstOp &Res);
646 /// Build and insert instructions to put \p Ops together at the specified p
647 /// Indices to form a larger register.
649 /// If the types of the input registers are uniform and cover the entirity of
650 /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
651 /// followed by a sequence of G_INSERT instructions.
653 /// \pre setBasicBlock or setMI must have been called.
654 /// \pre The final element of the sequence must not extend past the end of the
655 /// destination register.
656 /// \pre The bits defined by each Op (derived from index and scalar size) must
658 /// \pre \p Indices must be in ascending order of bit position.
659 void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
660 ArrayRef<uint64_t> Indices);
662 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
664 /// G_MERGE_VALUES combines the input elements contiguously into a larger
667 /// \pre setBasicBlock or setMI must have been called.
668 /// \pre The entire register \p Res (and no more) must be covered by the input
670 /// \pre The type of all \p Ops registers must be identical.
672 /// \return a MachineInstrBuilder for the newly created instruction.
673 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<unsigned> Ops);
675 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
677 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
679 /// \pre setBasicBlock or setMI must have been called.
680 /// \pre The entire register \p Res (and no more) must be covered by the input
682 /// \pre The type of all \p Res registers must be identical.
684 /// \return a MachineInstrBuilder for the newly created instruction.
685 MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
686 MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, const SrcOp &Op);
688 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
690 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
691 /// \pre setBasicBlock or setMI must have been called.
692 /// \pre The entire register \p Res (and no more) must be covered by the
693 /// input scalar registers.
694 /// \pre The type of all \p Ops registers must be identical.
696 /// \return a MachineInstrBuilder for the newly created instruction.
697 MachineInstrBuilder buildBuildVector(const DstOp &Res,
698 ArrayRef<unsigned> Ops);
700 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
702 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
703 /// which have types larger than the destination vector element type, and
704 /// truncates the values to fit.
706 /// If the operands given are already the same size as the vector elt type,
707 /// then this method will instead create a G_BUILD_VECTOR instruction.
709 /// \pre setBasicBlock or setMI must have been called.
710 /// \pre The type of all \p Ops registers must be identical.
712 /// \return a MachineInstrBuilder for the newly created instruction.
713 MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
714 ArrayRef<unsigned> Ops);
716 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
718 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
721 /// \pre setBasicBlock or setMI must have been called.
722 /// \pre The entire register \p Res (and no more) must be covered by the input
724 /// \pre The type of all source operands must be identical.
726 /// \return a MachineInstrBuilder for the newly created instruction.
727 MachineInstrBuilder buildConcatVectors(const DstOp &Res,
728 ArrayRef<unsigned> Ops);
730 MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
731 unsigned Op, unsigned Index);
733 /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
734 /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
735 /// result register definition unless \p Reg is NoReg (== 0). The second
736 /// operand will be the intrinsic's ID.
738 /// Callers are expected to add the required definitions and uses afterwards.
740 /// \pre setBasicBlock or setMI must have been called.
742 /// \return a MachineInstrBuilder for the newly created instruction.
743 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res,
744 bool HasSideEffects);
746 /// Build and insert \p Res = G_FPTRUNC \p Op
748 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
750 /// \pre setBasicBlock or setMI must have been called.
751 /// \pre \p Res must be a generic virtual register with scalar or vector type.
752 /// \pre \p Op must be a generic virtual register with scalar or vector type.
753 /// \pre \p Res must be smaller than \p Op
755 /// \return The newly created instruction.
756 MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
758 /// Build and insert \p Res = G_TRUNC \p Op
760 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
761 /// truncated independently before being packed into the destination.
763 /// \pre setBasicBlock or setMI must have been called.
764 /// \pre \p Res must be a generic virtual register with scalar or vector type.
765 /// \pre \p Op must be a generic virtual register with scalar or vector type.
766 /// \pre \p Res must be smaller than \p Op
768 /// \return The newly created instruction.
769 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
771 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
773 /// \pre setBasicBlock or setMI must have been called.
775 /// \pre \p Res must be a generic virtual register with scalar or
776 /// vector type. Typically this starts as s1 or <N x s1>.
777 /// \pre \p Op0 and Op1 must be generic virtual registers with the
778 /// same number of elements as \p Res. If \p Res is a scalar,
779 /// \p Op0 must be either a scalar or pointer.
780 /// \pre \p Pred must be an integer predicate.
782 /// \return a MachineInstrBuilder for the newly created instruction.
783 MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
784 const SrcOp &Op0, const SrcOp &Op1);
786 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
788 /// \pre setBasicBlock or setMI must have been called.
790 /// \pre \p Res must be a generic virtual register with scalar or
791 /// vector type. Typically this starts as s1 or <N x s1>.
792 /// \pre \p Op0 and Op1 must be generic virtual registers with the
793 /// same number of elements as \p Res (or scalar, if \p Res is
795 /// \pre \p Pred must be a floating-point predicate.
797 /// \return a MachineInstrBuilder for the newly created instruction.
798 MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
799 const SrcOp &Op0, const SrcOp &Op1);
801 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
803 /// \pre setBasicBlock or setMI must have been called.
804 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
805 /// with the same type.
806 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
807 /// vector type. If vector then it must have the same number of
808 /// elements as the other parameters.
810 /// \return a MachineInstrBuilder for the newly created instruction.
811 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
812 const SrcOp &Op0, const SrcOp &Op1);
814 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
817 /// \pre setBasicBlock or setMI must have been called.
818 /// \pre \p Res and \p Val must be a generic virtual register
819 // with the same vector type.
820 /// \pre \p Elt and \p Idx must be a generic virtual register
821 /// with scalar type.
823 /// \return The newly created instruction.
824 MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
829 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
831 /// \pre setBasicBlock or setMI must have been called.
832 /// \pre \p Res must be a generic virtual register with scalar type.
833 /// \pre \p Val must be a generic virtual register with vector type.
834 /// \pre \p Idx must be a generic virtual register with scalar type.
836 /// \return The newly created instruction.
837 MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
841 /// Build and insert `OldValRes<def>, SuccessRes<def> =
842 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
844 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
845 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
846 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
848 /// \pre setBasicBlock or setMI must have been called.
849 /// \pre \p OldValRes must be a generic virtual register of scalar type.
850 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
851 /// will be assigned 0 on failure and 1 on success.
852 /// \pre \p Addr must be a generic virtual register with pointer type.
853 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
854 /// registers of the same type.
856 /// \return a MachineInstrBuilder for the newly created instruction.
858 buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
859 unsigned Addr, unsigned CmpVal, unsigned NewVal,
860 MachineMemOperand &MMO);
862 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
865 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
866 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
869 /// \pre setBasicBlock or setMI must have been called.
870 /// \pre \p OldValRes must be a generic virtual register of scalar type.
871 /// \pre \p Addr must be a generic virtual register with pointer type.
872 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
873 /// registers of the same type.
875 /// \return a MachineInstrBuilder for the newly created instruction.
876 MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
877 unsigned CmpVal, unsigned NewVal,
878 MachineMemOperand &MMO);
880 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
882 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
883 /// original value from \p Addr in \p OldValRes. The modification is
884 /// determined by the opcode.
886 /// \pre setBasicBlock or setMI must have been called.
887 /// \pre \p OldValRes must be a generic virtual register.
888 /// \pre \p Addr must be a generic virtual register with pointer type.
889 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
892 /// \return a MachineInstrBuilder for the newly created instruction.
893 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
894 unsigned Addr, unsigned Val,
895 MachineMemOperand &MMO);
897 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
899 /// Atomically replace the value at \p Addr with \p Val. Puts the original
900 /// value from \p Addr in \p OldValRes.
902 /// \pre setBasicBlock or setMI must have been called.
903 /// \pre \p OldValRes must be a generic virtual register.
904 /// \pre \p Addr must be a generic virtual register with pointer type.
905 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
908 /// \return a MachineInstrBuilder for the newly created instruction.
909 MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
910 unsigned Val, MachineMemOperand &MMO);
912 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
914 /// Atomically replace the value at \p Addr with the addition of \p Val and
915 /// the original value. Puts the original value from \p Addr in \p OldValRes.
917 /// \pre setBasicBlock or setMI must have been called.
918 /// \pre \p OldValRes must be a generic virtual register.
919 /// \pre \p Addr must be a generic virtual register with pointer type.
920 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
923 /// \return a MachineInstrBuilder for the newly created instruction.
924 MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
925 unsigned Val, MachineMemOperand &MMO);
927 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
929 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
930 /// the original value. Puts the original value from \p Addr in \p OldValRes.
932 /// \pre setBasicBlock or setMI must have been called.
933 /// \pre \p OldValRes must be a generic virtual register.
934 /// \pre \p Addr must be a generic virtual register with pointer type.
935 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
938 /// \return a MachineInstrBuilder for the newly created instruction.
939 MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
940 unsigned Val, MachineMemOperand &MMO);
942 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
944 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
945 /// the original value. Puts the original value from \p Addr in \p OldValRes.
947 /// \pre setBasicBlock or setMI must have been called.
948 /// \pre \p OldValRes must be a generic virtual register.
949 /// \pre \p Addr must be a generic virtual register with pointer type.
950 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
953 /// \return a MachineInstrBuilder for the newly created instruction.
954 MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
955 unsigned Val, MachineMemOperand &MMO);
957 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
959 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
960 /// and the original value. Puts the original value from \p Addr in \p
963 /// \pre setBasicBlock or setMI must have been called.
964 /// \pre \p OldValRes must be a generic virtual register.
965 /// \pre \p Addr must be a generic virtual register with pointer type.
966 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
969 /// \return a MachineInstrBuilder for the newly created instruction.
970 MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
971 unsigned Val, MachineMemOperand &MMO);
973 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
975 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
976 /// the original value. Puts the original value from \p Addr in \p OldValRes.
978 /// \pre setBasicBlock or setMI must have been called.
979 /// \pre \p OldValRes must be a generic virtual register.
980 /// \pre \p Addr must be a generic virtual register with pointer type.
981 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
984 /// \return a MachineInstrBuilder for the newly created instruction.
985 MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
986 unsigned Val, MachineMemOperand &MMO);
988 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
990 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
991 /// the original value. Puts the original value from \p Addr in \p OldValRes.
993 /// \pre setBasicBlock or setMI must have been called.
994 /// \pre \p OldValRes must be a generic virtual register.
995 /// \pre \p Addr must be a generic virtual register with pointer type.
996 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
999 /// \return a MachineInstrBuilder for the newly created instruction.
1000 MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
1001 unsigned Val, MachineMemOperand &MMO);
1003 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1005 /// Atomically replace the value at \p Addr with the signed maximum of \p
1006 /// Val and the original value. Puts the original value from \p Addr in \p
1009 /// \pre setBasicBlock or setMI must have been called.
1010 /// \pre \p OldValRes must be a generic virtual register.
1011 /// \pre \p Addr must be a generic virtual register with pointer type.
1012 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1015 /// \return a MachineInstrBuilder for the newly created instruction.
1016 MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
1017 unsigned Val, MachineMemOperand &MMO);
1019 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1021 /// Atomically replace the value at \p Addr with the signed minimum of \p
1022 /// Val and the original value. Puts the original value from \p Addr in \p
1025 /// \pre setBasicBlock or setMI must have been called.
1026 /// \pre \p OldValRes must be a generic virtual register.
1027 /// \pre \p Addr must be a generic virtual register with pointer type.
1028 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1031 /// \return a MachineInstrBuilder for the newly created instruction.
1032 MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
1033 unsigned Val, MachineMemOperand &MMO);
1035 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1037 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1038 /// Val and the original value. Puts the original value from \p Addr in \p
1041 /// \pre setBasicBlock or setMI must have been called.
1042 /// \pre \p OldValRes must be a generic virtual register.
1043 /// \pre \p Addr must be a generic virtual register with pointer type.
1044 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1047 /// \return a MachineInstrBuilder for the newly created instruction.
1048 MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
1049 unsigned Val, MachineMemOperand &MMO);
1051 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1053 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1054 /// Val and the original value. Puts the original value from \p Addr in \p
1057 /// \pre setBasicBlock or setMI must have been called.
1058 /// \pre \p OldValRes must be a generic virtual register.
1059 /// \pre \p Addr must be a generic virtual register with pointer type.
1060 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1063 /// \return a MachineInstrBuilder for the newly created instruction.
1064 MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
1065 unsigned Val, MachineMemOperand &MMO);
1067 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1069 /// G_BLOCK_ADDR computes the address of a basic block.
1071 /// \pre setBasicBlock or setMI must have been called.
1072 /// \pre \p Res must be a generic virtual register of a pointer type.
1074 /// \return The newly created instruction.
1075 MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
1077 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1079 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1080 /// truncated to their width.
1082 /// \pre setBasicBlock or setMI must have been called.
1083 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1084 /// with the same (scalar or vector) type).
1086 /// \return a MachineInstrBuilder for the newly created instruction.
1088 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1090 Optional<unsigned> Flags = None) {
1091 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1094 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1096 /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1097 /// truncated to their width.
1099 /// \pre setBasicBlock or setMI must have been called.
1100 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1101 /// with the same (scalar or vector) type).
1103 /// \return a MachineInstrBuilder for the newly created instruction.
1105 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1107 Optional<unsigned> Flags = None) {
1108 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1111 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1113 /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1114 /// truncated to their width.
1116 /// \pre setBasicBlock or setMI must have been called.
1117 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1118 /// with the same (scalar or vector) type).
1120 /// \return a MachineInstrBuilder for the newly created instruction.
1121 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1123 Optional<unsigned> Flags = None) {
1124 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1127 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1129 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1132 /// \pre setBasicBlock or setMI must have been called.
1133 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1134 /// with the same (scalar or vector) type).
1136 /// \return a MachineInstrBuilder for the newly created instruction.
1138 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1139 const SrcOp &Src1) {
1140 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1143 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1145 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1148 /// \pre setBasicBlock or setMI must have been called.
1149 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1150 /// with the same (scalar or vector) type).
1152 /// \return a MachineInstrBuilder for the newly created instruction.
1153 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1154 const SrcOp &Src1) {
1155 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1158 virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1159 ArrayRef<SrcOp> SrcOps,
1160 Optional<unsigned> Flags = None);
1163 } // End namespace llvm.
1164 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H