1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file This file declares the API for the register bank info.
11 /// This API is responsible for handling the register banks.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
16 #define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/Hashing.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/iterator_range.h"
22 #include "llvm/Support/ErrorHandling.h"
24 #include <initializer_list>
30 class MachineRegisterInfo;
33 class TargetInstrInfo;
34 class TargetRegisterClass;
35 class TargetRegisterInfo;
37 /// Holds all the information related to register banks.
38 class RegisterBankInfo {
40 /// Helper struct that represents how a value is partially mapped
42 /// The StartIdx and Length represent what region of the orginal
43 /// value this partial mapping covers.
44 /// This can be represented as a Mask of contiguous bit starting
45 /// at StartIdx bit and spanning Length bits.
46 /// StartIdx is the number of bits from the less significant bits.
47 struct PartialMapping {
48 /// Number of bits at which this partial mapping starts in the
49 /// original value. The bits are counted from less significant
50 /// bits to most significant bits.
53 /// Length of this mapping in bits. This is how many bits this
54 /// partial mapping covers in the original value:
55 /// from StartIdx to StartIdx + Length -1.
58 /// Register bank where the partial value lives.
59 const RegisterBank *RegBank;
61 PartialMapping() = default;
63 /// Provide a shortcut for quickly building PartialMapping.
64 PartialMapping(unsigned StartIdx, unsigned Length,
65 const RegisterBank &RegBank)
66 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
68 /// \return the index of in the original value of the most
69 /// significant bit that this partial mapping covers.
70 unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
72 /// Print this partial mapping on dbgs() stream.
75 /// Print this partial mapping on \p OS;
76 void print(raw_ostream &OS) const;
78 /// Check that the Mask is compatible with the RegBank.
79 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
80 /// there is no way this mapping is valid.
82 /// \note This method does not check anything when assertions are disabled.
84 /// \return True is the check was successful.
88 /// Helper struct that represents how a value is mapped through
89 /// different register banks.
91 /// \note: So far we do not have any users of the complex mappings
92 /// (mappings with more than one partial mapping), but when we do,
93 /// we would have needed to duplicate partial mappings.
94 /// The alternative could be to use an array of pointers of partial
95 /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
99 /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
101 /// <2 x 32-bit> add into 2 x 32-bit add.
103 /// Currently the TableGen-like file would look like:
105 /// PartialMapping[] = {
106 /// /*32-bit add*/ {0, 32, GPR},
107 /// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x
108 /// /*<2x32-bit> vadd {0, 64, VPR}
109 /// }; // PartialMapping duplicated.
112 /// /*plain 32-bit add*/ {&PartialMapping[0], 1},
113 /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
114 /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
118 /// With the array of pointer, we would have:
120 /// PartialMapping[] = {
121 /// /*32-bit add*/ {0, 32, GPR},
122 /// /*<2x32-bit> vadd {0, 64, VPR}
123 /// }; // No more duplication.
126 /// /*AddBreakDown*/ &PartialMapping[0],
127 /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[0],
128 /// /*VAddBreakDown*/ &PartialMapping[1]
129 /// }; // Addresses of PartialMapping duplicated (smaller).
132 /// /*plain 32-bit add*/ {&BreakDowns[0], 1},
133 /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
134 /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
138 /// Given that a PartialMapping is actually small, the code size
139 /// impact is actually a degradation. Moreover the compile time will
140 /// be hit by the additional indirection.
141 /// If PartialMapping gets bigger we may reconsider.
142 struct ValueMapping {
143 /// How the value is broken down between the different register banks.
144 const PartialMapping *BreakDown;
146 /// Number of partial mapping to break down this value.
147 unsigned NumBreakDowns;
149 /// The default constructor creates an invalid (isValid() == false)
151 ValueMapping() : ValueMapping(nullptr, 0) {}
153 /// Initialize a ValueMapping with the given parameter.
154 /// \p BreakDown needs to have a life time at least as long
155 /// as this instance.
156 ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
157 : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {}
159 /// Iterators through the PartialMappings.
160 const PartialMapping *begin() const { return BreakDown; }
161 const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
163 /// Check if this ValueMapping is valid.
164 bool isValid() const { return BreakDown && NumBreakDowns; }
166 /// Verify that this mapping makes sense for a value of
167 /// \p MeaningfulBitWidth.
168 /// \note This method does not check anything when assertions are disabled.
170 /// \return True is the check was successful.
171 bool verify(unsigned MeaningfulBitWidth) const;
173 /// Print this on dbgs() stream.
176 /// Print this on \p OS;
177 void print(raw_ostream &OS) const;
180 /// Helper class that represents how the value of an instruction may be
181 /// mapped and what is the related cost of such mapping.
182 class InstructionMapping {
183 /// Identifier of the mapping.
184 /// This is used to communicate between the target and the optimizers
185 /// which mapping should be realized.
186 unsigned ID = InvalidMappingID;
188 /// Cost of this mapping.
191 /// Mapping of all the operands.
192 const ValueMapping *OperandsMapping;
194 /// Number of operands.
195 unsigned NumOperands = 0;
197 const ValueMapping &getOperandMapping(unsigned i) {
198 assert(i < getNumOperands() && "Out of bound operand");
199 return OperandsMapping[i];
203 /// Constructor for the mapping of an instruction.
204 /// \p NumOperands must be equal to number of all the operands of
205 /// the related instruction.
206 /// The rationale is that it is more efficient for the optimizers
207 /// to be able to assume that the mapping of the ith operand is
210 /// \pre ID != InvalidMappingID
211 InstructionMapping(unsigned ID, unsigned Cost,
212 const ValueMapping *OperandsMapping,
213 unsigned NumOperands)
214 : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
215 NumOperands(NumOperands) {
216 assert(getID() != InvalidMappingID &&
217 "Use the default constructor for invalid mapping");
220 /// Default constructor.
221 /// Use this constructor to express that the mapping is invalid.
222 InstructionMapping() = default;
225 unsigned getCost() const { return Cost; }
228 unsigned getID() const { return ID; }
230 /// Get the number of operands.
231 unsigned getNumOperands() const { return NumOperands; }
233 /// Get the value mapping of the ith operand.
234 /// \pre The mapping for the ith operand has been set.
235 /// \pre The ith operand is a register.
236 const ValueMapping &getOperandMapping(unsigned i) const {
237 const ValueMapping &ValMapping =
238 const_cast<InstructionMapping *>(this)->getOperandMapping(i);
242 /// Set the mapping for all the operands.
243 /// In other words, OpdsMapping should hold at least getNumOperands
245 void setOperandsMapping(const ValueMapping *OpdsMapping) {
246 OperandsMapping = OpdsMapping;
249 /// Check whether this object is valid.
250 /// This is a lightweight check for obvious wrong instance.
251 bool isValid() const {
252 return getID() != InvalidMappingID && OperandsMapping;
255 /// Verifiy that this mapping makes sense for \p MI.
256 /// \pre \p MI must be connected to a MachineFunction.
258 /// \note This method does not check anything when assertions are disabled.
260 /// \return True is the check was successful.
261 bool verify(const MachineInstr &MI) const;
263 /// Print this on dbgs() stream.
266 /// Print this on \p OS;
267 void print(raw_ostream &OS) const;
270 /// Convenient type to represent the alternatives for mapping an
272 /// \todo When we move to TableGen this should be an array ref.
273 using InstructionMappings = SmallVector<const InstructionMapping *, 4>;
275 /// Helper class used to get/create the virtual registers that will be used
276 /// to replace the MachineOperand when applying a mapping.
277 class OperandsMapper {
278 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
279 /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
280 /// Note: We use a SmallVector to avoid heap allocation for most cases.
281 SmallVector<int, 8> OpToNewVRegIdx;
283 /// Hold the registers that will be used to map MI with InstrMapping.
284 SmallVector<unsigned, 8> NewVRegs;
286 /// Current MachineRegisterInfo, used to create new virtual registers.
287 MachineRegisterInfo &MRI;
289 /// Instruction being remapped.
292 /// New mapping of the instruction.
293 const InstructionMapping &InstrMapping;
295 /// Constant value identifying that the index in OpToNewVRegIdx
296 /// for an operand has not been set yet.
297 static const int DontKnowIdx;
299 /// Get the range in NewVRegs to store all the partial
300 /// values for the \p OpIdx-th operand.
302 /// \return The iterator range for the space created.
304 /// \pre getMI().getOperand(OpIdx).isReg()
305 iterator_range<SmallVectorImpl<unsigned>::iterator>
306 getVRegsMem(unsigned OpIdx);
308 /// Get the end iterator for a range starting at \p StartIdx and
309 /// spannig \p NumVal in NewVRegs.
310 /// \pre StartIdx + NumVal <= NewVRegs.size()
311 SmallVectorImpl<unsigned>::const_iterator
312 getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
313 SmallVectorImpl<unsigned>::iterator getNewVRegsEnd(unsigned StartIdx,
317 /// Create an OperandsMapper that will hold the information to apply \p
318 /// InstrMapping to \p MI.
319 /// \pre InstrMapping.verify(MI)
320 OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
321 MachineRegisterInfo &MRI);
325 /// The MachineInstr being remapped.
326 MachineInstr &getMI() const { return MI; }
328 /// The final mapping of the instruction.
329 const InstructionMapping &getInstrMapping() const { return InstrMapping; }
331 /// The MachineRegisterInfo we used to realize the mapping.
332 MachineRegisterInfo &getMRI() const { return MRI; }
335 /// Create as many new virtual registers as needed for the mapping of the \p
336 /// OpIdx-th operand.
337 /// The number of registers is determined by the number of breakdown for the
338 /// related operand in the instruction mapping.
339 /// The type of the new registers is a plain scalar of the right size.
340 /// The proper type is expected to be set when the mapping is applied to
341 /// the instruction(s) that realizes the mapping.
343 /// \pre getMI().getOperand(OpIdx).isReg()
345 /// \post All the partial mapping of the \p OpIdx-th operand have been
346 /// assigned a new virtual register.
347 void createVRegs(unsigned OpIdx);
349 /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
350 /// the OpIdx-th operand to \p NewVReg.
352 /// \pre getMI().getOperand(OpIdx).isReg()
353 /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
357 /// \post the \p PartialMapIdx-th register of the value mapping of the \p
358 /// OpIdx-th operand has been set.
359 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg);
361 /// Get all the virtual registers required to map the \p OpIdx-th operand of
364 /// This return an empty range when createVRegs or setVRegs has not been
366 /// The iterator may be invalidated by a call to setVRegs or createVRegs.
368 /// When \p ForDebug is true, we will not check that the list of new virtual
369 /// registers does not contain uninitialized values.
371 /// \pre getMI().getOperand(OpIdx).isReg()
372 /// \pre ForDebug || All partial mappings have been set a register
373 iterator_range<SmallVectorImpl<unsigned>::const_iterator>
374 getVRegs(unsigned OpIdx, bool ForDebug = false) const;
376 /// Print this operands mapper on dbgs() stream.
379 /// Print this operands mapper on \p OS stream.
380 void print(raw_ostream &OS, bool ForDebug = false) const;
384 /// Hold the set of supported register banks.
385 RegisterBank **RegBanks;
387 /// Total number of register banks.
388 unsigned NumRegBanks;
390 /// Keep dynamically allocated PartialMapping in a separate map.
391 /// This shouldn't be needed when everything gets TableGen'ed.
392 mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>>
393 MapOfPartialMappings;
395 /// Keep dynamically allocated ValueMapping in a separate map.
396 /// This shouldn't be needed when everything gets TableGen'ed.
397 mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping>>
400 /// Keep dynamically allocated array of ValueMapping in a separate map.
401 /// This shouldn't be needed when everything gets TableGen'ed.
402 mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>>
403 MapOfOperandsMappings;
405 /// Keep dynamically allocated InstructionMapping in a separate map.
406 /// This shouldn't be needed when everything gets TableGen'ed.
407 mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>>
408 MapOfInstructionMappings;
410 /// Getting the minimal register class of a physreg is expensive.
411 /// Cache this information as we get it.
412 mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs;
414 /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
415 /// RegisterBank instances.
416 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
418 /// This constructor is meaningless.
419 /// It just provides a default constructor that can be used at link time
420 /// when GlobalISel is not built.
421 /// That way, targets can still inherit from this class without doing
422 /// crazy gymnastic to avoid link time failures.
423 /// \note That works because the constructor is inlined.
425 llvm_unreachable("This constructor should not be executed");
428 /// Get the register bank identified by \p ID.
429 RegisterBank &getRegBank(unsigned ID) {
430 assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
431 return *RegBanks[ID];
434 /// Get the MinimalPhysRegClass for Reg.
435 /// \pre Reg is a physical register.
436 const TargetRegisterClass &
437 getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const;
439 /// Try to get the mapping of \p MI.
440 /// See getInstrMapping for more details on what a mapping represents.
442 /// Unlike getInstrMapping the returned InstructionMapping may be invalid
443 /// (isValid() == false).
444 /// This means that the target independent code is not smart enough
445 /// to get the mapping of \p MI and thus, the target has to provide the
446 /// information for \p MI.
448 /// This implementation is able to get the mapping of:
449 /// - Target specific instructions by looking at the encoding constraints.
450 /// - Any instruction if all the register operands have already been assigned
451 /// a register, a register class, or a register bank.
452 /// - Copies and phis if at least one of the operands has been assigned a
453 /// register, a register class, or a register bank.
454 /// In other words, this method will likely fail to find a mapping for
455 /// any generic opcode that has not been lowered by target specific code.
456 const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
458 /// Get the uniquely generated PartialMapping for the
460 const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
461 const RegisterBank &RegBank) const;
463 /// \name Methods to get a uniquely generated ValueMapping.
466 /// The most common ValueMapping consists of a single PartialMapping.
467 /// Feature a method for that.
468 const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
469 const RegisterBank &RegBank) const;
471 /// Get the ValueMapping for the given arguments.
472 const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
473 unsigned NumBreakDowns) const;
476 /// \name Methods to get a uniquely generated array of ValueMapping.
479 /// Get the uniquely generated array of ValueMapping for the
480 /// elements of between \p Begin and \p End.
482 /// Elements that are nullptr will be replaced by
483 /// invalid ValueMapping (ValueMapping::isValid == false).
485 /// \pre The pointers on ValueMapping between \p Begin and \p End
486 /// must uniquely identify a ValueMapping. Otherwise, there is no
487 /// guarantee that the return instance will be unique, i.e., another
488 /// OperandsMapping could have the same content.
489 template <typename Iterator>
490 const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
492 /// Get the uniquely generated array of ValueMapping for the
493 /// elements of \p OpdsMapping.
495 /// Elements of \p OpdsMapping that are nullptr will be replaced by
496 /// invalid ValueMapping (ValueMapping::isValid == false).
497 const ValueMapping *getOperandsMapping(
498 const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
500 /// Get the uniquely generated array of ValueMapping for the
503 /// Arguments that are nullptr will be replaced by invalid
504 /// ValueMapping (ValueMapping::isValid == false).
505 const ValueMapping *getOperandsMapping(
506 std::initializer_list<const ValueMapping *> OpdsMapping) const;
509 /// \name Methods to get a uniquely generated InstructionMapping.
513 /// Method to get a uniquely generated InstructionMapping.
514 const InstructionMapping &
515 getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
517 const ValueMapping *OperandsMapping = nullptr,
518 unsigned NumOperands = 0) const;
521 /// Method to get a uniquely generated InstructionMapping.
522 const InstructionMapping &
523 getInstructionMapping(unsigned ID, unsigned Cost,
524 const ValueMapping *OperandsMapping,
525 unsigned NumOperands) const {
526 return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
527 OperandsMapping, NumOperands);
530 /// Method to get a uniquely generated invalid InstructionMapping.
531 const InstructionMapping &getInvalidInstructionMapping() const {
532 return getInstructionMappingImpl(/*IsInvalid*/ true);
536 /// Get the register bank for the \p OpIdx-th operand of \p MI form
537 /// the encoding constraints, if any.
539 /// \return A register bank that covers the register class of the
540 /// related encoding constraints or nullptr if \p MI did not provide
541 /// enough information to deduce it.
543 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
544 const TargetInstrInfo &TII,
545 const TargetRegisterInfo &TRI) const;
547 /// Helper method to apply something that is like the default mapping.
548 /// Basically, that means that \p OpdMapper.getMI() is left untouched
549 /// aside from the reassignment of the register operand that have been
552 /// The type of all the new registers that have been created by the
553 /// mapper are properly remapped to the type of the original registers
554 /// they replace. In other words, the semantic of the instruction does
555 /// not change, only the register banks.
557 /// If the mapping of one of the operand spans several registers, this
558 /// method will abort as this is not like a default mapping anymore.
560 /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
561 /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
562 static void applyDefaultMapping(const OperandsMapper &OpdMapper);
564 /// See ::applyMapping.
565 virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
566 llvm_unreachable("The target has to implement that part");
570 virtual ~RegisterBankInfo() = default;
572 /// Get the register bank identified by \p ID.
573 const RegisterBank &getRegBank(unsigned ID) const {
574 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
577 /// Get the register bank of \p Reg.
578 /// If Reg has not been assigned a register, a register class,
579 /// or a register bank, then this returns nullptr.
581 /// \pre Reg != 0 (NoRegister)
582 const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
583 const TargetRegisterInfo &TRI) const;
585 /// Get the total number of register banks.
586 unsigned getNumRegBanks() const { return NumRegBanks; }
588 /// Get a register bank that covers \p RC.
590 /// \pre \p RC is a user-defined register class (as opposed as one
591 /// generated by TableGen).
593 /// \note The mapping RC -> RegBank could be built while adding the
594 /// coverage for the register banks. However, we do not do it, because,
595 /// at least for now, we only need this information for register classes
596 /// that are used in the description of instruction. In other words,
597 /// there are just a handful of them and we do not want to waste space.
599 /// \todo This should be TableGen'ed.
600 virtual const RegisterBank &
601 getRegBankFromRegClass(const TargetRegisterClass &RC) const {
602 llvm_unreachable("The target must override this method");
605 /// Get the cost of a copy from \p B to \p A, or put differently,
606 /// get the cost of A = COPY B. Since register banks may cover
607 /// different size, \p Size specifies what will be the size in bits
608 /// that will be copied around.
610 /// \note Since this is a copy, both registers have the same size.
611 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
612 unsigned Size) const {
613 // Optimistically assume that copies are coalesced. I.e., when
614 // they are on the same bank, they are free.
615 // Otherwise assume a non-zero cost of 1. The targets are supposed
616 // to override that properly anyway if they care.
620 /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
622 /// \pre \p Reg is a virtual register that either has a bank or a class.
623 /// \returns The constrained register class, or nullptr if there is none.
624 /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
625 /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel
626 /// purpose, including non-select passes of GlobalISel
627 static const TargetRegisterClass *
628 constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC,
629 MachineRegisterInfo &MRI);
631 /// Identifier used when the related instruction mapping instance
632 /// is generated by target independent code.
633 /// Make sure not to use that identifier to avoid possible collision.
634 static const unsigned DefaultMappingID;
636 /// Identifier used when the related instruction mapping instance
637 /// is generated by the default constructor.
638 /// Make sure not to use that identifier.
639 static const unsigned InvalidMappingID;
641 /// Get the mapping of the different operands of \p MI
642 /// on the register bank.
643 /// This mapping should be the direct translation of \p MI.
644 /// In other words, when \p MI is mapped with the returned mapping,
645 /// only the register banks of the operands of \p MI need to be updated.
646 /// In particular, neither the opcode nor the type of \p MI needs to be
647 /// updated for this direct mapping.
649 /// The target independent implementation gives a mapping based on
650 /// the register classes for the target specific opcode.
651 /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
652 /// Make sure you do not use that ID for the alternative mapping
653 /// for MI. See getInstrAlternativeMappings for the alternative
656 /// For instance, if \p MI is a vector add, the mapping should
657 /// not be a scalarization of the add.
659 /// \post returnedVal.verify(MI).
661 /// \note If returnedVal does not verify MI, this would probably mean
662 /// that the target does not support that instruction.
663 virtual const InstructionMapping &
664 getInstrMapping(const MachineInstr &MI) const;
666 /// Get the alternative mappings for \p MI.
667 /// Alternative in the sense different from getInstrMapping.
668 virtual InstructionMappings
669 getInstrAlternativeMappings(const MachineInstr &MI) const;
671 /// Get the possible mapping for \p MI.
672 /// A mapping defines where the different operands may live and at what cost.
673 /// For instance, let us consider:
674 /// v0(16) = G_ADD <2 x i8> v1, v2
675 /// The possible mapping could be:
677 /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
678 /// /*v2*/{(0xFFFF, VPR)}}
679 /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
680 /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
681 /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
683 /// \note The first alternative of the returned mapping should be the
684 /// direct translation of \p MI current form.
686 /// \post !returnedVal.empty().
687 InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;
689 /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
690 /// After this call \p OpdMapper.getMI() may not be valid anymore.
691 /// \p OpdMapper.getInstrMapping().getID() carries the information of
692 /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
693 /// by the various getInstrXXXMapping method.
695 /// Therefore, getting the mapping and applying it should be kept in
697 void applyMapping(const OperandsMapper &OpdMapper) const {
698 // The only mapping we know how to handle is the default mapping.
699 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
700 return applyDefaultMapping(OpdMapper);
701 // For other mapping, the target needs to do the right thing.
702 // If that means calling applyDefaultMapping, fine, but this
703 // must be explicitly stated.
704 applyMappingImpl(OpdMapper);
707 /// Get the size in bits of \p Reg.
708 /// Utility method to get the size of any registers. Unlike
709 /// MachineRegisterInfo::getSize, the register does not need to be a
710 /// virtual register.
712 /// \pre \p Reg != 0 (NoRegister).
713 unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
714 const TargetRegisterInfo &TRI) const;
716 /// Check that information hold by this instance make sense for the
719 /// \note This method does not check anything when assertions are disabled.
721 /// \return True is the check was successful.
722 bool verify(const TargetRegisterInfo &TRI) const;
726 operator<<(raw_ostream &OS,
727 const RegisterBankInfo::PartialMapping &PartMapping) {
728 PartMapping.print(OS);
733 operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) {
734 ValMapping.print(OS);
739 operator<<(raw_ostream &OS,
740 const RegisterBankInfo::InstructionMapping &InstrMapping) {
741 InstrMapping.print(OS);
746 operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
747 OpdMapper.print(OS, /*ForDebug*/ false);
751 /// Hashing function for PartialMapping.
752 /// It is required for the hashing of ValueMapping.
753 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
755 } // end namespace llvm
757 #endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H