1 //==-- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ----------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file This file declares the API for the register bank info.
11 /// This API is responsible for handling the register banks.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
16 #define LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/Hashing.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
23 #include "llvm/CodeGen/MachineValueType.h" // For SimpleValueType.
24 #include "llvm/Support/ErrorHandling.h"
27 #include <memory> // For unique_ptr.
31 class MachineRegisterInfo;
32 class TargetInstrInfo;
33 class TargetRegisterInfo;
36 /// Holds all the information related to register banks.
37 class RegisterBankInfo {
39 /// Helper struct that represents how a value is partially mapped
41 /// The StartIdx and Length represent what region of the orginal
42 /// value this partial mapping covers.
43 /// This can be represented as a Mask of contiguous bit starting
44 /// at StartIdx bit and spanning Length bits.
45 /// StartIdx is the number of bits from the less significant bits.
46 struct PartialMapping {
47 /// Number of bits at which this partial mapping starts in the
48 /// original value. The bits are counted from less significant
49 /// bits to most significant bits.
51 /// Length of this mapping in bits. This is how many bits this
52 /// partial mapping covers in the original value:
53 /// from StartIdx to StartIdx + Length -1.
55 /// Register bank where the partial value lives.
56 const RegisterBank *RegBank;
58 PartialMapping() = default;
60 /// Provide a shortcut for quickly building PartialMapping.
61 PartialMapping(unsigned StartIdx, unsigned Length,
62 const RegisterBank &RegBank)
63 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
65 /// \return the index of in the original value of the most
66 /// significant bit that this partial mapping covers.
67 unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
69 /// Print this partial mapping on dbgs() stream.
72 /// Print this partial mapping on \p OS;
73 void print(raw_ostream &OS) const;
75 /// Check that the Mask is compatible with the RegBank.
76 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
77 /// there is no way this mapping is valid.
79 /// \note This method does not check anything when assertions are disabled.
81 /// \return True is the check was successful.
85 /// Helper struct that represents how a value is mapped through
86 /// different register banks.
88 /// \note: So far we do not have any users of the complex mappings
89 /// (mappings with more than one partial mapping), but when we do,
90 /// we would have needed to duplicate partial mappings.
91 /// The alternative could be to use an array of pointers of partial
92 /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
96 /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
98 /// <2 x 32-bit> add into 2 x 32-bit add.
100 /// Currently the TableGen-like file would look like:
102 /// PartialMapping[] = {
103 /// /*32-bit add*/ {0, 32, GPR},
104 /// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x
105 /// /*<2x32-bit> vadd {0, 64, VPR}
106 /// }; // PartialMapping duplicated.
109 /// /*plain 32-bit add*/ {&PartialMapping[0], 1},
110 /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
111 /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
115 /// With the array of pointer, we would have:
117 /// PartialMapping[] = {
118 /// /*32-bit add*/ {0, 32, GPR},
119 /// /*<2x32-bit> vadd {0, 64, VPR}
120 /// }; // No more duplication.
123 /// /*AddBreakDown*/ &PartialMapping[0],
124 /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[0],
125 /// /*VAddBreakDown*/ &PartialMapping[1]
126 /// }; // Addresses of PartialMapping duplicated (smaller).
129 /// /*plain 32-bit add*/ {&BreakDowns[0], 1},
130 /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
131 /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
135 /// Given that a PartialMapping is actually small, the code size
136 /// impact is actually a degradation. Moreover the compile time will
137 /// be hit by the additional indirection.
138 /// If PartialMapping gets bigger we may reconsider.
139 struct ValueMapping {
140 /// How the value is broken down between the different register banks.
141 const PartialMapping *BreakDown;
143 /// Number of partial mapping to break down this value.
144 unsigned NumBreakDowns;
146 /// The default constructor creates an invalid (isValid() == false)
148 ValueMapping() : ValueMapping(nullptr, 0) {}
150 /// Initialize a ValueMapping with the given parameter.
151 /// \p BreakDown needs to have a life time at least as long
152 /// as this instance.
153 ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
154 : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {}
156 /// Iterators through the PartialMappings.
157 const PartialMapping *begin() const { return BreakDown; }
158 const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
160 /// Check if this ValueMapping is valid.
161 bool isValid() const { return BreakDown && NumBreakDowns; }
163 /// Verify that this mapping makes sense for a value of
164 /// \p MeaningfulBitWidth.
165 /// \note This method does not check anything when assertions are disabled.
167 /// \return True is the check was successful.
168 bool verify(unsigned MeaningfulBitWidth) const;
170 /// Print this on dbgs() stream.
173 /// Print this on \p OS;
174 void print(raw_ostream &OS) const;
177 /// Helper class that represents how the value of an instruction may be
178 /// mapped and what is the related cost of such mapping.
179 class InstructionMapping {
180 /// Identifier of the mapping.
181 /// This is used to communicate between the target and the optimizers
182 /// which mapping should be realized.
184 /// Cost of this mapping.
186 /// Mapping of all the operands.
187 const ValueMapping *OperandsMapping;
188 /// Number of operands.
189 unsigned NumOperands;
191 const ValueMapping &getOperandMapping(unsigned i) {
192 assert(i < getNumOperands() && "Out of bound operand");
193 return OperandsMapping[i];
197 /// Constructor for the mapping of an instruction.
198 /// \p NumOperands must be equal to number of all the operands of
199 /// the related instruction.
200 /// The rationale is that it is more efficient for the optimizers
201 /// to be able to assume that the mapping of the ith operand is
204 /// \pre ID != InvalidMappingID
205 InstructionMapping(unsigned ID, unsigned Cost,
206 const ValueMapping *OperandsMapping,
207 unsigned NumOperands)
208 : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
209 NumOperands(NumOperands) {
210 assert(getID() != InvalidMappingID &&
211 "Use the default constructor for invalid mapping");
214 /// Default constructor.
215 /// Use this constructor to express that the mapping is invalid.
216 InstructionMapping() : ID(InvalidMappingID), Cost(0), NumOperands(0) {}
219 unsigned getCost() const { return Cost; }
222 unsigned getID() const { return ID; }
224 /// Get the number of operands.
225 unsigned getNumOperands() const { return NumOperands; }
227 /// Get the value mapping of the ith operand.
228 /// \pre The mapping for the ith operand has been set.
229 /// \pre The ith operand is a register.
230 const ValueMapping &getOperandMapping(unsigned i) const {
231 const ValueMapping &ValMapping =
232 const_cast<InstructionMapping *>(this)->getOperandMapping(i);
236 /// Set the mapping for all the operands.
237 /// In other words, OpdsMapping should hold at least getNumOperands
239 void setOperandsMapping(const ValueMapping *OpdsMapping) {
240 OperandsMapping = OpdsMapping;
243 /// Check whether this object is valid.
244 /// This is a lightweight check for obvious wrong instance.
245 bool isValid() const {
246 return getID() != InvalidMappingID && OperandsMapping;
249 /// Verifiy that this mapping makes sense for \p MI.
250 /// \pre \p MI must be connected to a MachineFunction.
252 /// \note This method does not check anything when assertions are disabled.
254 /// \return True is the check was successful.
255 bool verify(const MachineInstr &MI) const;
257 /// Print this on dbgs() stream.
260 /// Print this on \p OS;
261 void print(raw_ostream &OS) const;
264 /// Convenient type to represent the alternatives for mapping an
266 /// \todo When we move to TableGen this should be an array ref.
267 typedef SmallVector<InstructionMapping, 4> InstructionMappings;
269 /// Helper class used to get/create the virtual registers that will be used
270 /// to replace the MachineOperand when applying a mapping.
271 class OperandsMapper {
272 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
273 /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
274 /// Note: We use a SmallVector to avoid heap allocation for most cases.
275 SmallVector<int, 8> OpToNewVRegIdx;
276 /// Hold the registers that will be used to map MI with InstrMapping.
277 SmallVector<unsigned, 8> NewVRegs;
278 /// Current MachineRegisterInfo, used to create new virtual registers.
279 MachineRegisterInfo &MRI;
280 /// Instruction being remapped.
282 /// New mapping of the instruction.
283 const InstructionMapping &InstrMapping;
285 /// Constant value identifying that the index in OpToNewVRegIdx
286 /// for an operand has not been set yet.
287 static const int DontKnowIdx;
289 /// Get the range in NewVRegs to store all the partial
290 /// values for the \p OpIdx-th operand.
292 /// \return The iterator range for the space created.
294 /// \pre getMI().getOperand(OpIdx).isReg()
295 iterator_range<SmallVectorImpl<unsigned>::iterator>
296 getVRegsMem(unsigned OpIdx);
298 /// Get the end iterator for a range starting at \p StartIdx and
299 /// spannig \p NumVal in NewVRegs.
300 /// \pre StartIdx + NumVal <= NewVRegs.size()
301 SmallVectorImpl<unsigned>::const_iterator
302 getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
303 SmallVectorImpl<unsigned>::iterator getNewVRegsEnd(unsigned StartIdx,
307 /// Create an OperandsMapper that will hold the information to apply \p
308 /// InstrMapping to \p MI.
309 /// \pre InstrMapping.verify(MI)
310 OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
311 MachineRegisterInfo &MRI);
315 /// The MachineInstr being remapped.
316 MachineInstr &getMI() const { return MI; }
318 /// The final mapping of the instruction.
319 const InstructionMapping &getInstrMapping() const { return InstrMapping; }
322 /// Create as many new virtual registers as needed for the mapping of the \p
323 /// OpIdx-th operand.
324 /// The number of registers is determined by the number of breakdown for the
325 /// related operand in the instruction mapping.
327 /// \pre getMI().getOperand(OpIdx).isReg()
329 /// \post All the partial mapping of the \p OpIdx-th operand have been
330 /// assigned a new virtual register.
331 void createVRegs(unsigned OpIdx);
333 /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
334 /// the OpIdx-th operand to \p NewVReg.
336 /// \pre getMI().getOperand(OpIdx).isReg()
337 /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
341 /// \post the \p PartialMapIdx-th register of the value mapping of the \p
342 /// OpIdx-th operand has been set.
343 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg);
345 /// Get all the virtual registers required to map the \p OpIdx-th operand of
348 /// This return an empty range when createVRegs or setVRegs has not been
350 /// The iterator may be invalidated by a call to setVRegs or createVRegs.
352 /// When \p ForDebug is true, we will not check that the list of new virtual
353 /// registers does not contain uninitialized values.
355 /// \pre getMI().getOperand(OpIdx).isReg()
356 /// \pre ForDebug || All partial mappings have been set a register
357 iterator_range<SmallVectorImpl<unsigned>::const_iterator>
358 getVRegs(unsigned OpIdx, bool ForDebug = false) const;
360 /// Print this operands mapper on dbgs() stream.
363 /// Print this operands mapper on \p OS stream.
364 void print(raw_ostream &OS, bool ForDebug = false) const;
368 /// Hold the set of supported register banks.
369 RegisterBank **RegBanks;
370 /// Total number of register banks.
371 unsigned NumRegBanks;
373 /// Keep dynamically allocated PartialMapping in a separate map.
374 /// This shouldn't be needed when everything gets TableGen'ed.
375 mutable DenseMap<unsigned, const PartialMapping *> MapOfPartialMappings;
377 /// Keep dynamically allocated ValueMapping in a separate map.
378 /// This shouldn't be needed when everything gets TableGen'ed.
379 mutable DenseMap<unsigned, const ValueMapping *> MapOfValueMappings;
381 /// Keep dynamically allocated array of ValueMapping in a separate map.
382 /// This shouldn't be needed when everything gets TableGen'ed.
383 mutable DenseMap<unsigned, ValueMapping *> MapOfOperandsMappings;
385 /// Create a RegisterBankInfo that can accomodate up to \p NumRegBanks
386 /// RegisterBank instances.
388 /// \note For the verify method to succeed all the \p NumRegBanks
389 /// must be initialized by createRegisterBank and updated with
390 /// addRegBankCoverage RegisterBank.
391 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
393 /// This constructor is meaningless.
394 /// It just provides a default constructor that can be used at link time
395 /// when GlobalISel is not built.
396 /// That way, targets can still inherit from this class without doing
397 /// crazy gymnastic to avoid link time failures.
398 /// \note That works because the constructor is inlined.
400 llvm_unreachable("This constructor should not be executed");
403 /// Create a new register bank with the given parameter and add it
405 /// \pre \p ID must not already be used.
406 /// \pre \p ID < NumRegBanks.
407 void createRegisterBank(unsigned ID, const char *Name);
409 /// Add \p RCId to the set of register class that the register bank,
410 /// identified \p ID, covers.
411 /// This method transitively adds all the sub classes and the subreg-classes
412 /// of \p RCId to the set of covered register classes.
413 /// It also adjusts the size of the register bank to reflect the maximal
414 /// size of a value that can be hold into that register bank.
416 /// \note This method does *not* add the super classes of \p RCId.
417 /// The rationale is if \p ID covers the registers of \p RCId, that
418 /// does not necessarily mean that \p ID covers the set of registers
419 /// of RCId's superclasses.
420 /// This method does *not* add the superreg classes as well for consistents.
421 /// The expected use is to add the coverage top-down with respect to the
422 /// register hierarchy.
424 /// \todo TableGen should just generate the BitSet vector for us.
425 void addRegBankCoverage(unsigned ID, unsigned RCId,
426 const TargetRegisterInfo &TRI);
428 /// Get the register bank identified by \p ID.
429 RegisterBank &getRegBank(unsigned ID) {
430 assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
431 return *RegBanks[ID];
434 /// Try to get the mapping of \p MI.
435 /// See getInstrMapping for more details on what a mapping represents.
437 /// Unlike getInstrMapping the returned InstructionMapping may be invalid
438 /// (isValid() == false).
439 /// This means that the target independent code is not smart enough
440 /// to get the mapping of \p MI and thus, the target has to provide the
441 /// information for \p MI.
443 /// This implementation is able to get the mapping of:
444 /// - Target specific instructions by looking at the encoding constraints.
445 /// - Any instruction if all the register operands have already been assigned
446 /// a register, a register class, or a register bank.
447 /// - Copies and phis if at least one of the operands has been assigned a
448 /// register, a register class, or a register bank.
449 /// In other words, this method will likely fail to find a mapping for
450 /// any generic opcode that has not been lowered by target specific code.
451 InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const;
453 /// Get the uniquely generated PartialMapping for the
455 const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
456 const RegisterBank &RegBank) const;
458 /// Methods to get a uniquely generated ValueMapping.
461 /// The most common ValueMapping consists of a single PartialMapping.
462 /// Feature a method for that.
463 const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
464 const RegisterBank &RegBank) const;
466 /// Get the ValueMapping for the given arguments.
467 const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
468 unsigned NumBreakDowns) const;
471 /// Methods to get a uniquely generated array of ValueMapping.
474 /// Get the uniquely generated array of ValueMapping for the
475 /// elements of between \p Begin and \p End.
477 /// Elements that are nullptr will be replaced by
478 /// invalid ValueMapping (ValueMapping::isValid == false).
480 /// \pre The pointers on ValueMapping between \p Begin and \p End
481 /// must uniquely identify a ValueMapping. Otherwise, there is no
482 /// guarantee that the return instance will be unique, i.e., another
483 /// OperandsMapping could have the same content.
484 template <typename Iterator>
485 const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
487 /// Get the uniquely generated array of ValueMapping for the
488 /// elements of \p OpdsMapping.
490 /// Elements of \p OpdsMapping that are nullptr will be replaced by
491 /// invalid ValueMapping (ValueMapping::isValid == false).
492 const ValueMapping *getOperandsMapping(
493 const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
495 /// Get the uniquely generated array of ValueMapping for the
498 /// Arguments that are nullptr will be replaced by invalid
499 /// ValueMapping (ValueMapping::isValid == false).
500 const ValueMapping *getOperandsMapping(
501 std::initializer_list<const ValueMapping *> OpdsMapping) const;
504 /// Get the register bank for the \p OpIdx-th operand of \p MI form
505 /// the encoding constraints, if any.
507 /// \return A register bank that covers the register class of the
508 /// related encoding constraints or nullptr if \p MI did not provide
509 /// enough information to deduce it.
511 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
512 const TargetInstrInfo &TII,
513 const TargetRegisterInfo &TRI) const;
515 /// Helper method to apply something that is like the default mapping.
516 /// Basically, that means that \p OpdMapper.getMI() is left untouched
517 /// aside from the reassignment of the register operand that have been
519 /// If the mapping of one of the operand spans several registers, this
520 /// method will abort as this is not like a default mapping anymore.
522 /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
523 /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
524 static void applyDefaultMapping(const OperandsMapper &OpdMapper);
526 /// See ::applyMapping.
527 virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
528 llvm_unreachable("The target has to implement that part");
532 virtual ~RegisterBankInfo();
534 /// Get the register bank identified by \p ID.
535 const RegisterBank &getRegBank(unsigned ID) const {
536 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
539 /// Get the register bank of \p Reg.
540 /// If Reg has not been assigned a register, a register class,
541 /// or a register bank, then this returns nullptr.
543 /// \pre Reg != 0 (NoRegister)
544 const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
545 const TargetRegisterInfo &TRI) const;
547 /// Get the total number of register banks.
548 unsigned getNumRegBanks() const { return NumRegBanks; }
550 /// Get a register bank that covers \p RC.
552 /// \pre \p RC is a user-defined register class (as opposed as one
553 /// generated by TableGen).
555 /// \note The mapping RC -> RegBank could be built while adding the
556 /// coverage for the register banks. However, we do not do it, because,
557 /// at least for now, we only need this information for register classes
558 /// that are used in the description of instruction. In other words,
559 /// there are just a handful of them and we do not want to waste space.
561 /// \todo This should be TableGen'ed.
562 virtual const RegisterBank &
563 getRegBankFromRegClass(const TargetRegisterClass &RC) const {
564 llvm_unreachable("The target must override this method");
567 /// Get the cost of a copy from \p B to \p A, or put differently,
568 /// get the cost of A = COPY B. Since register banks may cover
569 /// different size, \p Size specifies what will be the size in bits
570 /// that will be copied around.
572 /// \note Since this is a copy, both registers have the same size.
573 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
574 unsigned Size) const {
575 // Optimistically assume that copies are coalesced. I.e., when
576 // they are on the same bank, they are free.
577 // Otherwise assume a non-zero cost of 1. The targets are supposed
578 // to override that properly anyway if they care.
582 /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
584 /// \pre \p Reg is a virtual register that either has a bank or a class.
585 /// \returns The constrained register class, or nullptr if there is none.
586 /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
587 static const TargetRegisterClass *
588 constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC,
589 MachineRegisterInfo &MRI);
591 /// Identifier used when the related instruction mapping instance
592 /// is generated by target independent code.
593 /// Make sure not to use that identifier to avoid possible collision.
594 static const unsigned DefaultMappingID;
596 /// Identifier used when the related instruction mapping instance
597 /// is generated by the default constructor.
598 /// Make sure not to use that identifier.
599 static const unsigned InvalidMappingID;
601 /// Get the mapping of the different operands of \p MI
602 /// on the register bank.
603 /// This mapping should be the direct translation of \p MI.
604 /// In other words, when \p MI is mapped with the returned mapping,
605 /// only the register banks of the operands of \p MI need to be updated.
606 /// In particular, neither the opcode nor the type of \p MI needs to be
607 /// updated for this direct mapping.
609 /// The target independent implementation gives a mapping based on
610 /// the register classes for the target specific opcode.
611 /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
612 /// Make sure you do not use that ID for the alternative mapping
613 /// for MI. See getInstrAlternativeMappings for the alternative
616 /// For instance, if \p MI is a vector add, the mapping should
617 /// not be a scalarization of the add.
619 /// \post returnedVal.verify(MI).
621 /// \note If returnedVal does not verify MI, this would probably mean
622 /// that the target does not support that instruction.
623 virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const;
625 /// Get the alternative mappings for \p MI.
626 /// Alternative in the sense different from getInstrMapping.
627 virtual InstructionMappings
628 getInstrAlternativeMappings(const MachineInstr &MI) const;
630 /// Get the possible mapping for \p MI.
631 /// A mapping defines where the different operands may live and at what cost.
632 /// For instance, let us consider:
633 /// v0(16) = G_ADD <2 x i8> v1, v2
634 /// The possible mapping could be:
636 /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
637 /// /*v2*/{(0xFFFF, VPR)}}
638 /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
639 /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
640 /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
642 /// \note The first alternative of the returned mapping should be the
643 /// direct translation of \p MI current form.
645 /// \post !returnedVal.empty().
646 InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;
648 /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
649 /// After this call \p OpdMapper.getMI() may not be valid anymore.
650 /// \p OpdMapper.getInstrMapping().getID() carries the information of
651 /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
652 /// by the various getInstrXXXMapping method.
654 /// Therefore, getting the mapping and applying it should be kept in
656 void applyMapping(const OperandsMapper &OpdMapper) const {
657 // The only mapping we know how to handle is the default mapping.
658 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
659 return applyDefaultMapping(OpdMapper);
660 // For other mapping, the target needs to do the right thing.
661 // If that means calling applyDefaultMapping, fine, but this
662 // must be explicitly stated.
663 applyMappingImpl(OpdMapper);
666 /// Get the size in bits of \p Reg.
667 /// Utility method to get the size of any registers. Unlike
668 /// MachineRegisterInfo::getSize, the register does not need to be a
669 /// virtual register.
671 /// \pre \p Reg != 0 (NoRegister).
672 static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
673 const TargetRegisterInfo &TRI);
675 /// Check that information hold by this instance make sense for the
678 /// \note This method does not check anything when assertions are disabled.
680 /// \return True is the check was successful.
681 bool verify(const TargetRegisterInfo &TRI) const;
685 operator<<(raw_ostream &OS,
686 const RegisterBankInfo::PartialMapping &PartMapping) {
687 PartMapping.print(OS);
692 operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) {
693 ValMapping.print(OS);
698 operator<<(raw_ostream &OS,
699 const RegisterBankInfo::InstructionMapping &InstrMapping) {
700 InstrMapping.print(OS);
705 operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
706 OpdMapper.print(OS, /*ForDebug*/ false);
710 /// Hashing function for PartialMapping.
711 /// It is required for the hashing of ValueMapping.
712 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
713 } // End namespace llvm.