1 //==-- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ----------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file This file declares the API for the register bank info.
11 /// This API is responsible for handling the register banks.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
16 #define LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/Hashing.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
23 #include "llvm/CodeGen/MachineValueType.h" // For SimpleValueType.
24 #include "llvm/Support/ErrorHandling.h"
27 #include <memory> // For unique_ptr.
31 class MachineRegisterInfo;
32 class TargetInstrInfo;
33 class TargetRegisterInfo;
36 /// Holds all the information related to register banks.
37 class RegisterBankInfo {
39 /// Helper struct that represents how a value is partially mapped
41 /// The StartIdx and Length represent what region of the orginal
42 /// value this partial mapping covers.
43 /// This can be represented as a Mask of contiguous bit starting
44 /// at StartIdx bit and spanning Length bits.
45 /// StartIdx is the number of bits from the less significant bits.
46 struct PartialMapping {
47 /// Number of bits at which this partial mapping starts in the
48 /// original value. The bits are counted from less significant
49 /// bits to most significant bits.
51 /// Length of this mapping in bits. This is how many bits this
52 /// partial mapping covers in the original value:
53 /// from StartIdx to StartIdx + Length -1.
55 /// Register bank where the partial value lives.
56 const RegisterBank *RegBank;
58 PartialMapping() = default;
60 /// Provide a shortcut for quickly building PartialMapping.
61 PartialMapping(unsigned StartIdx, unsigned Length,
62 const RegisterBank &RegBank)
63 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
65 /// \return the index of in the original value of the most
66 /// significant bit that this partial mapping covers.
67 unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
69 /// Print this partial mapping on dbgs() stream.
72 /// Print this partial mapping on \p OS;
73 void print(raw_ostream &OS) const;
75 /// Check that the Mask is compatible with the RegBank.
76 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
77 /// there is no way this mapping is valid.
79 /// \note This method does not check anything when assertions are disabled.
81 /// \return True is the check was successful.
85 /// Helper struct that represents how a value is mapped through
86 /// different register banks.
88 /// \note: So far we do not have any users of the complex mappings
89 /// (mappings with more than one partial mapping), but when we do,
90 /// we would have needed to duplicate partial mappings.
91 /// The alternative could be to use an array of pointers of partial
92 /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
96 /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
98 /// <2 x 32-bit> add into 2 x 32-bit add.
100 /// Currently the TableGen-like file would look like:
102 /// PartialMapping[] = {
103 /// /*32-bit add*/ {0, 32, GPR},
104 /// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x
105 /// /*<2x32-bit> vadd {0, 64, VPR}
106 /// }; // PartialMapping duplicated.
109 /// /*plain 32-bit add*/ {&PartialMapping[0], 1},
110 /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
111 /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
115 /// With the array of pointer, we would have:
117 /// PartialMapping[] = {
118 /// /*32-bit add*/ {0, 32, GPR},
119 /// /*<2x32-bit> vadd {0, 64, VPR}
120 /// }; // No more duplication.
123 /// /*AddBreakDown*/ &PartialMapping[0],
124 /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[0],
125 /// /*VAddBreakDown*/ &PartialMapping[1]
126 /// }; // Addresses of PartialMapping duplicated (smaller).
129 /// /*plain 32-bit add*/ {&BreakDowns[0], 1},
130 /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
131 /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
135 /// Given that a PartialMapping is actually small, the code size
136 /// impact is actually a degradation. Moreover the compile time will
137 /// be hit by the additional indirection.
138 /// If PartialMapping gets bigger we may reconsider.
139 struct ValueMapping {
140 /// How the value is broken down between the different register banks.
141 const PartialMapping *BreakDown;
143 /// Number of partial mapping to break down this value.
144 unsigned NumBreakDowns;
146 /// The default constructor creates an invalid (isValid() == false)
148 ValueMapping() : ValueMapping(nullptr, 0) {}
150 /// Initialize a ValueMapping with the given parameter.
151 /// \p BreakDown needs to have a life time at least as long
152 /// as this instance.
153 ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
154 : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {}
156 /// Iterators through the PartialMappings.
157 const PartialMapping *begin() const { return BreakDown; }
158 const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
160 /// Check if this ValueMapping is valid.
161 bool isValid() const { return BreakDown && NumBreakDowns; }
163 /// Verify that this mapping makes sense for a value of
164 /// \p MeaningfulBitWidth.
165 /// \note This method does not check anything when assertions are disabled.
167 /// \return True is the check was successful.
168 bool verify(unsigned MeaningfulBitWidth) const;
170 /// Print this on dbgs() stream.
173 /// Print this on \p OS;
174 void print(raw_ostream &OS) const;
177 /// Helper class that represents how the value of an instruction may be
178 /// mapped and what is the related cost of such mapping.
179 class InstructionMapping {
180 /// Identifier of the mapping.
181 /// This is used to communicate between the target and the optimizers
182 /// which mapping should be realized.
184 /// Cost of this mapping.
186 /// Mapping of all the operands.
187 const ValueMapping *OperandsMapping;
188 /// Number of operands.
189 unsigned NumOperands;
191 const ValueMapping &getOperandMapping(unsigned i) {
192 assert(i < getNumOperands() && "Out of bound operand");
193 return OperandsMapping[i];
197 /// Constructor for the mapping of an instruction.
198 /// \p NumOperands must be equal to number of all the operands of
199 /// the related instruction.
200 /// The rationale is that it is more efficient for the optimizers
201 /// to be able to assume that the mapping of the ith operand is
204 /// \pre ID != InvalidMappingID
205 InstructionMapping(unsigned ID, unsigned Cost,
206 const ValueMapping *OperandsMapping,
207 unsigned NumOperands)
208 : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
209 NumOperands(NumOperands) {
210 assert(getID() != InvalidMappingID &&
211 "Use the default constructor for invalid mapping");
214 /// Default constructor.
215 /// Use this constructor to express that the mapping is invalid.
216 InstructionMapping() : ID(InvalidMappingID), Cost(0), NumOperands(0) {}
219 unsigned getCost() const { return Cost; }
222 unsigned getID() const { return ID; }
224 /// Get the number of operands.
225 unsigned getNumOperands() const { return NumOperands; }
227 /// Get the value mapping of the ith operand.
228 /// \pre The mapping for the ith operand has been set.
229 /// \pre The ith operand is a register.
230 const ValueMapping &getOperandMapping(unsigned i) const {
231 const ValueMapping &ValMapping =
232 const_cast<InstructionMapping *>(this)->getOperandMapping(i);
236 /// Set the mapping for all the operands.
237 /// In other words, OpdsMapping should hold at least getNumOperands
239 void setOperandsMapping(const ValueMapping *OpdsMapping) {
240 OperandsMapping = OpdsMapping;
243 /// Check whether this object is valid.
244 /// This is a lightweight check for obvious wrong instance.
245 bool isValid() const {
246 return getID() != InvalidMappingID && OperandsMapping;
249 /// Verifiy that this mapping makes sense for \p MI.
250 /// \pre \p MI must be connected to a MachineFunction.
252 /// \note This method does not check anything when assertions are disabled.
254 /// \return True is the check was successful.
255 bool verify(const MachineInstr &MI) const;
257 /// Print this on dbgs() stream.
260 /// Print this on \p OS;
261 void print(raw_ostream &OS) const;
264 /// Convenient type to represent the alternatives for mapping an
266 /// \todo When we move to TableGen this should be an array ref.
267 typedef SmallVector<InstructionMapping, 4> InstructionMappings;
269 /// Helper class used to get/create the virtual registers that will be used
270 /// to replace the MachineOperand when applying a mapping.
271 class OperandsMapper {
272 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
273 /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
274 /// Note: We use a SmallVector to avoid heap allocation for most cases.
275 SmallVector<int, 8> OpToNewVRegIdx;
276 /// Hold the registers that will be used to map MI with InstrMapping.
277 SmallVector<unsigned, 8> NewVRegs;
278 /// Current MachineRegisterInfo, used to create new virtual registers.
279 MachineRegisterInfo &MRI;
280 /// Instruction being remapped.
282 /// New mapping of the instruction.
283 const InstructionMapping &InstrMapping;
285 /// Constant value identifying that the index in OpToNewVRegIdx
286 /// for an operand has not been set yet.
287 static const int DontKnowIdx;
289 /// Get the range in NewVRegs to store all the partial
290 /// values for the \p OpIdx-th operand.
292 /// \return The iterator range for the space created.
294 /// \pre getMI().getOperand(OpIdx).isReg()
295 iterator_range<SmallVectorImpl<unsigned>::iterator>
296 getVRegsMem(unsigned OpIdx);
298 /// Get the end iterator for a range starting at \p StartIdx and
299 /// spannig \p NumVal in NewVRegs.
300 /// \pre StartIdx + NumVal <= NewVRegs.size()
301 SmallVectorImpl<unsigned>::const_iterator
302 getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
303 SmallVectorImpl<unsigned>::iterator getNewVRegsEnd(unsigned StartIdx,
307 /// Create an OperandsMapper that will hold the information to apply \p
308 /// InstrMapping to \p MI.
309 /// \pre InstrMapping.verify(MI)
310 OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
311 MachineRegisterInfo &MRI);
315 /// The MachineInstr being remapped.
316 MachineInstr &getMI() const { return MI; }
318 /// The final mapping of the instruction.
319 const InstructionMapping &getInstrMapping() const { return InstrMapping; }
322 /// Create as many new virtual registers as needed for the mapping of the \p
323 /// OpIdx-th operand.
324 /// The number of registers is determined by the number of breakdown for the
325 /// related operand in the instruction mapping.
327 /// \pre getMI().getOperand(OpIdx).isReg()
329 /// \post All the partial mapping of the \p OpIdx-th operand have been
330 /// assigned a new virtual register.
331 void createVRegs(unsigned OpIdx);
333 /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
334 /// the OpIdx-th operand to \p NewVReg.
336 /// \pre getMI().getOperand(OpIdx).isReg()
337 /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
341 /// \post the \p PartialMapIdx-th register of the value mapping of the \p
342 /// OpIdx-th operand has been set.
343 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg);
345 /// Get all the virtual registers required to map the \p OpIdx-th operand of
348 /// This return an empty range when createVRegs or setVRegs has not been
350 /// The iterator may be invalidated by a call to setVRegs or createVRegs.
352 /// When \p ForDebug is true, we will not check that the list of new virtual
353 /// registers does not contain uninitialized values.
355 /// \pre getMI().getOperand(OpIdx).isReg()
356 /// \pre ForDebug || All partial mappings have been set a register
357 iterator_range<SmallVectorImpl<unsigned>::const_iterator>
358 getVRegs(unsigned OpIdx, bool ForDebug = false) const;
360 /// Print this operands mapper on dbgs() stream.
363 /// Print this operands mapper on \p OS stream.
364 void print(raw_ostream &OS, bool ForDebug = false) const;
368 /// Hold the set of supported register banks.
369 RegisterBank **RegBanks;
370 /// Total number of register banks.
371 unsigned NumRegBanks;
373 /// Keep dynamically allocated PartialMapping in a separate map.
374 /// This shouldn't be needed when everything gets TableGen'ed.
375 mutable DenseMap<unsigned, const PartialMapping *> MapOfPartialMappings;
377 /// Keep dynamically allocated ValueMapping in a separate map.
378 /// This shouldn't be needed when everything gets TableGen'ed.
379 mutable DenseMap<unsigned, const ValueMapping *> MapOfValueMappings;
381 /// Keep dynamically allocated array of ValueMapping in a separate map.
382 /// This shouldn't be needed when everything gets TableGen'ed.
383 mutable DenseMap<unsigned, ValueMapping *> MapOfOperandsMappings;
385 /// Create a RegisterBankInfo that can accomodate up to \p NumRegBanks
386 /// RegisterBank instances.
387 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
389 /// This constructor is meaningless.
390 /// It just provides a default constructor that can be used at link time
391 /// when GlobalISel is not built.
392 /// That way, targets can still inherit from this class without doing
393 /// crazy gymnastic to avoid link time failures.
394 /// \note That works because the constructor is inlined.
396 llvm_unreachable("This constructor should not be executed");
399 /// Get the register bank identified by \p ID.
400 RegisterBank &getRegBank(unsigned ID) {
401 assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
402 return *RegBanks[ID];
405 /// Try to get the mapping of \p MI.
406 /// See getInstrMapping for more details on what a mapping represents.
408 /// Unlike getInstrMapping the returned InstructionMapping may be invalid
409 /// (isValid() == false).
410 /// This means that the target independent code is not smart enough
411 /// to get the mapping of \p MI and thus, the target has to provide the
412 /// information for \p MI.
414 /// This implementation is able to get the mapping of:
415 /// - Target specific instructions by looking at the encoding constraints.
416 /// - Any instruction if all the register operands have already been assigned
417 /// a register, a register class, or a register bank.
418 /// - Copies and phis if at least one of the operands has been assigned a
419 /// register, a register class, or a register bank.
420 /// In other words, this method will likely fail to find a mapping for
421 /// any generic opcode that has not been lowered by target specific code.
422 InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const;
424 /// Get the uniquely generated PartialMapping for the
426 const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
427 const RegisterBank &RegBank) const;
429 /// Methods to get a uniquely generated ValueMapping.
432 /// The most common ValueMapping consists of a single PartialMapping.
433 /// Feature a method for that.
434 const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
435 const RegisterBank &RegBank) const;
437 /// Get the ValueMapping for the given arguments.
438 const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
439 unsigned NumBreakDowns) const;
442 /// Methods to get a uniquely generated array of ValueMapping.
445 /// Get the uniquely generated array of ValueMapping for the
446 /// elements of between \p Begin and \p End.
448 /// Elements that are nullptr will be replaced by
449 /// invalid ValueMapping (ValueMapping::isValid == false).
451 /// \pre The pointers on ValueMapping between \p Begin and \p End
452 /// must uniquely identify a ValueMapping. Otherwise, there is no
453 /// guarantee that the return instance will be unique, i.e., another
454 /// OperandsMapping could have the same content.
455 template <typename Iterator>
456 const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
458 /// Get the uniquely generated array of ValueMapping for the
459 /// elements of \p OpdsMapping.
461 /// Elements of \p OpdsMapping that are nullptr will be replaced by
462 /// invalid ValueMapping (ValueMapping::isValid == false).
463 const ValueMapping *getOperandsMapping(
464 const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
466 /// Get the uniquely generated array of ValueMapping for the
469 /// Arguments that are nullptr will be replaced by invalid
470 /// ValueMapping (ValueMapping::isValid == false).
471 const ValueMapping *getOperandsMapping(
472 std::initializer_list<const ValueMapping *> OpdsMapping) const;
475 /// Get the register bank for the \p OpIdx-th operand of \p MI form
476 /// the encoding constraints, if any.
478 /// \return A register bank that covers the register class of the
479 /// related encoding constraints or nullptr if \p MI did not provide
480 /// enough information to deduce it.
482 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
483 const TargetInstrInfo &TII,
484 const TargetRegisterInfo &TRI) const;
486 /// Helper method to apply something that is like the default mapping.
487 /// Basically, that means that \p OpdMapper.getMI() is left untouched
488 /// aside from the reassignment of the register operand that have been
490 /// If the mapping of one of the operand spans several registers, this
491 /// method will abort as this is not like a default mapping anymore.
493 /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
494 /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
495 static void applyDefaultMapping(const OperandsMapper &OpdMapper);
497 /// See ::applyMapping.
498 virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
499 llvm_unreachable("The target has to implement that part");
503 virtual ~RegisterBankInfo();
505 /// Get the register bank identified by \p ID.
506 const RegisterBank &getRegBank(unsigned ID) const {
507 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
510 /// Get the register bank of \p Reg.
511 /// If Reg has not been assigned a register, a register class,
512 /// or a register bank, then this returns nullptr.
514 /// \pre Reg != 0 (NoRegister)
515 const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
516 const TargetRegisterInfo &TRI) const;
518 /// Get the total number of register banks.
519 unsigned getNumRegBanks() const { return NumRegBanks; }
521 /// Get a register bank that covers \p RC.
523 /// \pre \p RC is a user-defined register class (as opposed as one
524 /// generated by TableGen).
526 /// \note The mapping RC -> RegBank could be built while adding the
527 /// coverage for the register banks. However, we do not do it, because,
528 /// at least for now, we only need this information for register classes
529 /// that are used in the description of instruction. In other words,
530 /// there are just a handful of them and we do not want to waste space.
532 /// \todo This should be TableGen'ed.
533 virtual const RegisterBank &
534 getRegBankFromRegClass(const TargetRegisterClass &RC) const {
535 llvm_unreachable("The target must override this method");
538 /// Get the cost of a copy from \p B to \p A, or put differently,
539 /// get the cost of A = COPY B. Since register banks may cover
540 /// different size, \p Size specifies what will be the size in bits
541 /// that will be copied around.
543 /// \note Since this is a copy, both registers have the same size.
544 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
545 unsigned Size) const {
546 // Optimistically assume that copies are coalesced. I.e., when
547 // they are on the same bank, they are free.
548 // Otherwise assume a non-zero cost of 1. The targets are supposed
549 // to override that properly anyway if they care.
553 /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
555 /// \pre \p Reg is a virtual register that either has a bank or a class.
556 /// \returns The constrained register class, or nullptr if there is none.
557 /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
558 static const TargetRegisterClass *
559 constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC,
560 MachineRegisterInfo &MRI);
562 /// Identifier used when the related instruction mapping instance
563 /// is generated by target independent code.
564 /// Make sure not to use that identifier to avoid possible collision.
565 static const unsigned DefaultMappingID;
567 /// Identifier used when the related instruction mapping instance
568 /// is generated by the default constructor.
569 /// Make sure not to use that identifier.
570 static const unsigned InvalidMappingID;
572 /// Get the mapping of the different operands of \p MI
573 /// on the register bank.
574 /// This mapping should be the direct translation of \p MI.
575 /// In other words, when \p MI is mapped with the returned mapping,
576 /// only the register banks of the operands of \p MI need to be updated.
577 /// In particular, neither the opcode nor the type of \p MI needs to be
578 /// updated for this direct mapping.
580 /// The target independent implementation gives a mapping based on
581 /// the register classes for the target specific opcode.
582 /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
583 /// Make sure you do not use that ID for the alternative mapping
584 /// for MI. See getInstrAlternativeMappings for the alternative
587 /// For instance, if \p MI is a vector add, the mapping should
588 /// not be a scalarization of the add.
590 /// \post returnedVal.verify(MI).
592 /// \note If returnedVal does not verify MI, this would probably mean
593 /// that the target does not support that instruction.
594 virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const;
596 /// Get the alternative mappings for \p MI.
597 /// Alternative in the sense different from getInstrMapping.
598 virtual InstructionMappings
599 getInstrAlternativeMappings(const MachineInstr &MI) const;
601 /// Get the possible mapping for \p MI.
602 /// A mapping defines where the different operands may live and at what cost.
603 /// For instance, let us consider:
604 /// v0(16) = G_ADD <2 x i8> v1, v2
605 /// The possible mapping could be:
607 /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
608 /// /*v2*/{(0xFFFF, VPR)}}
609 /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
610 /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
611 /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
613 /// \note The first alternative of the returned mapping should be the
614 /// direct translation of \p MI current form.
616 /// \post !returnedVal.empty().
617 InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;
619 /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
620 /// After this call \p OpdMapper.getMI() may not be valid anymore.
621 /// \p OpdMapper.getInstrMapping().getID() carries the information of
622 /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
623 /// by the various getInstrXXXMapping method.
625 /// Therefore, getting the mapping and applying it should be kept in
627 void applyMapping(const OperandsMapper &OpdMapper) const {
628 // The only mapping we know how to handle is the default mapping.
629 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
630 return applyDefaultMapping(OpdMapper);
631 // For other mapping, the target needs to do the right thing.
632 // If that means calling applyDefaultMapping, fine, but this
633 // must be explicitly stated.
634 applyMappingImpl(OpdMapper);
637 /// Get the size in bits of \p Reg.
638 /// Utility method to get the size of any registers. Unlike
639 /// MachineRegisterInfo::getSize, the register does not need to be a
640 /// virtual register.
642 /// \pre \p Reg != 0 (NoRegister).
643 static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
644 const TargetRegisterInfo &TRI);
646 /// Check that information hold by this instance make sense for the
649 /// \note This method does not check anything when assertions are disabled.
651 /// \return True is the check was successful.
652 bool verify(const TargetRegisterInfo &TRI) const;
656 operator<<(raw_ostream &OS,
657 const RegisterBankInfo::PartialMapping &PartMapping) {
658 PartMapping.print(OS);
663 operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) {
664 ValMapping.print(OS);
669 operator<<(raw_ostream &OS,
670 const RegisterBankInfo::InstructionMapping &InstrMapping) {
671 InstrMapping.print(OS);
676 operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
677 OpdMapper.print(OS, /*ForDebug*/ false);
681 /// Hashing function for PartialMapping.
682 /// It is required for the hashing of ValueMapping.
683 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
684 } // End namespace llvm.