1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
23 #include "llvm/ADT/IndexedMap.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/CodeGen/LiveInterval.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/SlotIndexes.h"
30 #include "llvm/Support/Allocator.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
37 extern cl::opt<bool> UseSegmentSetForPhysRegs;
43 class MachineDominatorTree;
44 class MachineLoopInfo;
45 class TargetRegisterInfo;
46 class MachineRegisterInfo;
47 class TargetInstrInfo;
48 class TargetRegisterClass;
50 class MachineBlockFrequencyInfo;
52 class LiveIntervals : public MachineFunctionPass {
54 MachineRegisterInfo* MRI;
55 const TargetRegisterInfo* TRI;
56 const TargetInstrInfo* TII;
59 MachineDominatorTree *DomTree;
60 LiveRangeCalc *LRCalc;
62 /// Special pool allocator for VNInfo's (LiveInterval val#).
64 VNInfo::Allocator VNInfoAllocator;
66 /// Live interval pointers for all the virtual registers.
67 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
69 /// RegMaskSlots - Sorted list of instructions with register mask operands.
70 /// Always use the 'r' slot, RegMasks are normal clobbers, not early
72 SmallVector<SlotIndex, 8> RegMaskSlots;
74 /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
75 /// pointer to the corresponding register mask. This pointer can be
78 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
79 /// unsigned OpNum = findRegMaskOperand(MI);
80 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
82 /// This is kept in a separate vector partly because some standard
83 /// libraries don't support lower_bound() with mixed objects, partly to
84 /// improve locality when searching in RegMaskSlots.
85 /// Also see the comment in LiveInterval::find().
86 SmallVector<const uint32_t*, 8> RegMaskBits;
88 /// For each basic block number, keep (begin, size) pairs indexing into the
89 /// RegMaskSlots and RegMaskBits arrays.
90 /// Note that basic block numbers may not be layout contiguous, that's why
91 /// we can't just keep track of the first register mask in each basic
93 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
95 /// Keeps a live range set for each register unit to track fixed physreg
97 SmallVector<LiveRange*, 0> RegUnitRanges;
100 static char ID; // Pass identification, replacement for typeid
102 ~LiveIntervals() override;
104 // Calculate the spill weight to assign to a single instruction.
105 static float getSpillWeight(bool isDef, bool isUse,
106 const MachineBlockFrequencyInfo *MBFI,
107 const MachineInstr &Instr);
109 LiveInterval &getInterval(unsigned Reg) {
110 if (hasInterval(Reg))
111 return *VirtRegIntervals[Reg];
113 return createAndComputeVirtRegInterval(Reg);
116 const LiveInterval &getInterval(unsigned Reg) const {
117 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
120 bool hasInterval(unsigned Reg) const {
121 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
124 // Interval creation.
125 LiveInterval &createEmptyInterval(unsigned Reg) {
126 assert(!hasInterval(Reg) && "Interval already exists!");
127 VirtRegIntervals.grow(Reg);
128 VirtRegIntervals[Reg] = createInterval(Reg);
129 return *VirtRegIntervals[Reg];
132 LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) {
133 LiveInterval &LI = createEmptyInterval(Reg);
134 computeVirtRegInterval(LI);
139 void removeInterval(unsigned Reg) {
140 delete VirtRegIntervals[Reg];
141 VirtRegIntervals[Reg] = nullptr;
144 /// Given a register and an instruction, adds a live segment from that
145 /// instruction to the end of its MBB.
146 LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
147 MachineInstr &startInst);
149 /// After removing some uses of a register, shrink its live range to just
150 /// the remaining uses. This method does not compute reaching defs for new
151 /// uses, and it doesn't remove dead defs.
152 /// Dead PHIDef values are marked as unused. New dead machine instructions
153 /// are added to the dead vector. Returns true if the interval may have been
154 /// separated into multiple connected components.
155 bool shrinkToUses(LiveInterval *li,
156 SmallVectorImpl<MachineInstr*> *dead = nullptr);
158 /// Specialized version of
159 /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
160 /// that works on a subregister live range and only looks at uses matching
161 /// the lane mask of the subregister range.
162 /// This may leave the subrange empty which needs to be cleaned up with
163 /// LiveInterval::removeEmptySubranges() afterwards.
164 void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
166 /// Extend the live range @p LR to reach all points in @p Indices. The
167 /// points in the @p Indices array must be jointly dominated by the union
168 /// of the existing defs in @p LR and points in @p Undefs.
170 /// PHI-defs are added as needed to maintain SSA form.
172 /// If a SlotIndex in @p Indices is the end index of a basic block, @p LR
173 /// will be extended to be live out of the basic block.
174 /// If a SlotIndex in @p Indices is jointy dominated only by points in
175 /// @p Undefs, the live range will not be extended to that point.
177 /// See also LiveRangeCalc::extend().
178 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
179 ArrayRef<SlotIndex> Undefs);
181 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) {
182 extendToIndices(LR, Indices, /*Undefs=*/{});
185 /// If @p LR has a live value at @p Kill, prune its live range by removing
186 /// any liveness reachable from Kill. Add live range end points to
187 /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
188 /// value's live range.
190 /// Calling pruneValue() and extendToIndices() can be used to reconstruct
191 /// SSA form after adding defs to a virtual register.
192 void pruneValue(LiveRange &LR, SlotIndex Kill,
193 SmallVectorImpl<SlotIndex> *EndPoints);
195 SlotIndexes *getSlotIndexes() const {
199 AliasAnalysis *getAliasAnalysis() const {
203 /// isNotInMIMap - returns true if the specified machine instr has been
204 /// removed or was never entered in the map.
205 bool isNotInMIMap(const MachineInstr &Instr) const {
206 return !Indexes->hasIndex(Instr);
209 /// Returns the base index of the given instruction.
210 SlotIndex getInstructionIndex(const MachineInstr &Instr) const {
211 return Indexes->getInstructionIndex(Instr);
214 /// Returns the instruction associated with the given index.
215 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
216 return Indexes->getInstructionFromIndex(index);
219 /// Return the first index in the given basic block.
220 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
221 return Indexes->getMBBStartIdx(mbb);
224 /// Return the last index in the given basic block.
225 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
226 return Indexes->getMBBEndIdx(mbb);
229 bool isLiveInToMBB(const LiveRange &LR,
230 const MachineBasicBlock *mbb) const {
231 return LR.liveAt(getMBBStartIdx(mbb));
234 bool isLiveOutOfMBB(const LiveRange &LR,
235 const MachineBasicBlock *mbb) const {
236 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
239 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
240 return Indexes->getMBBFromIndex(index);
243 void insertMBBInMaps(MachineBasicBlock *MBB) {
244 Indexes->insertMBBInMaps(MBB);
245 assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
246 "Blocks must be added in order.");
247 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
250 SlotIndex InsertMachineInstrInMaps(MachineInstr &MI) {
251 return Indexes->insertMachineInstrInMaps(MI);
254 void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
255 MachineBasicBlock::iterator E) {
256 for (MachineBasicBlock::iterator I = B; I != E; ++I)
257 Indexes->insertMachineInstrInMaps(*I);
260 void RemoveMachineInstrFromMaps(MachineInstr &MI) {
261 Indexes->removeMachineInstrFromMaps(MI);
264 SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
265 return Indexes->replaceMachineInstrInMaps(MI, NewMI);
268 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
270 void getAnalysisUsage(AnalysisUsage &AU) const override;
271 void releaseMemory() override;
273 /// runOnMachineFunction - pass entry point
274 bool runOnMachineFunction(MachineFunction&) override;
276 /// print - Implement the dump method.
277 void print(raw_ostream &O, const Module* = nullptr) const override;
279 /// intervalIsInOneMBB - If LI is confined to a single basic block, return
280 /// a pointer to that block. If LI is live in to or out of any block,
282 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
284 /// Returns true if VNI is killed by any PHI-def values in LI.
285 /// This may conservatively return true to avoid expensive computations.
286 bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
288 /// addKillFlags - Add kill flags to any instruction that kills a virtual
290 void addKillFlags(const VirtRegMap*);
292 /// handleMove - call this method to notify LiveIntervals that
293 /// instruction 'mi' has been moved within a basic block. This will update
294 /// the live intervals for all operands of mi. Moves between basic blocks
295 /// are not supported.
297 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
298 void handleMove(MachineInstr &MI, bool UpdateFlags = false);
300 /// moveIntoBundle - Update intervals for operands of MI so that they
301 /// begin/end on the SlotIndex for BundleStart.
303 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
305 /// Requires MI and BundleStart to have SlotIndexes, and assumes
306 /// existing liveness is accurate. BundleStart should be the first
307 /// instruction in the Bundle.
308 void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart,
309 bool UpdateFlags = false);
311 /// repairIntervalsInRange - Update live intervals for instructions in a
312 /// range of iterators. It is intended for use after target hooks that may
313 /// insert or remove instructions, and is only efficient for a small number
316 /// OrigRegs is a vector of registers that were originally used by the
317 /// instructions in the range between the two iterators.
319 /// Currently, the only only changes that are supported are simple removal
320 /// and addition of uses.
321 void repairIntervalsInRange(MachineBasicBlock *MBB,
322 MachineBasicBlock::iterator Begin,
323 MachineBasicBlock::iterator End,
324 ArrayRef<unsigned> OrigRegs);
326 // Register mask functions.
328 // Machine instructions may use a register mask operand to indicate that a
329 // large number of registers are clobbered by the instruction. This is
330 // typically used for calls.
332 // For compile time performance reasons, these clobbers are not recorded in
333 // the live intervals for individual physical registers. Instead,
334 // LiveIntervalAnalysis maintains a sorted list of instructions with
335 // register mask operands.
337 /// getRegMaskSlots - Returns a sorted array of slot indices of all
338 /// instructions with register mask operands.
339 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
341 /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
342 /// instructions with register mask operands in the basic block numbered
344 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
345 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
346 return getRegMaskSlots().slice(P.first, P.second);
349 /// getRegMaskBits() - Returns an array of register mask pointers
350 /// corresponding to getRegMaskSlots().
351 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
353 /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
354 /// to getRegMaskSlotsInBlock(MBBNum).
355 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
356 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
357 return getRegMaskBits().slice(P.first, P.second);
360 /// checkRegMaskInterference - Test if LI is live across any register mask
361 /// instructions, and compute a bit mask of physical registers that are not
362 /// clobbered by any of them.
364 /// Returns false if LI doesn't cross any register mask instructions. In
365 /// that case, the bit vector is not filled in.
366 bool checkRegMaskInterference(LiveInterval &LI,
367 BitVector &UsableRegs);
369 // Register unit functions.
371 // Fixed interference occurs when MachineInstrs use physregs directly
372 // instead of virtual registers. This typically happens when passing
373 // arguments to a function call, or when instructions require operands in
376 // Each physreg has one or more register units, see MCRegisterInfo. We
377 // track liveness per register unit to handle aliasing registers more
380 /// getRegUnit - Return the live range for Unit.
381 /// It will be computed if it doesn't exist.
382 LiveRange &getRegUnit(unsigned Unit) {
383 LiveRange *LR = RegUnitRanges[Unit];
385 // Compute missing ranges on demand.
386 // Use segment set to speed-up initial computation of the live range.
387 RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
388 computeRegUnitRange(*LR, Unit);
393 /// getCachedRegUnit - Return the live range for Unit if it has already
394 /// been computed, or NULL if it hasn't been computed yet.
395 LiveRange *getCachedRegUnit(unsigned Unit) {
396 return RegUnitRanges[Unit];
399 const LiveRange *getCachedRegUnit(unsigned Unit) const {
400 return RegUnitRanges[Unit];
403 /// removeRegUnit - Remove computed live range for Unit. Subsequent uses
404 /// should rely on on-demand recomputation.
405 void removeRegUnit(unsigned Unit) {
406 delete RegUnitRanges[Unit];
407 RegUnitRanges[Unit] = nullptr;
410 /// Remove value numbers and related live segments starting at position
411 /// @p Pos that are part of any liverange of physical register @p Reg or one
412 /// of its subregisters.
413 void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
415 /// Remove value number and related live segments of @p LI and its subranges
416 /// that start at position @p Pos.
417 void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
419 /// Split separate components in LiveInterval \p LI into separate intervals.
420 void splitSeparateComponents(LiveInterval &LI,
421 SmallVectorImpl<LiveInterval*> &SplitLIs);
423 /// For live interval \p LI with correct SubRanges construct matching
424 /// information for the main live range. Expects the main live range to not
425 /// have any segments or value numbers.
426 void constructMainRangeFromSubranges(LiveInterval &LI);
429 /// Compute live intervals for all virtual registers.
430 void computeVirtRegs();
432 /// Compute RegMaskSlots and RegMaskBits.
433 void computeRegMasks();
435 /// Walk the values in @p LI and check for dead values:
436 /// - Dead PHIDef values are marked as unused.
437 /// - Dead operands are marked as such.
438 /// - Completely dead machine instructions are added to the @p dead vector
439 /// if it is not nullptr.
440 /// Returns true if any PHI value numbers have been removed which may
441 /// have separated the interval into multiple connected components.
442 bool computeDeadValues(LiveInterval &LI,
443 SmallVectorImpl<MachineInstr*> *dead);
445 static LiveInterval* createInterval(unsigned Reg);
447 void printInstrs(raw_ostream &O) const;
448 void dumpInstrs() const;
450 void computeLiveInRegUnits();
451 void computeRegUnitRange(LiveRange&, unsigned Unit);
452 void computeVirtRegInterval(LiveInterval&);
455 /// Helper function for repairIntervalsInRange(), walks backwards and
456 /// creates/modifies live segments in @p LR to match the operands found.
457 /// Only full operands or operands with subregisters matching @p LaneMask
459 void repairOldRegInRange(MachineBasicBlock::iterator Begin,
460 MachineBasicBlock::iterator End,
461 const SlotIndex endIdx, LiveRange &LR,
463 LaneBitmask LaneMask = LaneBitmask::getAll());
467 } // End llvm namespace