1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/ilist.h"
21 #include "llvm/ADT/ilist_node.h"
22 #include "llvm/ADT/iterator_range.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/IR/InlineAsm.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/Support/ArrayRecycler.h"
29 #include "llvm/Target/TargetOpcodes.h"
37 template <typename T> class ArrayRef;
39 class DILocalVariable;
40 class MachineBasicBlock;
41 class MachineFunction;
42 class MachineMemOperand;
43 class MachineRegisterInfo;
44 class ModuleSlotTracker;
46 template <typename T> class SmallVectorImpl;
48 class TargetInstrInfo;
49 class TargetRegisterClass;
50 class TargetRegisterInfo;
52 //===----------------------------------------------------------------------===//
53 /// Representation of each machine instruction.
55 /// This class isn't a POD type, but it must have a trivial destructor. When a
56 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
57 /// without having their destructor called.
60 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
61 ilist_sentinel_tracking<true>> {
63 using mmo_iterator = MachineMemOperand **;
65 /// Flags to specify different kinds of comments to output in
66 /// assembly code. These flags carry semantic information not
67 /// otherwise easily derivable from the IR text.
70 ReloadReuse = 0x1 // higher bits are reserved for target dep comments.
75 FrameSetup = 1 << 0, // Instruction is used as a part of
76 // function frame setup code.
77 FrameDestroy = 1 << 1, // Instruction is used as a part of
78 // function frame destruction code.
79 BundledPred = 1 << 2, // Instruction has bundled predecessors.
80 BundledSucc = 1 << 3 // Instruction has bundled successors.
84 const MCInstrDesc *MCID; // Instruction descriptor.
85 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
87 // Operands are allocated by an ArrayRecycler.
88 MachineOperand *Operands = nullptr; // Pointer to the first operand.
89 unsigned NumOperands = 0; // Number of operands on instruction.
90 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
91 OperandCapacity CapOperands; // Capacity of the Operands array.
93 uint8_t Flags = 0; // Various bits of additional
94 // information about machine
97 uint8_t AsmPrinterFlags = 0; // Various bits of information used by
98 // the AsmPrinter to emit helpful
99 // comments. This is *not* semantic
100 // information. Do not use this for
101 // anything other than to convey comment
102 // information to AsmPrinter.
104 uint8_t NumMemRefs = 0; // Information on memory references.
105 // Note that MemRefs == nullptr, means 'don't know', not 'no memory access'.
106 // Calling code must treat missing information conservatively. If the number
107 // of memory operands required to be precise exceeds the maximum value of
108 // NumMemRefs - currently 256 - we remove the operands entirely. Note also
109 // that this is a non-owning reference to a shared copy on write buffer owned
110 // by the MachineFunction and created via MF.allocateMemRefsArray.
111 mmo_iterator MemRefs = nullptr;
113 DebugLoc debugLoc; // Source line information.
115 // Intrusive list support
116 friend struct ilist_traits<MachineInstr>;
117 friend struct ilist_callback_traits<MachineBasicBlock>;
118 void setParent(MachineBasicBlock *P) { Parent = P; }
120 /// This constructor creates a copy of the given
121 /// MachineInstr in the given MachineFunction.
122 MachineInstr(MachineFunction &, const MachineInstr &);
124 /// This constructor create a MachineInstr and add the implicit operands.
125 /// It reserves space for number of operands specified by
126 /// MCInstrDesc. An explicit DebugLoc is supplied.
127 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
130 // MachineInstrs are pool-allocated and owned by MachineFunction.
131 friend class MachineFunction;
134 MachineInstr(const MachineInstr &) = delete;
135 MachineInstr &operator=(const MachineInstr &) = delete;
136 // Use MachineFunction::DeleteMachineInstr() instead.
137 ~MachineInstr() = delete;
139 const MachineBasicBlock* getParent() const { return Parent; }
140 MachineBasicBlock* getParent() { return Parent; }
142 /// Return the asm printer flags bitvector.
143 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
145 /// Clear the AsmPrinter bitvector.
146 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
148 /// Return whether an AsmPrinter flag is set.
149 bool getAsmPrinterFlag(CommentFlag Flag) const {
150 return AsmPrinterFlags & Flag;
153 /// Set a flag for the AsmPrinter.
154 void setAsmPrinterFlag(uint8_t Flag) {
155 AsmPrinterFlags |= Flag;
158 /// Clear specific AsmPrinter flags.
159 void clearAsmPrinterFlag(CommentFlag Flag) {
160 AsmPrinterFlags &= ~Flag;
163 /// Return the MI flags bitvector.
164 uint8_t getFlags() const {
168 /// Return whether an MI flag is set.
169 bool getFlag(MIFlag Flag) const {
174 void setFlag(MIFlag Flag) {
175 Flags |= (uint8_t)Flag;
178 void setFlags(unsigned flags) {
179 // Filter out the automatically maintained flags.
180 unsigned Mask = BundledPred | BundledSucc;
181 Flags = (Flags & Mask) | (flags & ~Mask);
184 /// clearFlag - Clear a MI flag.
185 void clearFlag(MIFlag Flag) {
186 Flags &= ~((uint8_t)Flag);
189 /// Return true if MI is in a bundle (but not the first MI in a bundle).
191 /// A bundle looks like this before it's finalized:
203 /// In this case, the first MI starts a bundle but is not inside a bundle, the
204 /// next 2 MIs are considered "inside" the bundle.
206 /// After a bundle is finalized, it looks like this:
222 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
223 /// a bundle, but the next three MIs are.
224 bool isInsideBundle() const {
225 return getFlag(BundledPred);
228 /// Return true if this instruction part of a bundle. This is true
229 /// if either itself or its following instruction is marked "InsideBundle".
230 bool isBundled() const {
231 return isBundledWithPred() || isBundledWithSucc();
234 /// Return true if this instruction is part of a bundle, and it is not the
235 /// first instruction in the bundle.
236 bool isBundledWithPred() const { return getFlag(BundledPred); }
238 /// Return true if this instruction is part of a bundle, and it is not the
239 /// last instruction in the bundle.
240 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
242 /// Bundle this instruction with its predecessor. This can be an unbundled
243 /// instruction, or it can be the first instruction in a bundle.
244 void bundleWithPred();
246 /// Bundle this instruction with its successor. This can be an unbundled
247 /// instruction, or it can be the last instruction in a bundle.
248 void bundleWithSucc();
250 /// Break bundle above this instruction.
251 void unbundleFromPred();
253 /// Break bundle below this instruction.
254 void unbundleFromSucc();
256 /// Returns the debug location id of this MachineInstr.
257 const DebugLoc &getDebugLoc() const { return debugLoc; }
259 /// Return the debug variable referenced by
260 /// this DBG_VALUE instruction.
261 const DILocalVariable *getDebugVariable() const;
263 /// Return the complex address expression referenced by
264 /// this DBG_VALUE instruction.
265 const DIExpression *getDebugExpression() const;
267 /// Emit an error referring to the source location of this instruction.
268 /// This should only be used for inline assembly that is somehow
269 /// impossible to compile. Other errors should have been handled much
272 /// If this method returns, the caller should try to recover from the error.
273 void emitError(StringRef Msg) const;
275 /// Returns the target instruction descriptor of this MachineInstr.
276 const MCInstrDesc &getDesc() const { return *MCID; }
278 /// Returns the opcode of this MachineInstr.
279 unsigned getOpcode() const { return MCID->Opcode; }
281 /// Access to explicit operands of the instruction.
282 unsigned getNumOperands() const { return NumOperands; }
284 const MachineOperand& getOperand(unsigned i) const {
285 assert(i < getNumOperands() && "getOperand() out of range!");
288 MachineOperand& getOperand(unsigned i) {
289 assert(i < getNumOperands() && "getOperand() out of range!");
293 /// Returns the number of non-implicit operands.
294 unsigned getNumExplicitOperands() const;
296 /// iterator/begin/end - Iterate over all operands of a machine instruction.
297 using mop_iterator = MachineOperand *;
298 using const_mop_iterator = const MachineOperand *;
300 mop_iterator operands_begin() { return Operands; }
301 mop_iterator operands_end() { return Operands + NumOperands; }
303 const_mop_iterator operands_begin() const { return Operands; }
304 const_mop_iterator operands_end() const { return Operands + NumOperands; }
306 iterator_range<mop_iterator> operands() {
307 return make_range(operands_begin(), operands_end());
309 iterator_range<const_mop_iterator> operands() const {
310 return make_range(operands_begin(), operands_end());
312 iterator_range<mop_iterator> explicit_operands() {
313 return make_range(operands_begin(),
314 operands_begin() + getNumExplicitOperands());
316 iterator_range<const_mop_iterator> explicit_operands() const {
317 return make_range(operands_begin(),
318 operands_begin() + getNumExplicitOperands());
320 iterator_range<mop_iterator> implicit_operands() {
321 return make_range(explicit_operands().end(), operands_end());
323 iterator_range<const_mop_iterator> implicit_operands() const {
324 return make_range(explicit_operands().end(), operands_end());
326 /// Returns a range over all explicit operands that are register definitions.
327 /// Implicit definition are not included!
328 iterator_range<mop_iterator> defs() {
329 return make_range(operands_begin(),
330 operands_begin() + getDesc().getNumDefs());
333 iterator_range<const_mop_iterator> defs() const {
334 return make_range(operands_begin(),
335 operands_begin() + getDesc().getNumDefs());
337 /// Returns a range that includes all operands that are register uses.
338 /// This may include unrelated operands which are not register uses.
339 iterator_range<mop_iterator> uses() {
340 return make_range(operands_begin() + getDesc().getNumDefs(),
344 iterator_range<const_mop_iterator> uses() const {
345 return make_range(operands_begin() + getDesc().getNumDefs(),
348 iterator_range<mop_iterator> explicit_uses() {
349 return make_range(operands_begin() + getDesc().getNumDefs(),
350 operands_begin() + getNumExplicitOperands() );
352 iterator_range<const_mop_iterator> explicit_uses() const {
353 return make_range(operands_begin() + getDesc().getNumDefs(),
354 operands_begin() + getNumExplicitOperands() );
357 /// Returns the number of the operand iterator \p I points to.
358 unsigned getOperandNo(const_mop_iterator I) const {
359 return I - operands_begin();
362 /// Access to memory operands of the instruction
363 mmo_iterator memoperands_begin() const { return MemRefs; }
364 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
365 /// Return true if we don't have any memory operands which described the the
366 /// memory access done by this instruction. If this is true, calling code
367 /// must be conservative.
368 bool memoperands_empty() const { return NumMemRefs == 0; }
370 iterator_range<mmo_iterator> memoperands() {
371 return make_range(memoperands_begin(), memoperands_end());
373 iterator_range<mmo_iterator> memoperands() const {
374 return make_range(memoperands_begin(), memoperands_end());
377 /// Return true if this instruction has exactly one MachineMemOperand.
378 bool hasOneMemOperand() const {
379 return NumMemRefs == 1;
382 /// Return the number of memory operands.
383 unsigned getNumMemOperands() const { return NumMemRefs; }
385 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
386 /// queries but they are bundle aware.
389 IgnoreBundle, // Ignore bundles
390 AnyInBundle, // Return true if any instruction in bundle has property
391 AllInBundle // Return true if all instructions in bundle have property
394 /// Return true if the instruction (or in the case of a bundle,
395 /// the instructions inside the bundle) has the specified property.
396 /// The first argument is the property being queried.
397 /// The second argument indicates whether the query should look inside
398 /// instruction bundles.
399 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
400 // Inline the fast path for unbundled or bundle-internal instructions.
401 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
402 return getDesc().getFlags() & (1ULL << MCFlag);
404 // If this is the first instruction in a bundle, take the slow path.
405 return hasPropertyInBundle(1ULL << MCFlag, Type);
408 /// Return true if this instruction can have a variable number of operands.
409 /// In this case, the variable operands will be after the normal
410 /// operands but before the implicit definitions and uses (if any are
412 bool isVariadic(QueryType Type = IgnoreBundle) const {
413 return hasProperty(MCID::Variadic, Type);
416 /// Set if this instruction has an optional definition, e.g.
417 /// ARM instructions which can set condition code if 's' bit is set.
418 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
419 return hasProperty(MCID::HasOptionalDef, Type);
422 /// Return true if this is a pseudo instruction that doesn't
423 /// correspond to a real machine instruction.
424 bool isPseudo(QueryType Type = IgnoreBundle) const {
425 return hasProperty(MCID::Pseudo, Type);
428 bool isReturn(QueryType Type = AnyInBundle) const {
429 return hasProperty(MCID::Return, Type);
432 bool isCall(QueryType Type = AnyInBundle) const {
433 return hasProperty(MCID::Call, Type);
436 /// Returns true if the specified instruction stops control flow
437 /// from executing the instruction immediately following it. Examples include
438 /// unconditional branches and return instructions.
439 bool isBarrier(QueryType Type = AnyInBundle) const {
440 return hasProperty(MCID::Barrier, Type);
443 /// Returns true if this instruction part of the terminator for a basic block.
444 /// Typically this is things like return and branch instructions.
446 /// Various passes use this to insert code into the bottom of a basic block,
447 /// but before control flow occurs.
448 bool isTerminator(QueryType Type = AnyInBundle) const {
449 return hasProperty(MCID::Terminator, Type);
452 /// Returns true if this is a conditional, unconditional, or indirect branch.
453 /// Predicates below can be used to discriminate between
454 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
455 /// get more information.
456 bool isBranch(QueryType Type = AnyInBundle) const {
457 return hasProperty(MCID::Branch, Type);
460 /// Return true if this is an indirect branch, such as a
461 /// branch through a register.
462 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
463 return hasProperty(MCID::IndirectBranch, Type);
466 /// Return true if this is a branch which may fall
467 /// through to the next instruction or may transfer control flow to some other
468 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
469 /// information about this branch.
470 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
471 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
474 /// Return true if this is a branch which always
475 /// transfers control flow to some other block. The
476 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
477 /// about this branch.
478 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
479 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
482 /// Return true if this instruction has a predicate operand that
483 /// controls execution. It may be set to 'always', or may be set to other
484 /// values. There are various methods in TargetInstrInfo that can be used to
485 /// control and modify the predicate in this instruction.
486 bool isPredicable(QueryType Type = AllInBundle) const {
487 // If it's a bundle than all bundled instructions must be predicable for this
489 return hasProperty(MCID::Predicable, Type);
492 /// Return true if this instruction is a comparison.
493 bool isCompare(QueryType Type = IgnoreBundle) const {
494 return hasProperty(MCID::Compare, Type);
497 /// Return true if this instruction is a move immediate
498 /// (including conditional moves) instruction.
499 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
500 return hasProperty(MCID::MoveImm, Type);
503 /// Return true if this instruction is a bitcast instruction.
504 bool isBitcast(QueryType Type = IgnoreBundle) const {
505 return hasProperty(MCID::Bitcast, Type);
508 /// Return true if this instruction is a select instruction.
509 bool isSelect(QueryType Type = IgnoreBundle) const {
510 return hasProperty(MCID::Select, Type);
513 /// Return true if this instruction cannot be safely duplicated.
514 /// For example, if the instruction has a unique labels attached
515 /// to it, duplicating it would cause multiple definition errors.
516 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
517 return hasProperty(MCID::NotDuplicable, Type);
520 /// Return true if this instruction is convergent.
521 /// Convergent instructions can not be made control-dependent on any
522 /// additional values.
523 bool isConvergent(QueryType Type = AnyInBundle) const {
525 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
526 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
529 return hasProperty(MCID::Convergent, Type);
532 /// Returns true if the specified instruction has a delay slot
533 /// which must be filled by the code generator.
534 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
535 return hasProperty(MCID::DelaySlot, Type);
538 /// Return true for instructions that can be folded as
539 /// memory operands in other instructions. The most common use for this
540 /// is instructions that are simple loads from memory that don't modify
541 /// the loaded value in any way, but it can also be used for instructions
542 /// that can be expressed as constant-pool loads, such as V_SETALLONES
543 /// on x86, to allow them to be folded when it is beneficial.
544 /// This should only be set on instructions that return a value in their
545 /// only virtual register definition.
546 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
547 return hasProperty(MCID::FoldableAsLoad, Type);
550 /// \brief Return true if this instruction behaves
551 /// the same way as the generic REG_SEQUENCE instructions.
553 /// dX VMOVDRR rY, rZ
555 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
557 /// Note that for the optimizers to be able to take advantage of
558 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
559 /// override accordingly.
560 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
561 return hasProperty(MCID::RegSequence, Type);
564 /// \brief Return true if this instruction behaves
565 /// the same way as the generic EXTRACT_SUBREG instructions.
567 /// rX, rY VMOVRRD dZ
568 /// is equivalent to two EXTRACT_SUBREG:
569 /// rX = EXTRACT_SUBREG dZ, ssub_0
570 /// rY = EXTRACT_SUBREG dZ, ssub_1
572 /// Note that for the optimizers to be able to take advantage of
573 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
574 /// override accordingly.
575 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
576 return hasProperty(MCID::ExtractSubreg, Type);
579 /// \brief Return true if this instruction behaves
580 /// the same way as the generic INSERT_SUBREG instructions.
582 /// dX = VSETLNi32 dY, rZ, Imm
583 /// is equivalent to a INSERT_SUBREG:
584 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
586 /// Note that for the optimizers to be able to take advantage of
587 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
588 /// override accordingly.
589 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
590 return hasProperty(MCID::InsertSubreg, Type);
593 //===--------------------------------------------------------------------===//
594 // Side Effect Analysis
595 //===--------------------------------------------------------------------===//
597 /// Return true if this instruction could possibly read memory.
598 /// Instructions with this flag set are not necessarily simple load
599 /// instructions, they may load a value and modify it, for example.
600 bool mayLoad(QueryType Type = AnyInBundle) const {
602 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
603 if (ExtraInfo & InlineAsm::Extra_MayLoad)
606 return hasProperty(MCID::MayLoad, Type);
609 /// Return true if this instruction could possibly modify memory.
610 /// Instructions with this flag set are not necessarily simple store
611 /// instructions, they may store a modified value based on their operands, or
612 /// may not actually modify anything, for example.
613 bool mayStore(QueryType Type = AnyInBundle) const {
615 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
616 if (ExtraInfo & InlineAsm::Extra_MayStore)
619 return hasProperty(MCID::MayStore, Type);
622 /// Return true if this instruction could possibly read or modify memory.
623 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
624 return mayLoad(Type) || mayStore(Type);
627 //===--------------------------------------------------------------------===//
628 // Flags that indicate whether an instruction can be modified by a method.
629 //===--------------------------------------------------------------------===//
631 /// Return true if this may be a 2- or 3-address
632 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
633 /// result if Y and Z are exchanged. If this flag is set, then the
634 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
637 /// Note that this flag may be set on instructions that are only commutable
638 /// sometimes. In these cases, the call to commuteInstruction will fail.
639 /// Also note that some instructions require non-trivial modification to
641 bool isCommutable(QueryType Type = IgnoreBundle) const {
642 return hasProperty(MCID::Commutable, Type);
645 /// Return true if this is a 2-address instruction
646 /// which can be changed into a 3-address instruction if needed. Doing this
647 /// transformation can be profitable in the register allocator, because it
648 /// means that the instruction can use a 2-address form if possible, but
649 /// degrade into a less efficient form if the source and dest register cannot
650 /// be assigned to the same register. For example, this allows the x86
651 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
652 /// is the same speed as the shift but has bigger code size.
654 /// If this returns true, then the target must implement the
655 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
656 /// is allowed to fail if the transformation isn't valid for this specific
657 /// instruction (e.g. shl reg, 4 on x86).
659 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
660 return hasProperty(MCID::ConvertibleTo3Addr, Type);
663 /// Return true if this instruction requires
664 /// custom insertion support when the DAG scheduler is inserting it into a
665 /// machine basic block. If this is true for the instruction, it basically
666 /// means that it is a pseudo instruction used at SelectionDAG time that is
667 /// expanded out into magic code by the target when MachineInstrs are formed.
669 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
670 /// is used to insert this into the MachineBasicBlock.
671 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
672 return hasProperty(MCID::UsesCustomInserter, Type);
675 /// Return true if this instruction requires *adjustment*
676 /// after instruction selection by calling a target hook. For example, this
677 /// can be used to fill in ARM 's' optional operand depending on whether
678 /// the conditional flag register is used.
679 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
680 return hasProperty(MCID::HasPostISelHook, Type);
683 /// Returns true if this instruction is a candidate for remat.
684 /// This flag is deprecated, please don't use it anymore. If this
685 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
686 /// verify the instruction is really rematable.
687 bool isRematerializable(QueryType Type = AllInBundle) const {
688 // It's only possible to re-mat a bundle if all bundled instructions are
689 // re-materializable.
690 return hasProperty(MCID::Rematerializable, Type);
693 /// Returns true if this instruction has the same cost (or less) than a move
694 /// instruction. This is useful during certain types of optimizations
695 /// (e.g., remat during two-address conversion or machine licm)
696 /// where we would like to remat or hoist the instruction, but not if it costs
697 /// more than moving the instruction into the appropriate register. Note, we
698 /// are not marking copies from and to the same register class with this flag.
699 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
700 // Only returns true for a bundle if all bundled instructions are cheap.
701 return hasProperty(MCID::CheapAsAMove, Type);
704 /// Returns true if this instruction source operands
705 /// have special register allocation requirements that are not captured by the
706 /// operand register classes. e.g. ARM::STRD's two source registers must be an
707 /// even / odd pair, ARM::STM registers have to be in ascending order.
708 /// Post-register allocation passes should not attempt to change allocations
709 /// for sources of instructions with this flag.
710 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
711 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
714 /// Returns true if this instruction def operands
715 /// have special register allocation requirements that are not captured by the
716 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
717 /// even / odd pair, ARM::LDM registers have to be in ascending order.
718 /// Post-register allocation passes should not attempt to change allocations
719 /// for definitions of instructions with this flag.
720 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
721 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
725 CheckDefs, // Check all operands for equality
726 CheckKillDead, // Check all operands including kill / dead markers
727 IgnoreDefs, // Ignore all definitions
728 IgnoreVRegDefs // Ignore virtual register definitions
731 /// Return true if this instruction is identical to \p Other.
732 /// Two instructions are identical if they have the same opcode and all their
733 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
734 /// Note that this means liveness related flags (dead, undef, kill) do not
735 /// affect the notion of identical.
736 bool isIdenticalTo(const MachineInstr &Other,
737 MICheckType Check = CheckDefs) const;
739 /// Unlink 'this' from the containing basic block, and return it without
742 /// This function can not be used on bundled instructions, use
743 /// removeFromBundle() to remove individual instructions from a bundle.
744 MachineInstr *removeFromParent();
746 /// Unlink this instruction from its basic block and return it without
749 /// If the instruction is part of a bundle, the other instructions in the
750 /// bundle remain bundled.
751 MachineInstr *removeFromBundle();
753 /// Unlink 'this' from the containing basic block and delete it.
755 /// If this instruction is the header of a bundle, the whole bundle is erased.
756 /// This function can not be used for instructions inside a bundle, use
757 /// eraseFromBundle() to erase individual bundled instructions.
758 void eraseFromParent();
760 /// Unlink 'this' from the containing basic block and delete it.
762 /// For all definitions mark their uses in DBG_VALUE nodes
763 /// as undefined. Otherwise like eraseFromParent().
764 void eraseFromParentAndMarkDBGValuesForRemoval();
766 /// Unlink 'this' form its basic block and delete it.
768 /// If the instruction is part of a bundle, the other instructions in the
769 /// bundle remain bundled.
770 void eraseFromBundle();
772 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
773 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
775 /// Returns true if the MachineInstr represents a label.
776 bool isLabel() const { return isEHLabel() || isGCLabel(); }
778 bool isCFIInstruction() const {
779 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
782 // True if the instruction represents a position in the function.
783 bool isPosition() const { return isLabel() || isCFIInstruction(); }
785 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
787 /// A DBG_VALUE is indirect iff the first operand is a register and
788 /// the second operand is an immediate.
789 bool isIndirectDebugValue() const {
790 return isDebugValue()
791 && getOperand(0).isReg()
792 && getOperand(1).isImm();
795 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
796 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
797 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
798 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
800 bool isMSInlineAsm() const {
801 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
804 bool isStackAligningInlineAsm() const;
805 InlineAsm::AsmDialect getInlineAsmDialect() const;
807 bool isInsertSubreg() const {
808 return getOpcode() == TargetOpcode::INSERT_SUBREG;
811 bool isSubregToReg() const {
812 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
815 bool isRegSequence() const {
816 return getOpcode() == TargetOpcode::REG_SEQUENCE;
819 bool isBundle() const {
820 return getOpcode() == TargetOpcode::BUNDLE;
823 bool isCopy() const {
824 return getOpcode() == TargetOpcode::COPY;
827 bool isFullCopy() const {
828 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
831 bool isExtractSubreg() const {
832 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
835 /// Return true if the instruction behaves like a copy.
836 /// This does not include native copy instructions.
837 bool isCopyLike() const {
838 return isCopy() || isSubregToReg();
841 /// Return true is the instruction is an identity copy.
842 bool isIdentityCopy() const {
843 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
844 getOperand(0).getSubReg() == getOperand(1).getSubReg();
847 /// Return true if this instruction doesn't produce any output in the form of
848 /// executable instructions.
849 bool isMetaInstruction() const {
850 switch (getOpcode()) {
853 case TargetOpcode::IMPLICIT_DEF:
854 case TargetOpcode::KILL:
855 case TargetOpcode::CFI_INSTRUCTION:
856 case TargetOpcode::EH_LABEL:
857 case TargetOpcode::GC_LABEL:
858 case TargetOpcode::DBG_VALUE:
863 /// Return true if this is a transient instruction that is either very likely
864 /// to be eliminated during register allocation (such as copy-like
865 /// instructions), or if this instruction doesn't have an execution-time cost.
866 bool isTransient() const {
867 switch (getOpcode()) {
869 return isMetaInstruction();
870 // Copy-like instructions are usually eliminated during register allocation.
871 case TargetOpcode::PHI:
872 case TargetOpcode::COPY:
873 case TargetOpcode::INSERT_SUBREG:
874 case TargetOpcode::SUBREG_TO_REG:
875 case TargetOpcode::REG_SEQUENCE:
880 /// Return the number of instructions inside the MI bundle, excluding the
883 /// This is the number of instructions that MachineBasicBlock::iterator
884 /// skips, 0 for unbundled instructions.
885 unsigned getBundleSize() const;
887 /// Return true if the MachineInstr reads the specified register.
888 /// If TargetRegisterInfo is passed, then it also checks if there
889 /// is a read of a super-register.
890 /// This does not count partial redefines of virtual registers as reads:
892 bool readsRegister(unsigned Reg,
893 const TargetRegisterInfo *TRI = nullptr) const {
894 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
897 /// Return true if the MachineInstr reads the specified virtual register.
898 /// Take into account that a partial define is a
899 /// read-modify-write operation.
900 bool readsVirtualRegister(unsigned Reg) const {
901 return readsWritesVirtualRegister(Reg).first;
904 /// Return a pair of bools (reads, writes) indicating if this instruction
905 /// reads or writes Reg. This also considers partial defines.
906 /// If Ops is not null, all operand indices for Reg are added.
907 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
908 SmallVectorImpl<unsigned> *Ops = nullptr) const;
910 /// Return true if the MachineInstr kills the specified register.
911 /// If TargetRegisterInfo is passed, then it also checks if there is
912 /// a kill of a super-register.
913 bool killsRegister(unsigned Reg,
914 const TargetRegisterInfo *TRI = nullptr) const {
915 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
918 /// Return true if the MachineInstr fully defines the specified register.
919 /// If TargetRegisterInfo is passed, then it also checks
920 /// if there is a def of a super-register.
921 /// NOTE: It's ignoring subreg indices on virtual registers.
922 bool definesRegister(unsigned Reg,
923 const TargetRegisterInfo *TRI = nullptr) const {
924 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
927 /// Return true if the MachineInstr modifies (fully define or partially
928 /// define) the specified register.
929 /// NOTE: It's ignoring subreg indices on virtual registers.
930 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
931 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
934 /// Returns true if the register is dead in this machine instruction.
935 /// If TargetRegisterInfo is passed, then it also checks
936 /// if there is a dead def of a super-register.
937 bool registerDefIsDead(unsigned Reg,
938 const TargetRegisterInfo *TRI = nullptr) const {
939 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
942 /// Returns true if the MachineInstr has an implicit-use operand of exactly
943 /// the given register (not considering sub/super-registers).
944 bool hasRegisterImplicitUseOperand(unsigned Reg) const;
946 /// Returns the operand index that is a use of the specific register or -1
947 /// if it is not found. It further tightens the search criteria to a use
948 /// that kills the register if isKill is true.
949 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
950 const TargetRegisterInfo *TRI = nullptr) const;
952 /// Wrapper for findRegisterUseOperandIdx, it returns
953 /// a pointer to the MachineOperand rather than an index.
954 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
955 const TargetRegisterInfo *TRI = nullptr) {
956 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
957 return (Idx == -1) ? nullptr : &getOperand(Idx);
960 const MachineOperand *findRegisterUseOperand(
961 unsigned Reg, bool isKill = false,
962 const TargetRegisterInfo *TRI = nullptr) const {
963 return const_cast<MachineInstr *>(this)->
964 findRegisterUseOperand(Reg, isKill, TRI);
967 /// Returns the operand index that is a def of the specified register or
968 /// -1 if it is not found. If isDead is true, defs that are not dead are
969 /// skipped. If Overlap is true, then it also looks for defs that merely
970 /// overlap the specified register. If TargetRegisterInfo is non-null,
971 /// then it also checks if there is a def of a super-register.
972 /// This may also return a register mask operand when Overlap is true.
973 int findRegisterDefOperandIdx(unsigned Reg,
974 bool isDead = false, bool Overlap = false,
975 const TargetRegisterInfo *TRI = nullptr) const;
977 /// Wrapper for findRegisterDefOperandIdx, it returns
978 /// a pointer to the MachineOperand rather than an index.
979 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
980 const TargetRegisterInfo *TRI = nullptr) {
981 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
982 return (Idx == -1) ? nullptr : &getOperand(Idx);
985 /// Find the index of the first operand in the
986 /// operand list that is used to represent the predicate. It returns -1 if
988 int findFirstPredOperandIdx() const;
990 /// Find the index of the flag word operand that
991 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
992 /// getOperand(OpIdx) does not belong to an inline asm operand group.
994 /// If GroupNo is not NULL, it will receive the number of the operand group
995 /// containing OpIdx.
997 /// The flag operand is an immediate that can be decoded with methods like
998 /// InlineAsm::hasRegClassConstraint().
999 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1001 /// Compute the static register class constraint for operand OpIdx.
1002 /// For normal instructions, this is derived from the MCInstrDesc.
1003 /// For inline assembly it is derived from the flag words.
1005 /// Returns NULL if the static register class constraint cannot be
1007 const TargetRegisterClass*
1008 getRegClassConstraint(unsigned OpIdx,
1009 const TargetInstrInfo *TII,
1010 const TargetRegisterInfo *TRI) const;
1012 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
1013 /// the given \p CurRC.
1014 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1015 /// instructions inside the bundle will be taken into account. In other words,
1016 /// this method accumulates all the constraints of the operand of this MI and
1017 /// the related bundle if MI is a bundle or inside a bundle.
1019 /// Returns the register class that satisfies both \p CurRC and the
1020 /// constraints set by MI. Returns NULL if such a register class does not
1023 /// \pre CurRC must not be NULL.
1024 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1025 unsigned Reg, const TargetRegisterClass *CurRC,
1026 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1027 bool ExploreBundle = false) const;
1029 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
1030 /// to the given \p CurRC.
1032 /// Returns the register class that satisfies both \p CurRC and the
1033 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1036 /// \pre CurRC must not be NULL.
1037 /// \pre The operand at \p OpIdx must be a register.
1038 const TargetRegisterClass *
1039 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1040 const TargetInstrInfo *TII,
1041 const TargetRegisterInfo *TRI) const;
1043 /// Add a tie between the register operands at DefIdx and UseIdx.
1044 /// The tie will cause the register allocator to ensure that the two
1045 /// operands are assigned the same physical register.
1047 /// Tied operands are managed automatically for explicit operands in the
1048 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1049 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1051 /// Given the index of a tied register operand, find the
1052 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1053 /// index of the tied operand which must exist.
1054 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1056 /// Given the index of a register def operand,
1057 /// check if the register def is tied to a source operand, due to either
1058 /// two-address elimination or inline assembly constraints. Returns the
1059 /// first tied use operand index by reference if UseOpIdx is not null.
1060 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1061 unsigned *UseOpIdx = nullptr) const {
1062 const MachineOperand &MO = getOperand(DefOpIdx);
1063 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1066 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1070 /// Return true if the use operand of the specified index is tied to a def
1071 /// operand. It also returns the def operand index by reference if DefOpIdx
1073 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1074 unsigned *DefOpIdx = nullptr) const {
1075 const MachineOperand &MO = getOperand(UseOpIdx);
1076 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1079 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1083 /// Clears kill flags on all operands.
1084 void clearKillInfo();
1086 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1087 /// properly composing subreg indices where necessary.
1088 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1089 const TargetRegisterInfo &RegInfo);
1091 /// We have determined MI kills a register. Look for the
1092 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1093 /// add a implicit operand if it's not found. Returns true if the operand
1094 /// exists / is added.
1095 bool addRegisterKilled(unsigned IncomingReg,
1096 const TargetRegisterInfo *RegInfo,
1097 bool AddIfNotFound = false);
1099 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1100 /// all aliasing registers.
1101 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1103 /// We have determined MI defined a register without a use.
1104 /// Look for the operand that defines it and mark it as IsDead. If
1105 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1106 /// true if the operand exists / is added.
1107 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1108 bool AddIfNotFound = false);
1110 /// Clear all dead flags on operands defining register @p Reg.
1111 void clearRegisterDeads(unsigned Reg);
1113 /// Mark all subregister defs of register @p Reg with the undef flag.
1114 /// This function is used when we determined to have a subregister def in an
1115 /// otherwise undefined super register.
1116 void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1118 /// We have determined MI defines a register. Make sure there is an operand
1120 void addRegisterDefined(unsigned Reg,
1121 const TargetRegisterInfo *RegInfo = nullptr);
1123 /// Mark every physreg used by this instruction as
1124 /// dead except those in the UsedRegs list.
1126 /// On instructions with register mask operands, also add implicit-def
1127 /// operands for all registers in UsedRegs.
1128 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1129 const TargetRegisterInfo &TRI);
1131 /// Return true if it is safe to move this instruction. If
1132 /// SawStore is set to true, it means that there is a store (or call) between
1133 /// the instruction's location and its intended destination.
1134 bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1136 /// Returns true if this instruction's memory access aliases the memory
1137 /// access of Other.
1139 /// Assumes any physical registers used to compute addresses
1140 /// have the same value for both instructions. Returns false if neither
1141 /// instruction writes to memory.
1143 /// @param AA Optional alias analysis, used to compare memory operands.
1144 /// @param Other MachineInstr to check aliasing against.
1145 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1146 bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA);
1148 /// Return true if this instruction may have an ordered
1149 /// or volatile memory reference, or if the information describing the memory
1150 /// reference is not available. Return false if it is known to have no
1151 /// ordered or volatile memory references.
1152 bool hasOrderedMemoryRef() const;
1154 /// Return true if this load instruction never traps and points to a memory
1155 /// location whose value doesn't change during the execution of this function.
1157 /// Examples include loading a value from the constant pool or from the
1158 /// argument area of a function (if it does not change). If the instruction
1159 /// does multiple loads, this returns true only if all of the loads are
1160 /// dereferenceable and invariant.
1161 bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
1163 /// If the specified instruction is a PHI that always merges together the
1164 /// same virtual register, return the register, otherwise return 0.
1165 unsigned isConstantValuePHI() const;
1167 /// Return true if this instruction has side effects that are not modeled
1168 /// by mayLoad / mayStore, etc.
1169 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1170 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1171 /// INLINEASM instruction, in which case the side effect property is encoded
1172 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1174 bool hasUnmodeledSideEffects() const;
1176 /// Returns true if it is illegal to fold a load across this instruction.
1177 bool isLoadFoldBarrier() const;
1179 /// Return true if all the defs of this instruction are dead.
1180 bool allDefsAreDead() const;
1182 /// Copy implicit register operands from specified
1183 /// instruction to this instruction.
1184 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1186 /// Debugging support
1188 /// Print this MI to \p OS.
1189 /// Only print the defs and the opcode if \p SkipOpers is true.
1190 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1191 /// Otherwise, also print the debug loc, with a terminating newline.
1192 /// \p TII is used to print the opcode name. If it's not present, but the
1193 /// MI is in a function, the opcode will be printed using the function's TII.
1194 void print(raw_ostream &OS, bool SkipOpers = false, bool SkipDebugLoc = false,
1195 const TargetInstrInfo *TII = nullptr) const;
1196 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool SkipOpers = false,
1197 bool SkipDebugLoc = false,
1198 const TargetInstrInfo *TII = nullptr) const;
1202 //===--------------------------------------------------------------------===//
1203 // Accessors used to build up machine instructions.
1205 /// Add the specified operand to the instruction. If it is an implicit
1206 /// operand, it is added to the end of the operand list. If it is an
1207 /// explicit operand it is added at the end of the explicit operand list
1208 /// (before the first implicit operand).
1210 /// MF must be the machine function that was used to allocate this
1213 /// MachineInstrBuilder provides a more convenient interface for creating
1214 /// instructions and adding operands.
1215 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1217 /// Add an operand without providing an MF reference. This only works for
1218 /// instructions that are inserted in a basic block.
1220 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1222 void addOperand(const MachineOperand &Op);
1224 /// Replace the instruction descriptor (thus opcode) of
1225 /// the current instruction with a new one.
1226 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1228 /// Replace current source information with new such.
1229 /// Avoid using this, the constructor argument is preferable.
1230 void setDebugLoc(DebugLoc dl) {
1231 debugLoc = std::move(dl);
1232 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1235 /// Erase an operand from an instruction, leaving it with one
1236 /// fewer operand than it started with.
1237 void RemoveOperand(unsigned i);
1239 /// Add a MachineMemOperand to the machine instruction.
1240 /// This function should be used only occasionally. The setMemRefs function
1241 /// is the primary method for setting up a MachineInstr's MemRefs list.
1242 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1244 /// Assign this MachineInstr's memory reference descriptor list.
1245 /// This does not transfer ownership.
1246 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1247 setMemRefs(std::make_pair(NewMemRefs, NewMemRefsEnd-NewMemRefs));
1250 /// Assign this MachineInstr's memory reference descriptor list. First
1251 /// element in the pair is the begin iterator/pointer to the array; the
1252 /// second is the number of MemoryOperands. This does not transfer ownership
1253 /// of the underlying memory.
1254 void setMemRefs(std::pair<mmo_iterator, unsigned> NewMemRefs) {
1255 MemRefs = NewMemRefs.first;
1256 NumMemRefs = uint8_t(NewMemRefs.second);
1257 assert(NumMemRefs == NewMemRefs.second &&
1258 "Too many memrefs - must drop memory operands");
1261 /// Return a set of memrefs (begin iterator, size) which conservatively
1262 /// describe the memory behavior of both MachineInstrs. This is appropriate
1263 /// for use when merging two MachineInstrs into one. This routine does not
1264 /// modify the memrefs of the this MachineInstr.
1265 std::pair<mmo_iterator, unsigned> mergeMemRefsWith(const MachineInstr& Other);
1267 /// Clear this MachineInstr's memory reference descriptor list. This resets
1268 /// the memrefs to their most conservative state. This should be used only
1269 /// as a last resort since it greatly pessimizes our knowledge of the memory
1270 /// access performed by the instruction.
1271 void dropMemRefs() {
1276 /// Break any tie involving OpIdx.
1277 void untieRegOperand(unsigned OpIdx) {
1278 MachineOperand &MO = getOperand(OpIdx);
1279 if (MO.isReg() && MO.isTied()) {
1280 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1285 /// Add all implicit def and use operands to this instruction.
1286 void addImplicitDefUseOperands(MachineFunction &MF);
1289 /// If this instruction is embedded into a MachineFunction, return the
1290 /// MachineRegisterInfo object for the current function, otherwise
1292 MachineRegisterInfo *getRegInfo();
1294 /// Unlink all of the register operands in this instruction from their
1295 /// respective use lists. This requires that the operands already be on their
1297 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1299 /// Add all of the register operands in this instruction from their
1300 /// respective use lists. This requires that the operands not be on their
1302 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1304 /// Slow path for hasProperty when we're dealing with a bundle.
1305 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1307 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1308 /// this MI and the given operand index \p OpIdx.
1309 /// If the related operand does not constrained Reg, this returns CurRC.
1310 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1311 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1312 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1315 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1316 /// instruction rather than by pointer value.
1317 /// The hashing and equality testing functions ignore definitions so this is
1318 /// useful for CSE, etc.
1319 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1320 static inline MachineInstr *getEmptyKey() {
1324 static inline MachineInstr *getTombstoneKey() {
1325 return reinterpret_cast<MachineInstr*>(-1);
1328 static unsigned getHashValue(const MachineInstr* const &MI);
1330 static bool isEqual(const MachineInstr* const &LHS,
1331 const MachineInstr* const &RHS) {
1332 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1333 LHS == getEmptyKey() || LHS == getTombstoneKey())
1335 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1339 //===----------------------------------------------------------------------===//
1340 // Debugging Support
1342 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1347 } // end namespace llvm
1349 #endif // LLVM_CODEGEN_MACHINEINSTR_H