1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/ilist.h"
21 #include "llvm/ADT/ilist_node.h"
22 #include "llvm/ADT/iterator_range.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/IR/InlineAsm.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/Support/ArrayRecycler.h"
29 #include "llvm/Target/TargetOpcodes.h"
37 template <typename T> class ArrayRef;
39 class DILocalVariable;
40 class MachineBasicBlock;
41 class MachineFunction;
42 class MachineMemOperand;
43 class MachineRegisterInfo;
44 class ModuleSlotTracker;
46 template <typename T> class SmallVectorImpl;
48 class TargetInstrInfo;
49 class TargetRegisterClass;
50 class TargetRegisterInfo;
52 //===----------------------------------------------------------------------===//
53 /// Representation of each machine instruction.
55 /// This class isn't a POD type, but it must have a trivial destructor. When a
56 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
57 /// without having their destructor called.
60 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
61 ilist_sentinel_tracking<true>> {
63 using mmo_iterator = MachineMemOperand **;
65 /// Flags to specify different kinds of comments to output in
66 /// assembly code. These flags carry semantic information not
67 /// otherwise easily derivable from the IR text.
70 ReloadReuse = 0x1 // higher bits are reserved for target dep comments.
75 FrameSetup = 1 << 0, // Instruction is used as a part of
76 // function frame setup code.
77 FrameDestroy = 1 << 1, // Instruction is used as a part of
78 // function frame destruction code.
79 BundledPred = 1 << 2, // Instruction has bundled predecessors.
80 BundledSucc = 1 << 3 // Instruction has bundled successors.
84 const MCInstrDesc *MCID; // Instruction descriptor.
85 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
87 // Operands are allocated by an ArrayRecycler.
88 MachineOperand *Operands = nullptr; // Pointer to the first operand.
89 unsigned NumOperands = 0; // Number of operands on instruction.
90 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
91 OperandCapacity CapOperands; // Capacity of the Operands array.
93 uint8_t Flags = 0; // Various bits of additional
94 // information about machine
97 uint8_t AsmPrinterFlags = 0; // Various bits of information used by
98 // the AsmPrinter to emit helpful
99 // comments. This is *not* semantic
100 // information. Do not use this for
101 // anything other than to convey comment
102 // information to AsmPrinter.
104 uint8_t NumMemRefs = 0; // Information on memory references.
105 // Note that MemRefs == nullptr, means 'don't know', not 'no memory access'.
106 // Calling code must treat missing information conservatively. If the number
107 // of memory operands required to be precise exceeds the maximum value of
108 // NumMemRefs - currently 256 - we remove the operands entirely. Note also
109 // that this is a non-owning reference to a shared copy on write buffer owned
110 // by the MachineFunction and created via MF.allocateMemRefsArray.
111 mmo_iterator MemRefs = nullptr;
113 DebugLoc debugLoc; // Source line information.
115 // Intrusive list support
116 friend struct ilist_traits<MachineInstr>;
117 friend struct ilist_callback_traits<MachineBasicBlock>;
118 void setParent(MachineBasicBlock *P) { Parent = P; }
120 /// This constructor creates a copy of the given
121 /// MachineInstr in the given MachineFunction.
122 MachineInstr(MachineFunction &, const MachineInstr &);
124 /// This constructor create a MachineInstr and add the implicit operands.
125 /// It reserves space for number of operands specified by
126 /// MCInstrDesc. An explicit DebugLoc is supplied.
127 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
130 // MachineInstrs are pool-allocated and owned by MachineFunction.
131 friend class MachineFunction;
134 MachineInstr(const MachineInstr &) = delete;
135 MachineInstr &operator=(const MachineInstr &) = delete;
136 // Use MachineFunction::DeleteMachineInstr() instead.
137 ~MachineInstr() = delete;
139 const MachineBasicBlock* getParent() const { return Parent; }
140 MachineBasicBlock* getParent() { return Parent; }
142 /// Return the asm printer flags bitvector.
143 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
145 /// Clear the AsmPrinter bitvector.
146 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
148 /// Return whether an AsmPrinter flag is set.
149 bool getAsmPrinterFlag(CommentFlag Flag) const {
150 return AsmPrinterFlags & Flag;
153 /// Set a flag for the AsmPrinter.
154 void setAsmPrinterFlag(uint8_t Flag) {
155 AsmPrinterFlags |= Flag;
158 /// Clear specific AsmPrinter flags.
159 void clearAsmPrinterFlag(CommentFlag Flag) {
160 AsmPrinterFlags &= ~Flag;
163 /// Return the MI flags bitvector.
164 uint8_t getFlags() const {
168 /// Return whether an MI flag is set.
169 bool getFlag(MIFlag Flag) const {
174 void setFlag(MIFlag Flag) {
175 Flags |= (uint8_t)Flag;
178 void setFlags(unsigned flags) {
179 // Filter out the automatically maintained flags.
180 unsigned Mask = BundledPred | BundledSucc;
181 Flags = (Flags & Mask) | (flags & ~Mask);
184 /// clearFlag - Clear a MI flag.
185 void clearFlag(MIFlag Flag) {
186 Flags &= ~((uint8_t)Flag);
189 /// Return true if MI is in a bundle (but not the first MI in a bundle).
191 /// A bundle looks like this before it's finalized:
203 /// In this case, the first MI starts a bundle but is not inside a bundle, the
204 /// next 2 MIs are considered "inside" the bundle.
206 /// After a bundle is finalized, it looks like this:
222 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
223 /// a bundle, but the next three MIs are.
224 bool isInsideBundle() const {
225 return getFlag(BundledPred);
228 /// Return true if this instruction part of a bundle. This is true
229 /// if either itself or its following instruction is marked "InsideBundle".
230 bool isBundled() const {
231 return isBundledWithPred() || isBundledWithSucc();
234 /// Return true if this instruction is part of a bundle, and it is not the
235 /// first instruction in the bundle.
236 bool isBundledWithPred() const { return getFlag(BundledPred); }
238 /// Return true if this instruction is part of a bundle, and it is not the
239 /// last instruction in the bundle.
240 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
242 /// Bundle this instruction with its predecessor. This can be an unbundled
243 /// instruction, or it can be the first instruction in a bundle.
244 void bundleWithPred();
246 /// Bundle this instruction with its successor. This can be an unbundled
247 /// instruction, or it can be the last instruction in a bundle.
248 void bundleWithSucc();
250 /// Break bundle above this instruction.
251 void unbundleFromPred();
253 /// Break bundle below this instruction.
254 void unbundleFromSucc();
256 /// Returns the debug location id of this MachineInstr.
257 const DebugLoc &getDebugLoc() const { return debugLoc; }
259 /// Return the debug variable referenced by
260 /// this DBG_VALUE instruction.
261 const DILocalVariable *getDebugVariable() const;
263 /// Return the complex address expression referenced by
264 /// this DBG_VALUE instruction.
265 const DIExpression *getDebugExpression() const;
267 /// Emit an error referring to the source location of this instruction.
268 /// This should only be used for inline assembly that is somehow
269 /// impossible to compile. Other errors should have been handled much
272 /// If this method returns, the caller should try to recover from the error.
273 void emitError(StringRef Msg) const;
275 /// Returns the target instruction descriptor of this MachineInstr.
276 const MCInstrDesc &getDesc() const { return *MCID; }
278 /// Returns the opcode of this MachineInstr.
279 unsigned getOpcode() const { return MCID->Opcode; }
281 /// Access to explicit operands of the instruction.
282 unsigned getNumOperands() const { return NumOperands; }
284 const MachineOperand& getOperand(unsigned i) const {
285 assert(i < getNumOperands() && "getOperand() out of range!");
288 MachineOperand& getOperand(unsigned i) {
289 assert(i < getNumOperands() && "getOperand() out of range!");
293 /// Returns the number of non-implicit operands.
294 unsigned getNumExplicitOperands() const;
296 /// iterator/begin/end - Iterate over all operands of a machine instruction.
297 using mop_iterator = MachineOperand *;
298 using const_mop_iterator = const MachineOperand *;
300 mop_iterator operands_begin() { return Operands; }
301 mop_iterator operands_end() { return Operands + NumOperands; }
303 const_mop_iterator operands_begin() const { return Operands; }
304 const_mop_iterator operands_end() const { return Operands + NumOperands; }
306 iterator_range<mop_iterator> operands() {
307 return make_range(operands_begin(), operands_end());
309 iterator_range<const_mop_iterator> operands() const {
310 return make_range(operands_begin(), operands_end());
312 iterator_range<mop_iterator> explicit_operands() {
313 return make_range(operands_begin(),
314 operands_begin() + getNumExplicitOperands());
316 iterator_range<const_mop_iterator> explicit_operands() const {
317 return make_range(operands_begin(),
318 operands_begin() + getNumExplicitOperands());
320 iterator_range<mop_iterator> implicit_operands() {
321 return make_range(explicit_operands().end(), operands_end());
323 iterator_range<const_mop_iterator> implicit_operands() const {
324 return make_range(explicit_operands().end(), operands_end());
326 /// Returns a range over all explicit operands that are register definitions.
327 /// Implicit definition are not included!
328 iterator_range<mop_iterator> defs() {
329 return make_range(operands_begin(),
330 operands_begin() + getDesc().getNumDefs());
333 iterator_range<const_mop_iterator> defs() const {
334 return make_range(operands_begin(),
335 operands_begin() + getDesc().getNumDefs());
337 /// Returns a range that includes all operands that are register uses.
338 /// This may include unrelated operands which are not register uses.
339 iterator_range<mop_iterator> uses() {
340 return make_range(operands_begin() + getDesc().getNumDefs(),
344 iterator_range<const_mop_iterator> uses() const {
345 return make_range(operands_begin() + getDesc().getNumDefs(),
348 iterator_range<mop_iterator> explicit_uses() {
349 return make_range(operands_begin() + getDesc().getNumDefs(),
350 operands_begin() + getNumExplicitOperands() );
352 iterator_range<const_mop_iterator> explicit_uses() const {
353 return make_range(operands_begin() + getDesc().getNumDefs(),
354 operands_begin() + getNumExplicitOperands() );
357 /// Returns the number of the operand iterator \p I points to.
358 unsigned getOperandNo(const_mop_iterator I) const {
359 return I - operands_begin();
362 /// Access to memory operands of the instruction
363 mmo_iterator memoperands_begin() const { return MemRefs; }
364 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
365 /// Return true if we don't have any memory operands which described the the
366 /// memory access done by this instruction. If this is true, calling code
367 /// must be conservative.
368 bool memoperands_empty() const { return NumMemRefs == 0; }
370 iterator_range<mmo_iterator> memoperands() {
371 return make_range(memoperands_begin(), memoperands_end());
373 iterator_range<mmo_iterator> memoperands() const {
374 return make_range(memoperands_begin(), memoperands_end());
377 /// Return true if this instruction has exactly one MachineMemOperand.
378 bool hasOneMemOperand() const {
379 return NumMemRefs == 1;
382 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
383 /// queries but they are bundle aware.
386 IgnoreBundle, // Ignore bundles
387 AnyInBundle, // Return true if any instruction in bundle has property
388 AllInBundle // Return true if all instructions in bundle have property
391 /// Return true if the instruction (or in the case of a bundle,
392 /// the instructions inside the bundle) has the specified property.
393 /// The first argument is the property being queried.
394 /// The second argument indicates whether the query should look inside
395 /// instruction bundles.
396 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
397 // Inline the fast path for unbundled or bundle-internal instructions.
398 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
399 return getDesc().getFlags() & (1ULL << MCFlag);
401 // If this is the first instruction in a bundle, take the slow path.
402 return hasPropertyInBundle(1ULL << MCFlag, Type);
405 /// Return true if this instruction can have a variable number of operands.
406 /// In this case, the variable operands will be after the normal
407 /// operands but before the implicit definitions and uses (if any are
409 bool isVariadic(QueryType Type = IgnoreBundle) const {
410 return hasProperty(MCID::Variadic, Type);
413 /// Set if this instruction has an optional definition, e.g.
414 /// ARM instructions which can set condition code if 's' bit is set.
415 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
416 return hasProperty(MCID::HasOptionalDef, Type);
419 /// Return true if this is a pseudo instruction that doesn't
420 /// correspond to a real machine instruction.
421 bool isPseudo(QueryType Type = IgnoreBundle) const {
422 return hasProperty(MCID::Pseudo, Type);
425 bool isReturn(QueryType Type = AnyInBundle) const {
426 return hasProperty(MCID::Return, Type);
429 bool isCall(QueryType Type = AnyInBundle) const {
430 return hasProperty(MCID::Call, Type);
433 /// Returns true if the specified instruction stops control flow
434 /// from executing the instruction immediately following it. Examples include
435 /// unconditional branches and return instructions.
436 bool isBarrier(QueryType Type = AnyInBundle) const {
437 return hasProperty(MCID::Barrier, Type);
440 /// Returns true if this instruction part of the terminator for a basic block.
441 /// Typically this is things like return and branch instructions.
443 /// Various passes use this to insert code into the bottom of a basic block,
444 /// but before control flow occurs.
445 bool isTerminator(QueryType Type = AnyInBundle) const {
446 return hasProperty(MCID::Terminator, Type);
449 /// Returns true if this is a conditional, unconditional, or indirect branch.
450 /// Predicates below can be used to discriminate between
451 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
452 /// get more information.
453 bool isBranch(QueryType Type = AnyInBundle) const {
454 return hasProperty(MCID::Branch, Type);
457 /// Return true if this is an indirect branch, such as a
458 /// branch through a register.
459 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
460 return hasProperty(MCID::IndirectBranch, Type);
463 /// Return true if this is a branch which may fall
464 /// through to the next instruction or may transfer control flow to some other
465 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
466 /// information about this branch.
467 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
468 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
471 /// Return true if this is a branch which always
472 /// transfers control flow to some other block. The
473 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
474 /// about this branch.
475 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
476 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
479 /// Return true if this instruction has a predicate operand that
480 /// controls execution. It may be set to 'always', or may be set to other
481 /// values. There are various methods in TargetInstrInfo that can be used to
482 /// control and modify the predicate in this instruction.
483 bool isPredicable(QueryType Type = AllInBundle) const {
484 // If it's a bundle than all bundled instructions must be predicable for this
486 return hasProperty(MCID::Predicable, Type);
489 /// Return true if this instruction is a comparison.
490 bool isCompare(QueryType Type = IgnoreBundle) const {
491 return hasProperty(MCID::Compare, Type);
494 /// Return true if this instruction is a move immediate
495 /// (including conditional moves) instruction.
496 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
497 return hasProperty(MCID::MoveImm, Type);
500 /// Return true if this instruction is a bitcast instruction.
501 bool isBitcast(QueryType Type = IgnoreBundle) const {
502 return hasProperty(MCID::Bitcast, Type);
505 /// Return true if this instruction is a select instruction.
506 bool isSelect(QueryType Type = IgnoreBundle) const {
507 return hasProperty(MCID::Select, Type);
510 /// Return true if this instruction cannot be safely duplicated.
511 /// For example, if the instruction has a unique labels attached
512 /// to it, duplicating it would cause multiple definition errors.
513 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
514 return hasProperty(MCID::NotDuplicable, Type);
517 /// Return true if this instruction is convergent.
518 /// Convergent instructions can not be made control-dependent on any
519 /// additional values.
520 bool isConvergent(QueryType Type = AnyInBundle) const {
522 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
523 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
526 return hasProperty(MCID::Convergent, Type);
529 /// Returns true if the specified instruction has a delay slot
530 /// which must be filled by the code generator.
531 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
532 return hasProperty(MCID::DelaySlot, Type);
535 /// Return true for instructions that can be folded as
536 /// memory operands in other instructions. The most common use for this
537 /// is instructions that are simple loads from memory that don't modify
538 /// the loaded value in any way, but it can also be used for instructions
539 /// that can be expressed as constant-pool loads, such as V_SETALLONES
540 /// on x86, to allow them to be folded when it is beneficial.
541 /// This should only be set on instructions that return a value in their
542 /// only virtual register definition.
543 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
544 return hasProperty(MCID::FoldableAsLoad, Type);
547 /// \brief Return true if this instruction behaves
548 /// the same way as the generic REG_SEQUENCE instructions.
550 /// dX VMOVDRR rY, rZ
552 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
554 /// Note that for the optimizers to be able to take advantage of
555 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
556 /// override accordingly.
557 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
558 return hasProperty(MCID::RegSequence, Type);
561 /// \brief Return true if this instruction behaves
562 /// the same way as the generic EXTRACT_SUBREG instructions.
564 /// rX, rY VMOVRRD dZ
565 /// is equivalent to two EXTRACT_SUBREG:
566 /// rX = EXTRACT_SUBREG dZ, ssub_0
567 /// rY = EXTRACT_SUBREG dZ, ssub_1
569 /// Note that for the optimizers to be able to take advantage of
570 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
571 /// override accordingly.
572 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
573 return hasProperty(MCID::ExtractSubreg, Type);
576 /// \brief Return true if this instruction behaves
577 /// the same way as the generic INSERT_SUBREG instructions.
579 /// dX = VSETLNi32 dY, rZ, Imm
580 /// is equivalent to a INSERT_SUBREG:
581 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
583 /// Note that for the optimizers to be able to take advantage of
584 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
585 /// override accordingly.
586 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
587 return hasProperty(MCID::InsertSubreg, Type);
590 //===--------------------------------------------------------------------===//
591 // Side Effect Analysis
592 //===--------------------------------------------------------------------===//
594 /// Return true if this instruction could possibly read memory.
595 /// Instructions with this flag set are not necessarily simple load
596 /// instructions, they may load a value and modify it, for example.
597 bool mayLoad(QueryType Type = AnyInBundle) const {
599 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
600 if (ExtraInfo & InlineAsm::Extra_MayLoad)
603 return hasProperty(MCID::MayLoad, Type);
606 /// Return true if this instruction could possibly modify memory.
607 /// Instructions with this flag set are not necessarily simple store
608 /// instructions, they may store a modified value based on their operands, or
609 /// may not actually modify anything, for example.
610 bool mayStore(QueryType Type = AnyInBundle) const {
612 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
613 if (ExtraInfo & InlineAsm::Extra_MayStore)
616 return hasProperty(MCID::MayStore, Type);
619 /// Return true if this instruction could possibly read or modify memory.
620 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
621 return mayLoad(Type) || mayStore(Type);
624 //===--------------------------------------------------------------------===//
625 // Flags that indicate whether an instruction can be modified by a method.
626 //===--------------------------------------------------------------------===//
628 /// Return true if this may be a 2- or 3-address
629 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
630 /// result if Y and Z are exchanged. If this flag is set, then the
631 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
634 /// Note that this flag may be set on instructions that are only commutable
635 /// sometimes. In these cases, the call to commuteInstruction will fail.
636 /// Also note that some instructions require non-trivial modification to
638 bool isCommutable(QueryType Type = IgnoreBundle) const {
639 return hasProperty(MCID::Commutable, Type);
642 /// Return true if this is a 2-address instruction
643 /// which can be changed into a 3-address instruction if needed. Doing this
644 /// transformation can be profitable in the register allocator, because it
645 /// means that the instruction can use a 2-address form if possible, but
646 /// degrade into a less efficient form if the source and dest register cannot
647 /// be assigned to the same register. For example, this allows the x86
648 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
649 /// is the same speed as the shift but has bigger code size.
651 /// If this returns true, then the target must implement the
652 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
653 /// is allowed to fail if the transformation isn't valid for this specific
654 /// instruction (e.g. shl reg, 4 on x86).
656 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
657 return hasProperty(MCID::ConvertibleTo3Addr, Type);
660 /// Return true if this instruction requires
661 /// custom insertion support when the DAG scheduler is inserting it into a
662 /// machine basic block. If this is true for the instruction, it basically
663 /// means that it is a pseudo instruction used at SelectionDAG time that is
664 /// expanded out into magic code by the target when MachineInstrs are formed.
666 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
667 /// is used to insert this into the MachineBasicBlock.
668 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
669 return hasProperty(MCID::UsesCustomInserter, Type);
672 /// Return true if this instruction requires *adjustment*
673 /// after instruction selection by calling a target hook. For example, this
674 /// can be used to fill in ARM 's' optional operand depending on whether
675 /// the conditional flag register is used.
676 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
677 return hasProperty(MCID::HasPostISelHook, Type);
680 /// Returns true if this instruction is a candidate for remat.
681 /// This flag is deprecated, please don't use it anymore. If this
682 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
683 /// verify the instruction is really rematable.
684 bool isRematerializable(QueryType Type = AllInBundle) const {
685 // It's only possible to re-mat a bundle if all bundled instructions are
686 // re-materializable.
687 return hasProperty(MCID::Rematerializable, Type);
690 /// Returns true if this instruction has the same cost (or less) than a move
691 /// instruction. This is useful during certain types of optimizations
692 /// (e.g., remat during two-address conversion or machine licm)
693 /// where we would like to remat or hoist the instruction, but not if it costs
694 /// more than moving the instruction into the appropriate register. Note, we
695 /// are not marking copies from and to the same register class with this flag.
696 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
697 // Only returns true for a bundle if all bundled instructions are cheap.
698 return hasProperty(MCID::CheapAsAMove, Type);
701 /// Returns true if this instruction source operands
702 /// have special register allocation requirements that are not captured by the
703 /// operand register classes. e.g. ARM::STRD's two source registers must be an
704 /// even / odd pair, ARM::STM registers have to be in ascending order.
705 /// Post-register allocation passes should not attempt to change allocations
706 /// for sources of instructions with this flag.
707 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
708 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
711 /// Returns true if this instruction def operands
712 /// have special register allocation requirements that are not captured by the
713 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
714 /// even / odd pair, ARM::LDM registers have to be in ascending order.
715 /// Post-register allocation passes should not attempt to change allocations
716 /// for definitions of instructions with this flag.
717 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
718 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
722 CheckDefs, // Check all operands for equality
723 CheckKillDead, // Check all operands including kill / dead markers
724 IgnoreDefs, // Ignore all definitions
725 IgnoreVRegDefs // Ignore virtual register definitions
728 /// Return true if this instruction is identical to \p Other.
729 /// Two instructions are identical if they have the same opcode and all their
730 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
731 /// Note that this means liveness related flags (dead, undef, kill) do not
732 /// affect the notion of identical.
733 bool isIdenticalTo(const MachineInstr &Other,
734 MICheckType Check = CheckDefs) const;
736 /// Unlink 'this' from the containing basic block, and return it without
739 /// This function can not be used on bundled instructions, use
740 /// removeFromBundle() to remove individual instructions from a bundle.
741 MachineInstr *removeFromParent();
743 /// Unlink this instruction from its basic block and return it without
746 /// If the instruction is part of a bundle, the other instructions in the
747 /// bundle remain bundled.
748 MachineInstr *removeFromBundle();
750 /// Unlink 'this' from the containing basic block and delete it.
752 /// If this instruction is the header of a bundle, the whole bundle is erased.
753 /// This function can not be used for instructions inside a bundle, use
754 /// eraseFromBundle() to erase individual bundled instructions.
755 void eraseFromParent();
757 /// Unlink 'this' from the containing basic block and delete it.
759 /// For all definitions mark their uses in DBG_VALUE nodes
760 /// as undefined. Otherwise like eraseFromParent().
761 void eraseFromParentAndMarkDBGValuesForRemoval();
763 /// Unlink 'this' form its basic block and delete it.
765 /// If the instruction is part of a bundle, the other instructions in the
766 /// bundle remain bundled.
767 void eraseFromBundle();
769 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
770 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
772 /// Returns true if the MachineInstr represents a label.
773 bool isLabel() const { return isEHLabel() || isGCLabel(); }
775 bool isCFIInstruction() const {
776 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
779 // True if the instruction represents a position in the function.
780 bool isPosition() const { return isLabel() || isCFIInstruction(); }
782 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
784 /// A DBG_VALUE is indirect iff the first operand is a register and
785 /// the second operand is an immediate.
786 bool isIndirectDebugValue() const {
787 return isDebugValue()
788 && getOperand(0).isReg()
789 && getOperand(1).isImm();
792 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
793 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
794 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
795 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
797 bool isMSInlineAsm() const {
798 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
801 bool isStackAligningInlineAsm() const;
802 InlineAsm::AsmDialect getInlineAsmDialect() const;
804 bool isInsertSubreg() const {
805 return getOpcode() == TargetOpcode::INSERT_SUBREG;
808 bool isSubregToReg() const {
809 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
812 bool isRegSequence() const {
813 return getOpcode() == TargetOpcode::REG_SEQUENCE;
816 bool isBundle() const {
817 return getOpcode() == TargetOpcode::BUNDLE;
820 bool isCopy() const {
821 return getOpcode() == TargetOpcode::COPY;
824 bool isFullCopy() const {
825 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
828 bool isExtractSubreg() const {
829 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
832 /// Return true if the instruction behaves like a copy.
833 /// This does not include native copy instructions.
834 bool isCopyLike() const {
835 return isCopy() || isSubregToReg();
838 /// Return true is the instruction is an identity copy.
839 bool isIdentityCopy() const {
840 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
841 getOperand(0).getSubReg() == getOperand(1).getSubReg();
844 /// Return true if this instruction doesn't produce any output in the form of
845 /// executable instructions.
846 bool isMetaInstruction() const {
847 switch (getOpcode()) {
850 case TargetOpcode::IMPLICIT_DEF:
851 case TargetOpcode::KILL:
852 case TargetOpcode::CFI_INSTRUCTION:
853 case TargetOpcode::EH_LABEL:
854 case TargetOpcode::GC_LABEL:
855 case TargetOpcode::DBG_VALUE:
860 /// Return true if this is a transient instruction that is either very likely
861 /// to be eliminated during register allocation (such as copy-like
862 /// instructions), or if this instruction doesn't have an execution-time cost.
863 bool isTransient() const {
864 switch (getOpcode()) {
866 return isMetaInstruction();
867 // Copy-like instructions are usually eliminated during register allocation.
868 case TargetOpcode::PHI:
869 case TargetOpcode::COPY:
870 case TargetOpcode::INSERT_SUBREG:
871 case TargetOpcode::SUBREG_TO_REG:
872 case TargetOpcode::REG_SEQUENCE:
877 /// Return the number of instructions inside the MI bundle, excluding the
880 /// This is the number of instructions that MachineBasicBlock::iterator
881 /// skips, 0 for unbundled instructions.
882 unsigned getBundleSize() const;
884 /// Return true if the MachineInstr reads the specified register.
885 /// If TargetRegisterInfo is passed, then it also checks if there
886 /// is a read of a super-register.
887 /// This does not count partial redefines of virtual registers as reads:
889 bool readsRegister(unsigned Reg,
890 const TargetRegisterInfo *TRI = nullptr) const {
891 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
894 /// Return true if the MachineInstr reads the specified virtual register.
895 /// Take into account that a partial define is a
896 /// read-modify-write operation.
897 bool readsVirtualRegister(unsigned Reg) const {
898 return readsWritesVirtualRegister(Reg).first;
901 /// Return a pair of bools (reads, writes) indicating if this instruction
902 /// reads or writes Reg. This also considers partial defines.
903 /// If Ops is not null, all operand indices for Reg are added.
904 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
905 SmallVectorImpl<unsigned> *Ops = nullptr) const;
907 /// Return true if the MachineInstr kills the specified register.
908 /// If TargetRegisterInfo is passed, then it also checks if there is
909 /// a kill of a super-register.
910 bool killsRegister(unsigned Reg,
911 const TargetRegisterInfo *TRI = nullptr) const {
912 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
915 /// Return true if the MachineInstr fully defines the specified register.
916 /// If TargetRegisterInfo is passed, then it also checks
917 /// if there is a def of a super-register.
918 /// NOTE: It's ignoring subreg indices on virtual registers.
919 bool definesRegister(unsigned Reg,
920 const TargetRegisterInfo *TRI = nullptr) const {
921 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
924 /// Return true if the MachineInstr modifies (fully define or partially
925 /// define) the specified register.
926 /// NOTE: It's ignoring subreg indices on virtual registers.
927 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
928 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
931 /// Returns true if the register is dead in this machine instruction.
932 /// If TargetRegisterInfo is passed, then it also checks
933 /// if there is a dead def of a super-register.
934 bool registerDefIsDead(unsigned Reg,
935 const TargetRegisterInfo *TRI = nullptr) const {
936 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
939 /// Returns true if the MachineInstr has an implicit-use operand of exactly
940 /// the given register (not considering sub/super-registers).
941 bool hasRegisterImplicitUseOperand(unsigned Reg) const;
943 /// Returns the operand index that is a use of the specific register or -1
944 /// if it is not found. It further tightens the search criteria to a use
945 /// that kills the register if isKill is true.
946 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
947 const TargetRegisterInfo *TRI = nullptr) const;
949 /// Wrapper for findRegisterUseOperandIdx, it returns
950 /// a pointer to the MachineOperand rather than an index.
951 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
952 const TargetRegisterInfo *TRI = nullptr) {
953 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
954 return (Idx == -1) ? nullptr : &getOperand(Idx);
957 const MachineOperand *findRegisterUseOperand(
958 unsigned Reg, bool isKill = false,
959 const TargetRegisterInfo *TRI = nullptr) const {
960 return const_cast<MachineInstr *>(this)->
961 findRegisterUseOperand(Reg, isKill, TRI);
964 /// Returns the operand index that is a def of the specified register or
965 /// -1 if it is not found. If isDead is true, defs that are not dead are
966 /// skipped. If Overlap is true, then it also looks for defs that merely
967 /// overlap the specified register. If TargetRegisterInfo is non-null,
968 /// then it also checks if there is a def of a super-register.
969 /// This may also return a register mask operand when Overlap is true.
970 int findRegisterDefOperandIdx(unsigned Reg,
971 bool isDead = false, bool Overlap = false,
972 const TargetRegisterInfo *TRI = nullptr) const;
974 /// Wrapper for findRegisterDefOperandIdx, it returns
975 /// a pointer to the MachineOperand rather than an index.
976 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
977 const TargetRegisterInfo *TRI = nullptr) {
978 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
979 return (Idx == -1) ? nullptr : &getOperand(Idx);
982 /// Find the index of the first operand in the
983 /// operand list that is used to represent the predicate. It returns -1 if
985 int findFirstPredOperandIdx() const;
987 /// Find the index of the flag word operand that
988 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
989 /// getOperand(OpIdx) does not belong to an inline asm operand group.
991 /// If GroupNo is not NULL, it will receive the number of the operand group
992 /// containing OpIdx.
994 /// The flag operand is an immediate that can be decoded with methods like
995 /// InlineAsm::hasRegClassConstraint().
996 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
998 /// Compute the static register class constraint for operand OpIdx.
999 /// For normal instructions, this is derived from the MCInstrDesc.
1000 /// For inline assembly it is derived from the flag words.
1002 /// Returns NULL if the static register class constraint cannot be
1004 const TargetRegisterClass*
1005 getRegClassConstraint(unsigned OpIdx,
1006 const TargetInstrInfo *TII,
1007 const TargetRegisterInfo *TRI) const;
1009 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
1010 /// the given \p CurRC.
1011 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1012 /// instructions inside the bundle will be taken into account. In other words,
1013 /// this method accumulates all the constraints of the operand of this MI and
1014 /// the related bundle if MI is a bundle or inside a bundle.
1016 /// Returns the register class that satisfies both \p CurRC and the
1017 /// constraints set by MI. Returns NULL if such a register class does not
1020 /// \pre CurRC must not be NULL.
1021 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1022 unsigned Reg, const TargetRegisterClass *CurRC,
1023 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1024 bool ExploreBundle = false) const;
1026 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
1027 /// to the given \p CurRC.
1029 /// Returns the register class that satisfies both \p CurRC and the
1030 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1033 /// \pre CurRC must not be NULL.
1034 /// \pre The operand at \p OpIdx must be a register.
1035 const TargetRegisterClass *
1036 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1037 const TargetInstrInfo *TII,
1038 const TargetRegisterInfo *TRI) const;
1040 /// Add a tie between the register operands at DefIdx and UseIdx.
1041 /// The tie will cause the register allocator to ensure that the two
1042 /// operands are assigned the same physical register.
1044 /// Tied operands are managed automatically for explicit operands in the
1045 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1046 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1048 /// Given the index of a tied register operand, find the
1049 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1050 /// index of the tied operand which must exist.
1051 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1053 /// Given the index of a register def operand,
1054 /// check if the register def is tied to a source operand, due to either
1055 /// two-address elimination or inline assembly constraints. Returns the
1056 /// first tied use operand index by reference if UseOpIdx is not null.
1057 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1058 unsigned *UseOpIdx = nullptr) const {
1059 const MachineOperand &MO = getOperand(DefOpIdx);
1060 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1063 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1067 /// Return true if the use operand of the specified index is tied to a def
1068 /// operand. It also returns the def operand index by reference if DefOpIdx
1070 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1071 unsigned *DefOpIdx = nullptr) const {
1072 const MachineOperand &MO = getOperand(UseOpIdx);
1073 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1076 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1080 /// Clears kill flags on all operands.
1081 void clearKillInfo();
1083 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1084 /// properly composing subreg indices where necessary.
1085 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1086 const TargetRegisterInfo &RegInfo);
1088 /// We have determined MI kills a register. Look for the
1089 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1090 /// add a implicit operand if it's not found. Returns true if the operand
1091 /// exists / is added.
1092 bool addRegisterKilled(unsigned IncomingReg,
1093 const TargetRegisterInfo *RegInfo,
1094 bool AddIfNotFound = false);
1096 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1097 /// all aliasing registers.
1098 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1100 /// We have determined MI defined a register without a use.
1101 /// Look for the operand that defines it and mark it as IsDead. If
1102 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1103 /// true if the operand exists / is added.
1104 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1105 bool AddIfNotFound = false);
1107 /// Clear all dead flags on operands defining register @p Reg.
1108 void clearRegisterDeads(unsigned Reg);
1110 /// Mark all subregister defs of register @p Reg with the undef flag.
1111 /// This function is used when we determined to have a subregister def in an
1112 /// otherwise undefined super register.
1113 void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1115 /// We have determined MI defines a register. Make sure there is an operand
1117 void addRegisterDefined(unsigned Reg,
1118 const TargetRegisterInfo *RegInfo = nullptr);
1120 /// Mark every physreg used by this instruction as
1121 /// dead except those in the UsedRegs list.
1123 /// On instructions with register mask operands, also add implicit-def
1124 /// operands for all registers in UsedRegs.
1125 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1126 const TargetRegisterInfo &TRI);
1128 /// Return true if it is safe to move this instruction. If
1129 /// SawStore is set to true, it means that there is a store (or call) between
1130 /// the instruction's location and its intended destination.
1131 bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1133 /// Returns true if this instruction's memory access aliases the memory
1134 /// access of Other.
1136 /// Assumes any physical registers used to compute addresses
1137 /// have the same value for both instructions. Returns false if neither
1138 /// instruction writes to memory.
1140 /// @param AA Optional alias analysis, used to compare memory operands.
1141 /// @param Other MachineInstr to check aliasing against.
1142 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1143 bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA);
1145 /// Return true if this instruction may have an ordered
1146 /// or volatile memory reference, or if the information describing the memory
1147 /// reference is not available. Return false if it is known to have no
1148 /// ordered or volatile memory references.
1149 bool hasOrderedMemoryRef() const;
1151 /// Return true if this load instruction never traps and points to a memory
1152 /// location whose value doesn't change during the execution of this function.
1154 /// Examples include loading a value from the constant pool or from the
1155 /// argument area of a function (if it does not change). If the instruction
1156 /// does multiple loads, this returns true only if all of the loads are
1157 /// dereferenceable and invariant.
1158 bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
1160 /// If the specified instruction is a PHI that always merges together the
1161 /// same virtual register, return the register, otherwise return 0.
1162 unsigned isConstantValuePHI() const;
1164 /// Return true if this instruction has side effects that are not modeled
1165 /// by mayLoad / mayStore, etc.
1166 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1167 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1168 /// INLINEASM instruction, in which case the side effect property is encoded
1169 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1171 bool hasUnmodeledSideEffects() const;
1173 /// Returns true if it is illegal to fold a load across this instruction.
1174 bool isLoadFoldBarrier() const;
1176 /// Return true if all the defs of this instruction are dead.
1177 bool allDefsAreDead() const;
1179 /// Copy implicit register operands from specified
1180 /// instruction to this instruction.
1181 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1183 /// Debugging support
1185 /// Print this MI to \p OS.
1186 /// Only print the defs and the opcode if \p SkipOpers is true.
1187 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1188 /// Otherwise, also print the debug loc, with a terminating newline.
1189 /// \p TII is used to print the opcode name. If it's not present, but the
1190 /// MI is in a function, the opcode will be printed using the function's TII.
1191 void print(raw_ostream &OS, bool SkipOpers = false, bool SkipDebugLoc = false,
1192 const TargetInstrInfo *TII = nullptr) const;
1193 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool SkipOpers = false,
1194 bool SkipDebugLoc = false,
1195 const TargetInstrInfo *TII = nullptr) const;
1199 //===--------------------------------------------------------------------===//
1200 // Accessors used to build up machine instructions.
1202 /// Add the specified operand to the instruction. If it is an implicit
1203 /// operand, it is added to the end of the operand list. If it is an
1204 /// explicit operand it is added at the end of the explicit operand list
1205 /// (before the first implicit operand).
1207 /// MF must be the machine function that was used to allocate this
1210 /// MachineInstrBuilder provides a more convenient interface for creating
1211 /// instructions and adding operands.
1212 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1214 /// Add an operand without providing an MF reference. This only works for
1215 /// instructions that are inserted in a basic block.
1217 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1219 void addOperand(const MachineOperand &Op);
1221 /// Replace the instruction descriptor (thus opcode) of
1222 /// the current instruction with a new one.
1223 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1225 /// Replace current source information with new such.
1226 /// Avoid using this, the constructor argument is preferable.
1227 void setDebugLoc(DebugLoc dl) {
1228 debugLoc = std::move(dl);
1229 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1232 /// Erase an operand from an instruction, leaving it with one
1233 /// fewer operand than it started with.
1234 void RemoveOperand(unsigned i);
1236 /// Add a MachineMemOperand to the machine instruction.
1237 /// This function should be used only occasionally. The setMemRefs function
1238 /// is the primary method for setting up a MachineInstr's MemRefs list.
1239 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1241 /// Assign this MachineInstr's memory reference descriptor list.
1242 /// This does not transfer ownership.
1243 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1244 setMemRefs(std::make_pair(NewMemRefs, NewMemRefsEnd-NewMemRefs));
1247 /// Assign this MachineInstr's memory reference descriptor list. First
1248 /// element in the pair is the begin iterator/pointer to the array; the
1249 /// second is the number of MemoryOperands. This does not transfer ownership
1250 /// of the underlying memory.
1251 void setMemRefs(std::pair<mmo_iterator, unsigned> NewMemRefs) {
1252 MemRefs = NewMemRefs.first;
1253 NumMemRefs = uint8_t(NewMemRefs.second);
1254 assert(NumMemRefs == NewMemRefs.second &&
1255 "Too many memrefs - must drop memory operands");
1258 /// Return a set of memrefs (begin iterator, size) which conservatively
1259 /// describe the memory behavior of both MachineInstrs. This is appropriate
1260 /// for use when merging two MachineInstrs into one. This routine does not
1261 /// modify the memrefs of the this MachineInstr.
1262 std::pair<mmo_iterator, unsigned> mergeMemRefsWith(const MachineInstr& Other);
1264 /// Clear this MachineInstr's memory reference descriptor list. This resets
1265 /// the memrefs to their most conservative state. This should be used only
1266 /// as a last resort since it greatly pessimizes our knowledge of the memory
1267 /// access performed by the instruction.
1268 void dropMemRefs() {
1273 /// Break any tie involving OpIdx.
1274 void untieRegOperand(unsigned OpIdx) {
1275 MachineOperand &MO = getOperand(OpIdx);
1276 if (MO.isReg() && MO.isTied()) {
1277 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1282 /// Add all implicit def and use operands to this instruction.
1283 void addImplicitDefUseOperands(MachineFunction &MF);
1286 /// If this instruction is embedded into a MachineFunction, return the
1287 /// MachineRegisterInfo object for the current function, otherwise
1289 MachineRegisterInfo *getRegInfo();
1291 /// Unlink all of the register operands in this instruction from their
1292 /// respective use lists. This requires that the operands already be on their
1294 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1296 /// Add all of the register operands in this instruction from their
1297 /// respective use lists. This requires that the operands not be on their
1299 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1301 /// Slow path for hasProperty when we're dealing with a bundle.
1302 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1304 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1305 /// this MI and the given operand index \p OpIdx.
1306 /// If the related operand does not constrained Reg, this returns CurRC.
1307 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1308 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1309 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1312 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1313 /// instruction rather than by pointer value.
1314 /// The hashing and equality testing functions ignore definitions so this is
1315 /// useful for CSE, etc.
1316 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1317 static inline MachineInstr *getEmptyKey() {
1321 static inline MachineInstr *getTombstoneKey() {
1322 return reinterpret_cast<MachineInstr*>(-1);
1325 static unsigned getHashValue(const MachineInstr* const &MI);
1327 static bool isEqual(const MachineInstr* const &LHS,
1328 const MachineInstr* const &RHS) {
1329 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1330 LHS == getEmptyKey() || LHS == getTombstoneKey())
1332 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1336 //===----------------------------------------------------------------------===//
1337 // Debugging Support
1339 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1344 } // end namespace llvm
1346 #endif // LLVM_CODEGEN_MACHINEINSTR_H