1 //==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineMemOperand class, which is a
11 // description of a memory reference. It is used to help track dependencies
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
17 #define LLVM_CODEGEN_MACHINEMEMOPERAND_H
19 #include "llvm/ADT/BitmaskEnum.h"
20 #include "llvm/ADT/PointerUnion.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/IR/Instructions.h"
23 #include "llvm/IR/Metadata.h"
24 #include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
25 #include "llvm/Support/AtomicOrdering.h"
26 #include "llvm/Support/DataTypes.h"
30 class FoldingSetNodeID;
33 class MachineFunction;
34 class ModuleSlotTracker;
36 /// This class contains a discriminated union of information about pointers in
37 /// memory operands, relating them back to LLVM IR or to virtual locations (such
38 /// as frame indices) that are exposed during codegen.
39 struct MachinePointerInfo {
40 /// This is the IR pointer value for the access, or it is null if unknown.
41 /// If this is null, then the access is to a pointer in the default address
43 PointerUnion<const Value *, const PseudoSourceValue *> V;
45 /// Offset - This is an offset from the base Value*.
48 explicit MachinePointerInfo(const Value *v = nullptr, int64_t offset = 0)
49 : V(v), Offset(offset) {}
51 explicit MachinePointerInfo(const PseudoSourceValue *v,
53 : V(v), Offset(offset) {}
55 MachinePointerInfo getWithOffset(int64_t O) const {
56 if (V.isNull()) return MachinePointerInfo();
57 if (V.is<const Value*>())
58 return MachinePointerInfo(V.get<const Value*>(), Offset+O);
59 return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset+O);
62 /// Return true if memory region [V, V+Offset+Size) is known to be
64 bool isDereferenceable(unsigned Size, LLVMContext &C,
65 const DataLayout &DL) const;
67 /// Return the LLVM IR address space number that this pointer points into.
68 unsigned getAddrSpace() const;
70 /// Return a MachinePointerInfo record that refers to the constant pool.
71 static MachinePointerInfo getConstantPool(MachineFunction &MF);
73 /// Return a MachinePointerInfo record that refers to the specified
75 static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI,
78 /// Return a MachinePointerInfo record that refers to a jump table entry.
79 static MachinePointerInfo getJumpTable(MachineFunction &MF);
81 /// Return a MachinePointerInfo record that refers to a GOT entry.
82 static MachinePointerInfo getGOT(MachineFunction &MF);
84 /// Stack pointer relative access.
85 static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset);
89 //===----------------------------------------------------------------------===//
90 /// A description of a memory reference used in the backend.
91 /// Instead of holding a StoreInst or LoadInst, this class holds the address
92 /// Value of the reference along with a byte size and offset. This allows it
93 /// to describe lowered loads and stores. Also, the special PseudoSourceValue
94 /// objects can be used to represent loads and stores to memory locations
95 /// that aren't explicit in the regular LLVM IR.
97 class MachineMemOperand {
99 /// Flags values. These may be or'd together.
100 enum Flags : uint16_t {
103 /// The memory access reads data.
105 /// The memory access writes data.
107 /// The memory access is volatile.
108 MOVolatile = 1u << 2,
109 /// The memory access is non-temporal.
110 MONonTemporal = 1u << 3,
111 /// The memory access is dereferenceable (i.e., doesn't trap).
112 MODereferenceable = 1u << 4,
113 /// The memory access always returns the same value (or traps).
114 MOInvariant = 1u << 5,
116 // Reserved for use by target-specific passes.
117 // Targets may override getSerializableMachineMemOperandTargetFlags() to
118 // enable MIR serialization/parsing of these flags. If more of these flags
119 // are added, the MIR printing/parsing code will need to be updated as well.
120 MOTargetFlag1 = 1u << 6,
121 MOTargetFlag2 = 1u << 7,
122 MOTargetFlag3 = 1u << 8,
124 LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
128 /// Atomic information for this memory operation.
129 struct MachineAtomicInfo {
130 /// Synchronization scope ID for this memory operation.
131 unsigned SSID : 8; // SyncScope::ID
132 /// Atomic ordering requirements for this memory operation. For cmpxchg
133 /// atomic operations, atomic ordering requirements when store occurs.
134 unsigned Ordering : 4; // enum AtomicOrdering
135 /// For cmpxchg atomic operations, atomic ordering requirements when store
137 unsigned FailureOrdering : 4; // enum AtomicOrdering
140 MachinePointerInfo PtrInfo;
143 uint16_t BaseAlignLog2; // log_2(base_alignment) + 1
144 MachineAtomicInfo AtomicInfo;
146 const MDNode *Ranges;
149 /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
150 /// size, and base alignment. For atomic operations the synchronization scope
151 /// and atomic ordering requirements must also be specified. For cmpxchg
152 /// atomic operations the atomic ordering requirements when store does not
153 /// occur must also be specified.
154 MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
155 unsigned base_alignment,
156 const AAMDNodes &AAInfo = AAMDNodes(),
157 const MDNode *Ranges = nullptr,
158 SyncScope::ID SSID = SyncScope::System,
159 AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
160 AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
162 const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
164 /// Return the base address of the memory access. This may either be a normal
165 /// LLVM IR Value, or one of the special values used in CodeGen.
166 /// Special values are those obtained via
167 /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
168 /// other PseudoSourceValue member functions which return objects which stand
169 /// for frame/stack pointer relative references and other special references
170 /// which are not representable in the high-level IR.
171 const Value *getValue() const { return PtrInfo.V.dyn_cast<const Value*>(); }
173 const PseudoSourceValue *getPseudoValue() const {
174 return PtrInfo.V.dyn_cast<const PseudoSourceValue*>();
177 const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
179 /// Return the raw flags of the source value, \see Flags.
180 Flags getFlags() const { return FlagVals; }
182 /// Bitwise OR the current flags with the given flags.
183 void setFlags(Flags f) { FlagVals |= f; }
185 /// For normal values, this is a byte offset added to the base address.
186 /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
187 int64_t getOffset() const { return PtrInfo.Offset; }
189 unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
191 /// Return the size in bytes of the memory reference.
192 uint64_t getSize() const { return Size; }
194 /// Return the minimum known alignment in bytes of the actual memory
196 uint64_t getAlignment() const;
198 /// Return the minimum known alignment in bytes of the base address, without
200 uint64_t getBaseAlignment() const { return (1u << BaseAlignLog2) >> 1; }
202 /// Return the AA tags for the memory reference.
203 AAMDNodes getAAInfo() const { return AAInfo; }
205 /// Return the range tag for the memory reference.
206 const MDNode *getRanges() const { return Ranges; }
208 /// Returns the synchronization scope ID for this memory operation.
209 SyncScope::ID getSyncScopeID() const {
210 return static_cast<SyncScope::ID>(AtomicInfo.SSID);
213 /// Return the atomic ordering requirements for this memory operation. For
214 /// cmpxchg atomic operations, return the atomic ordering requirements when
216 AtomicOrdering getOrdering() const {
217 return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
220 /// For cmpxchg atomic operations, return the atomic ordering requirements
221 /// when store does not occur.
222 AtomicOrdering getFailureOrdering() const {
223 return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
226 bool isLoad() const { return FlagVals & MOLoad; }
227 bool isStore() const { return FlagVals & MOStore; }
228 bool isVolatile() const { return FlagVals & MOVolatile; }
229 bool isNonTemporal() const { return FlagVals & MONonTemporal; }
230 bool isDereferenceable() const { return FlagVals & MODereferenceable; }
231 bool isInvariant() const { return FlagVals & MOInvariant; }
233 /// Returns true if this operation has an atomic ordering requirement of
234 /// unordered or higher, false otherwise.
235 bool isAtomic() const { return getOrdering() != AtomicOrdering::NotAtomic; }
237 /// Returns true if this memory operation doesn't have any ordering
238 /// constraints other than normal aliasing. Volatile and atomic memory
239 /// operations can't be reordered.
241 /// Currently, we don't model the difference between volatile and atomic
242 /// operations. They should retain their ordering relative to all memory
244 bool isUnordered() const { return !isVolatile(); }
246 /// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
247 /// greater alignment. This must only be used when the new alignment applies
248 /// to all users of this MachineMemOperand.
249 void refineAlignment(const MachineMemOperand *MMO);
251 /// Change the SourceValue for this MachineMemOperand. This should only be
252 /// used when an object is being relocated and all references to it are being
254 void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
255 void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
256 void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
258 /// Profile - Gather unique data for the object.
260 void Profile(FoldingSetNodeID &ID) const;
262 /// Support for operator<<.
264 void print(raw_ostream &OS) const;
265 void print(raw_ostream &OS, ModuleSlotTracker &MST) const;
268 friend bool operator==(const MachineMemOperand &LHS,
269 const MachineMemOperand &RHS) {
270 return LHS.getValue() == RHS.getValue() &&
271 LHS.getPseudoValue() == RHS.getPseudoValue() &&
272 LHS.getSize() == RHS.getSize() &&
273 LHS.getOffset() == RHS.getOffset() &&
274 LHS.getFlags() == RHS.getFlags() &&
275 LHS.getAAInfo() == RHS.getAAInfo() &&
276 LHS.getRanges() == RHS.getRanges() &&
277 LHS.getAlignment() == RHS.getAlignment() &&
278 LHS.getAddrSpace() == RHS.getAddrSpace();
281 friend bool operator!=(const MachineMemOperand &LHS,
282 const MachineMemOperand &RHS) {
283 return !(LHS == RHS);
287 inline raw_ostream &operator<<(raw_ostream &OS, const MachineMemOperand &MRO) {
292 } // End llvm namespace