1 //===-- RegisterScavenging.h - Machine register scavenging ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file declares the machine register scavenger class. It can provide
12 /// information such as unused register at any point in a machine basic block.
13 /// It also provides a mechanism to make registers available by evicting them
16 //===----------------------------------------------------------------------===//
18 #ifndef LLVM_CODEGEN_REGISTERSCAVENGING_H
19 #define LLVM_CODEGEN_REGISTERSCAVENGING_H
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 class MachineRegisterInfo;
28 class TargetRegisterInfo;
29 class TargetInstrInfo;
30 class TargetRegisterClass;
33 const TargetRegisterInfo *TRI;
34 const TargetInstrInfo *TII;
35 MachineRegisterInfo* MRI;
36 MachineBasicBlock *MBB;
37 MachineBasicBlock::iterator MBBI;
40 /// True if RegScavenger is currently tracking the liveness of registers.
43 /// Information on scavenged registers (held in a spill slot).
44 struct ScavengedInfo {
45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(nullptr) {}
47 /// A spill slot used for scavenging a register post register allocation.
50 /// If non-zero, the specific register is currently being
51 /// scavenged. That is, it is spilled to this scavenging stack slot.
54 /// The instruction that restores the scavenged register from stack.
55 const MachineInstr *Restore;
58 /// A vector of information on scavenged registers.
59 SmallVector<ScavengedInfo, 2> Scavenged;
61 /// The current state of each reg unit immediately before MBBI.
62 /// One bit per register unit. If bit is not set it means any
63 /// register containing that register unit is currently being used.
64 BitVector RegUnitsAvailable;
66 // These BitVectors are only used internally to forward(). They are members
67 // to avoid frequent reallocations.
68 BitVector KillRegUnits, DefRegUnits;
69 BitVector TmpRegUnits;
73 : MBB(nullptr), NumRegUnits(0), Tracking(false) {}
75 /// Start tracking liveness from the begin of basic block \p MBB.
76 void enterBasicBlock(MachineBasicBlock &MBB);
78 /// Start tracking liveness from the end of basic block \p MBB.
79 /// Use backward() to move towards the beginning of the block. This is
80 /// preferred to enterBasicBlock() and forward() because it does not depend
81 /// on the presence of kill flags.
82 void enterBasicBlockEnd(MachineBasicBlock &MBB);
84 /// Move the internal MBB iterator and update register states.
87 /// Move the internal MBB iterator and update register states until
88 /// it has processed the specific iterator.
89 void forward(MachineBasicBlock::iterator I) {
90 if (!Tracking && MBB->begin() != I) forward();
91 while (MBBI != I) forward();
94 /// Invert the behavior of forward() on the current instruction (undo the
95 /// changes to the available registers made by forward()).
98 /// Unprocess instructions until you reach the provided iterator.
99 void unprocess(MachineBasicBlock::iterator I) {
100 while (MBBI != I) unprocess();
103 /// Update internal register state and move MBB iterator backwards.
104 /// Contrary to unprocess() this method gives precise results even in the
105 /// absence of kill flags.
108 /// Call backward() as long as the internal iterator does not point to \p I.
109 void backward(MachineBasicBlock::iterator I) {
114 /// Move the internal MBB iterator but do not update register states.
115 void skipTo(MachineBasicBlock::iterator I) {
116 if (I == MachineBasicBlock::iterator(nullptr))
121 MachineBasicBlock::iterator getCurrentPosition() const { return MBBI; }
123 /// Return if a specific register is currently used.
124 bool isRegUsed(unsigned Reg, bool includeReserved = true) const;
126 /// Return all available registers in the register class in Mask.
127 BitVector getRegsAvailable(const TargetRegisterClass *RC);
129 /// Find an unused register of the specified register class.
130 /// Return 0 if none is found.
131 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
133 /// Add a scavenging frame index.
134 void addScavengingFrameIndex(int FI) {
135 Scavenged.push_back(ScavengedInfo(FI));
138 /// Query whether a frame index is a scavenging frame index.
139 bool isScavengingFrameIndex(int FI) const {
140 for (SmallVectorImpl<ScavengedInfo>::const_iterator I = Scavenged.begin(),
141 IE = Scavenged.end(); I != IE; ++I)
142 if (I->FrameIndex == FI)
148 /// Get an array of scavenging frame indices.
149 void getScavengingFrameIndices(SmallVectorImpl<int> &A) const {
150 for (SmallVectorImpl<ScavengedInfo>::const_iterator I = Scavenged.begin(),
151 IE = Scavenged.end(); I != IE; ++I)
152 if (I->FrameIndex >= 0)
153 A.push_back(I->FrameIndex);
156 /// Make a register of the specific register class
157 /// available and do the appropriate bookkeeping. SPAdj is the stack
158 /// adjustment due to call frame, it's passed along to eliminateFrameIndex().
159 /// Returns the scavenged register.
160 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
161 MachineBasicBlock::iterator I, int SPAdj);
162 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
163 return scavengeRegister(RegClass, MBBI, SPAdj);
166 /// Tell the scavenger a register is used.
167 void setRegUsed(unsigned Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
169 /// Returns true if a register is reserved. It is never "unused".
170 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
172 /// setUsed / setUnused - Mark the state of one or a number of register units.
174 void setUsed(BitVector &RegUnits) {
175 RegUnitsAvailable.reset(RegUnits);
177 void setUnused(BitVector &RegUnits) {
178 RegUnitsAvailable |= RegUnits;
181 /// Processes the current instruction and fill the KillRegUnits and
182 /// DefRegUnits bit vectors.
183 void determineKillsAndDefs();
185 /// Add all Reg Units that Reg contains to BV.
186 void addRegUnits(BitVector &BV, unsigned Reg);
188 /// Remove all Reg Units that \p Reg contains from \p BV.
189 void removeRegUnits(BitVector &BV, unsigned Reg);
191 /// Return the candidate register that is unused for the longest after
192 /// StartMI. UseMI is set to the instruction where the search stopped.
194 /// No more than InstrLimit instructions are inspected.
195 unsigned findSurvivorReg(MachineBasicBlock::iterator StartMI,
196 BitVector &Candidates,
198 MachineBasicBlock::iterator &UseMI);
200 /// Initialize RegisterScavenger.
201 void init(MachineBasicBlock &MBB);
203 /// Mark live-in registers of basic block as used.
204 void setLiveInsUsed(const MachineBasicBlock &MBB);
207 } // End llvm namespace