contrib/llvm/include/llvm/CodeGen/SchedulerRegistry.h

   1 //===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the implementation for instruction scheduler function
  11 // pass registry (RegisterScheduler).
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
  16 #define LLVM_CODEGEN_SCHEDULERREGISTRY_H
  17
  18 #include "llvm/CodeGen/MachinePassRegistry.h"
  19 #include "llvm/Support/CodeGen.h"
  20
  21 namespace llvm {
  22
  23 //===----------------------------------------------------------------------===//
  24 ///
  25 /// RegisterScheduler class - Track the registration of instruction schedulers.
  26 ///
  27 //===----------------------------------------------------------------------===//
  28
  29 class ScheduleDAGSDNodes;
  30 class SelectionDAGISel;
  31
  32 class RegisterScheduler : public MachinePassRegistryNode {
  33 public:
  34   using FunctionPassCtor = ScheduleDAGSDNodes *(*)(SelectionDAGISel*,
  35                                                    CodeGenOpt::Level);
  36
  37   static MachinePassRegistry Registry;
  38
  39   RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
  40   : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
  41   { Registry.Add(this); }
  42   ~RegisterScheduler() { Registry.Remove(this); }
  43
  44
  45   // Accessors.
  46   RegisterScheduler *getNext() const {
  47     return (RegisterScheduler *)MachinePassRegistryNode::getNext();
  48   }
  49
  50   static RegisterScheduler *getList() {
  51     return (RegisterScheduler *)Registry.getList();
  52   }
  53
  54   static void setListener(MachinePassRegistryListener *L) {
  55     Registry.setListener(L);
  56   }
  57 };
  58
  59 /// createBURRListDAGScheduler - This creates a bottom up register usage
  60 /// reduction list scheduler.
  61 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
  62                                                CodeGenOpt::Level OptLevel);
  63
  64 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
  65 /// schedules nodes in source code order when possible.
  66 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
  67                                                  CodeGenOpt::Level OptLevel);
  68
  69 /// createHybridListDAGScheduler - This creates a bottom up register pressure
  70 /// aware list scheduler that make use of latency information to avoid stalls
  71 /// for long latency instructions in low register pressure mode. In high
  72 /// register pressure mode it schedules to reduce register pressure.
  73 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
  74                                                  CodeGenOpt::Level);
  75
  76 /// createILPListDAGScheduler - This creates a bottom up register pressure
  77 /// aware list scheduler that tries to increase instruction level parallelism
  78 /// in low register pressure mode. In high register pressure mode it schedules
  79 /// to reduce register pressure.
  80 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
  81                                               CodeGenOpt::Level);
  82
  83 /// createFastDAGScheduler - This creates a "fast" scheduler.
  84 ///
  85 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
  86                                            CodeGenOpt::Level OptLevel);
  87
  88 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
  89 /// DFA driven list scheduler with clustering heuristic to control
  90 /// register pressure.
  91 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
  92                                            CodeGenOpt::Level OptLevel);
  93 /// createDefaultScheduler - This creates an instruction scheduler appropriate
  94 /// for the target.
  95 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
  96                                            CodeGenOpt::Level OptLevel);
  97
  98 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
  99 /// linearize the DAG using topological order.
 100 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
 101                                         CodeGenOpt::Level OptLevel);
 102
 103 } // end namespace llvm
 104
 105 #endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H