1 //===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation for instruction scheduler function
11 // pass registry (RegisterScheduler).
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
16 #define LLVM_CODEGEN_SCHEDULERREGISTRY_H
18 #include "llvm/CodeGen/MachinePassRegistry.h"
19 #include "llvm/Support/CodeGen.h"
23 //===----------------------------------------------------------------------===//
25 /// RegisterScheduler class - Track the registration of instruction schedulers.
27 //===----------------------------------------------------------------------===//
29 class ScheduleDAGSDNodes;
30 class SelectionDAGISel;
32 class RegisterScheduler : public MachinePassRegistryNode {
34 using FunctionPassCtor = ScheduleDAGSDNodes *(*)(SelectionDAGISel*,
37 static MachinePassRegistry Registry;
39 RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
40 : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
41 { Registry.Add(this); }
42 ~RegisterScheduler() { Registry.Remove(this); }
46 RegisterScheduler *getNext() const {
47 return (RegisterScheduler *)MachinePassRegistryNode::getNext();
50 static RegisterScheduler *getList() {
51 return (RegisterScheduler *)Registry.getList();
54 static void setListener(MachinePassRegistryListener *L) {
55 Registry.setListener(L);
59 /// createBURRListDAGScheduler - This creates a bottom up register usage
60 /// reduction list scheduler.
61 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
62 CodeGenOpt::Level OptLevel);
64 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
65 /// schedules nodes in source code order when possible.
66 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
67 CodeGenOpt::Level OptLevel);
69 /// createHybridListDAGScheduler - This creates a bottom up register pressure
70 /// aware list scheduler that make use of latency information to avoid stalls
71 /// for long latency instructions in low register pressure mode. In high
72 /// register pressure mode it schedules to reduce register pressure.
73 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
76 /// createILPListDAGScheduler - This creates a bottom up register pressure
77 /// aware list scheduler that tries to increase instruction level parallelism
78 /// in low register pressure mode. In high register pressure mode it schedules
79 /// to reduce register pressure.
80 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
83 /// createFastDAGScheduler - This creates a "fast" scheduler.
85 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
86 CodeGenOpt::Level OptLevel);
88 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
89 /// DFA driven list scheduler with clustering heuristic to control
90 /// register pressure.
91 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
92 CodeGenOpt::Level OptLevel);
93 /// createDefaultScheduler - This creates an instruction scheduler appropriate
95 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
96 CodeGenOpt::Level OptLevel);
98 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
99 /// linearize the DAG using topological order.
100 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
101 CodeGenOpt::Level OptLevel);
103 } // end namespace llvm
105 #endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H