1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/TargetSubtargetInfo.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/Pass.h"
27 class SelectionDAGBuilder;
29 class MachineRegisterInfo;
30 class MachineBasicBlock;
31 class MachineFunction;
33 class OptimizationRemarkEmitter;
35 class TargetLibraryInfo;
36 class FunctionLoweringInfo;
37 class ScheduleHazardRecognizer;
39 class ScheduleDAGSDNodes;
42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
43 /// pattern-matching instruction selectors.
44 class SelectionDAGISel : public MachineFunctionPass {
47 const TargetLibraryInfo *LibInfo;
48 FunctionLoweringInfo *FuncInfo;
50 MachineRegisterInfo *RegInfo;
52 SelectionDAGBuilder *SDB;
55 CodeGenOpt::Level OptLevel;
56 const TargetInstrInfo *TII;
57 const TargetLowering *TLI;
59 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
61 /// Current optimization remark emitter.
62 /// Used to report things like combines and FastISel failures.
63 std::unique_ptr<OptimizationRemarkEmitter> ORE;
67 explicit SelectionDAGISel(TargetMachine &tm,
68 CodeGenOpt::Level OL = CodeGenOpt::Default);
69 ~SelectionDAGISel() override;
71 const TargetLowering *getTargetLowering() const { return TLI; }
73 void getAnalysisUsage(AnalysisUsage &AU) const override;
75 bool runOnMachineFunction(MachineFunction &MF) override;
77 virtual void EmitFunctionEntryCode() {}
79 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
80 /// instruction selection starts.
81 virtual void PreprocessISelDAG() {}
83 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
84 /// right after selection.
85 virtual void PostprocessISelDAG() {}
87 /// Main hook for targets to transform nodes into machine nodes.
88 virtual void Select(SDNode *N) = 0;
90 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
91 /// addressing mode, according to the specified constraint. If this does
92 /// not match or is not implemented, return true. The resultant operands
93 /// (which will appear in the machine instruction) should be added to the
95 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
96 unsigned ConstraintID,
97 std::vector<SDValue> &OutOps) {
101 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
102 /// operand node N of U during instruction selection that starts at Root.
103 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
105 /// IsLegalToFold - Returns true if the specific operand node N of
106 /// U can be folded during instruction selection that starts at Root.
107 /// FIXME: This is a static member function because the MSP430/X86
108 /// targets, which uses it during isel. This could become a proper member.
109 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
110 CodeGenOpt::Level OptLevel,
111 bool IgnoreChains = false);
113 static void InvalidateNodeId(SDNode *N);
114 static int getUninvalidatedNodeId(SDNode *N);
116 static void EnforceNodeIdInvariant(SDNode *N);
118 // Opcodes used by the DAG state machine:
119 enum BuiltinOpcodes {
122 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
123 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
125 OPC_CaptureGlueInput,
127 OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3,
128 OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7,
131 OPC_CheckChild0Same, OPC_CheckChild1Same,
132 OPC_CheckChild2Same, OPC_CheckChild3Same,
133 OPC_CheckPatternPredicate,
140 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
141 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
142 OPC_CheckChild6Type, OPC_CheckChild7Type,
144 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
145 OPC_CheckChild3Integer, OPC_CheckChild4Integer,
149 OPC_CheckAndImm, OPC_CheckOrImm,
150 OPC_CheckFoldableChainNode,
155 OPC_EmitConvertToTarget,
156 OPC_EmitMergeInputChains,
157 OPC_EmitMergeInputChains1_0,
158 OPC_EmitMergeInputChains1_1,
159 OPC_EmitMergeInputChains1_2,
163 // Space-optimized forms that implicitly encode number of result VTs.
164 OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2,
166 // Space-optimized forms that implicitly encode number of result VTs.
167 OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2,
169 // Contains offset in table for pattern being selected
174 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
175 OPFL_Chain = 1, // Node has a chain input.
176 OPFL_GlueInput = 2, // Node has a glue input.
177 OPFL_GlueOutput = 4, // Node has a glue output.
178 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
179 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
180 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
181 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
182 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
183 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
184 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
185 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
187 OPFL_VariadicInfo = OPFL_Variadic6
190 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
191 /// number of fixed arity values that should be skipped when copying from the
193 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
194 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
199 /// DAGSize - Size of DAG being instruction selected.
203 /// ReplaceUses - replace all uses of the old node F with the use
204 /// of the new node T.
205 void ReplaceUses(SDValue F, SDValue T) {
206 CurDAG->ReplaceAllUsesOfValueWith(F, T);
207 EnforceNodeIdInvariant(T.getNode());
210 /// ReplaceUses - replace all uses of the old nodes F with the use
211 /// of the new nodes T.
212 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
213 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
214 for (unsigned i = 0; i < Num; ++i)
215 EnforceNodeIdInvariant(T[i].getNode());
218 /// ReplaceUses - replace all uses of the old node F with the use
219 /// of the new node T.
220 void ReplaceUses(SDNode *F, SDNode *T) {
221 CurDAG->ReplaceAllUsesWith(F, T);
222 EnforceNodeIdInvariant(T);
225 /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
226 void ReplaceNode(SDNode *F, SDNode *T) {
227 CurDAG->ReplaceAllUsesWith(F, T);
228 EnforceNodeIdInvariant(T);
229 CurDAG->RemoveDeadNode(F);
232 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
233 /// by tblgen. Others should not call it.
234 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
237 /// getPatternForIndex - Patterns selected by tablegen during ISEL
238 virtual StringRef getPatternForIndex(unsigned index) {
239 llvm_unreachable("Tblgen should generate the implementation of this!");
242 /// getIncludePathForIndex - get the td source location of pattern instantiation
243 virtual StringRef getIncludePathForIndex(unsigned index) {
244 llvm_unreachable("Tblgen should generate the implementation of this!");
247 // Calls to these predicates are generated by tblgen.
248 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
249 int64_t DesiredMaskS) const;
250 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
251 int64_t DesiredMaskS) const;
254 /// CheckPatternPredicate - This function is generated by tblgen in the
255 /// target. It runs the specified pattern predicate and returns true if it
256 /// succeeds or false if it fails. The number is a private implementation
257 /// detail to the code tblgen produces.
258 virtual bool CheckPatternPredicate(unsigned PredNo) const {
259 llvm_unreachable("Tblgen should generate the implementation of this!");
262 /// CheckNodePredicate - This function is generated by tblgen in the target.
263 /// It runs node predicate number PredNo and returns true if it succeeds or
264 /// false if it fails. The number is a private implementation
265 /// detail to the code tblgen produces.
266 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
267 llvm_unreachable("Tblgen should generate the implementation of this!");
270 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
272 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
273 llvm_unreachable("Tblgen should generate the implementation of this!");
276 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
277 llvm_unreachable("Tblgen should generate this!");
280 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
283 /// Return true if complex patterns for this target can mutate the
285 virtual bool ComplexPatternFuncMutatesDAG() const {
289 bool isOrEquivalentToAdd(const SDNode *N) const;
293 // Calls to these functions are generated by tblgen.
294 void Select_INLINEASM(SDNode *N);
295 void Select_READ_REGISTER(SDNode *Op);
296 void Select_WRITE_REGISTER(SDNode *Op);
297 void Select_UNDEF(SDNode *N);
298 void CannotYetSelect(SDNode *N);
301 void DoInstructionSelection();
302 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
303 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
305 SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
307 /// Prepares the landing pad to take incoming values or do other EH
308 /// personality specific tasks. Returns true if the block should be
309 /// instruction selected, false if no code should be emitted for it.
310 bool PrepareEHLandingPad();
312 /// Perform instruction selection on all basic blocks in the function.
313 void SelectAllBasicBlocks(const Function &Fn);
315 /// Perform instruction selection on a single basic block, for
316 /// instructions between \p Begin and \p End. \p HadTailCall will be set
317 /// to true if a call in the block was translated as a tail call.
318 void SelectBasicBlock(BasicBlock::const_iterator Begin,
319 BasicBlock::const_iterator End,
321 void FinishBasicBlock();
323 void CodeGenAndEmitDAG();
325 /// Generate instructions for lowering the incoming arguments of the
327 void LowerArguments(const Function &F);
329 void ComputeLiveOutVRegInfo();
331 /// Create the scheduler. If a specific scheduler was specified
332 /// via the SchedulerRegistry, use it, otherwise select the
333 /// one preferred by the target.
335 ScheduleDAGSDNodes *CreateScheduler();
337 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
338 /// state machines that start with a OPC_SwitchOpcode node.
339 std::vector<unsigned> OpcodeOffset;
341 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
342 SmallVectorImpl<SDNode *> &ChainNodesMatched,
348 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */