1 //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// Target-Independent Code Generator Pass Configuration Options pass.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
15 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
17 #include "llvm/Pass.h"
18 #include "llvm/Support/CodeGen.h"
24 class LLVMTargetMachine;
25 struct MachineSchedContext;
27 class ScheduleDAGInstrs;
29 // The old pass manager infrastructure is hidden in a legacy namespace now.
32 class PassManagerBase;
34 } // end namespace legacy
36 using legacy::PassManagerBase;
38 /// Discriminated union of Pass ID types.
40 /// The PassConfig API prefers dealing with IDs because they are safer and more
41 /// efficient. IDs decouple configuration from instantiation. This way, when a
42 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
43 /// refer to a Pass pointer after adding it to a pass manager, which deletes
44 /// redundant pass instances.
46 /// However, it is convient to directly instantiate target passes with
47 /// non-default ctors. These often don't have a registered PassInfo. Rather than
48 /// force all target passes to implement the pass registry boilerplate, allow
49 /// the PassConfig API to handle either type.
51 /// AnalysisID is sadly char*, so PointerIntPair won't work.
52 class IdentifyingPassPtr {
57 bool IsInstance = false;
60 IdentifyingPassPtr() : P(nullptr) {}
61 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
62 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
64 bool isValid() const { return P; }
65 bool isInstance() const { return IsInstance; }
67 AnalysisID getID() const {
68 assert(!IsInstance && "Not a Pass ID");
72 Pass *getInstance() const {
73 assert(IsInstance && "Not a Pass Instance");
78 template <> struct isPodLike<IdentifyingPassPtr> {
79 static const bool value = true;
82 /// Target-Independent Code Generator Pass Configuration Options.
84 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
85 /// to the internals of other CodeGen passes.
86 class TargetPassConfig : public ImmutablePass {
88 PassManagerBase *PM = nullptr;
89 AnalysisID StartBefore = nullptr;
90 AnalysisID StartAfter = nullptr;
91 AnalysisID StopBefore = nullptr;
92 AnalysisID StopAfter = nullptr;
94 unsigned StartBeforeInstanceNum = 0;
95 unsigned StartBeforeCount = 0;
97 unsigned StartAfterInstanceNum = 0;
98 unsigned StartAfterCount = 0;
100 unsigned StopBeforeInstanceNum = 0;
101 unsigned StopBeforeCount = 0;
103 unsigned StopAfterInstanceNum = 0;
104 unsigned StopAfterCount = 0;
107 bool Stopped = false;
108 bool AddingMachinePasses = false;
110 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
111 /// a portion of the normal code-gen pass sequence.
113 /// If the StartAfter and StartBefore pass ID is zero, then compilation will
114 /// begin at the normal point; otherwise, clear the Started flag to indicate
115 /// that passes should not be added until the starting pass is seen. If the
116 /// Stop pass ID is zero, then compilation will continue to the end.
118 /// This function expects that at least one of the StartAfter or the
119 /// StartBefore pass IDs is null.
120 void setStartStopPasses();
123 LLVMTargetMachine *TM;
124 PassConfigImpl *Impl = nullptr; // Internal data structures
125 bool Initialized = false; // Flagged after all passes are configured.
127 // Target Pass Options
128 // Targets provide a default setting, user flags override.
129 bool DisableVerify = false;
131 /// Default setting for -enable-tail-merge on this target.
132 bool EnableTailMerge = true;
134 /// Require processing of functions such that callees are generated before
136 bool RequireCodeGenSCCOrder = false;
138 /// Add the actual instruction selection passes. This does not include
139 /// preparation passes on IR.
140 bool addCoreISelPasses();
143 TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
144 // Dummy constructor.
147 ~TargetPassConfig() override;
151 /// Get the right type of TargetMachine for this target.
152 template<typename TMC> TMC &getTM() const {
153 return *static_cast<TMC*>(TM);
157 void setInitialized() { Initialized = true; }
159 CodeGenOpt::Level getOptLevel() const;
161 /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
162 /// or `-stop-before` options is set.
163 static bool hasLimitedCodeGenPipeline();
165 /// Returns true if none of the `-stop-before` and `-stop-after` options is
167 static bool willCompleteCodeGenPipeline();
169 /// If hasLimitedCodeGenPipeline is true, this method
170 /// returns a string with the name of the options, separated
171 /// by \p Separator that caused this pipeline to be limited.
173 getLimitedCodeGenPipelineReason(const char *Separator = "/") const;
175 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
177 bool getEnableTailMerge() const { return EnableTailMerge; }
178 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
180 bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
181 void setRequiresCodeGenSCCOrder(bool Enable = true) {
182 setOpt(RequireCodeGenSCCOrder, Enable);
185 /// Allow the target to override a specific pass without overriding the pass
186 /// pipeline. When passes are added to the standard pipeline at the
187 /// point where StandardID is expected, add TargetID in its place.
188 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
190 /// Insert InsertedPassID pass after TargetPassID pass.
191 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
192 bool VerifyAfter = true, bool PrintAfter = true);
194 /// Allow the target to enable a specific standard pass by default.
195 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
197 /// Allow the target to disable a specific standard pass by default.
198 void disablePass(AnalysisID PassID) {
199 substitutePass(PassID, IdentifyingPassPtr());
202 /// Return the pass substituted for StandardID by the target.
203 /// If no substitution exists, return StandardID.
204 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
206 /// Return true if the pass has been substituted by the target or
207 /// overridden on the command line.
208 bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
210 /// Return true if the optimized regalloc pipeline is enabled.
211 bool getOptimizeRegAlloc() const;
213 /// Return true if the default global register allocator is in use and
214 /// has not be overriden on the command line with '-regalloc=...'
215 bool usingDefaultRegAlloc() const;
217 /// High level function that adds all passes necessary to go from llvm IR
218 /// representation to the MI representation.
219 /// Adds IR based lowering and target specific optimization passes and finally
220 /// the core instruction selection passes.
221 /// \returns true if an error occurred, false otherwise.
222 bool addISelPasses();
224 /// Add common target configurable passes that perform LLVM IR to IR
225 /// transforms following machine independent optimization.
226 virtual void addIRPasses();
228 /// Add passes to lower exception handling for the code generator.
229 void addPassesToHandleExceptions();
231 /// Add pass to prepare the LLVM IR for code generation. This should be done
232 /// before exception handling preparation passes.
233 virtual void addCodeGenPrepare();
235 /// Add common passes that perform LLVM IR to IR transforms in preparation for
236 /// instruction selection.
237 virtual void addISelPrepare();
239 /// addInstSelector - This method should install an instruction selector pass,
240 /// which converts from LLVM code to machine instructions.
241 virtual bool addInstSelector() {
245 /// This method should install an IR translator pass, which converts from
246 /// LLVM code to machine instructions with possibly generic opcodes.
247 virtual bool addIRTranslator() { return true; }
249 /// This method may be implemented by targets that want to run passes
250 /// immediately before legalization.
251 virtual void addPreLegalizeMachineIR() {}
253 /// This method should install a legalize pass, which converts the instruction
254 /// sequence into one that can be selected by the target.
255 virtual bool addLegalizeMachineIR() { return true; }
257 /// This method may be implemented by targets that want to run passes
258 /// immediately before the register bank selection.
259 virtual void addPreRegBankSelect() {}
261 /// This method should install a register bank selector pass, which
262 /// assigns register banks to virtual registers without a register
263 /// class or register banks.
264 virtual bool addRegBankSelect() { return true; }
266 /// This method may be implemented by targets that want to run passes
267 /// immediately before the (global) instruction selection.
268 virtual void addPreGlobalInstructionSelect() {}
270 /// This method should install a (global) instruction selector pass, which
271 /// converts possibly generic instructions to fully target-specific
272 /// instructions, thereby constraining all generic virtual registers to
273 /// register classes.
274 virtual bool addGlobalInstructionSelect() { return true; }
276 /// Add the complete, standard set of LLVM CodeGen passes.
277 /// Fully developed targets will not generally override this.
278 virtual void addMachinePasses();
280 /// Create an instance of ScheduleDAGInstrs to be run within the standard
281 /// MachineScheduler pass for this function and target at the current
282 /// optimization level.
284 /// This can also be used to plug a new MachineSchedStrategy into an instance
285 /// of the standard ScheduleDAGMI:
286 /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
288 /// Return NULL to select the default (generic) machine scheduler.
289 virtual ScheduleDAGInstrs *
290 createMachineScheduler(MachineSchedContext *C) const {
294 /// Similar to createMachineScheduler but used when postRA machine scheduling
296 virtual ScheduleDAGInstrs *
297 createPostMachineScheduler(MachineSchedContext *C) const {
301 /// printAndVerify - Add a pass to dump then verify the machine function, if
302 /// those steps are enabled.
303 void printAndVerify(const std::string &Banner);
305 /// Add a pass to print the machine function if printing is enabled.
306 void addPrintPass(const std::string &Banner);
308 /// Add a pass to perform basic verification of the machine function if
309 /// verification is enabled.
310 void addVerifyPass(const std::string &Banner);
312 /// Check whether or not GlobalISel should abort on error.
313 /// When this is disabled, GlobalISel will fall back on SDISel instead of
315 bool isGlobalISelAbortEnabled() const;
317 /// Check whether or not a diagnostic should be emitted when GlobalISel
318 /// uses the fallback path. In other words, it will emit a diagnostic
319 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
320 virtual bool reportDiagnosticWhenGlobalISelFallback() const;
323 // Helper to verify the analysis is really immutable.
324 void setOpt(bool &Opt, bool Val);
326 /// Methods with trivial inline returns are convenient points in the common
327 /// codegen pass pipeline where targets may insert passes. Methods with
328 /// out-of-line standard implementations are major CodeGen stages called by
329 /// addMachinePasses. Some targets may override major stages when inserting
330 /// passes is insufficient, but maintaining overriden stages is more work.
333 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
334 /// passes (which are run just before instruction selector).
335 virtual bool addPreISel() {
339 /// addMachineSSAOptimization - Add standard passes that optimize machine
340 /// instructions in SSA form.
341 virtual void addMachineSSAOptimization();
343 /// Add passes that optimize instruction level parallelism for out-of-order
344 /// targets. These passes are run while the machine code is still in SSA
345 /// form, so they can use MachineTraceMetrics to control their heuristics.
347 /// All passes added here should preserve the MachineDominatorTree,
348 /// MachineLoopInfo, and MachineTraceMetrics analyses.
349 virtual bool addILPOpts() {
353 /// This method may be implemented by targets that want to run passes
354 /// immediately before register allocation.
355 virtual void addPreRegAlloc() { }
357 /// createTargetRegisterAllocator - Create the register allocator pass for
358 /// this target at the current optimization level.
359 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
361 /// addFastRegAlloc - Add the minimum set of target-independent passes that
362 /// are required for fast register allocation.
363 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
365 /// addOptimizedRegAlloc - Add passes related to register allocation.
366 /// LLVMTargetMachine provides standard regalloc passes for most targets.
367 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
369 /// addPreRewrite - Add passes to the optimized register allocation pipeline
370 /// after register allocation is complete, but before virtual registers are
371 /// rewritten to physical registers.
373 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
374 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
375 /// When these passes run, VirtRegMap contains legal physreg assignments for
376 /// all virtual registers.
377 virtual bool addPreRewrite() {
381 /// This method may be implemented by targets that want to run passes after
382 /// register allocation pass pipeline but before prolog-epilog insertion.
383 virtual void addPostRegAlloc() { }
385 /// Add passes that optimize machine instructions after register allocation.
386 virtual void addMachineLateOptimization();
388 /// This method may be implemented by targets that want to run passes after
389 /// prolog-epilog insertion and before the second instruction scheduling pass.
390 virtual void addPreSched2() { }
392 /// addGCPasses - Add late codegen passes that analyze code for garbage
393 /// collection. This should return true if GC info should be printed after
395 virtual bool addGCPasses();
397 /// Add standard basic block placement passes.
398 virtual void addBlockPlacement();
400 /// This pass may be implemented by targets that want to run passes
401 /// immediately before machine code is emitted.
402 virtual void addPreEmitPass() { }
404 /// Targets may add passes immediately before machine code is emitted in this
405 /// callback. This is called even later than `addPreEmitPass`.
406 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
407 // position and remove the `2` suffix here as this callback is what
408 // `addPreEmitPass` *should* be but in reality isn't.
409 virtual void addPreEmitPass2() {}
411 /// Utilities for targets to add passes to the pass manager.
414 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
415 /// Return the pass that was added, or zero if no pass was added.
416 /// @p printAfter if true and adding a machine function pass add an extra
417 /// machine printer pass afterwards
418 /// @p verifyAfter if true and adding a machine function pass add an extra
419 /// machine verification pass afterwards.
420 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
421 bool printAfter = true);
423 /// Add a pass to the PassManager if that pass is supposed to be run, as
424 /// determined by the StartAfter and StopAfter options. Takes ownership of the
426 /// @p printAfter if true and adding a machine function pass add an extra
427 /// machine printer pass afterwards
428 /// @p verifyAfter if true and adding a machine function pass add an extra
429 /// machine verification pass afterwards.
430 void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
432 /// addMachinePasses helper to create the target-selected or overriden
434 FunctionPass *createRegAllocPass(bool Optimized);
437 } // end namespace llvm
439 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H