1 //===- llvm/CodeGen/TargetSchedule.h - Sched Machine Model ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a wrapper around MCSchedModel that allows the interface to
11 // benefit from information currently only available in TargetInstrInfo.
12 // Ideally, the scheduling interface would be fully defined in the MC layer.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
17 #define LLVM_CODEGEN_TARGETSCHEDULE_H
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/Config/llvm-config.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/MC/MCSchedule.h"
29 class TargetInstrInfo;
31 /// Provide an instruction scheduling machine model to CodeGen passes.
32 class TargetSchedModel {
33 // For efficiency, hold a copy of the statically defined MCSchedModel for this
35 MCSchedModel SchedModel;
36 InstrItineraryData InstrItins;
37 const TargetSubtargetInfo *STI = nullptr;
38 const TargetInstrInfo *TII = nullptr;
40 SmallVector<unsigned, 16> ResourceFactors;
41 unsigned MicroOpFactor; // Multiply to normalize microops to resource units.
42 unsigned ResourceLCM; // Resource units per cycle. Latency normalization factor.
44 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
47 TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {}
49 /// Initialize the machine model for instruction scheduling.
51 /// The machine model API keeps a copy of the top-level MCSchedModel table
52 /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
53 /// dynamic properties.
54 void init(const TargetSubtargetInfo *TSInfo);
56 /// Return the MCSchedClassDesc for this instruction.
57 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
59 /// TargetSubtargetInfo getter.
60 const TargetSubtargetInfo *getSubtargetInfo() const { return STI; }
62 /// TargetInstrInfo getter.
63 const TargetInstrInfo *getInstrInfo() const { return TII; }
65 /// Return true if this machine model includes an instruction-level
68 /// This is more detailed than the course grain IssueWidth and default
69 /// latency properties, but separate from the per-cycle itinerary data.
70 bool hasInstrSchedModel() const;
72 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
74 /// Return true if this machine model includes cycle-to-cycle itinerary
77 /// This models scheduling at each stage in the processor pipeline.
78 bool hasInstrItineraries() const;
80 const InstrItineraryData *getInstrItineraries() const {
81 if (hasInstrItineraries())
86 /// Return true if this machine model includes an instruction-level
87 /// scheduling model or cycle-to-cycle itinerary data.
88 bool hasInstrSchedModelOrItineraries() const {
89 return hasInstrSchedModel() || hasInstrItineraries();
92 /// Identify the processor corresponding to the current subtarget.
93 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
95 /// Maximum number of micro-ops that may be scheduled per cycle.
96 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
98 /// Return true if new group must begin.
99 bool mustBeginGroup(const MachineInstr *MI,
100 const MCSchedClassDesc *SC = nullptr) const;
101 /// Return true if current group must end.
102 bool mustEndGroup(const MachineInstr *MI,
103 const MCSchedClassDesc *SC = nullptr) const;
105 /// Return the number of issue slots required for this MI.
106 unsigned getNumMicroOps(const MachineInstr *MI,
107 const MCSchedClassDesc *SC = nullptr) const;
109 /// Get the number of kinds of resources for this target.
110 unsigned getNumProcResourceKinds() const {
111 return SchedModel.getNumProcResourceKinds();
114 /// Get a processor resource by ID for convenience.
115 const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
116 return SchedModel.getProcResource(PIdx);
119 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
120 const char *getResourceName(unsigned PIdx) const {
123 return SchedModel.getProcResource(PIdx)->Name;
127 using ProcResIter = const MCWriteProcResEntry *;
129 // Get an iterator into the processor resources consumed by this
131 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
132 // The subtarget holds a single resource table for all processors.
133 return STI->getWriteProcResBegin(SC);
135 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
136 return STI->getWriteProcResEnd(SC);
139 /// Multiply the number of units consumed for a resource by this factor
140 /// to normalize it relative to other resources.
141 unsigned getResourceFactor(unsigned ResIdx) const {
142 return ResourceFactors[ResIdx];
145 /// Multiply number of micro-ops by this factor to normalize it
146 /// relative to other resources.
147 unsigned getMicroOpFactor() const {
148 return MicroOpFactor;
151 /// Multiply cycle count by this factor to normalize it relative to
152 /// other resources. This is the number of resource units per cycle.
153 unsigned getLatencyFactor() const {
157 /// Number of micro-ops that may be buffered for OOO execution.
158 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
160 /// Number of resource units that may be buffered for OOO execution.
161 /// \return The buffer size in resource units or -1 for unlimited.
162 int getResourceBufferSize(unsigned PIdx) const {
163 return SchedModel.getProcResource(PIdx)->BufferSize;
166 /// Compute operand latency based on the available machine model.
168 /// Compute and return the latency of the given data dependent def and use
169 /// when the operand indices are already known. UseMI may be NULL for an
171 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
172 const MachineInstr *UseMI, unsigned UseOperIdx)
175 /// Compute the instruction latency based on the available machine
178 /// Compute and return the expected latency of this instruction independent of
179 /// a particular use. computeOperandLatency is the preferred API, but this is
180 /// occasionally useful to help estimate instruction cost.
182 /// If UseDefaultDefLatency is false and no new machine sched model is
183 /// present this method falls back to TII->getInstrLatency with an empty
184 /// instruction itinerary (this is so we preserve the previous behavior of the
185 /// if converter after moving it to TargetSchedModel).
186 unsigned computeInstrLatency(const MachineInstr *MI,
187 bool UseDefaultDefLatency = true) const;
188 unsigned computeInstrLatency(const MCInst &Inst) const;
189 unsigned computeInstrLatency(unsigned Opcode) const;
192 /// Output dependency latency of a pair of defs of the same register.
194 /// This is typically one cycle.
195 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
196 const MachineInstr *DepMI) const;
198 /// Compute the reciprocal throughput of the given instruction.
199 double computeReciprocalThroughput(const MachineInstr *MI) const;
200 double computeReciprocalThroughput(const MCInst &MI) const;
201 double computeReciprocalThroughput(unsigned Opcode) const;
204 } // end namespace llvm
206 #endif // LLVM_CODEGEN_TARGETSCHEDULE_H