1 //===- llvm/CodeGen/TargetSchedule.h - Sched Machine Model ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a wrapper around MCSchedModel that allows the interface to
11 // benefit from information currently only available in TargetInstrInfo.
12 // Ideally, the scheduling interface would be fully defined in the MC layer.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
17 #define LLVM_CODEGEN_TARGETSCHEDULE_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/MC/MCInstrItineraries.h"
21 #include "llvm/MC/MCSchedule.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
27 class TargetInstrInfo;
29 /// Provide an instruction scheduling machine model to CodeGen passes.
30 class TargetSchedModel {
31 // For efficiency, hold a copy of the statically defined MCSchedModel for this
33 MCSchedModel SchedModel;
34 InstrItineraryData InstrItins;
35 const TargetSubtargetInfo *STI = nullptr;
36 const TargetInstrInfo *TII = nullptr;
38 SmallVector<unsigned, 16> ResourceFactors;
39 unsigned MicroOpFactor; // Multiply to normalize microops to resource units.
40 unsigned ResourceLCM; // Resource units per cycle. Latency normalization factor.
42 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
45 TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {}
47 /// \brief Initialize the machine model for instruction scheduling.
49 /// The machine model API keeps a copy of the top-level MCSchedModel table
50 /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
51 /// dynamic properties.
52 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
53 const TargetInstrInfo *tii);
55 /// Return the MCSchedClassDesc for this instruction.
56 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
58 /// \brief TargetInstrInfo getter.
59 const TargetInstrInfo *getInstrInfo() const { return TII; }
61 /// \brief Return true if this machine model includes an instruction-level
64 /// This is more detailed than the course grain IssueWidth and default
65 /// latency properties, but separate from the per-cycle itinerary data.
66 bool hasInstrSchedModel() const;
68 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
70 /// \brief Return true if this machine model includes cycle-to-cycle itinerary
73 /// This models scheduling at each stage in the processor pipeline.
74 bool hasInstrItineraries() const;
76 const InstrItineraryData *getInstrItineraries() const {
77 if (hasInstrItineraries())
82 /// \brief Return true if this machine model includes an instruction-level
83 /// scheduling model or cycle-to-cycle itinerary data.
84 bool hasInstrSchedModelOrItineraries() const {
85 return hasInstrSchedModel() || hasInstrItineraries();
88 /// \brief Identify the processor corresponding to the current subtarget.
89 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
91 /// \brief Maximum number of micro-ops that may be scheduled per cycle.
92 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
94 /// \brief Return true if new group must begin.
95 bool mustBeginGroup(const MachineInstr *MI,
96 const MCSchedClassDesc *SC = nullptr) const;
97 /// \brief Return true if current group must end.
98 bool mustEndGroup(const MachineInstr *MI,
99 const MCSchedClassDesc *SC = nullptr) const;
101 /// \brief Return the number of issue slots required for this MI.
102 unsigned getNumMicroOps(const MachineInstr *MI,
103 const MCSchedClassDesc *SC = nullptr) const;
105 /// \brief Get the number of kinds of resources for this target.
106 unsigned getNumProcResourceKinds() const {
107 return SchedModel.getNumProcResourceKinds();
110 /// \brief Get a processor resource by ID for convenience.
111 const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
112 return SchedModel.getProcResource(PIdx);
116 const char *getResourceName(unsigned PIdx) const {
119 return SchedModel.getProcResource(PIdx)->Name;
123 typedef const MCWriteProcResEntry *ProcResIter;
125 // \brief Get an iterator into the processor resources consumed by this
127 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
128 // The subtarget holds a single resource table for all processors.
129 return STI->getWriteProcResBegin(SC);
131 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
132 return STI->getWriteProcResEnd(SC);
135 /// \brief Multiply the number of units consumed for a resource by this factor
136 /// to normalize it relative to other resources.
137 unsigned getResourceFactor(unsigned ResIdx) const {
138 return ResourceFactors[ResIdx];
141 /// \brief Multiply number of micro-ops by this factor to normalize it
142 /// relative to other resources.
143 unsigned getMicroOpFactor() const {
144 return MicroOpFactor;
147 /// \brief Multiply cycle count by this factor to normalize it relative to
148 /// other resources. This is the number of resource units per cycle.
149 unsigned getLatencyFactor() const {
153 /// \brief Number of micro-ops that may be buffered for OOO execution.
154 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
156 /// \brief Number of resource units that may be buffered for OOO execution.
157 /// \return The buffer size in resource units or -1 for unlimited.
158 int getResourceBufferSize(unsigned PIdx) const {
159 return SchedModel.getProcResource(PIdx)->BufferSize;
162 /// \brief Compute operand latency based on the available machine model.
164 /// Compute and return the latency of the given data dependent def and use
165 /// when the operand indices are already known. UseMI may be NULL for an
167 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
168 const MachineInstr *UseMI, unsigned UseOperIdx)
171 /// \brief Compute the instruction latency based on the available machine
174 /// Compute and return the expected latency of this instruction independent of
175 /// a particular use. computeOperandLatency is the preferred API, but this is
176 /// occasionally useful to help estimate instruction cost.
178 /// If UseDefaultDefLatency is false and no new machine sched model is
179 /// present this method falls back to TII->getInstrLatency with an empty
180 /// instruction itinerary (this is so we preserve the previous behavior of the
181 /// if converter after moving it to TargetSchedModel).
182 unsigned computeInstrLatency(const MachineInstr *MI,
183 bool UseDefaultDefLatency = true) const;
184 unsigned computeInstrLatency(unsigned Opcode) const;
187 /// \brief Output dependency latency of a pair of defs of the same register.
189 /// This is typically one cycle.
190 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
191 const MachineInstr *DepMI) const;
193 /// \brief Compute the reciprocal throughput of the given instruction.
194 Optional<double> computeInstrRThroughput(const MachineInstr *MI) const;
195 Optional<double> computeInstrRThroughput(unsigned Opcode) const;
198 } // end namespace llvm
200 #endif // LLVM_CODEGEN_TARGETSCHEDULE_H