1 //===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a virtual register map. This maps virtual registers to
11 // physical registers and virtual registers to stack slots. It is created and
12 // updated by a register allocator and then used by a machine code rewriter that
13 // adds spill code and rewrites virtual into physical register references.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_VIRTREGMAP_H
18 #define LLVM_CODEGEN_VIRTREGMAP_H
20 #include "llvm/ADT/IndexedMap.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
26 class MachineFunction;
27 class MachineRegisterInfo;
28 class TargetInstrInfo;
32 class VirtRegMap : public MachineFunctionPass {
36 NO_STACK_SLOT = (1L << 30)-1,
37 MAX_STACK_SLOT = (1L << 18)-1
41 MachineRegisterInfo *MRI;
42 const TargetInstrInfo *TII;
43 const TargetRegisterInfo *TRI;
46 /// Virt2PhysMap - This is a virtual to physical register
47 /// mapping. Each virtual register is required to have an entry in
48 /// it; even spilled virtual registers (the register mapped to a
49 /// spilled register is the temporary used to load it from the
51 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
53 /// Virt2StackSlotMap - This is virtual register to stack slot
54 /// mapping. Each spilled virtual register has an entry in it
55 /// which corresponds to the stack slot this register is spilled
57 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
59 /// Virt2SplitMap - This is virtual register to splitted virtual register
61 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
63 /// createSpillSlot - Allocate a spill slot for RC from MFI.
64 unsigned createSpillSlot(const TargetRegisterClass *RC);
66 VirtRegMap(const VirtRegMap&) = delete;
67 void operator=(const VirtRegMap&) = delete;
71 VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
72 Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) { }
73 bool runOnMachineFunction(MachineFunction &MF) override;
75 void getAnalysisUsage(AnalysisUsage &AU) const override {
77 MachineFunctionPass::getAnalysisUsage(AU);
80 MachineFunction &getMachineFunction() const {
81 assert(MF && "getMachineFunction called before runOnMachineFunction");
85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
86 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
90 /// @brief returns true if the specified virtual register is
91 /// mapped to a physical register
92 bool hasPhys(unsigned virtReg) const {
93 return getPhys(virtReg) != NO_PHYS_REG;
96 /// @brief returns the physical register mapped to the specified
98 unsigned getPhys(unsigned virtReg) const {
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
100 return Virt2PhysMap[virtReg];
103 /// @brief creates a mapping for the specified virtual register to
104 /// the specified physical register
105 void assignVirt2Phys(unsigned virtReg, MCPhysReg physReg);
107 /// @brief clears the specified virtual register's, physical
109 void clearVirt(unsigned virtReg) {
110 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
111 assert(Virt2PhysMap[virtReg] != NO_PHYS_REG &&
112 "attempt to clear a not assigned virtual register");
113 Virt2PhysMap[virtReg] = NO_PHYS_REG;
116 /// @brief clears all virtual to physical register mappings
117 void clearAllVirt() {
118 Virt2PhysMap.clear();
122 /// @brief returns true if VirtReg is assigned to its preferred physreg.
123 bool hasPreferredPhys(unsigned VirtReg);
125 /// @brief returns true if VirtReg has a known preferred register.
126 /// This returns false if VirtReg has a preference that is a virtual
127 /// register that hasn't been assigned yet.
128 bool hasKnownPreference(unsigned VirtReg);
130 /// @brief records virtReg is a split live interval from SReg.
131 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
132 Virt2SplitMap[virtReg] = SReg;
135 /// @brief returns the live interval virtReg is split from.
136 unsigned getPreSplitReg(unsigned virtReg) const {
137 return Virt2SplitMap[virtReg];
140 /// getOriginal - Return the original virtual register that VirtReg descends
141 /// from through splitting.
142 /// A register that was not created by splitting is its own original.
143 /// This operation is idempotent.
144 unsigned getOriginal(unsigned VirtReg) const {
145 unsigned Orig = getPreSplitReg(VirtReg);
146 return Orig ? Orig : VirtReg;
149 /// @brief returns true if the specified virtual register is not
150 /// mapped to a stack slot or rematerialized.
151 bool isAssignedReg(unsigned virtReg) const {
152 if (getStackSlot(virtReg) == NO_STACK_SLOT)
154 // Split register can be assigned a physical register as well as a
155 // stack slot or remat id.
156 return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG);
159 /// @brief returns the stack slot mapped to the specified virtual
161 int getStackSlot(unsigned virtReg) const {
162 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
163 return Virt2StackSlotMap[virtReg];
166 /// @brief create a mapping for the specifed virtual register to
167 /// the next available stack slot
168 int assignVirt2StackSlot(unsigned virtReg);
169 /// @brief create a mapping for the specified virtual register to
170 /// the specified stack slot
171 void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
173 void print(raw_ostream &OS, const Module* M = nullptr) const override;
177 inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
181 } // End llvm namespace