1 //===- llvm/InlineAsm.h - Class to represent inline asm strings -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class represents the inline asm strings, which are Value*'s that are
11 // used as the callee operand of call instructions. InlineAsm's are uniqued
12 // like constants, and created via InlineAsm::get(...).
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_IR_INLINEASM_H
17 #define LLVM_IR_INLINEASM_H
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/IR/Value.h"
29 template <class ConstantClass> class ConstantUniqueMap;
31 class InlineAsm : public Value {
39 friend struct InlineAsmKeyType;
40 friend class ConstantUniqueMap<InlineAsm>;
42 std::string AsmString, Constraints;
48 InlineAsm(FunctionType *Ty, const std::string &AsmString,
49 const std::string &Constraints, bool hasSideEffects,
50 bool isAlignStack, AsmDialect asmDialect);
51 ~InlineAsm() override;
53 /// When the ConstantUniqueMap merges two types and makes two InlineAsms
54 /// identical, it destroys one of them with this method.
55 void destroyConstant();
58 InlineAsm(const InlineAsm &) = delete;
59 InlineAsm &operator=(const InlineAsm &) = delete;
61 /// InlineAsm::get - Return the specified uniqued inline asm string.
63 static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
64 StringRef Constraints, bool hasSideEffects,
65 bool isAlignStack = false,
66 AsmDialect asmDialect = AD_ATT);
68 bool hasSideEffects() const { return HasSideEffects; }
69 bool isAlignStack() const { return IsAlignStack; }
70 AsmDialect getDialect() const { return Dialect; }
72 /// getType - InlineAsm's are always pointers.
74 PointerType *getType() const {
75 return reinterpret_cast<PointerType*>(Value::getType());
78 /// getFunctionType - InlineAsm's are always pointers to functions.
80 FunctionType *getFunctionType() const;
82 const std::string &getAsmString() const { return AsmString; }
83 const std::string &getConstraintString() const { return Constraints; }
85 /// Verify - This static method can be used by the parser to check to see if
86 /// the specified constraint string is legal for the type. This returns true
87 /// if legal, false if not.
89 static bool Verify(FunctionType *Ty, StringRef Constraints);
91 // Constraint String Parsing
92 enum ConstraintPrefix {
98 typedef std::vector<std::string> ConstraintCodeVector;
100 struct SubConstraintInfo {
101 /// MatchingInput - If this is not -1, this is an output constraint where an
102 /// input constraint is required to match it (e.g. "0"). The value is the
103 /// constraint number that matches this one (for example, if this is
104 /// constraint #0 and constraint #4 has the value "0", this will be 4).
105 signed char MatchingInput = -1;
107 /// Code - The constraint code, either the register name (in braces) or the
108 /// constraint letter/number.
109 ConstraintCodeVector Codes;
111 /// Default constructor.
112 SubConstraintInfo() = default;
115 typedef std::vector<SubConstraintInfo> SubConstraintInfoVector;
116 struct ConstraintInfo;
117 typedef std::vector<ConstraintInfo> ConstraintInfoVector;
119 struct ConstraintInfo {
120 /// Type - The basic type of the constraint: input/output/clobber
122 ConstraintPrefix Type = isInput;
124 /// isEarlyClobber - "&": output operand writes result before inputs are all
125 /// read. This is only ever set for an output operand.
126 bool isEarlyClobber = false;
128 /// MatchingInput - If this is not -1, this is an output constraint where an
129 /// input constraint is required to match it (e.g. "0"). The value is the
130 /// constraint number that matches this one (for example, if this is
131 /// constraint #0 and constraint #4 has the value "0", this will be 4).
132 signed char MatchingInput = -1;
134 /// hasMatchingInput - Return true if this is an output constraint that has
135 /// a matching input constraint.
136 bool hasMatchingInput() const { return MatchingInput != -1; }
138 /// isCommutative - This is set to true for a constraint that is commutative
139 /// with the next operand.
140 bool isCommutative = false;
142 /// isIndirect - True if this operand is an indirect operand. This means
143 /// that the address of the source or destination is present in the call
144 /// instruction, instead of it being returned or passed in explicitly. This
145 /// is represented with a '*' in the asm string.
146 bool isIndirect = false;
148 /// Code - The constraint code, either the register name (in braces) or the
149 /// constraint letter/number.
150 ConstraintCodeVector Codes;
152 /// isMultipleAlternative - '|': has multiple-alternative constraints.
153 bool isMultipleAlternative = false;
155 /// multipleAlternatives - If there are multiple alternative constraints,
156 /// this array will contain them. Otherwise it will be empty.
157 SubConstraintInfoVector multipleAlternatives;
159 /// The currently selected alternative constraint index.
160 unsigned currentAlternativeIndex = 0;
162 /// Default constructor.
163 ConstraintInfo() = default;
165 /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
166 /// fields in this structure. If the constraint string is not understood,
167 /// return true, otherwise return false.
168 bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
170 /// selectAlternative - Point this constraint to the alternative constraint
171 /// indicated by the index.
172 void selectAlternative(unsigned index);
175 /// ParseConstraints - Split up the constraint string into the specific
176 /// constraints and their prefixes. If this returns an empty vector, and if
177 /// the constraint string itself isn't empty, there was an error parsing.
178 static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
180 /// ParseConstraints - Parse the constraints of this inlineasm object,
181 /// returning them the same way that ParseConstraints(str) does.
182 ConstraintInfoVector ParseConstraints() const {
183 return ParseConstraints(Constraints);
186 // Methods for support type inquiry through isa, cast, and dyn_cast:
187 static inline bool classof(const Value *V) {
188 return V->getValueID() == Value::InlineAsmVal;
191 // These are helper methods for dealing with flags in the INLINEASM SDNode
194 // The encoding of the flag word is currently:
195 // Bits 2-0 - A Kind_* value indicating the kind of the operand.
196 // Bits 15-3 - The number of SDNode operands associated with this inline
199 // Bit 30-16 - The operand number that this operand must match.
200 // When bits 2-0 are Kind_Mem, the Constraint_* value must be
201 // obtained from the flags for this operand number.
202 // Else if bits 2-0 are Kind_Mem:
203 // Bit 30-16 - A Constraint_* value indicating the original constraint
206 // Bit 30-16 - The register class ID to use for the operand.
209 // Fixed operands on an INLINEASM SDNode.
213 Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
216 // Fixed operands on an INLINEASM MachineInstr.
218 MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
219 MIOp_FirstOperand = 2,
221 // Interpretation of the MIOp_ExtraInfo bit field.
222 Extra_HasSideEffects = 1,
223 Extra_IsAlignStack = 2,
224 Extra_AsmDialect = 4,
227 Extra_IsConvergent = 32,
229 // Inline asm operands map to multiple SDNode / MachineInstr operands.
230 // The first operand is an immediate describing the asm operand, the low
232 Kind_RegUse = 1, // Input register, "r".
233 Kind_RegDef = 2, // Output register, "=r".
234 Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
235 Kind_Clobber = 4, // Clobbered register, "~r".
236 Kind_Imm = 5, // Immediate.
237 Kind_Mem = 6, // Memory operand, "m".
239 // Memory constraint codes.
240 // These could be tablegenerated but there's little need to do that since
241 // there's plenty of space in the encoding to support the union of all
242 // constraint codes for all targets.
243 Constraint_Unknown = 0,
264 Constraints_Max = Constraint_Zy,
265 Constraints_ShiftAmount = 16,
267 Flag_MatchingOperand = 0x80000000
270 static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
271 assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
272 assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
273 return Kind | (NumOps << 3);
276 static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
277 static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
278 static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
279 static bool isRegDefEarlyClobberKind(unsigned Flag) {
280 return getKind(Flag) == Kind_RegDefEarlyClobber;
282 static bool isClobberKind(unsigned Flag) {
283 return getKind(Flag) == Kind_Clobber;
286 /// getFlagWordForMatchingOp - Augment an existing flag word returned by
287 /// getFlagWord with information indicating that this input operand is tied
288 /// to a previous output operand.
289 static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
290 unsigned MatchedOperandNo) {
291 assert(MatchedOperandNo <= 0x7fff && "Too big matched operand");
292 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
293 return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16);
296 /// getFlagWordForRegClass - Augment an existing flag word returned by
297 /// getFlagWord with the required register class for the following register
299 /// A tied use operand cannot have a register class, use the register class
300 /// from the def operand instead.
301 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
302 // Store RC + 1, reserve the value 0 to mean 'no register class'.
304 assert(!isImmKind(InputFlag) && "Immediates cannot have a register class");
305 assert(!isMemKind(InputFlag) && "Memory operand cannot have a register class");
306 assert(RC <= 0x7fff && "Too large register class ID");
307 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
308 return InputFlag | (RC << 16);
311 /// Augment an existing flag word returned by getFlagWord with the constraint
312 /// code for a memory constraint.
313 static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
314 assert(isMemKind(InputFlag) && "InputFlag is not a memory constraint!");
315 assert(Constraint <= 0x7fff && "Too large a memory constraint ID");
316 assert(Constraint <= Constraints_Max && "Unknown constraint ID");
317 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
318 return InputFlag | (Constraint << Constraints_ShiftAmount);
321 static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) {
322 assert(isMemKind(InputFlag));
323 return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
326 static unsigned getKind(unsigned Flags) {
330 static unsigned getMemoryConstraintID(unsigned Flag) {
331 assert(isMemKind(Flag));
332 return (Flag >> Constraints_ShiftAmount) & 0x7fff;
335 /// getNumOperandRegisters - Extract the number of registers field from the
336 /// inline asm operand flag.
337 static unsigned getNumOperandRegisters(unsigned Flag) {
338 return (Flag & 0xffff) >> 3;
341 /// isUseOperandTiedToDef - Return true if the flag of the inline asm
342 /// operand indicates it is an use operand that's matched to a def operand.
343 static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
344 if ((Flag & Flag_MatchingOperand) == 0)
346 Idx = (Flag & ~Flag_MatchingOperand) >> 16;
350 /// hasRegClassConstraint - Returns true if the flag contains a register
351 /// class constraint. Sets RC to the register class ID.
352 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
353 if (Flag & Flag_MatchingOperand)
355 unsigned High = Flag >> 16;
356 // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
365 } // end namespace llvm
367 #endif // LLVM_IR_INLINEASM_H