contrib/llvm/include/llvm/IR/IntrinsicsAArch64.td

   1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the AARCH64-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let TargetPrefix = "aarch64" in {
  15
  16 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
  17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
  18 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
  19 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
  20
  21 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
  22 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
  23 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
  24                                [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
  25 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
  26                                 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
  27
  28 def int_aarch64_clrex : Intrinsic<[]>;
  29
  30 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  31                                 LLVMMatchType<0>], [IntrNoMem]>;
  32 def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  33                                 LLVMMatchType<0>], [IntrNoMem]>;
  34
  35 //===----------------------------------------------------------------------===//
  36 // HINT
  37
  38 def int_aarch64_hint : Intrinsic<[], [llvm_i32_ty]>;
  39
  40 //===----------------------------------------------------------------------===//
  41 // Data Barrier Instructions
  42
  43 def int_aarch64_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">, Intrinsic<[], [llvm_i32_ty]>;
  44 def int_aarch64_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">, Intrinsic<[], [llvm_i32_ty]>;
  45 def int_aarch64_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">, Intrinsic<[], [llvm_i32_ty]>;
  46
  47 }
  48
  49 //===----------------------------------------------------------------------===//
  50 // Advanced SIMD (NEON)
  51
  52 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
  53   class AdvSIMD_2Scalar_Float_Intrinsic
  54     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  55                 [IntrNoMem]>;
  56
  57   class AdvSIMD_FPToIntRounding_Intrinsic
  58     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
  59
  60   class AdvSIMD_1IntArg_Intrinsic
  61     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  62   class AdvSIMD_1FloatArg_Intrinsic
  63     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  64   class AdvSIMD_1VectorArg_Intrinsic
  65     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  66   class AdvSIMD_1VectorArg_Expand_Intrinsic
  67     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  68   class AdvSIMD_1VectorArg_Long_Intrinsic
  69     : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
  70   class AdvSIMD_1IntArg_Narrow_Intrinsic
  71     : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
  72   class AdvSIMD_1VectorArg_Narrow_Intrinsic
  73     : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
  74   class AdvSIMD_1VectorArg_Int_Across_Intrinsic
  75     : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  76   class AdvSIMD_1VectorArg_Float_Across_Intrinsic
  77     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  78
  79   class AdvSIMD_2IntArg_Intrinsic
  80     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  81                 [IntrNoMem]>;
  82   class AdvSIMD_2FloatArg_Intrinsic
  83     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  84                 [IntrNoMem]>;
  85   class AdvSIMD_2VectorArg_Intrinsic
  86     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  87                 [IntrNoMem]>;
  88   class AdvSIMD_2VectorArg_Compare_Intrinsic
  89     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
  90                 [IntrNoMem]>;
  91   class AdvSIMD_2Arg_FloatCompare_Intrinsic
  92     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
  93                 [IntrNoMem]>;
  94   class AdvSIMD_2VectorArg_Long_Intrinsic
  95     : Intrinsic<[llvm_anyvector_ty],
  96                 [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
  97                 [IntrNoMem]>;
  98   class AdvSIMD_2VectorArg_Wide_Intrinsic
  99     : Intrinsic<[llvm_anyvector_ty],
 100                 [LLVMMatchType<0>, LLVMTruncatedType<0>],
 101                 [IntrNoMem]>;
 102   class AdvSIMD_2VectorArg_Narrow_Intrinsic
 103     : Intrinsic<[llvm_anyvector_ty],
 104                 [LLVMExtendedType<0>, LLVMExtendedType<0>],
 105                 [IntrNoMem]>;
 106   class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
 107     : Intrinsic<[llvm_anyint_ty],
 108                 [LLVMExtendedType<0>, llvm_i32_ty],
 109                 [IntrNoMem]>;
 110   class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
 111     : Intrinsic<[llvm_anyvector_ty],
 112                 [llvm_anyvector_ty],
 113                 [IntrNoMem]>;
 114   class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
 115     : Intrinsic<[llvm_anyvector_ty],
 116                 [LLVMTruncatedType<0>],
 117                 [IntrNoMem]>;
 118   class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
 119     : Intrinsic<[llvm_anyvector_ty],
 120                 [LLVMTruncatedType<0>, llvm_i32_ty],
 121                 [IntrNoMem]>;
 122   class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
 123     : Intrinsic<[llvm_anyvector_ty],
 124                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
 125                 [IntrNoMem]>;
 126
 127   class AdvSIMD_3VectorArg_Intrinsic
 128       : Intrinsic<[llvm_anyvector_ty],
 129                [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 130                [IntrNoMem]>;
 131   class AdvSIMD_3VectorArg_Scalar_Intrinsic
 132       : Intrinsic<[llvm_anyvector_ty],
 133                [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
 134                [IntrNoMem]>;
 135   class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
 136       : Intrinsic<[llvm_anyvector_ty],
 137                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
 138                 LLVMMatchType<1>], [IntrNoMem]>;
 139   class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
 140     : Intrinsic<[llvm_anyvector_ty],
 141                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
 142                 [IntrNoMem]>;
 143   class AdvSIMD_CvtFxToFP_Intrinsic
 144     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
 145                 [IntrNoMem]>;
 146   class AdvSIMD_CvtFPToFx_Intrinsic
 147     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
 148                 [IntrNoMem]>;
 149
 150   class AdvSIMD_1Arg_Intrinsic
 151     : Intrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 152
 153   class AdvSIMD_Dot_Intrinsic
 154     : Intrinsic<[llvm_anyvector_ty],
 155                 [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>],
 156                 [IntrNoMem]>;
 157 }
 158
 159 // Arithmetic ops
 160
 161 let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem] in {
 162   // Vector Add Across Lanes
 163   def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 164   def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 165   def int_aarch64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 166
 167   // Vector Long Add Across Lanes
 168   def int_aarch64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 169   def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 170
 171   // Vector Halving Add
 172   def int_aarch64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
 173   def int_aarch64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
 174
 175   // Vector Rounding Halving Add
 176   def int_aarch64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
 177   def int_aarch64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
 178
 179   // Vector Saturating Add
 180   def int_aarch64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
 181   def int_aarch64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
 182   def int_aarch64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
 183   def int_aarch64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
 184
 185   // Vector Add High-Half
 186   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 187   // header is no longer supported.
 188   def int_aarch64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 189
 190   // Vector Rounding Add High-Half
 191   def int_aarch64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 192
 193   // Vector Saturating Doubling Multiply High
 194   def int_aarch64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
 195
 196   // Vector Saturating Rounding Doubling Multiply High
 197   def int_aarch64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
 198
 199   // Vector Polynominal Multiply
 200   def int_aarch64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
 201
 202   // Vector Long Multiply
 203   def int_aarch64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
 204   def int_aarch64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
 205   def int_aarch64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 206
 207   // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
 208   // it with a v16i8.
 209   def int_aarch64_neon_pmull64 :
 210         Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
 211
 212   // Vector Extending Multiply
 213   def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
 214     let IntrProperties = [IntrNoMem, Commutative];
 215   }
 216
 217   // Vector Saturating Doubling Long Multiply
 218   def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 219   def int_aarch64_neon_sqdmulls_scalar
 220     : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 221
 222   // Vector Halving Subtract
 223   def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
 224   def int_aarch64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
 225
 226   // Vector Saturating Subtract
 227   def int_aarch64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
 228   def int_aarch64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
 229
 230   // Vector Subtract High-Half
 231   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 232   // header is no longer supported.
 233   def int_aarch64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 234
 235   // Vector Rounding Subtract High-Half
 236   def int_aarch64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 237
 238   // Vector Compare Absolute Greater-than-or-equal
 239   def int_aarch64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 240
 241   // Vector Compare Absolute Greater-than
 242   def int_aarch64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 243
 244   // Vector Absolute Difference
 245   def int_aarch64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
 246   def int_aarch64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
 247   def int_aarch64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
 248
 249   // Scalar Absolute Difference
 250   def int_aarch64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
 251
 252   // Vector Max
 253   def int_aarch64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
 254   def int_aarch64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
 255   def int_aarch64_neon_fmax : AdvSIMD_2FloatArg_Intrinsic;
 256   def int_aarch64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
 257
 258   // Vector Max Across Lanes
 259   def int_aarch64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 260   def int_aarch64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 261   def int_aarch64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 262   def int_aarch64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 263
 264   // Vector Min
 265   def int_aarch64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
 266   def int_aarch64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
 267   def int_aarch64_neon_fmin : AdvSIMD_2FloatArg_Intrinsic;
 268   def int_aarch64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
 269
 270   // Vector Min/Max Number
 271   def int_aarch64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
 272   def int_aarch64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
 273
 274   // Vector Min Across Lanes
 275   def int_aarch64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 276   def int_aarch64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 277   def int_aarch64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 278   def int_aarch64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 279
 280   // Pairwise Add
 281   def int_aarch64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
 282
 283   // Long Pairwise Add
 284   // FIXME: In theory, we shouldn't need intrinsics for saddlp or
 285   // uaddlp, but tblgen's type inference currently can't handle the
 286   // pattern fragments this ends up generating.
 287   def int_aarch64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 288   def int_aarch64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 289
 290   // Folding Maximum
 291   def int_aarch64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
 292   def int_aarch64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
 293   def int_aarch64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
 294
 295   // Folding Minimum
 296   def int_aarch64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
 297   def int_aarch64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
 298   def int_aarch64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
 299
 300   // Reciprocal Estimate/Step
 301   def int_aarch64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
 302   def int_aarch64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
 303
 304   // Reciprocal Exponent
 305   def int_aarch64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic;
 306
 307   // Vector Saturating Shift Left
 308   def int_aarch64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
 309   def int_aarch64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
 310
 311   // Vector Rounding Shift Left
 312   def int_aarch64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
 313   def int_aarch64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
 314
 315   // Vector Saturating Rounding Shift Left
 316   def int_aarch64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
 317   def int_aarch64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
 318
 319   // Vector Signed->Unsigned Shift Left by Constant
 320   def int_aarch64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
 321
 322   // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
 323   def int_aarch64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 324
 325   // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
 326   def int_aarch64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 327
 328   // Vector Narrowing Shift Right by Constant
 329   def int_aarch64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 330   def int_aarch64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 331
 332   // Vector Rounding Narrowing Shift Right by Constant
 333   def int_aarch64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 334
 335   // Vector Rounding Narrowing Saturating Shift Right by Constant
 336   def int_aarch64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 337   def int_aarch64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 338
 339   // Vector Shift Left
 340   def int_aarch64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
 341   def int_aarch64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
 342
 343   // Vector Widening Shift Left by Constant
 344   def int_aarch64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
 345   def int_aarch64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 346   def int_aarch64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 347
 348   // Vector Shift Right by Constant and Insert
 349   def int_aarch64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 350
 351   // Vector Shift Left by Constant and Insert
 352   def int_aarch64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 353
 354   // Vector Saturating Narrow
 355   def int_aarch64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
 356   def int_aarch64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
 357   def int_aarch64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 358   def int_aarch64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 359
 360   // Vector Saturating Extract and Unsigned Narrow
 361   def int_aarch64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
 362   def int_aarch64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 363
 364   // Vector Absolute Value
 365   def int_aarch64_neon_abs : AdvSIMD_1Arg_Intrinsic;
 366
 367   // Vector Saturating Absolute Value
 368   def int_aarch64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
 369
 370   // Vector Saturating Negation
 371   def int_aarch64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
 372
 373   // Vector Count Leading Sign Bits
 374   def int_aarch64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
 375
 376   // Vector Reciprocal Estimate
 377   def int_aarch64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
 378   def int_aarch64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic;
 379
 380   // Vector Square Root Estimate
 381   def int_aarch64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
 382   def int_aarch64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic;
 383
 384   // Vector Bitwise Reverse
 385   def int_aarch64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
 386
 387   // Vector Conversions Between Half-Precision and Single-Precision.
 388   def int_aarch64_neon_vcvtfp2hf
 389     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 390   def int_aarch64_neon_vcvthf2fp
 391     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 392
 393   // Vector Conversions Between Floating-point and Fixed-point.
 394   def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
 395   def int_aarch64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
 396   def int_aarch64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 397   def int_aarch64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 398
 399   // Vector FP->Int Conversions
 400   def int_aarch64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
 401   def int_aarch64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
 402   def int_aarch64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
 403   def int_aarch64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
 404   def int_aarch64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
 405   def int_aarch64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
 406   def int_aarch64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
 407   def int_aarch64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
 408   def int_aarch64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
 409   def int_aarch64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
 410
 411   // Vector FP Rounding: only ties to even is unrepresented by a normal
 412   // intrinsic.
 413   def int_aarch64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
 414
 415   // Scalar FP->Int conversions
 416
 417   // Vector FP Inexact Narrowing
 418   def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
 419
 420   // Scalar FP Inexact Narrowing
 421   def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
 422                                         [IntrNoMem]>;
 423
 424   // v8.2-A Dot Product
 425   def int_aarch64_neon_udot : AdvSIMD_Dot_Intrinsic;
 426   def int_aarch64_neon_sdot : AdvSIMD_Dot_Intrinsic;
 427 }
 428
 429 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 430   class AdvSIMD_2Vector2Index_Intrinsic
 431     : Intrinsic<[llvm_anyvector_ty],
 432                 [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
 433                 [IntrNoMem]>;
 434 }
 435
 436 // Vector element to element moves
 437 def int_aarch64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
 438
 439 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 440   class AdvSIMD_1Vec_Load_Intrinsic
 441       : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
 442                   [IntrReadMem, IntrArgMemOnly]>;
 443   class AdvSIMD_1Vec_Store_Lane_Intrinsic
 444     : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
 445                 [IntrArgMemOnly, NoCapture<2>]>;
 446
 447   class AdvSIMD_2Vec_Load_Intrinsic
 448     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 449                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 450                 [IntrReadMem, IntrArgMemOnly]>;
 451   class AdvSIMD_2Vec_Load_Lane_Intrinsic
 452     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 453                 [LLVMMatchType<0>, LLVMMatchType<0>,
 454                  llvm_i64_ty, llvm_anyptr_ty],
 455                 [IntrReadMem, IntrArgMemOnly]>;
 456   class AdvSIMD_2Vec_Store_Intrinsic
 457     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 458                      LLVMAnyPointerType<LLVMMatchType<0>>],
 459                 [IntrArgMemOnly, NoCapture<2>]>;
 460   class AdvSIMD_2Vec_Store_Lane_Intrinsic
 461     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 462                  llvm_i64_ty, llvm_anyptr_ty],
 463                 [IntrArgMemOnly, NoCapture<3>]>;
 464
 465   class AdvSIMD_3Vec_Load_Intrinsic
 466     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 467                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 468                 [IntrReadMem, IntrArgMemOnly]>;
 469   class AdvSIMD_3Vec_Load_Lane_Intrinsic
 470     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 471                 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
 472                  llvm_i64_ty, llvm_anyptr_ty],
 473                 [IntrReadMem, IntrArgMemOnly]>;
 474   class AdvSIMD_3Vec_Store_Intrinsic
 475     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 476                      LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
 477                 [IntrArgMemOnly, NoCapture<3>]>;
 478   class AdvSIMD_3Vec_Store_Lane_Intrinsic
 479     : Intrinsic<[], [llvm_anyvector_ty,
 480                  LLVMMatchType<0>, LLVMMatchType<0>,
 481                  llvm_i64_ty, llvm_anyptr_ty],
 482                 [IntrArgMemOnly, NoCapture<4>]>;
 483
 484   class AdvSIMD_4Vec_Load_Intrinsic
 485     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 486                  LLVMMatchType<0>, LLVMMatchType<0>],
 487                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 488                 [IntrReadMem, IntrArgMemOnly]>;
 489   class AdvSIMD_4Vec_Load_Lane_Intrinsic
 490     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 491                  LLVMMatchType<0>, LLVMMatchType<0>],
 492                 [LLVMMatchType<0>, LLVMMatchType<0>,
 493                  LLVMMatchType<0>, LLVMMatchType<0>,
 494                  llvm_i64_ty, llvm_anyptr_ty],
 495                 [IntrReadMem, IntrArgMemOnly]>;
 496   class AdvSIMD_4Vec_Store_Intrinsic
 497     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 498                  LLVMMatchType<0>, LLVMMatchType<0>,
 499                  LLVMAnyPointerType<LLVMMatchType<0>>],
 500                 [IntrArgMemOnly, NoCapture<4>]>;
 501   class AdvSIMD_4Vec_Store_Lane_Intrinsic
 502     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 503                  LLVMMatchType<0>, LLVMMatchType<0>,
 504                  llvm_i64_ty, llvm_anyptr_ty],
 505                 [IntrArgMemOnly, NoCapture<5>]>;
 506 }
 507
 508 // Memory ops
 509
 510 def int_aarch64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
 511 def int_aarch64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
 512 def int_aarch64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
 513
 514 def int_aarch64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
 515 def int_aarch64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
 516 def int_aarch64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
 517
 518 def int_aarch64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
 519 def int_aarch64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
 520 def int_aarch64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
 521
 522 def int_aarch64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
 523 def int_aarch64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
 524 def int_aarch64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
 525
 526 def int_aarch64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
 527 def int_aarch64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
 528 def int_aarch64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
 529
 530 def int_aarch64_neon_st2  : AdvSIMD_2Vec_Store_Intrinsic;
 531 def int_aarch64_neon_st3  : AdvSIMD_3Vec_Store_Intrinsic;
 532 def int_aarch64_neon_st4  : AdvSIMD_4Vec_Store_Intrinsic;
 533
 534 def int_aarch64_neon_st2lane  : AdvSIMD_2Vec_Store_Lane_Intrinsic;
 535 def int_aarch64_neon_st3lane  : AdvSIMD_3Vec_Store_Lane_Intrinsic;
 536 def int_aarch64_neon_st4lane  : AdvSIMD_4Vec_Store_Lane_Intrinsic;
 537
 538 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 539   class AdvSIMD_Tbl1_Intrinsic
 540     : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
 541                 [IntrNoMem]>;
 542   class AdvSIMD_Tbl2_Intrinsic
 543     : Intrinsic<[llvm_anyvector_ty],
 544                 [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
 545   class AdvSIMD_Tbl3_Intrinsic
 546     : Intrinsic<[llvm_anyvector_ty],
 547                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 548                  LLVMMatchType<0>],
 549                 [IntrNoMem]>;
 550   class AdvSIMD_Tbl4_Intrinsic
 551     : Intrinsic<[llvm_anyvector_ty],
 552                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 553                  LLVMMatchType<0>],
 554                 [IntrNoMem]>;
 555
 556   class AdvSIMD_Tbx1_Intrinsic
 557     : Intrinsic<[llvm_anyvector_ty],
 558                 [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
 559                 [IntrNoMem]>;
 560   class AdvSIMD_Tbx2_Intrinsic
 561     : Intrinsic<[llvm_anyvector_ty],
 562                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 563                  LLVMMatchType<0>],
 564                 [IntrNoMem]>;
 565   class AdvSIMD_Tbx3_Intrinsic
 566     : Intrinsic<[llvm_anyvector_ty],
 567                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 568                  llvm_v16i8_ty, LLVMMatchType<0>],
 569                 [IntrNoMem]>;
 570   class AdvSIMD_Tbx4_Intrinsic
 571     : Intrinsic<[llvm_anyvector_ty],
 572                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 573                  llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
 574                 [IntrNoMem]>;
 575 }
 576 def int_aarch64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
 577 def int_aarch64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
 578 def int_aarch64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
 579 def int_aarch64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
 580
 581 def int_aarch64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
 582 def int_aarch64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
 583 def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
 584 def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
 585
 586 let TargetPrefix = "aarch64" in {
 587   class FPCR_Get_Intrinsic
 588     : Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
 589 }
 590
 591 // FPCR
 592 def int_aarch64_get_fpcr : FPCR_Get_Intrinsic;
 593
 594 let TargetPrefix = "aarch64" in {
 595   class Crypto_AES_DataKey_Intrinsic
 596     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
 597
 598   class Crypto_AES_Data_Intrinsic
 599     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
 600
 601   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 602   // (v4i32).
 603   class Crypto_SHA_5Hash4Schedule_Intrinsic
 604     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 605                 [IntrNoMem]>;
 606
 607   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 608   // (v4i32).
 609   class Crypto_SHA_1Hash_Intrinsic
 610     : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 611
 612   // SHA intrinsic taking 8 words of the schedule
 613   class Crypto_SHA_8Schedule_Intrinsic
 614     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
 615
 616   // SHA intrinsic taking 12 words of the schedule
 617   class Crypto_SHA_12Schedule_Intrinsic
 618     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 619                 [IntrNoMem]>;
 620
 621   // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
 622   class Crypto_SHA_8Hash4Schedule_Intrinsic
 623     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 624                 [IntrNoMem]>;
 625 }
 626
 627 // AES
 628 def int_aarch64_crypto_aese   : Crypto_AES_DataKey_Intrinsic;
 629 def int_aarch64_crypto_aesd   : Crypto_AES_DataKey_Intrinsic;
 630 def int_aarch64_crypto_aesmc  : Crypto_AES_Data_Intrinsic;
 631 def int_aarch64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
 632
 633 // SHA1
 634 def int_aarch64_crypto_sha1c  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 635 def int_aarch64_crypto_sha1p  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 636 def int_aarch64_crypto_sha1m  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 637 def int_aarch64_crypto_sha1h  : Crypto_SHA_1Hash_Intrinsic;
 638
 639 def int_aarch64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
 640 def int_aarch64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
 641
 642 // SHA256
 643 def int_aarch64_crypto_sha256h   : Crypto_SHA_8Hash4Schedule_Intrinsic;
 644 def int_aarch64_crypto_sha256h2  : Crypto_SHA_8Hash4Schedule_Intrinsic;
 645 def int_aarch64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
 646 def int_aarch64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
 647
 648 //===----------------------------------------------------------------------===//
 649 // CRC32
 650
 651 let TargetPrefix = "aarch64" in {
 652
 653 def int_aarch64_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 654     [IntrNoMem]>;
 655 def int_aarch64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 656     [IntrNoMem]>;
 657 def int_aarch64_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 658     [IntrNoMem]>;
 659 def int_aarch64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 660     [IntrNoMem]>;
 661 def int_aarch64_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 662     [IntrNoMem]>;
 663 def int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 664     [IntrNoMem]>;
 665 def int_aarch64_crc32x  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 666     [IntrNoMem]>;
 667 def int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 668     [IntrNoMem]>;
 669 }