contrib/llvm/include/llvm/IR/IntrinsicsAMDGPU.td

   1 //===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the R600-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 class AMDGPUReadPreloadRegisterIntrinsic
  15   : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
  16
  17 class AMDGPUReadPreloadRegisterIntrinsicNamed<string name>
  18   : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>, GCCBuiltin<name>;
  19
  20 let TargetPrefix = "r600" in {
  21
  22 multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz {
  23   def _x : AMDGPUReadPreloadRegisterIntrinsic;
  24   def _y : AMDGPUReadPreloadRegisterIntrinsic;
  25   def _z : AMDGPUReadPreloadRegisterIntrinsic;
  26 }
  27
  28 multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz_named<string prefix> {
  29   def _x : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_x")>;
  30   def _y : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_y")>;
  31   def _z : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_z")>;
  32 }
  33
  34 defm int_r600_read_global_size : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
  35                                  <"__builtin_r600_read_global_size">;
  36 defm int_r600_read_ngroups : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
  37                              <"__builtin_r600_read_ngroups">;
  38 defm int_r600_read_tgid : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
  39                           <"__builtin_r600_read_tgid">;
  40
  41 defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz;
  42 defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz;
  43
  44 def int_r600_group_barrier : GCCBuiltin<"__builtin_r600_group_barrier">,
  45   Intrinsic<[], [], [IntrConvergent]>;
  46
  47 // AS 7 is PARAM_I_ADDRESS, used for kernel arguments
  48 def int_r600_implicitarg_ptr :
  49   GCCBuiltin<"__builtin_r600_implicitarg_ptr">,
  50   Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 7>], [],
  51   [IntrNoMem, IntrSpeculatable]>;
  52
  53 def int_r600_rat_store_typed :
  54   // 1st parameter: Data
  55   // 2nd parameter: Index
  56   // 3rd parameter: Constant RAT ID
  57   Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], []>,
  58   GCCBuiltin<"__builtin_r600_rat_store_typed">;
  59
  60 def int_r600_recipsqrt_ieee :  Intrinsic<
  61   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
  62 >;
  63
  64 def int_r600_recipsqrt_clamped : Intrinsic<
  65   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
  66 >;
  67
  68 def int_r600_cube : Intrinsic<
  69   [llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable]
  70 >;
  71
  72 } // End TargetPrefix = "r600"
  73
  74 let TargetPrefix = "amdgcn" in {
  75
  76 //===----------------------------------------------------------------------===//
  77 // ABI Special Intrinsics
  78 //===----------------------------------------------------------------------===//
  79
  80 defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz;
  81 defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
  82                                <"__builtin_amdgcn_workgroup_id">;
  83
  84 def int_amdgcn_dispatch_ptr :
  85   GCCBuiltin<"__builtin_amdgcn_dispatch_ptr">,
  86   Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [],
  87   [IntrNoMem, IntrSpeculatable]>;
  88
  89 def int_amdgcn_queue_ptr :
  90   GCCBuiltin<"__builtin_amdgcn_queue_ptr">,
  91   Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [],
  92   [IntrNoMem, IntrSpeculatable]>;
  93
  94 def int_amdgcn_kernarg_segment_ptr :
  95   GCCBuiltin<"__builtin_amdgcn_kernarg_segment_ptr">,
  96   Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [],
  97   [IntrNoMem, IntrSpeculatable]>;
  98
  99 def int_amdgcn_implicitarg_ptr :
 100   GCCBuiltin<"__builtin_amdgcn_implicitarg_ptr">,
 101   Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [],
 102   [IntrNoMem, IntrSpeculatable]>;
 103
 104 def int_amdgcn_groupstaticsize :
 105   GCCBuiltin<"__builtin_amdgcn_groupstaticsize">,
 106   Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
 107
 108 def int_amdgcn_dispatch_id :
 109   GCCBuiltin<"__builtin_amdgcn_dispatch_id">,
 110   Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable]>;
 111
 112 def int_amdgcn_implicit_buffer_ptr :
 113   GCCBuiltin<"__builtin_amdgcn_implicit_buffer_ptr">,
 114   Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [],
 115   [IntrNoMem, IntrSpeculatable]>;
 116
 117 // Set EXEC to the 64-bit value given.
 118 // This is always moved to the beginning of the basic block.
 119 def int_amdgcn_init_exec : Intrinsic<[],
 120   [llvm_i64_ty],      // 64-bit literal constant
 121   [IntrConvergent]>;
 122
 123 // Set EXEC according to a thread count packed in an SGPR input:
 124 //    thread_count = (input >> bitoffset) & 0x7f;
 125 // This is always moved to the beginning of the basic block.
 126 def int_amdgcn_init_exec_from_input : Intrinsic<[],
 127   [llvm_i32_ty,       // 32-bit SGPR input
 128    llvm_i32_ty],      // bit offset of the thread count
 129   [IntrConvergent]>;
 130
 131
 132 //===----------------------------------------------------------------------===//
 133 // Instruction Intrinsics
 134 //===----------------------------------------------------------------------===//
 135
 136 // The first parameter is s_sendmsg immediate (i16),
 137 // the second one is copied to m0
 138 def int_amdgcn_s_sendmsg : GCCBuiltin<"__builtin_amdgcn_s_sendmsg">,
 139   Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
 140 def int_amdgcn_s_sendmsghalt : GCCBuiltin<"__builtin_amdgcn_s_sendmsghalt">,
 141   Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
 142
 143 def int_amdgcn_s_barrier : GCCBuiltin<"__builtin_amdgcn_s_barrier">,
 144   Intrinsic<[], [], [IntrConvergent]>;
 145
 146 def int_amdgcn_wave_barrier : GCCBuiltin<"__builtin_amdgcn_wave_barrier">,
 147   Intrinsic<[], [], [IntrConvergent]>;
 148
 149 def int_amdgcn_s_waitcnt : GCCBuiltin<"__builtin_amdgcn_s_waitcnt">,
 150   Intrinsic<[], [llvm_i32_ty], []>;
 151
 152 def int_amdgcn_div_scale : Intrinsic<
 153   // 1st parameter: Numerator
 154   // 2nd parameter: Denominator
 155   // 3rd parameter: Constant to select select between first and
 156   //                second. (0 = first, 1 = second).
 157   [llvm_anyfloat_ty, llvm_i1_ty],
 158   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
 159   [IntrNoMem, IntrSpeculatable]
 160 >;
 161
 162 def int_amdgcn_div_fmas : Intrinsic<[llvm_anyfloat_ty],
 163   [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
 164   [IntrNoMem, IntrSpeculatable]
 165 >;
 166
 167 def int_amdgcn_div_fixup : Intrinsic<[llvm_anyfloat_ty],
 168   [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 169   [IntrNoMem, IntrSpeculatable]
 170 >;
 171
 172 def int_amdgcn_trig_preop : Intrinsic<
 173   [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty],
 174   [IntrNoMem, IntrSpeculatable]
 175 >;
 176
 177 def int_amdgcn_sin : Intrinsic<
 178   [llvm_anyfloat_ty], [LLVMMatchType<0>],
 179   [IntrNoMem, IntrSpeculatable]
 180 >;
 181
 182 def int_amdgcn_cos : Intrinsic<
 183   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 184 >;
 185
 186 def int_amdgcn_log_clamp : Intrinsic<
 187   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 188 >;
 189
 190 def int_amdgcn_fmul_legacy : GCCBuiltin<"__builtin_amdgcn_fmul_legacy">,
 191   Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
 192   [IntrNoMem, IntrSpeculatable]
 193 >;
 194
 195 def int_amdgcn_rcp : Intrinsic<
 196   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 197 >;
 198
 199 def int_amdgcn_rcp_legacy : GCCBuiltin<"__builtin_amdgcn_rcp_legacy">,
 200   Intrinsic<[llvm_float_ty], [llvm_float_ty],
 201   [IntrNoMem, IntrSpeculatable]
 202 >;
 203
 204 def int_amdgcn_rsq :  Intrinsic<
 205   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 206 >;
 207
 208 def int_amdgcn_rsq_legacy :  GCCBuiltin<"__builtin_amdgcn_rsq_legacy">,
 209   Intrinsic<
 210   [llvm_float_ty], [llvm_float_ty], [IntrNoMem, IntrSpeculatable]
 211 >;
 212
 213 def int_amdgcn_rsq_clamp : Intrinsic<
 214   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]>;
 215
 216 def int_amdgcn_ldexp : Intrinsic<
 217   [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty],
 218   [IntrNoMem, IntrSpeculatable]
 219 >;
 220
 221 def int_amdgcn_frexp_mant : Intrinsic<
 222   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 223 >;
 224
 225 def int_amdgcn_frexp_exp : Intrinsic<
 226   [llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem, IntrSpeculatable]
 227 >;
 228
 229 // v_fract is buggy on SI/CI. It mishandles infinities, may return 1.0
 230 // and always uses rtz, so is not suitable for implementing the OpenCL
 231 // fract function. It should be ok on VI.
 232 def int_amdgcn_fract : Intrinsic<
 233   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 234 >;
 235
 236 def int_amdgcn_cvt_pkrtz : Intrinsic<
 237   [llvm_v2f16_ty], [llvm_float_ty, llvm_float_ty],
 238   [IntrNoMem, IntrSpeculatable]
 239 >;
 240
 241 def int_amdgcn_cvt_pknorm_i16 : Intrinsic<
 242   [llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty],
 243   [IntrNoMem, IntrSpeculatable]
 244 >;
 245
 246 def int_amdgcn_cvt_pknorm_u16 : Intrinsic<
 247   [llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty],
 248   [IntrNoMem, IntrSpeculatable]
 249 >;
 250
 251 def int_amdgcn_cvt_pk_i16 : Intrinsic<
 252   [llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty],
 253   [IntrNoMem, IntrSpeculatable]
 254 >;
 255
 256 def int_amdgcn_cvt_pk_u16 : Intrinsic<
 257   [llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty],
 258   [IntrNoMem, IntrSpeculatable]
 259 >;
 260
 261 def int_amdgcn_class : Intrinsic<
 262   [llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty],
 263   [IntrNoMem, IntrSpeculatable]
 264 >;
 265
 266 def int_amdgcn_fmed3 : GCCBuiltin<"__builtin_amdgcn_fmed3">,
 267   Intrinsic<[llvm_anyfloat_ty],
 268     [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 269     [IntrNoMem, IntrSpeculatable]
 270 >;
 271
 272 def int_amdgcn_cubeid : GCCBuiltin<"__builtin_amdgcn_cubeid">,
 273   Intrinsic<[llvm_float_ty],
 274     [llvm_float_ty, llvm_float_ty, llvm_float_ty],
 275     [IntrNoMem, IntrSpeculatable]
 276 >;
 277
 278 def int_amdgcn_cubema : GCCBuiltin<"__builtin_amdgcn_cubema">,
 279   Intrinsic<[llvm_float_ty],
 280   [llvm_float_ty, llvm_float_ty, llvm_float_ty],
 281   [IntrNoMem, IntrSpeculatable]
 282 >;
 283
 284 def int_amdgcn_cubesc : GCCBuiltin<"__builtin_amdgcn_cubesc">,
 285   Intrinsic<[llvm_float_ty],
 286     [llvm_float_ty, llvm_float_ty, llvm_float_ty],
 287     [IntrNoMem, IntrSpeculatable]
 288 >;
 289
 290 def int_amdgcn_cubetc : GCCBuiltin<"__builtin_amdgcn_cubetc">,
 291   Intrinsic<[llvm_float_ty],
 292     [llvm_float_ty, llvm_float_ty, llvm_float_ty],
 293     [IntrNoMem, IntrSpeculatable]
 294 >;
 295
 296 // v_ffbh_i32, as opposed to v_ffbh_u32. For v_ffbh_u32, llvm.ctlz
 297 // should be used.
 298 def int_amdgcn_sffbh :
 299   Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>],
 300   [IntrNoMem, IntrSpeculatable]
 301 >;
 302
 303
 304 // Fields should mirror atomicrmw
 305 class AMDGPUAtomicIncIntrin : Intrinsic<[llvm_anyint_ty],
 306   [llvm_anyptr_ty,
 307   LLVMMatchType<0>,
 308   llvm_i32_ty, // ordering
 309   llvm_i32_ty, // scope
 310   llvm_i1_ty], // isVolatile
 311   [IntrArgMemOnly, NoCapture<0>], "",
 312   [SDNPMemOperand]
 313 >;
 314
 315 def int_amdgcn_atomic_inc : AMDGPUAtomicIncIntrin;
 316 def int_amdgcn_atomic_dec : AMDGPUAtomicIncIntrin;
 317
 318 class AMDGPUImageLoad<bit NoMem = 0> : Intrinsic <
 319   [llvm_anyfloat_ty], // vdata(VGPR)
 320   [llvm_anyint_ty,    // vaddr(VGPR)
 321    llvm_anyint_ty,    // rsrc(SGPR)
 322    llvm_i32_ty,       // dmask(imm)
 323    llvm_i1_ty,        // glc(imm)
 324    llvm_i1_ty,        // slc(imm)
 325    llvm_i1_ty,        // lwe(imm)
 326    llvm_i1_ty],       // da(imm)
 327   !if(NoMem, [IntrNoMem], [IntrReadMem]), "",
 328   !if(NoMem, [], [SDNPMemOperand])>;
 329
 330 def int_amdgcn_image_load : AMDGPUImageLoad;
 331 def int_amdgcn_image_load_mip : AMDGPUImageLoad;
 332 def int_amdgcn_image_getresinfo : AMDGPUImageLoad<1>;
 333
 334 class AMDGPUImageStore : Intrinsic <
 335   [],
 336   [llvm_anyfloat_ty,  // vdata(VGPR)
 337    llvm_anyint_ty,    // vaddr(VGPR)
 338    llvm_anyint_ty,    // rsrc(SGPR)
 339    llvm_i32_ty,       // dmask(imm)
 340    llvm_i1_ty,        // glc(imm)
 341    llvm_i1_ty,        // slc(imm)
 342    llvm_i1_ty,        // lwe(imm)
 343    llvm_i1_ty],       // da(imm)
 344   [IntrWriteMem], "", [SDNPMemOperand]>;
 345
 346 def int_amdgcn_image_store : AMDGPUImageStore;
 347 def int_amdgcn_image_store_mip : AMDGPUImageStore;
 348
 349 class AMDGPUImageSample<bit NoMem = 0> : Intrinsic <
 350     [llvm_anyfloat_ty], // vdata(VGPR)
 351     [llvm_anyfloat_ty,  // vaddr(VGPR)
 352      llvm_anyint_ty,    // rsrc(SGPR)
 353      llvm_v4i32_ty,     // sampler(SGPR)
 354      llvm_i32_ty,       // dmask(imm)
 355      llvm_i1_ty,        // unorm(imm)
 356      llvm_i1_ty,        // glc(imm)
 357      llvm_i1_ty,        // slc(imm)
 358      llvm_i1_ty,        // lwe(imm)
 359      llvm_i1_ty],       // da(imm)
 360      !if(NoMem, [IntrNoMem], [IntrReadMem]), "",
 361      !if(NoMem, [], [SDNPMemOperand])>;
 362
 363 // Basic sample
 364 def int_amdgcn_image_sample : AMDGPUImageSample;
 365 def int_amdgcn_image_sample_cl : AMDGPUImageSample;
 366 def int_amdgcn_image_sample_d : AMDGPUImageSample;
 367 def int_amdgcn_image_sample_d_cl : AMDGPUImageSample;
 368 def int_amdgcn_image_sample_l : AMDGPUImageSample;
 369 def int_amdgcn_image_sample_b : AMDGPUImageSample;
 370 def int_amdgcn_image_sample_b_cl : AMDGPUImageSample;
 371 def int_amdgcn_image_sample_lz : AMDGPUImageSample;
 372 def int_amdgcn_image_sample_cd : AMDGPUImageSample;
 373 def int_amdgcn_image_sample_cd_cl : AMDGPUImageSample;
 374
 375 // Sample with comparison
 376 def int_amdgcn_image_sample_c : AMDGPUImageSample;
 377 def int_amdgcn_image_sample_c_cl : AMDGPUImageSample;
 378 def int_amdgcn_image_sample_c_d : AMDGPUImageSample;
 379 def int_amdgcn_image_sample_c_d_cl : AMDGPUImageSample;
 380 def int_amdgcn_image_sample_c_l : AMDGPUImageSample;
 381 def int_amdgcn_image_sample_c_b : AMDGPUImageSample;
 382 def int_amdgcn_image_sample_c_b_cl : AMDGPUImageSample;
 383 def int_amdgcn_image_sample_c_lz : AMDGPUImageSample;
 384 def int_amdgcn_image_sample_c_cd : AMDGPUImageSample;
 385 def int_amdgcn_image_sample_c_cd_cl : AMDGPUImageSample;
 386
 387 // Sample with offsets
 388 def int_amdgcn_image_sample_o : AMDGPUImageSample;
 389 def int_amdgcn_image_sample_cl_o : AMDGPUImageSample;
 390 def int_amdgcn_image_sample_d_o : AMDGPUImageSample;
 391 def int_amdgcn_image_sample_d_cl_o : AMDGPUImageSample;
 392 def int_amdgcn_image_sample_l_o : AMDGPUImageSample;
 393 def int_amdgcn_image_sample_b_o : AMDGPUImageSample;
 394 def int_amdgcn_image_sample_b_cl_o : AMDGPUImageSample;
 395 def int_amdgcn_image_sample_lz_o : AMDGPUImageSample;
 396 def int_amdgcn_image_sample_cd_o : AMDGPUImageSample;
 397 def int_amdgcn_image_sample_cd_cl_o : AMDGPUImageSample;
 398
 399 // Sample with comparison and offsets
 400 def int_amdgcn_image_sample_c_o : AMDGPUImageSample;
 401 def int_amdgcn_image_sample_c_cl_o : AMDGPUImageSample;
 402 def int_amdgcn_image_sample_c_d_o : AMDGPUImageSample;
 403 def int_amdgcn_image_sample_c_d_cl_o : AMDGPUImageSample;
 404 def int_amdgcn_image_sample_c_l_o : AMDGPUImageSample;
 405 def int_amdgcn_image_sample_c_b_o : AMDGPUImageSample;
 406 def int_amdgcn_image_sample_c_b_cl_o : AMDGPUImageSample;
 407 def int_amdgcn_image_sample_c_lz_o : AMDGPUImageSample;
 408 def int_amdgcn_image_sample_c_cd_o : AMDGPUImageSample;
 409 def int_amdgcn_image_sample_c_cd_cl_o : AMDGPUImageSample;
 410
 411 // Basic gather4
 412 def int_amdgcn_image_gather4 : AMDGPUImageSample;
 413 def int_amdgcn_image_gather4_cl : AMDGPUImageSample;
 414 def int_amdgcn_image_gather4_l : AMDGPUImageSample;
 415 def int_amdgcn_image_gather4_b : AMDGPUImageSample;
 416 def int_amdgcn_image_gather4_b_cl : AMDGPUImageSample;
 417 def int_amdgcn_image_gather4_lz : AMDGPUImageSample;
 418
 419 // Gather4 with comparison
 420 def int_amdgcn_image_gather4_c : AMDGPUImageSample;
 421 def int_amdgcn_image_gather4_c_cl : AMDGPUImageSample;
 422 def int_amdgcn_image_gather4_c_l : AMDGPUImageSample;
 423 def int_amdgcn_image_gather4_c_b : AMDGPUImageSample;
 424 def int_amdgcn_image_gather4_c_b_cl : AMDGPUImageSample;
 425 def int_amdgcn_image_gather4_c_lz : AMDGPUImageSample;
 426
 427 // Gather4 with offsets
 428 def int_amdgcn_image_gather4_o : AMDGPUImageSample;
 429 def int_amdgcn_image_gather4_cl_o : AMDGPUImageSample;
 430 def int_amdgcn_image_gather4_l_o : AMDGPUImageSample;
 431 def int_amdgcn_image_gather4_b_o : AMDGPUImageSample;
 432 def int_amdgcn_image_gather4_b_cl_o : AMDGPUImageSample;
 433 def int_amdgcn_image_gather4_lz_o : AMDGPUImageSample;
 434
 435 // Gather4 with comparison and offsets
 436 def int_amdgcn_image_gather4_c_o : AMDGPUImageSample;
 437 def int_amdgcn_image_gather4_c_cl_o : AMDGPUImageSample;
 438 def int_amdgcn_image_gather4_c_l_o : AMDGPUImageSample;
 439 def int_amdgcn_image_gather4_c_b_o : AMDGPUImageSample;
 440 def int_amdgcn_image_gather4_c_b_cl_o : AMDGPUImageSample;
 441 def int_amdgcn_image_gather4_c_lz_o : AMDGPUImageSample;
 442
 443 def int_amdgcn_image_getlod : AMDGPUImageSample<1>;
 444
 445 class AMDGPUImageAtomic : Intrinsic <
 446   [llvm_i32_ty],
 447   [llvm_i32_ty,       // vdata(VGPR)
 448    llvm_anyint_ty,    // vaddr(VGPR)
 449    llvm_v8i32_ty,     // rsrc(SGPR)
 450    llvm_i1_ty,        // r128(imm)
 451    llvm_i1_ty,        // da(imm)
 452    llvm_i1_ty],       // slc(imm)
 453   [], "", [SDNPMemOperand]>;
 454
 455 def int_amdgcn_image_atomic_swap : AMDGPUImageAtomic;
 456 def int_amdgcn_image_atomic_add : AMDGPUImageAtomic;
 457 def int_amdgcn_image_atomic_sub : AMDGPUImageAtomic;
 458 def int_amdgcn_image_atomic_smin : AMDGPUImageAtomic;
 459 def int_amdgcn_image_atomic_umin : AMDGPUImageAtomic;
 460 def int_amdgcn_image_atomic_smax : AMDGPUImageAtomic;
 461 def int_amdgcn_image_atomic_umax : AMDGPUImageAtomic;
 462 def int_amdgcn_image_atomic_and : AMDGPUImageAtomic;
 463 def int_amdgcn_image_atomic_or : AMDGPUImageAtomic;
 464 def int_amdgcn_image_atomic_xor : AMDGPUImageAtomic;
 465 def int_amdgcn_image_atomic_inc : AMDGPUImageAtomic;
 466 def int_amdgcn_image_atomic_dec : AMDGPUImageAtomic;
 467 def int_amdgcn_image_atomic_cmpswap : Intrinsic <
 468   [llvm_i32_ty],
 469   [llvm_i32_ty,       // src(VGPR)
 470    llvm_i32_ty,       // cmp(VGPR)
 471    llvm_anyint_ty,    // vaddr(VGPR)
 472    llvm_v8i32_ty,     // rsrc(SGPR)
 473    llvm_i1_ty,        // r128(imm)
 474    llvm_i1_ty,        // da(imm)
 475    llvm_i1_ty],       // slc(imm)
 476   [], "", [SDNPMemOperand]>;
 477
 478 class AMDGPUBufferLoad : Intrinsic <
 479   [llvm_anyfloat_ty],
 480   [llvm_v4i32_ty,     // rsrc(SGPR)
 481    llvm_i32_ty,       // vindex(VGPR)
 482    llvm_i32_ty,       // offset(SGPR/VGPR/imm)
 483    llvm_i1_ty,        // glc(imm)
 484    llvm_i1_ty],       // slc(imm)
 485   [IntrReadMem], "", [SDNPMemOperand]>;
 486 def int_amdgcn_buffer_load_format : AMDGPUBufferLoad;
 487 def int_amdgcn_buffer_load : AMDGPUBufferLoad;
 488
 489 class AMDGPUBufferStore : Intrinsic <
 490   [],
 491   [llvm_anyfloat_ty,  // vdata(VGPR) -- can currently only select f32, v2f32, v4f32
 492    llvm_v4i32_ty,     // rsrc(SGPR)
 493    llvm_i32_ty,       // vindex(VGPR)
 494    llvm_i32_ty,       // offset(SGPR/VGPR/imm)
 495    llvm_i1_ty,        // glc(imm)
 496    llvm_i1_ty],       // slc(imm)
 497   [IntrWriteMem], "", [SDNPMemOperand]>;
 498 def int_amdgcn_buffer_store_format : AMDGPUBufferStore;
 499 def int_amdgcn_buffer_store : AMDGPUBufferStore;
 500
 501 def int_amdgcn_tbuffer_load : Intrinsic <
 502     [llvm_any_ty],    // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
 503     [llvm_v4i32_ty,   // rsrc(SGPR)
 504      llvm_i32_ty,     // vindex(VGPR)
 505      llvm_i32_ty,     // voffset(VGPR)
 506      llvm_i32_ty,     // soffset(SGPR)
 507      llvm_i32_ty,     // offset(imm)
 508      llvm_i32_ty,     // dfmt(imm)
 509      llvm_i32_ty,     // nfmt(imm)
 510      llvm_i1_ty,     // glc(imm)
 511      llvm_i1_ty],    // slc(imm)
 512     [IntrReadMem], "", [SDNPMemOperand]>;
 513
 514 def int_amdgcn_tbuffer_store : Intrinsic <
 515     [],
 516     [llvm_any_ty,    // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
 517      llvm_v4i32_ty,  // rsrc(SGPR)
 518      llvm_i32_ty,    // vindex(VGPR)
 519      llvm_i32_ty,    // voffset(VGPR)
 520      llvm_i32_ty,    // soffset(SGPR)
 521      llvm_i32_ty,    // offset(imm)
 522      llvm_i32_ty,    // dfmt(imm)
 523      llvm_i32_ty,    // nfmt(imm)
 524      llvm_i1_ty,     // glc(imm)
 525      llvm_i1_ty],    // slc(imm)
 526     [IntrWriteMem], "", [SDNPMemOperand]>;
 527
 528 class AMDGPUBufferAtomic : Intrinsic <
 529   [llvm_i32_ty],
 530   [llvm_i32_ty,       // vdata(VGPR)
 531    llvm_v4i32_ty,     // rsrc(SGPR)
 532    llvm_i32_ty,       // vindex(VGPR)
 533    llvm_i32_ty,       // offset(SGPR/VGPR/imm)
 534    llvm_i1_ty],       // slc(imm)
 535   [], "", [SDNPMemOperand]>;
 536 def int_amdgcn_buffer_atomic_swap : AMDGPUBufferAtomic;
 537 def int_amdgcn_buffer_atomic_add : AMDGPUBufferAtomic;
 538 def int_amdgcn_buffer_atomic_sub : AMDGPUBufferAtomic;
 539 def int_amdgcn_buffer_atomic_smin : AMDGPUBufferAtomic;
 540 def int_amdgcn_buffer_atomic_umin : AMDGPUBufferAtomic;
 541 def int_amdgcn_buffer_atomic_smax : AMDGPUBufferAtomic;
 542 def int_amdgcn_buffer_atomic_umax : AMDGPUBufferAtomic;
 543 def int_amdgcn_buffer_atomic_and : AMDGPUBufferAtomic;
 544 def int_amdgcn_buffer_atomic_or : AMDGPUBufferAtomic;
 545 def int_amdgcn_buffer_atomic_xor : AMDGPUBufferAtomic;
 546 def int_amdgcn_buffer_atomic_cmpswap : Intrinsic<
 547   [llvm_i32_ty],
 548   [llvm_i32_ty,       // src(VGPR)
 549    llvm_i32_ty,       // cmp(VGPR)
 550    llvm_v4i32_ty,     // rsrc(SGPR)
 551    llvm_i32_ty,       // vindex(VGPR)
 552    llvm_i32_ty,       // offset(SGPR/VGPR/imm)
 553    llvm_i1_ty],       // slc(imm)
 554   [], "", [SDNPMemOperand]>;
 555
 556 // Uses that do not set the done bit should set IntrWriteMem on the
 557 // call site.
 558 def int_amdgcn_exp : Intrinsic <[], [
 559   llvm_i32_ty,       // tgt,
 560   llvm_i32_ty,       // en
 561   llvm_any_ty,       // src0 (f32 or i32)
 562   LLVMMatchType<0>,  // src1
 563   LLVMMatchType<0>,  // src2
 564   LLVMMatchType<0>,  // src3
 565   llvm_i1_ty,        // done
 566   llvm_i1_ty         // vm
 567   ],
 568   []
 569 >;
 570
 571 // exp with compr bit set.
 572 def int_amdgcn_exp_compr : Intrinsic <[], [
 573   llvm_i32_ty,       // tgt,
 574   llvm_i32_ty,       // en
 575   llvm_anyvector_ty, // src0 (v2f16 or v2i16)
 576   LLVMMatchType<0>,  // src1
 577   llvm_i1_ty,        // done
 578   llvm_i1_ty],       // vm
 579   []
 580 >;
 581
 582 def int_amdgcn_buffer_wbinvl1_sc :
 583   GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_sc">,
 584   Intrinsic<[], [], []>;
 585
 586 def int_amdgcn_buffer_wbinvl1 :
 587   GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1">,
 588   Intrinsic<[], [], []>;
 589
 590 def int_amdgcn_s_dcache_inv :
 591   GCCBuiltin<"__builtin_amdgcn_s_dcache_inv">,
 592   Intrinsic<[], [], []>;
 593
 594 def int_amdgcn_s_memtime :
 595   GCCBuiltin<"__builtin_amdgcn_s_memtime">,
 596   Intrinsic<[llvm_i64_ty], [], [IntrReadMem]>;
 597
 598 def int_amdgcn_s_sleep :
 599   GCCBuiltin<"__builtin_amdgcn_s_sleep">,
 600   Intrinsic<[], [llvm_i32_ty], []> {
 601 }
 602
 603 def int_amdgcn_s_incperflevel :
 604   GCCBuiltin<"__builtin_amdgcn_s_incperflevel">,
 605   Intrinsic<[], [llvm_i32_ty], []> {
 606 }
 607
 608 def int_amdgcn_s_decperflevel :
 609   GCCBuiltin<"__builtin_amdgcn_s_decperflevel">,
 610   Intrinsic<[], [llvm_i32_ty], []> {
 611 }
 612
 613 def int_amdgcn_s_getreg :
 614   GCCBuiltin<"__builtin_amdgcn_s_getreg">,
 615   Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 616   [IntrReadMem, IntrSpeculatable]
 617 >;
 618
 619 // int_amdgcn_s_getpc is provided to allow a specific style of position
 620 // independent code to determine the high part of its address when it is
 621 // known (through convention) that the code and any data of interest does
 622 // not cross a 4Gb address boundary. Use for any other purpose may not
 623 // produce the desired results as optimizations may cause code movement,
 624 // especially as we explicitly use IntrNoMem to allow optimizations.
 625 def int_amdgcn_s_getpc :
 626   GCCBuiltin<"__builtin_amdgcn_s_getpc">,
 627   Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable]>;
 628
 629 // __builtin_amdgcn_interp_mov <param>, <attr_chan>, <attr>, <m0>
 630 // param values: 0 = P10, 1 = P20, 2 = P0
 631 def int_amdgcn_interp_mov :
 632   GCCBuiltin<"__builtin_amdgcn_interp_mov">,
 633   Intrinsic<[llvm_float_ty],
 634             [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 635             [IntrNoMem, IntrSpeculatable]>;
 636
 637 // __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0>
 638 // This intrinsic reads from lds, but the memory values are constant,
 639 // so it behaves like IntrNoMem.
 640 def int_amdgcn_interp_p1 :
 641   GCCBuiltin<"__builtin_amdgcn_interp_p1">,
 642   Intrinsic<[llvm_float_ty],
 643             [llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 644             [IntrNoMem, IntrSpeculatable]>;
 645
 646 // __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0>
 647 def int_amdgcn_interp_p2 :
 648   GCCBuiltin<"__builtin_amdgcn_interp_p2">,
 649   Intrinsic<[llvm_float_ty],
 650             [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 651             [IntrNoMem, IntrSpeculatable]>;
 652           // See int_amdgcn_v_interp_p1 for why this is IntrNoMem.
 653
 654 // Pixel shaders only: whether the current pixel is live (i.e. not a helper
 655 // invocation for derivative computation).
 656 def int_amdgcn_ps_live : Intrinsic <
 657   [llvm_i1_ty],
 658   [],
 659   [IntrNoMem]>;
 660
 661 def int_amdgcn_mbcnt_lo :
 662   GCCBuiltin<"__builtin_amdgcn_mbcnt_lo">,
 663   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 664
 665 def int_amdgcn_mbcnt_hi :
 666   GCCBuiltin<"__builtin_amdgcn_mbcnt_hi">,
 667   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 668
 669 // llvm.amdgcn.ds.swizzle src offset
 670 def int_amdgcn_ds_swizzle :
 671   GCCBuiltin<"__builtin_amdgcn_ds_swizzle">,
 672   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
 673
 674 def int_amdgcn_ubfe : Intrinsic<[llvm_anyint_ty],
 675   [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
 676   [IntrNoMem, IntrSpeculatable]
 677 >;
 678
 679 def int_amdgcn_sbfe : Intrinsic<[llvm_anyint_ty],
 680   [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
 681   [IntrNoMem, IntrSpeculatable]
 682 >;
 683
 684 def int_amdgcn_lerp :
 685   GCCBuiltin<"__builtin_amdgcn_lerp">,
 686   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 687   [IntrNoMem, IntrSpeculatable]
 688 >;
 689
 690 def int_amdgcn_sad_u8 :
 691   GCCBuiltin<"__builtin_amdgcn_sad_u8">,
 692   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 693   [IntrNoMem, IntrSpeculatable]
 694 >;
 695
 696 def int_amdgcn_msad_u8 :
 697   GCCBuiltin<"__builtin_amdgcn_msad_u8">,
 698   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 699   [IntrNoMem, IntrSpeculatable]
 700 >;
 701
 702 def int_amdgcn_sad_hi_u8 :
 703   GCCBuiltin<"__builtin_amdgcn_sad_hi_u8">,
 704   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 705   [IntrNoMem, IntrSpeculatable]
 706 >;
 707
 708 def int_amdgcn_sad_u16 :
 709   GCCBuiltin<"__builtin_amdgcn_sad_u16">,
 710   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 711   [IntrNoMem, IntrSpeculatable]
 712 >;
 713
 714 def int_amdgcn_qsad_pk_u16_u8 :
 715   GCCBuiltin<"__builtin_amdgcn_qsad_pk_u16_u8">,
 716   Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty],
 717   [IntrNoMem, IntrSpeculatable]
 718 >;
 719
 720 def int_amdgcn_mqsad_pk_u16_u8 :
 721   GCCBuiltin<"__builtin_amdgcn_mqsad_pk_u16_u8">,
 722   Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty],
 723   [IntrNoMem, IntrSpeculatable]
 724 >;
 725
 726 def int_amdgcn_mqsad_u32_u8 :
 727   GCCBuiltin<"__builtin_amdgcn_mqsad_u32_u8">,
 728   Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i32_ty, llvm_v4i32_ty],
 729   [IntrNoMem, IntrSpeculatable]
 730 >;
 731
 732 def int_amdgcn_cvt_pk_u8_f32 :
 733   GCCBuiltin<"__builtin_amdgcn_cvt_pk_u8_f32">,
 734   Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty],
 735   [IntrNoMem, IntrSpeculatable]
 736 >;
 737
 738 def int_amdgcn_icmp :
 739   Intrinsic<[llvm_i64_ty], [llvm_anyint_ty, LLVMMatchType<0>, llvm_i32_ty],
 740             [IntrNoMem, IntrConvergent]>;
 741
 742 def int_amdgcn_fcmp :
 743   Intrinsic<[llvm_i64_ty], [llvm_anyfloat_ty, LLVMMatchType<0>, llvm_i32_ty],
 744             [IntrNoMem, IntrConvergent]>;
 745
 746 def int_amdgcn_readfirstlane :
 747   GCCBuiltin<"__builtin_amdgcn_readfirstlane">,
 748   Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
 749
 750 // The lane argument must be uniform across the currently active threads of the
 751 // current wave. Otherwise, the result is undefined.
 752 def int_amdgcn_readlane :
 753   GCCBuiltin<"__builtin_amdgcn_readlane">,
 754   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
 755
 756 def int_amdgcn_alignbit : Intrinsic<[llvm_i32_ty],
 757   [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 758   [IntrNoMem, IntrSpeculatable]
 759 >;
 760
 761 def int_amdgcn_alignbyte : Intrinsic<[llvm_i32_ty],
 762   [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
 763   [IntrNoMem, IntrSpeculatable]
 764 >;
 765
 766
 767 // Copies the source value to the destination value, with the guarantee that
 768 // the source value is computed as if the entire program were executed in WQM.
 769 def int_amdgcn_wqm : Intrinsic<[llvm_any_ty],
 770   [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 771 >;
 772
 773 // Return true if at least one thread within the pixel quad passes true into
 774 // the function.
 775 def int_amdgcn_wqm_vote : Intrinsic<[llvm_i1_ty],
 776   [llvm_i1_ty], [IntrNoMem, IntrConvergent]
 777 >;
 778
 779 // If false, set EXEC=0 for the current thread until the end of program.
 780 def int_amdgcn_kill : Intrinsic<[], [llvm_i1_ty], []>;
 781
 782 // Copies the active channels of the source value to the destination value,
 783 // with the guarantee that the source value is computed as if the entire
 784 // program were executed in Whole Wavefront Mode, i.e. with all channels
 785 // enabled, with a few exceptions: - Phi nodes with require WWM return an
 786 // undefined value.
 787 def int_amdgcn_wwm : Intrinsic<[llvm_any_ty],
 788   [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 789 >;
 790
 791 // Given a value, copies it while setting all the inactive lanes to a given
 792 // value. Note that OpenGL helper lanes are considered active, so if the
 793 // program ever uses WQM, then the instruction and the first source will be
 794 // computed in WQM.
 795 def int_amdgcn_set_inactive :
 796   Intrinsic<[llvm_anyint_ty],
 797             [LLVMMatchType<0>, // value to be copied
 798              LLVMMatchType<0>], // value for the inactive lanes to take
 799             [IntrNoMem, IntrConvergent]>;
 800
 801 //===----------------------------------------------------------------------===//
 802 // CI+ Intrinsics
 803 //===----------------------------------------------------------------------===//
 804
 805 def int_amdgcn_s_dcache_inv_vol :
 806   GCCBuiltin<"__builtin_amdgcn_s_dcache_inv_vol">,
 807   Intrinsic<[], [], []>;
 808
 809 def int_amdgcn_buffer_wbinvl1_vol :
 810   GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_vol">,
 811   Intrinsic<[], [], []>;
 812
 813 //===----------------------------------------------------------------------===//
 814 // VI Intrinsics
 815 //===----------------------------------------------------------------------===//
 816
 817 // llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
 818 def int_amdgcn_mov_dpp :
 819   Intrinsic<[llvm_anyint_ty],
 820             [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 821              llvm_i1_ty], [IntrNoMem, IntrConvergent]>;
 822
 823 // llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
 824 // Should be equivalent to:
 825 // v_mov_b32 <dest> <old>
 826 // v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
 827 def int_amdgcn_update_dpp :
 828   Intrinsic<[llvm_anyint_ty],
 829             [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty,
 830              llvm_i32_ty, llvm_i1_ty], [IntrNoMem, IntrConvergent]>;
 831
 832 def int_amdgcn_s_dcache_wb :
 833   GCCBuiltin<"__builtin_amdgcn_s_dcache_wb">,
 834   Intrinsic<[], [], []>;
 835
 836 def int_amdgcn_s_dcache_wb_vol :
 837   GCCBuiltin<"__builtin_amdgcn_s_dcache_wb_vol">,
 838   Intrinsic<[], [], []>;
 839
 840 def int_amdgcn_s_memrealtime :
 841   GCCBuiltin<"__builtin_amdgcn_s_memrealtime">,
 842   Intrinsic<[llvm_i64_ty], [], [IntrReadMem]>;
 843
 844 // llvm.amdgcn.ds.permute <index> <src>
 845 def int_amdgcn_ds_permute :
 846   GCCBuiltin<"__builtin_amdgcn_ds_permute">,
 847   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
 848
 849 // llvm.amdgcn.ds.bpermute <index> <src>
 850 def int_amdgcn_ds_bpermute :
 851   GCCBuiltin<"__builtin_amdgcn_ds_bpermute">,
 852   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
 853
 854
 855 //===----------------------------------------------------------------------===//
 856 // Special Intrinsics for backend internal use only. No frontend
 857 // should emit calls to these.
 858 // ===----------------------------------------------------------------------===//
 859 def int_amdgcn_if : Intrinsic<[llvm_i1_ty, llvm_i64_ty],
 860   [llvm_i1_ty], [IntrConvergent]
 861 >;
 862
 863 def int_amdgcn_else : Intrinsic<[llvm_i1_ty, llvm_i64_ty],
 864   [llvm_i64_ty], [IntrConvergent]
 865 >;
 866
 867 def int_amdgcn_break : Intrinsic<[llvm_i64_ty],
 868   [llvm_i64_ty], [IntrNoMem, IntrConvergent]
 869 >;
 870
 871 def int_amdgcn_if_break : Intrinsic<[llvm_i64_ty],
 872   [llvm_i1_ty, llvm_i64_ty], [IntrNoMem, IntrConvergent]
 873 >;
 874
 875 def int_amdgcn_else_break : Intrinsic<[llvm_i64_ty],
 876   [llvm_i64_ty, llvm_i64_ty], [IntrNoMem, IntrConvergent]
 877 >;
 878
 879 def int_amdgcn_loop : Intrinsic<[llvm_i1_ty],
 880   [llvm_i64_ty], [IntrConvergent]
 881 >;
 882
 883 def int_amdgcn_end_cf : Intrinsic<[], [llvm_i64_ty], [IntrConvergent]>;
 884
 885 // Represent unreachable in a divergent region.
 886 def int_amdgcn_unreachable : Intrinsic<[], [], [IntrConvergent]>;
 887
 888 // Emit 2.5 ulp, no denormal division. Should only be inserted by
 889 // pass based on !fpmath metadata.
 890 def int_amdgcn_fdiv_fast : Intrinsic<
 891   [llvm_float_ty], [llvm_float_ty, llvm_float_ty],
 892   [IntrNoMem, IntrSpeculatable]
 893 >;
 894 }