1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
20 // A space-consuming intrinsic primarily for testing ARMConstantIslands. The
21 // first argument is the number of bytes this "instruction" takes up, the second
22 // and return value are essentially chains, used to force ordering during ISel.
23 def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
25 // 16-bit multiplications
26 def int_arm_smulbb : GCCBuiltin<"__builtin_arm_smulbb">,
27 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
28 def int_arm_smulbt : GCCBuiltin<"__builtin_arm_smulbt">,
29 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
30 def int_arm_smultb : GCCBuiltin<"__builtin_arm_smultb">,
31 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
32 def int_arm_smultt : GCCBuiltin<"__builtin_arm_smultt">,
33 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
34 def int_arm_smulwb : GCCBuiltin<"__builtin_arm_smulwb">,
35 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
36 def int_arm_smulwt : GCCBuiltin<"__builtin_arm_smulwt">,
37 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
39 //===----------------------------------------------------------------------===//
40 // Saturating Arithmetic
42 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
43 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
44 [Commutative, IntrNoMem]>;
45 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
46 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
47 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
48 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
49 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
50 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
52 // Accumulating multiplications
53 def int_arm_smlabb : GCCBuiltin<"__builtin_arm_smlabb">,
54 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
56 def int_arm_smlabt : GCCBuiltin<"__builtin_arm_smlabt">,
57 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
59 def int_arm_smlatb : GCCBuiltin<"__builtin_arm_smlatb">,
60 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
62 def int_arm_smlatt : GCCBuiltin<"__builtin_arm_smlatt">,
63 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
65 def int_arm_smlawb : GCCBuiltin<"__builtin_arm_smlawb">,
66 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
68 def int_arm_smlawt : GCCBuiltin<"__builtin_arm_smlawt">,
69 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
72 // Parallel 16-bit saturation
73 def int_arm_ssat16 : GCCBuiltin<"__builtin_arm_ssat16">,
74 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
75 def int_arm_usat16 : GCCBuiltin<"__builtin_arm_usat16">,
76 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
78 // Packing and unpacking
79 def int_arm_sxtab16 : GCCBuiltin<"__builtin_arm_sxtab16">,
80 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
81 def int_arm_sxtb16 : GCCBuiltin<"__builtin_arm_sxtb16">,
82 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
83 def int_arm_uxtab16 : GCCBuiltin<"__builtin_arm_uxtab16">,
84 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
85 def int_arm_uxtb16 : GCCBuiltin<"__builtin_arm_uxtb16">,
86 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
88 // Parallel selection, reads the GE flags.
89 def int_arm_sel : GCCBuiltin<"__builtin_arm_sel">,
90 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>;
92 // Parallel 8-bit addition and subtraction
93 def int_arm_qadd8 : GCCBuiltin<"__builtin_arm_qadd8">,
94 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
95 def int_arm_qsub8 : GCCBuiltin<"__builtin_arm_qsub8">,
96 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
97 // Writes to the GE bits.
98 def int_arm_sadd8 : GCCBuiltin<"__builtin_arm_sadd8">,
99 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
100 def int_arm_shadd8 : GCCBuiltin<"__builtin_arm_shadd8">,
101 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
102 def int_arm_shsub8 : GCCBuiltin<"__builtin_arm_shsub8">,
103 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
104 // Writes to the GE bits.
105 def int_arm_ssub8 : GCCBuiltin<"__builtin_arm_ssub8">,
106 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
107 // Writes to the GE bits.
108 def int_arm_uadd8 : GCCBuiltin<"__builtin_arm_uadd8">,
109 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
110 def int_arm_uhadd8 : GCCBuiltin<"__builtin_arm_uhadd8">,
111 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
112 def int_arm_uhsub8 : GCCBuiltin<"__builtin_arm_uhsub8">,
113 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
114 def int_arm_uqadd8 : GCCBuiltin<"__builtin_arm_uqadd8">,
115 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
116 def int_arm_uqsub8 : GCCBuiltin<"__builtin_arm_uqsub8">,
117 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
118 // Writes to the GE bits.
119 def int_arm_usub8 : GCCBuiltin<"__builtin_arm_usub8">,
120 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
122 // Sum of 8-bit absolute differences
123 def int_arm_usad8 : GCCBuiltin<"__builtin_arm_usad8">,
124 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
125 def int_arm_usada8 : GCCBuiltin<"__builtin_arm_usada8">,
126 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
129 // Parallel 16-bit addition and subtraction
130 def int_arm_qadd16 : GCCBuiltin<"__builtin_arm_qadd16">,
131 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
132 def int_arm_qasx : GCCBuiltin<"__builtin_arm_qasx">,
133 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
134 def int_arm_qsax : GCCBuiltin<"__builtin_arm_qsax">,
135 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
136 def int_arm_qsub16 : GCCBuiltin<"__builtin_arm_qsub16">,
137 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
138 // Writes to the GE bits.
139 def int_arm_sadd16 : GCCBuiltin<"__builtin_arm_sadd16">,
140 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
141 // Writes to the GE bits.
142 def int_arm_sasx : GCCBuiltin<"__builtin_arm_sasx">,
143 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
144 def int_arm_shadd16 : GCCBuiltin<"__builtin_arm_shadd16">,
145 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
146 def int_arm_shasx : GCCBuiltin<"__builtin_arm_shasx">,
147 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
148 def int_arm_shsax : GCCBuiltin<"__builtin_arm_shsax">,
149 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
150 def int_arm_shsub16 : GCCBuiltin<"__builtin_arm_shsub16">,
151 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
152 // Writes to the GE bits.
153 def int_arm_ssax : GCCBuiltin<"__builtin_arm_ssax">,
154 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
155 // Writes to the GE bits.
156 def int_arm_ssub16 : GCCBuiltin<"__builtin_arm_ssub16">,
157 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
158 // Writes to the GE bits.
159 def int_arm_uadd16 : GCCBuiltin<"__builtin_arm_uadd16">,
160 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
161 // Writes to the GE bits.
162 def int_arm_uasx : GCCBuiltin<"__builtin_arm_uasx">,
163 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
164 def int_arm_uhadd16 : GCCBuiltin<"__builtin_arm_uhadd16">,
165 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
166 def int_arm_uhasx : GCCBuiltin<"__builtin_arm_uhasx">,
167 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
168 def int_arm_uhsax : GCCBuiltin<"__builtin_arm_uhsax">,
169 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
170 def int_arm_uhsub16 : GCCBuiltin<"__builtin_arm_uhsub16">,
171 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
172 def int_arm_uqadd16 : GCCBuiltin<"__builtin_arm_uqadd16">,
173 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
174 def int_arm_uqasx : GCCBuiltin<"__builtin_arm_uqasx">,
175 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
176 def int_arm_uqsax : GCCBuiltin<"__builtin_arm_uqsax">,
177 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
178 def int_arm_uqsub16 : GCCBuiltin<"__builtin_arm_uqsub16">,
179 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
180 // Writes to the GE bits.
181 def int_arm_usax : GCCBuiltin<"__builtin_arm_usax">,
182 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
183 // Writes to the GE bits.
184 def int_arm_usub16 : GCCBuiltin<"__builtin_arm_usub16">,
185 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
187 // Parallel 16-bit multiplication
188 def int_arm_smlad : GCCBuiltin<"__builtin_arm_smlad">,
189 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
191 def int_arm_smladx : GCCBuiltin<"__builtin_arm_smladx">,
192 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
194 def int_arm_smlald : GCCBuiltin<"__builtin_arm_smlald">,
195 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
197 def int_arm_smlaldx : GCCBuiltin<"__builtin_arm_smlaldx">,
198 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
200 def int_arm_smlsd : GCCBuiltin<"__builtin_arm_smlsd">,
201 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
203 def int_arm_smlsdx : GCCBuiltin<"__builtin_arm_smlsdx">,
204 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
206 def int_arm_smlsld : GCCBuiltin<"__builtin_arm_smlsld">,
207 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
209 def int_arm_smlsldx : GCCBuiltin<"__builtin_arm_smlsldx">,
210 Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
212 def int_arm_smuad : GCCBuiltin<"__builtin_arm_smuad">,
213 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
214 def int_arm_smuadx : GCCBuiltin<"__builtin_arm_smuadx">,
215 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
216 def int_arm_smusd : GCCBuiltin<"__builtin_arm_smusd">,
217 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
218 def int_arm_smusdx : GCCBuiltin<"__builtin_arm_smusdx">,
219 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
222 //===----------------------------------------------------------------------===//
223 // Load, Store and Clear exclusive
225 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
226 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
228 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
229 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
231 def int_arm_clrex : Intrinsic<[]>;
233 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
235 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
237 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
238 [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
239 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
241 //===----------------------------------------------------------------------===//
242 // Data barrier instructions
243 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
244 Intrinsic<[], [llvm_i32_ty]>;
245 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
246 Intrinsic<[], [llvm_i32_ty]>;
247 def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
248 Intrinsic<[], [llvm_i32_ty]>;
250 //===----------------------------------------------------------------------===//
253 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
254 Intrinsic<[llvm_i32_ty], [], []>;
255 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
256 Intrinsic<[], [llvm_i32_ty], []>;
257 def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
259 def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
262 //===----------------------------------------------------------------------===//
265 def int_arm_ldc : GCCBuiltin<"__builtin_arm_ldc">,
266 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
267 def int_arm_ldcl : GCCBuiltin<"__builtin_arm_ldcl">,
268 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
269 def int_arm_ldc2 : GCCBuiltin<"__builtin_arm_ldc2">,
270 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
271 def int_arm_ldc2l : GCCBuiltin<"__builtin_arm_ldc2l">,
272 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
274 def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">,
275 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
276 def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">,
277 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
278 def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">,
279 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
280 def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">,
281 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
283 // Move to coprocessor
284 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
285 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
286 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
287 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
288 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
289 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
291 // Move from coprocessor
292 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
293 MSBuiltin<"_MoveFromCoprocessor">,
294 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
295 llvm_i32_ty, llvm_i32_ty], []>;
296 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
297 MSBuiltin<"_MoveFromCoprocessor2">,
298 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
299 llvm_i32_ty, llvm_i32_ty], []>;
301 // Coprocessor data processing
302 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
303 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
304 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
305 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
306 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
307 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
309 // Move from two registers to coprocessor
310 def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
311 llvm_i32_ty, llvm_i32_ty], []>;
312 def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
313 llvm_i32_ty, llvm_i32_ty], []>;
315 def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
316 llvm_i32_ty, llvm_i32_ty], []>;
317 def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
318 llvm_i32_ty, llvm_i32_ty], []>;
320 //===----------------------------------------------------------------------===//
323 def int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
325 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
327 def int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
329 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
331 def int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
333 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
336 //===----------------------------------------------------------------------===//
339 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
340 def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
342 //===----------------------------------------------------------------------===//
343 // UND (reserved undefined sequence)
345 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
347 //===----------------------------------------------------------------------===//
348 // Advanced SIMD (NEON)
350 // The following classes do not correspond directly to GCC builtins.
351 class Neon_1Arg_Intrinsic
352 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
353 class Neon_1Arg_Narrow_Intrinsic
354 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
355 class Neon_2Arg_Intrinsic
356 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
358 class Neon_2Arg_Narrow_Intrinsic
359 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
361 class Neon_2Arg_Long_Intrinsic
362 : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
364 class Neon_3Arg_Intrinsic
365 : Intrinsic<[llvm_anyvector_ty],
366 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
368 class Neon_3Arg_Long_Intrinsic
369 : Intrinsic<[llvm_anyvector_ty],
370 [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
373 class Neon_1FloatArg_Intrinsic
374 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
376 class Neon_CvtFxToFP_Intrinsic
377 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
378 class Neon_CvtFPToFx_Intrinsic
379 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
380 class Neon_CvtFPtoInt_1Arg_Intrinsic
381 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
383 class Neon_Compare_Intrinsic
384 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
387 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
388 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
389 // Overall, the classes range from 2 to 6 v8i8 arguments.
390 class Neon_Tbl2Arg_Intrinsic
391 : Intrinsic<[llvm_v8i8_ty],
392 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
393 class Neon_Tbl3Arg_Intrinsic
394 : Intrinsic<[llvm_v8i8_ty],
395 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
396 class Neon_Tbl4Arg_Intrinsic
397 : Intrinsic<[llvm_v8i8_ty],
398 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
400 class Neon_Tbl5Arg_Intrinsic
401 : Intrinsic<[llvm_v8i8_ty],
402 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
403 llvm_v8i8_ty], [IntrNoMem]>;
404 class Neon_Tbl6Arg_Intrinsic
405 : Intrinsic<[llvm_v8i8_ty],
406 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
407 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
411 let IntrProperties = [IntrNoMem, Commutative] in {
414 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
415 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
416 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
417 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
418 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
419 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
420 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
423 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
424 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
425 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
426 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
427 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
428 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
429 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
432 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
433 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
434 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
437 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
438 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
439 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
441 // Vector Reciprocal Step.
442 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
444 // Vector Reciprocal Square Root Step.
445 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
449 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
450 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
451 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
452 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
453 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
455 // Vector Absolute Compare.
456 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
457 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
459 // Vector Absolute Differences.
460 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
461 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
463 // Vector Pairwise Add.
464 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
466 // Vector Pairwise Add Long.
467 // Note: This is different than the other "long" NEON intrinsics because
468 // the result vector has half as many elements as the source vector.
469 // The source and destination vector types must be specified separately.
470 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
472 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
475 // Vector Pairwise Add and Accumulate Long.
476 // Note: This is similar to vpaddl but the destination vector also appears
477 // as the first argument.
478 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
479 [LLVMMatchType<0>, llvm_anyvector_ty],
481 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
482 [LLVMMatchType<0>, llvm_anyvector_ty],
485 // Vector Pairwise Maximum and Minimum.
486 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
487 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
488 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
489 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
493 // The various saturating and rounding vector shift operations need to be
494 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
495 // operation cannot be safely translated to LLVM's shift operators. VSHL can
496 // be used for both left and right shifts, or even combinations of the two,
497 // depending on the signs of the shift amounts. It also has well-defined
498 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
499 // by constants can be represented with LLVM's shift operators.
501 // The shift counts for these intrinsics are always vectors, even for constant
502 // shifts, where the constant is replicated. For consistency with VSHL (and
503 // other variable shift instructions), left shifts have positive shift counts
504 // and right shifts have negative shift counts. This convention is also used
505 // for constant right shift intrinsics, and to help preserve sanity, the
506 // intrinsic names use "shift" instead of either "shl" or "shr". Where
507 // applicable, signed and unsigned versions of the intrinsics are
508 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
509 // such as VQSHLU, take signed operands but produce unsigned results; these
510 // use a "su" suffix.
513 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
514 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
516 // Vector Rounding Shift.
517 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
518 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
519 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
521 // Vector Saturating Shift.
522 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
523 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
524 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
525 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
526 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
527 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
529 // Vector Saturating Rounding Shift.
530 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
531 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
532 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
533 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
534 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
536 // Vector Shift and Insert.
537 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
539 // Vector Absolute Value and Saturating Absolute Value.
540 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
541 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
543 // Vector Saturating Negate.
544 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
546 // Vector Count Leading Sign/Zero Bits.
547 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
549 // Vector Reciprocal Estimate.
550 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
552 // Vector Reciprocal Square Root Estimate.
553 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
555 // Vector Conversions Between Floating-point and Integer
556 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
557 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
558 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
559 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
560 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
561 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
562 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
563 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
565 // Vector Conversions Between Floating-point and Fixed-point.
566 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
567 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
568 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
569 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
571 // Vector Conversions Between Half-Precision and Single-Precision.
572 def int_arm_neon_vcvtfp2hf
573 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
574 def int_arm_neon_vcvthf2fp
575 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
577 // Narrowing Saturating Vector Moves.
578 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
579 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
580 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
582 // Vector Table Lookup.
583 // The first 1-4 arguments are the table.
584 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
585 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
586 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
587 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
589 // Vector Table Extension.
590 // Some elements of the destination vector may not be updated, so the original
591 // value of that vector is passed as the first argument. The next 1-4
592 // arguments after that are the table.
593 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
594 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
595 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
596 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
598 // Vector and Scalar Rounding.
599 def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
600 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
601 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
602 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
603 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
604 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
606 // De-interleaving vector loads from N-element structures.
607 // Source operands are the address and alignment.
608 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
609 [llvm_anyptr_ty, llvm_i32_ty],
610 [IntrReadMem, IntrArgMemOnly]>;
611 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
612 [llvm_anyptr_ty, llvm_i32_ty],
613 [IntrReadMem, IntrArgMemOnly]>;
614 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
616 [llvm_anyptr_ty, llvm_i32_ty],
617 [IntrReadMem, IntrArgMemOnly]>;
618 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
619 LLVMMatchType<0>, LLVMMatchType<0>],
620 [llvm_anyptr_ty, llvm_i32_ty],
621 [IntrReadMem, IntrArgMemOnly]>;
623 def int_arm_neon_vld1x2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
624 [LLVMAnyPointerType<LLVMMatchType<0>>],
625 [IntrReadMem, IntrArgMemOnly]>;
626 def int_arm_neon_vld1x3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
628 [LLVMAnyPointerType<LLVMMatchType<0>>],
629 [IntrReadMem, IntrArgMemOnly]>;
630 def int_arm_neon_vld1x4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
631 LLVMMatchType<0>, LLVMMatchType<0>],
632 [LLVMAnyPointerType<LLVMMatchType<0>>],
633 [IntrReadMem, IntrArgMemOnly]>;
635 // Vector load N-element structure to one lane.
636 // Source operands are: the address, the N input vectors (since only one
637 // lane is assigned), the lane number, and the alignment.
638 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
639 [llvm_anyptr_ty, LLVMMatchType<0>,
640 LLVMMatchType<0>, llvm_i32_ty,
641 llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
642 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
644 [llvm_anyptr_ty, LLVMMatchType<0>,
645 LLVMMatchType<0>, LLVMMatchType<0>,
646 llvm_i32_ty, llvm_i32_ty],
647 [IntrReadMem, IntrArgMemOnly]>;
648 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
649 LLVMMatchType<0>, LLVMMatchType<0>],
650 [llvm_anyptr_ty, LLVMMatchType<0>,
651 LLVMMatchType<0>, LLVMMatchType<0>,
652 LLVMMatchType<0>, llvm_i32_ty,
653 llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
655 // Vector load N-element structure to all lanes.
656 // Source operands are the address and alignment.
657 def int_arm_neon_vld2dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
658 [llvm_anyptr_ty, llvm_i32_ty],
659 [IntrReadMem, IntrArgMemOnly]>;
660 def int_arm_neon_vld3dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
662 [llvm_anyptr_ty, llvm_i32_ty],
663 [IntrReadMem, IntrArgMemOnly]>;
664 def int_arm_neon_vld4dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
665 LLVMMatchType<0>, LLVMMatchType<0>],
666 [llvm_anyptr_ty, llvm_i32_ty],
667 [IntrReadMem, IntrArgMemOnly]>;
669 // Interleaving vector stores from N-element structures.
670 // Source operands are: the address, the N vectors, and the alignment.
671 def int_arm_neon_vst1 : Intrinsic<[],
672 [llvm_anyptr_ty, llvm_anyvector_ty,
673 llvm_i32_ty], [IntrArgMemOnly]>;
674 def int_arm_neon_vst2 : Intrinsic<[],
675 [llvm_anyptr_ty, llvm_anyvector_ty,
676 LLVMMatchType<1>, llvm_i32_ty],
678 def int_arm_neon_vst3 : Intrinsic<[],
679 [llvm_anyptr_ty, llvm_anyvector_ty,
680 LLVMMatchType<1>, LLVMMatchType<1>,
681 llvm_i32_ty], [IntrArgMemOnly]>;
682 def int_arm_neon_vst4 : Intrinsic<[],
683 [llvm_anyptr_ty, llvm_anyvector_ty,
684 LLVMMatchType<1>, LLVMMatchType<1>,
685 LLVMMatchType<1>, llvm_i32_ty],
688 def int_arm_neon_vst1x2 : Intrinsic<[],
689 [llvm_anyptr_ty, llvm_anyvector_ty,
691 [IntrArgMemOnly, NoCapture<0>]>;
692 def int_arm_neon_vst1x3 : Intrinsic<[],
693 [llvm_anyptr_ty, llvm_anyvector_ty,
694 LLVMMatchType<1>, LLVMMatchType<1>],
695 [IntrArgMemOnly, NoCapture<0>]>;
696 def int_arm_neon_vst1x4 : Intrinsic<[],
697 [llvm_anyptr_ty, llvm_anyvector_ty,
698 LLVMMatchType<1>, LLVMMatchType<1>,
700 [IntrArgMemOnly, NoCapture<0>]>;
702 // Vector store N-element structure from one lane.
703 // Source operands are: the address, the N vectors, the lane number, and
705 def int_arm_neon_vst2lane : Intrinsic<[],
706 [llvm_anyptr_ty, llvm_anyvector_ty,
707 LLVMMatchType<1>, llvm_i32_ty,
708 llvm_i32_ty], [IntrArgMemOnly]>;
709 def int_arm_neon_vst3lane : Intrinsic<[],
710 [llvm_anyptr_ty, llvm_anyvector_ty,
711 LLVMMatchType<1>, LLVMMatchType<1>,
712 llvm_i32_ty, llvm_i32_ty],
714 def int_arm_neon_vst4lane : Intrinsic<[],
715 [llvm_anyptr_ty, llvm_anyvector_ty,
716 LLVMMatchType<1>, LLVMMatchType<1>,
717 LLVMMatchType<1>, llvm_i32_ty,
718 llvm_i32_ty], [IntrArgMemOnly]>;
720 // Vector bitwise select.
721 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
722 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
726 // Crypto instructions
727 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
728 [llvm_v16i8_ty], [IntrNoMem]>;
729 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
730 [llvm_v16i8_ty, llvm_v16i8_ty],
733 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
735 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
736 [llvm_v4i32_ty, llvm_v4i32_ty],
738 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
739 [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
741 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
742 [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
745 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
746 def int_arm_neon_aese : AES_2Arg_Intrinsic;
747 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
748 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
749 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
750 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
751 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
752 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
753 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
754 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
755 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
756 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
757 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
758 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
760 // Armv8.2-A dot product instructions
761 class Neon_Dot_Intrinsic
762 : Intrinsic<[llvm_anyvector_ty],
763 [LLVMMatchType<0>, llvm_anyvector_ty,
766 def int_arm_neon_udot : Neon_Dot_Intrinsic;
767 def int_arm_neon_sdot : Neon_Dot_Intrinsic;
770 } // end TargetPrefix