contrib/llvm/include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 // A space-consuming intrinsic primarily for testing ARMConstantIslands. The
  21 // first argument is the number of bytes this "instruction" takes up, the second
  22 // and return value are essentially chains, used to force ordering during ISel.
  23 def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // Saturating Arithmetic
  27
  28 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  29     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  30     [IntrNoMem, Commutative]>;
  31 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  36     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  37
  38 //===----------------------------------------------------------------------===//
  39 // Load, Store and Clear exclusive
  40
  41 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  42 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  43
  44 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  45 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  46
  47 def int_arm_clrex : Intrinsic<[]>;
  48
  49 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  50     llvm_ptr_ty]>;
  51 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  52
  53 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
  54                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
  55 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  56
  57 //===----------------------------------------------------------------------===//
  58 // Data barrier instructions
  59 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
  60                   Intrinsic<[], [llvm_i32_ty]>;
  61 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
  62                   Intrinsic<[], [llvm_i32_ty]>;
  63 def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
  64                   Intrinsic<[], [llvm_i32_ty]>;
  65
  66 //===----------------------------------------------------------------------===//
  67 // VFP
  68
  69 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  70                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  71 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  72                        Intrinsic<[], [llvm_i32_ty], []>;
  73 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  74                                   [IntrNoMem]>;
  75 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  76                                   [IntrNoMem]>;
  77
  78 //===----------------------------------------------------------------------===//
  79 // Coprocessor
  80
  81 def int_arm_ldc : GCCBuiltin<"__builtin_arm_ldc">,
  82    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  83 def int_arm_ldcl : GCCBuiltin<"__builtin_arm_ldcl">,
  84    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  85 def int_arm_ldc2 : GCCBuiltin<"__builtin_arm_ldc2">,
  86    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  87 def int_arm_ldc2l : GCCBuiltin<"__builtin_arm_ldc2l">,
  88    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  89
  90 def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">,
  91    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  92 def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">,
  93    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  94 def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">,
  95    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  96 def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">,
  97    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  98
  99 // Move to coprocessor
 100 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
 101    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 102                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 103 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
 104    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 105                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 106
 107 // Move from coprocessor
 108 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
 109                   MSBuiltin<"_MoveFromCoprocessor">,
 110    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 111                              llvm_i32_ty, llvm_i32_ty], []>;
 112 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
 113                    MSBuiltin<"_MoveFromCoprocessor2">,
 114    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 115                              llvm_i32_ty, llvm_i32_ty], []>;
 116
 117 // Coprocessor data processing
 118 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
 119    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 120                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 121 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
 122    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 123                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 124
 125 // Move from two registers to coprocessor
 126 def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 127                                   llvm_i32_ty, llvm_i32_ty], []>;
 128 def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 129                                    llvm_i32_ty, llvm_i32_ty], []>;
 130
 131 def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
 132                               llvm_i32_ty, llvm_i32_ty], []>;
 133 def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
 134                                llvm_i32_ty, llvm_i32_ty], []>;
 135
 136 //===----------------------------------------------------------------------===//
 137 // CRC32
 138
 139 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 140     [IntrNoMem]>;
 141 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 142     [IntrNoMem]>;
 143 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 144     [IntrNoMem]>;
 145 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 146     [IntrNoMem]>;
 147 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 148     [IntrNoMem]>;
 149 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 150     [IntrNoMem]>;
 151
 152 //===----------------------------------------------------------------------===//
 153 // HINT
 154
 155 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 156 def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
 157
 158 //===----------------------------------------------------------------------===//
 159 // RBIT
 160
 161 def int_arm_rbit : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 162
 163 //===----------------------------------------------------------------------===//
 164 // UND (reserved undefined sequence)
 165
 166 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
 167
 168 //===----------------------------------------------------------------------===//
 169 // Advanced SIMD (NEON)
 170
 171 // The following classes do not correspond directly to GCC builtins.
 172 class Neon_1Arg_Intrinsic
 173   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 174 class Neon_1Arg_Narrow_Intrinsic
 175   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
 176 class Neon_2Arg_Intrinsic
 177   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 178               [IntrNoMem]>;
 179 class Neon_2Arg_Narrow_Intrinsic
 180   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
 181               [IntrNoMem]>;
 182 class Neon_2Arg_Long_Intrinsic
 183   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 184               [IntrNoMem]>;
 185 class Neon_3Arg_Intrinsic
 186   : Intrinsic<[llvm_anyvector_ty],
 187               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 188               [IntrNoMem]>;
 189 class Neon_3Arg_Long_Intrinsic
 190   : Intrinsic<[llvm_anyvector_ty],
 191               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 192               [IntrNoMem]>;
 193 class Neon_CvtFxToFP_Intrinsic
 194   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 195 class Neon_CvtFPToFx_Intrinsic
 196   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 197 class Neon_CvtFPtoInt_1Arg_Intrinsic
 198   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 199
 200 class Neon_Compare_Intrinsic
 201   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
 202               [IntrNoMem]>;
 203
 204 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 205 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 206 // Overall, the classes range from 2 to 6 v8i8 arguments.
 207 class Neon_Tbl2Arg_Intrinsic
 208   : Intrinsic<[llvm_v8i8_ty],
 209               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 210 class Neon_Tbl3Arg_Intrinsic
 211   : Intrinsic<[llvm_v8i8_ty],
 212               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 213 class Neon_Tbl4Arg_Intrinsic
 214   : Intrinsic<[llvm_v8i8_ty],
 215               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 216               [IntrNoMem]>;
 217 class Neon_Tbl5Arg_Intrinsic
 218   : Intrinsic<[llvm_v8i8_ty],
 219               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 220                llvm_v8i8_ty], [IntrNoMem]>;
 221 class Neon_Tbl6Arg_Intrinsic
 222   : Intrinsic<[llvm_v8i8_ty],
 223               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 224                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 225
 226 // Arithmetic ops
 227
 228 let IntrProperties = [IntrNoMem, Commutative] in {
 229
 230   // Vector Add.
 231   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 232   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 233   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 234   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 235   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 236   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 237   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 238
 239   // Vector Multiply.
 240   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 241   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 242   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 243   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 244   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 245   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 246   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 247
 248   // Vector Maximum.
 249   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 250   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 251   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 252
 253   // Vector Minimum.
 254   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 255   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 256   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 257
 258   // Vector Reciprocal Step.
 259   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 260
 261   // Vector Reciprocal Square Root Step.
 262   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 263 }
 264
 265 // Vector Subtract.
 266 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 267 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 268 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 269 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 270 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 271
 272 // Vector Absolute Compare.
 273 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
 274 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
 275
 276 // Vector Absolute Differences.
 277 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 278 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 279
 280 // Vector Pairwise Add.
 281 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 282
 283 // Vector Pairwise Add Long.
 284 // Note: This is different than the other "long" NEON intrinsics because
 285 // the result vector has half as many elements as the source vector.
 286 // The source and destination vector types must be specified separately.
 287 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 288                                      [IntrNoMem]>;
 289 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 290                                      [IntrNoMem]>;
 291
 292 // Vector Pairwise Add and Accumulate Long.
 293 // Note: This is similar to vpaddl but the destination vector also appears
 294 // as the first argument.
 295 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 296                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 297                                      [IntrNoMem]>;
 298 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 299                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 300                                      [IntrNoMem]>;
 301
 302 // Vector Pairwise Maximum and Minimum.
 303 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 304 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 305 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 306 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 307
 308 // Vector Shifts:
 309 //
 310 // The various saturating and rounding vector shift operations need to be
 311 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 312 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 313 // be used for both left and right shifts, or even combinations of the two,
 314 // depending on the signs of the shift amounts.  It also has well-defined
 315 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 316 // by constants can be represented with LLVM's shift operators.
 317 //
 318 // The shift counts for these intrinsics are always vectors, even for constant
 319 // shifts, where the constant is replicated.  For consistency with VSHL (and
 320 // other variable shift instructions), left shifts have positive shift counts
 321 // and right shifts have negative shift counts.  This convention is also used
 322 // for constant right shift intrinsics, and to help preserve sanity, the
 323 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 324 // applicable, signed and unsigned versions of the intrinsics are
 325 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 326 // such as VQSHLU, take signed operands but produce unsigned results; these
 327 // use a "su" suffix.
 328
 329 // Vector Shift.
 330 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 331 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 332
 333 // Vector Rounding Shift.
 334 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 335 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 336 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 337
 338 // Vector Saturating Shift.
 339 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 340 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 341 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 342 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 343 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 344 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 345
 346 // Vector Saturating Rounding Shift.
 347 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 348 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 349 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 350 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 351 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 352
 353 // Vector Shift and Insert.
 354 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 355
 356 // Vector Absolute Value and Saturating Absolute Value.
 357 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 358 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 359
 360 // Vector Saturating Negate.
 361 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 362
 363 // Vector Count Leading Sign/Zero Bits.
 364 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 365
 366 // Vector Reciprocal Estimate.
 367 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 368
 369 // Vector Reciprocal Square Root Estimate.
 370 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 371
 372 // Vector Conversions Between Floating-point and Integer
 373 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 374 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 375 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 376 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 377 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 378 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 379 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 380 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 381
 382 // Vector Conversions Between Floating-point and Fixed-point.
 383 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 384 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 385 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 386 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 387
 388 // Vector Conversions Between Half-Precision and Single-Precision.
 389 def int_arm_neon_vcvtfp2hf
 390     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 391 def int_arm_neon_vcvthf2fp
 392     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 393
 394 // Narrowing Saturating Vector Moves.
 395 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 396 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 397 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 398
 399 // Vector Table Lookup.
 400 // The first 1-4 arguments are the table.
 401 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 402 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 403 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 404 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 405
 406 // Vector Table Extension.
 407 // Some elements of the destination vector may not be updated, so the original
 408 // value of that vector is passed as the first argument.  The next 1-4
 409 // arguments after that are the table.
 410 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 411 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 412 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 413 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 414
 415 // Vector Rounding
 416 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 417 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 418 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 419 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 420 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 421 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 422
 423 // De-interleaving vector loads from N-element structures.
 424 // Source operands are the address and alignment.
 425 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 426                                   [llvm_anyptr_ty, llvm_i32_ty],
 427                                   [IntrReadMem, IntrArgMemOnly]>;
 428 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 429                                   [llvm_anyptr_ty, llvm_i32_ty],
 430                                   [IntrReadMem, IntrArgMemOnly]>;
 431 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 432                                    LLVMMatchType<0>],
 433                                   [llvm_anyptr_ty, llvm_i32_ty],
 434                                   [IntrReadMem, IntrArgMemOnly]>;
 435 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 436                                    LLVMMatchType<0>, LLVMMatchType<0>],
 437                                   [llvm_anyptr_ty, llvm_i32_ty],
 438                                   [IntrReadMem, IntrArgMemOnly]>;
 439
 440 // Vector load N-element structure to one lane.
 441 // Source operands are: the address, the N input vectors (since only one
 442 // lane is assigned), the lane number, and the alignment.
 443 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 444                                       [llvm_anyptr_ty, LLVMMatchType<0>,
 445                                        LLVMMatchType<0>, llvm_i32_ty,
 446                                        llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
 447 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 448                                        LLVMMatchType<0>],
 449                                       [llvm_anyptr_ty, LLVMMatchType<0>,
 450                                        LLVMMatchType<0>, LLVMMatchType<0>,
 451                                        llvm_i32_ty, llvm_i32_ty],
 452                                       [IntrReadMem, IntrArgMemOnly]>;
 453 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 454                                        LLVMMatchType<0>, LLVMMatchType<0>],
 455                                       [llvm_anyptr_ty, LLVMMatchType<0>,
 456                                        LLVMMatchType<0>, LLVMMatchType<0>,
 457                                        LLVMMatchType<0>, llvm_i32_ty,
 458                                        llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
 459
 460 // Interleaving vector stores from N-element structures.
 461 // Source operands are: the address, the N vectors, and the alignment.
 462 def int_arm_neon_vst1 : Intrinsic<[],
 463                                   [llvm_anyptr_ty, llvm_anyvector_ty,
 464                                    llvm_i32_ty], [IntrArgMemOnly]>;
 465 def int_arm_neon_vst2 : Intrinsic<[],
 466                                   [llvm_anyptr_ty, llvm_anyvector_ty,
 467                                    LLVMMatchType<1>, llvm_i32_ty],
 468                                   [IntrArgMemOnly]>;
 469 def int_arm_neon_vst3 : Intrinsic<[],
 470                                   [llvm_anyptr_ty, llvm_anyvector_ty,
 471                                    LLVMMatchType<1>, LLVMMatchType<1>,
 472                                    llvm_i32_ty], [IntrArgMemOnly]>;
 473 def int_arm_neon_vst4 : Intrinsic<[],
 474                                   [llvm_anyptr_ty, llvm_anyvector_ty,
 475                                    LLVMMatchType<1>, LLVMMatchType<1>,
 476                                    LLVMMatchType<1>, llvm_i32_ty],
 477                                   [IntrArgMemOnly]>;
 478
 479 // Vector store N-element structure from one lane.
 480 // Source operands are: the address, the N vectors, the lane number, and
 481 // the alignment.
 482 def int_arm_neon_vst2lane : Intrinsic<[],
 483                                       [llvm_anyptr_ty, llvm_anyvector_ty,
 484                                        LLVMMatchType<1>, llvm_i32_ty,
 485                                        llvm_i32_ty], [IntrArgMemOnly]>;
 486 def int_arm_neon_vst3lane : Intrinsic<[],
 487                                       [llvm_anyptr_ty, llvm_anyvector_ty,
 488                                        LLVMMatchType<1>, LLVMMatchType<1>,
 489                                        llvm_i32_ty, llvm_i32_ty],
 490                                       [IntrArgMemOnly]>;
 491 def int_arm_neon_vst4lane : Intrinsic<[],
 492                                       [llvm_anyptr_ty, llvm_anyvector_ty,
 493                                        LLVMMatchType<1>, LLVMMatchType<1>,
 494                                        LLVMMatchType<1>, llvm_i32_ty,
 495                                        llvm_i32_ty], [IntrArgMemOnly]>;
 496
 497 // Vector bitwise select.
 498 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 499                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 500                         [IntrNoMem]>;
 501
 502
 503 // Crypto instructions
 504 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 505                                      [llvm_v16i8_ty], [IntrNoMem]>;
 506 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 507                                      [llvm_v16i8_ty, llvm_v16i8_ty],
 508                                      [IntrNoMem]>;
 509
 510 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 511                                      [IntrNoMem]>;
 512 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 513                                      [llvm_v4i32_ty, llvm_v4i32_ty],
 514                                      [IntrNoMem]>;
 515 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 516                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 517                                    [IntrNoMem]>;
 518 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 519                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
 520                                    [IntrNoMem]>;
 521
 522 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
 523 def int_arm_neon_aese : AES_2Arg_Intrinsic;
 524 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
 525 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
 526 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
 527 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
 528 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
 529 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 530 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 531 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 532 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 533 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 534 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 535 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 536
 537 } // end TargetPrefix