contrib/llvm/include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 // A space-consuming intrinsic primarily for testing ARMConstantIslands. The
  21 // first argument is the number of bytes this "instruction" takes up, the second
  22 // and return value are essentially chains, used to force ordering during ISel.
  23 def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // Saturating Arithmetic
  27
  28 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  29     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  30     [IntrNoMem, Commutative]>;
  31 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  36     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  37
  38 //===----------------------------------------------------------------------===//
  39 // Load, Store and Clear exclusive
  40
  41 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  42 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  43
  44 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  45 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  46
  47 def int_arm_clrex : Intrinsic<[]>;
  48
  49 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  50     llvm_ptr_ty]>;
  51 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  52
  53 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
  54                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
  55 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  56
  57 //===----------------------------------------------------------------------===//
  58 // Data barrier instructions
  59 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
  60                   Intrinsic<[], [llvm_i32_ty]>;
  61 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
  62                   Intrinsic<[], [llvm_i32_ty]>;
  63 def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
  64                   Intrinsic<[], [llvm_i32_ty]>;
  65
  66 //===----------------------------------------------------------------------===//
  67 // VFP
  68
  69 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  70                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  71 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  72                        Intrinsic<[], [llvm_i32_ty], []>;
  73 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  74                                   [IntrNoMem]>;
  75 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  76                                   [IntrNoMem]>;
  77
  78 //===----------------------------------------------------------------------===//
  79 // Coprocessor
  80
  81 def int_arm_ldc : GCCBuiltin<"__builtin_arm_ldc">,
  82    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  83 def int_arm_ldcl : GCCBuiltin<"__builtin_arm_ldcl">,
  84    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  85 def int_arm_ldc2 : GCCBuiltin<"__builtin_arm_ldc2">,
  86    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  87 def int_arm_ldc2l : GCCBuiltin<"__builtin_arm_ldc2l">,
  88    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  89
  90 def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">,
  91    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  92 def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">,
  93    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  94 def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">,
  95    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  96 def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">,
  97    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
  98
  99 // Move to coprocessor
 100 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
 101    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 102                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 103 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
 104    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 105                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 106
 107 // Move from coprocessor
 108 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
 109                   MSBuiltin<"_MoveFromCoprocessor">,
 110    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 111                              llvm_i32_ty, llvm_i32_ty], []>;
 112 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
 113                    MSBuiltin<"_MoveFromCoprocessor2">,
 114    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 115                              llvm_i32_ty, llvm_i32_ty], []>;
 116
 117 // Coprocessor data processing
 118 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
 119    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 120                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 121 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
 122    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 123                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 124
 125 // Move from two registers to coprocessor
 126 def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 127                                   llvm_i32_ty, llvm_i32_ty], []>;
 128 def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 129                                    llvm_i32_ty, llvm_i32_ty], []>;
 130
 131 def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
 132                               llvm_i32_ty, llvm_i32_ty], []>;
 133 def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
 134                                llvm_i32_ty, llvm_i32_ty], []>;
 135
 136 //===----------------------------------------------------------------------===//
 137 // CRC32
 138
 139 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 140     [IntrNoMem]>;
 141 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 142     [IntrNoMem]>;
 143 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 144     [IntrNoMem]>;
 145 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 146     [IntrNoMem]>;
 147 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 148     [IntrNoMem]>;
 149 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 150     [IntrNoMem]>;
 151
 152 //===----------------------------------------------------------------------===//
 153 // HINT
 154
 155 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 156 def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
 157
 158 //===----------------------------------------------------------------------===//
 159 // UND (reserved undefined sequence)
 160
 161 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
 162
 163 //===----------------------------------------------------------------------===//
 164 // Advanced SIMD (NEON)
 165
 166 // The following classes do not correspond directly to GCC builtins.
 167 class Neon_1Arg_Intrinsic
 168   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 169 class Neon_1Arg_Narrow_Intrinsic
 170   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
 171 class Neon_2Arg_Intrinsic
 172   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 173               [IntrNoMem]>;
 174 class Neon_2Arg_Narrow_Intrinsic
 175   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
 176               [IntrNoMem]>;
 177 class Neon_2Arg_Long_Intrinsic
 178   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 179               [IntrNoMem]>;
 180 class Neon_3Arg_Intrinsic
 181   : Intrinsic<[llvm_anyvector_ty],
 182               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 183               [IntrNoMem]>;
 184 class Neon_3Arg_Long_Intrinsic
 185   : Intrinsic<[llvm_anyvector_ty],
 186               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 187               [IntrNoMem]>;
 188 class Neon_CvtFxToFP_Intrinsic
 189   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 190 class Neon_CvtFPToFx_Intrinsic
 191   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 192 class Neon_CvtFPtoInt_1Arg_Intrinsic
 193   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 194
 195 class Neon_Compare_Intrinsic
 196   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
 197               [IntrNoMem]>;
 198
 199 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 200 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 201 // Overall, the classes range from 2 to 6 v8i8 arguments.
 202 class Neon_Tbl2Arg_Intrinsic
 203   : Intrinsic<[llvm_v8i8_ty],
 204               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 205 class Neon_Tbl3Arg_Intrinsic
 206   : Intrinsic<[llvm_v8i8_ty],
 207               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 208 class Neon_Tbl4Arg_Intrinsic
 209   : Intrinsic<[llvm_v8i8_ty],
 210               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 211               [IntrNoMem]>;
 212 class Neon_Tbl5Arg_Intrinsic
 213   : Intrinsic<[llvm_v8i8_ty],
 214               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 215                llvm_v8i8_ty], [IntrNoMem]>;
 216 class Neon_Tbl6Arg_Intrinsic
 217   : Intrinsic<[llvm_v8i8_ty],
 218               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 219                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 220
 221 // Arithmetic ops
 222
 223 let IntrProperties = [IntrNoMem, Commutative] in {
 224
 225   // Vector Add.
 226   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 227   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 228   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 229   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 230   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 231   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 232   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 233
 234   // Vector Multiply.
 235   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 236   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 237   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 238   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 239   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 240   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 241   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 242
 243   // Vector Maximum.
 244   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 245   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 246   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 247
 248   // Vector Minimum.
 249   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 250   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 251   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 252
 253   // Vector Reciprocal Step.
 254   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 255
 256   // Vector Reciprocal Square Root Step.
 257   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 258 }
 259
 260 // Vector Subtract.
 261 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 262 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 263 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 264 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 265 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 266
 267 // Vector Absolute Compare.
 268 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
 269 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
 270
 271 // Vector Absolute Differences.
 272 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 273 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 274
 275 // Vector Pairwise Add.
 276 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 277
 278 // Vector Pairwise Add Long.
 279 // Note: This is different than the other "long" NEON intrinsics because
 280 // the result vector has half as many elements as the source vector.
 281 // The source and destination vector types must be specified separately.
 282 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 283                                      [IntrNoMem]>;
 284 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 285                                      [IntrNoMem]>;
 286
 287 // Vector Pairwise Add and Accumulate Long.
 288 // Note: This is similar to vpaddl but the destination vector also appears
 289 // as the first argument.
 290 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 291                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 292                                      [IntrNoMem]>;
 293 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 294                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 295                                      [IntrNoMem]>;
 296
 297 // Vector Pairwise Maximum and Minimum.
 298 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 299 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 300 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 301 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 302
 303 // Vector Shifts:
 304 //
 305 // The various saturating and rounding vector shift operations need to be
 306 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 307 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 308 // be used for both left and right shifts, or even combinations of the two,
 309 // depending on the signs of the shift amounts.  It also has well-defined
 310 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 311 // by constants can be represented with LLVM's shift operators.
 312 //
 313 // The shift counts for these intrinsics are always vectors, even for constant
 314 // shifts, where the constant is replicated.  For consistency with VSHL (and
 315 // other variable shift instructions), left shifts have positive shift counts
 316 // and right shifts have negative shift counts.  This convention is also used
 317 // for constant right shift intrinsics, and to help preserve sanity, the
 318 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 319 // applicable, signed and unsigned versions of the intrinsics are
 320 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 321 // such as VQSHLU, take signed operands but produce unsigned results; these
 322 // use a "su" suffix.
 323
 324 // Vector Shift.
 325 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 326 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 327
 328 // Vector Rounding Shift.
 329 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 330 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 331 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 332
 333 // Vector Saturating Shift.
 334 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 335 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 336 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 337 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 338 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 339 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 340
 341 // Vector Saturating Rounding Shift.
 342 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 343 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 344 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 345 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 346 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 347
 348 // Vector Shift and Insert.
 349 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 350
 351 // Vector Absolute Value and Saturating Absolute Value.
 352 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 353 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 354
 355 // Vector Saturating Negate.
 356 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 357
 358 // Vector Count Leading Sign/Zero Bits.
 359 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 360
 361 // Vector Reciprocal Estimate.
 362 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 363
 364 // Vector Reciprocal Square Root Estimate.
 365 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 366
 367 // Vector Conversions Between Floating-point and Integer
 368 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 369 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 370 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 371 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 372 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 373 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 374 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 375 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 376
 377 // Vector Conversions Between Floating-point and Fixed-point.
 378 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 379 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 380 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 381 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 382
 383 // Vector Conversions Between Half-Precision and Single-Precision.
 384 def int_arm_neon_vcvtfp2hf
 385     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 386 def int_arm_neon_vcvthf2fp
 387     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 388
 389 // Narrowing Saturating Vector Moves.
 390 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 391 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 392 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 393
 394 // Vector Table Lookup.
 395 // The first 1-4 arguments are the table.
 396 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 397 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 398 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 399 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 400
 401 // Vector Table Extension.
 402 // Some elements of the destination vector may not be updated, so the original
 403 // value of that vector is passed as the first argument.  The next 1-4
 404 // arguments after that are the table.
 405 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 406 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 407 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 408 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 409
 410 // Vector Rounding
 411 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 412 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 413 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 414 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 415 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 416 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 417
 418 // De-interleaving vector loads from N-element structures.
 419 // Source operands are the address and alignment.
 420 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 421                                   [llvm_anyptr_ty, llvm_i32_ty],
 422                                   [IntrReadMem, IntrArgMemOnly]>;
 423 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 424                                   [llvm_anyptr_ty, llvm_i32_ty],
 425                                   [IntrReadMem, IntrArgMemOnly]>;
 426 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 427                                    LLVMMatchType<0>],
 428                                   [llvm_anyptr_ty, llvm_i32_ty],
 429                                   [IntrReadMem, IntrArgMemOnly]>;
 430 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 431                                    LLVMMatchType<0>, LLVMMatchType<0>],
 432                                   [llvm_anyptr_ty, llvm_i32_ty],
 433                                   [IntrReadMem, IntrArgMemOnly]>;
 434
 435 // Vector load N-element structure to one lane.
 436 // Source operands are: the address, the N input vectors (since only one
 437 // lane is assigned), the lane number, and the alignment.
 438 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 439                                       [llvm_anyptr_ty, LLVMMatchType<0>,
 440                                        LLVMMatchType<0>, llvm_i32_ty,
 441                                        llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
 442 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 443                                        LLVMMatchType<0>],
 444                                       [llvm_anyptr_ty, LLVMMatchType<0>,
 445                                        LLVMMatchType<0>, LLVMMatchType<0>,
 446                                        llvm_i32_ty, llvm_i32_ty],
 447                                       [IntrReadMem, IntrArgMemOnly]>;
 448 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 449                                        LLVMMatchType<0>, LLVMMatchType<0>],
 450                                       [llvm_anyptr_ty, LLVMMatchType<0>,
 451                                        LLVMMatchType<0>, LLVMMatchType<0>,
 452                                        LLVMMatchType<0>, llvm_i32_ty,
 453                                        llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
 454
 455 // Interleaving vector stores from N-element structures.
 456 // Source operands are: the address, the N vectors, and the alignment.
 457 def int_arm_neon_vst1 : Intrinsic<[],
 458                                   [llvm_anyptr_ty, llvm_anyvector_ty,
 459                                    llvm_i32_ty], [IntrArgMemOnly]>;
 460 def int_arm_neon_vst2 : Intrinsic<[],
 461                                   [llvm_anyptr_ty, llvm_anyvector_ty,
 462                                    LLVMMatchType<1>, llvm_i32_ty],
 463                                   [IntrArgMemOnly]>;
 464 def int_arm_neon_vst3 : Intrinsic<[],
 465                                   [llvm_anyptr_ty, llvm_anyvector_ty,
 466                                    LLVMMatchType<1>, LLVMMatchType<1>,
 467                                    llvm_i32_ty], [IntrArgMemOnly]>;
 468 def int_arm_neon_vst4 : Intrinsic<[],
 469                                   [llvm_anyptr_ty, llvm_anyvector_ty,
 470                                    LLVMMatchType<1>, LLVMMatchType<1>,
 471                                    LLVMMatchType<1>, llvm_i32_ty],
 472                                   [IntrArgMemOnly]>;
 473
 474 // Vector store N-element structure from one lane.
 475 // Source operands are: the address, the N vectors, the lane number, and
 476 // the alignment.
 477 def int_arm_neon_vst2lane : Intrinsic<[],
 478                                       [llvm_anyptr_ty, llvm_anyvector_ty,
 479                                        LLVMMatchType<1>, llvm_i32_ty,
 480                                        llvm_i32_ty], [IntrArgMemOnly]>;
 481 def int_arm_neon_vst3lane : Intrinsic<[],
 482                                       [llvm_anyptr_ty, llvm_anyvector_ty,
 483                                        LLVMMatchType<1>, LLVMMatchType<1>,
 484                                        llvm_i32_ty, llvm_i32_ty],
 485                                       [IntrArgMemOnly]>;
 486 def int_arm_neon_vst4lane : Intrinsic<[],
 487                                       [llvm_anyptr_ty, llvm_anyvector_ty,
 488                                        LLVMMatchType<1>, LLVMMatchType<1>,
 489                                        LLVMMatchType<1>, llvm_i32_ty,
 490                                        llvm_i32_ty], [IntrArgMemOnly]>;
 491
 492 // Vector bitwise select.
 493 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 494                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 495                         [IntrNoMem]>;
 496
 497
 498 // Crypto instructions
 499 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 500                                      [llvm_v16i8_ty], [IntrNoMem]>;
 501 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 502                                      [llvm_v16i8_ty, llvm_v16i8_ty],
 503                                      [IntrNoMem]>;
 504
 505 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 506                                      [IntrNoMem]>;
 507 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 508                                      [llvm_v4i32_ty, llvm_v4i32_ty],
 509                                      [IntrNoMem]>;
 510 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 511                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 512                                    [IntrNoMem]>;
 513 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 514                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
 515                                    [IntrNoMem]>;
 516
 517 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
 518 def int_arm_neon_aese : AES_2Arg_Intrinsic;
 519 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
 520 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
 521 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
 522 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
 523 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
 524 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 525 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 526 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 527 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 528 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 529 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 530 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 531
 532 } // end TargetPrefix