contrib/llvm/include/llvm/IR/IntrinsicsHexagon.td

   1 //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===//
   2 //                     The LLVM Compiler Infrastructure
   3 //
   4 // This file is distributed under the University of Illinois Open Source
   5 // License. See LICENSE.TXT for details.
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines all of the Hexagon-specific intrinsics.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Definitions for all Hexagon intrinsics.
  15 //
  16 // All Hexagon intrinsics start with "llvm.hexagon.".
  17 let TargetPrefix = "hexagon" in {
  18   /// Hexagon_Intrinsic - Base class for all Hexagon intrinsics.
  19   class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
  20                               list<LLVMType> param_types,
  21                               list<IntrinsicProperty> properties>
  22     : GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
  23       Intrinsic<ret_types, param_types, properties>;
  24
  25   /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon
  26   /// intrinsics.
  27   class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types,
  28                                  list<LLVMType> param_types,
  29                                  list<IntrinsicProperty> properties>
  30     : Intrinsic<ret_types, param_types, properties>;
  31 }
  32
  33 //===----------------------------------------------------------------------===//
  34 //
  35 // DEF_FUNCTION_TYPE_1(QI_ftype_MEM,BT_BOOL,BT_PTR) ->
  36 // Hexagon_qi_mem_Intrinsic<string GCCIntSuffix>
  37 //
  38 class Hexagon_qi_mem_Intrinsic<string GCCIntSuffix>
  39   : Hexagon_Intrinsic<GCCIntSuffix,
  40                           [llvm_i1_ty], [llvm_ptr_ty],
  41                           [IntrNoMem]>;
  42 //
  43 // DEF_FUNCTION_TYPE_1(HI_ftype_SI,BT_I16,BT_INT) ->
  44 // Hexagon_hi_si_Intrinsic<string GCCIntSuffix>
  45 //
  46 class Hexagon_hi_si_Intrinsic<string GCCIntSuffix>
  47   : Hexagon_Intrinsic<GCCIntSuffix,
  48                           [llvm_i16_ty], [llvm_i32_ty],
  49                           [IntrNoMem]>;
  50 //
  51 // DEF_FUNCTION_TYPE_1(SI_ftype_SI,BT_INT,BT_INT) ->
  52 // Hexagon_si_si_Intrinsic<string GCCIntSuffix>
  53 //
  54 class Hexagon_si_si_Intrinsic<string GCCIntSuffix>
  55   : Hexagon_Intrinsic<GCCIntSuffix,
  56                           [llvm_i32_ty], [llvm_i32_ty],
  57                           [IntrNoMem]>;
  58 //
  59 // DEF_FUNCTION_TYPE_1(DI_ftype_SI,BT_LONGLONG,BT_INT) ->
  60 // Hexagon_di_si_Intrinsic<string GCCIntSuffix>
  61 //
  62 class Hexagon_di_si_Intrinsic<string GCCIntSuffix>
  63   : Hexagon_Intrinsic<GCCIntSuffix,
  64                           [llvm_i64_ty], [llvm_i32_ty],
  65                           [IntrNoMem]>;
  66 //
  67 // DEF_FUNCTION_TYPE_1(SI_ftype_DI,BT_INT,BT_LONGLONG) ->
  68 // Hexagon_si_di_Intrinsic<string GCCIntSuffix>
  69 //
  70 class Hexagon_si_di_Intrinsic<string GCCIntSuffix>
  71   : Hexagon_Intrinsic<GCCIntSuffix,
  72                           [llvm_i32_ty], [llvm_i64_ty],
  73                           [IntrNoMem]>;
  74 //
  75 // DEF_FUNCTION_TYPE_1(DI_ftype_DI,BT_LONGLONG,BT_LONGLONG) ->
  76 // Hexagon_di_di_Intrinsic<string GCCIntSuffix>
  77 //
  78 class Hexagon_di_di_Intrinsic<string GCCIntSuffix>
  79   : Hexagon_Intrinsic<GCCIntSuffix,
  80                           [llvm_i64_ty], [llvm_i64_ty],
  81                           [IntrNoMem]>;
  82 //
  83 // DEF_FUNCTION_TYPE_1(QI_ftype_QI,BT_BOOL,BT_BOOL) ->
  84 // Hexagon_qi_qi_Intrinsic<string GCCIntSuffix>
  85 //
  86 class Hexagon_qi_qi_Intrinsic<string GCCIntSuffix>
  87   : Hexagon_Intrinsic<GCCIntSuffix,
  88                           [llvm_i1_ty], [llvm_i32_ty],
  89                           [IntrNoMem]>;
  90 //
  91 // DEF_FUNCTION_TYPE_1(QI_ftype_SI,BT_BOOL,BT_INT) ->
  92 // Hexagon_qi_si_Intrinsic<string GCCIntSuffix>
  93 //
  94 class Hexagon_qi_si_Intrinsic<string GCCIntSuffix>
  95   : Hexagon_Intrinsic<GCCIntSuffix,
  96                           [llvm_i1_ty], [llvm_i32_ty],
  97                           [IntrNoMem]>;
  98 //
  99 // DEF_FUNCTION_TYPE_1(DI_ftype_QI,BT_LONGLONG,BT_BOOL) ->
 100 // Hexagon_di_qi_Intrinsic<string GCCIntSuffix>
 101 //
 102 class Hexagon_di_qi_Intrinsic<string GCCIntSuffix>
 103   : Hexagon_Intrinsic<GCCIntSuffix,
 104                           [llvm_i64_ty], [llvm_i32_ty],
 105                           [IntrNoMem]>;
 106 //
 107 // DEF_FUNCTION_TYPE_1(SI_ftype_QI,BT_INT,BT_BOOL) ->
 108 // Hexagon_si_qi_Intrinsic<string GCCIntSuffix>
 109 //
 110 class Hexagon_si_qi_Intrinsic<string GCCIntSuffix>
 111   : Hexagon_Intrinsic<GCCIntSuffix,
 112                           [llvm_i32_ty], [llvm_i32_ty],
 113                           [IntrNoMem]>;
 114 //
 115 // DEF_FUNCTION_TYPE_2(QI_ftype_SISI,BT_BOOL,BT_INT,BT_INT) ->
 116 // Hexagon_qi_sisi_Intrinsic<string GCCIntSuffix>
 117 //
 118 class Hexagon_qi_sisi_Intrinsic<string GCCIntSuffix>
 119   : Hexagon_Intrinsic<GCCIntSuffix,
 120                           [llvm_i1_ty], [llvm_i32_ty, llvm_i32_ty],
 121                           [IntrNoMem]>;
 122 //
 123 // DEF_FUNCTION_TYPE_2(void_ftype_SISI,BT_VOID,BT_INT,BT_INT) ->
 124 // Hexagon_void_sisi_Intrinsic<string GCCIntSuffix>
 125 //
 126 class Hexagon_void_sisi_Intrinsic<string GCCIntSuffix>
 127   : Hexagon_Intrinsic<GCCIntSuffix,
 128                           [llvm_void_ty], [llvm_i32_ty, llvm_i32_ty],
 129                           [IntrNoMem]>;
 130 //
 131 // DEF_FUNCTION_TYPE_2(SI_ftype_SISI,BT_INT,BT_INT,BT_INT) ->
 132 // Hexagon_si_sisi_Intrinsic<string GCCIntSuffix>
 133 //
 134 class Hexagon_si_sisi_Intrinsic<string GCCIntSuffix>
 135   : Hexagon_Intrinsic<GCCIntSuffix,
 136                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 137                           [IntrNoMem]>;
 138 //
 139 // DEF_FUNCTION_TYPE_2(USI_ftype_SISI,BT_UINT,BT_INT,BT_INT) ->
 140 // Hexagon_usi_sisi_Intrinsic<string GCCIntSuffix>
 141 //
 142 class Hexagon_usi_sisi_Intrinsic<string GCCIntSuffix>
 143   : Hexagon_Intrinsic<GCCIntSuffix,
 144                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 145                           [IntrNoMem]>;
 146 //
 147 // DEF_FUNCTION_TYPE_2(DI_ftype_SISI,BT_LONGLONG,BT_INT,BT_INT) ->
 148 // Hexagon_di_sisi_Intrinsic<string GCCIntSuffix>
 149 //
 150 class Hexagon_di_sisi_Intrinsic<string GCCIntSuffix>
 151   : Hexagon_Intrinsic<GCCIntSuffix,
 152                           [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty],
 153                           [IntrNoMem]>;
 154 //
 155 // DEF_FUNCTION_TYPE_2(UDI_ftype_SISI,BT_ULONGLONG,BT_INT,BT_INT) ->
 156 // Hexagon_udi_sisi_Intrinsic<string GCCIntSuffix>
 157 //
 158 class Hexagon_udi_sisi_Intrinsic<string GCCIntSuffix>
 159   : Hexagon_Intrinsic<GCCIntSuffix,
 160                           [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty],
 161                           [IntrNoMem]>;
 162 //
 163 // DEF_FUNCTION_TYPE_2(DI_ftype_SIDI,BT_LONGLONG,BT_INT,BT_LONGLONG) ->
 164 // Hexagon_di_sidi_Intrinsic<string GCCIntSuffix>
 165 //
 166 class Hexagon_di_sidi_Intrinsic<string GCCIntSuffix>
 167   : Hexagon_Intrinsic<GCCIntSuffix,
 168                           [llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty],
 169                           [IntrNoMem]>;
 170 //
 171 // DEF_FUNCTION_TYPE_2(DI_ftype_DISI,BT_LONGLONG,BT_LONGLONG,BT_INT) ->
 172 // Hexagon_di_disi_Intrinsic<string GCCIntSuffix>
 173 //
 174 class Hexagon_di_disi_Intrinsic<string GCCIntSuffix>
 175   : Hexagon_Intrinsic<GCCIntSuffix,
 176                           [llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty],
 177                           [IntrNoMem]>;
 178 //
 179 // DEF_FUNCTION_TYPE_2(SI_ftype_SIDI,BT_INT,BT_INT,BT_LONGLONG) ->
 180 // Hexagon_si_sidi_Intrinsic<string GCCIntSuffix>
 181 //
 182 class Hexagon_si_sidi_Intrinsic<string GCCIntSuffix>
 183   : Hexagon_Intrinsic<GCCIntSuffix,
 184                           [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 185                           [IntrNoMem]>;
 186 //
 187 // DEF_FUNCTION_TYPE_2(SI_ftype_DIDI,BT_INT,BT_LONGLONG,BT_LONGLONG) ->
 188 // Hexagon_si_didi_Intrinsic<string GCCIntSuffix>
 189 //
 190 class Hexagon_si_didi_Intrinsic<string GCCIntSuffix>
 191   : Hexagon_Intrinsic<GCCIntSuffix,
 192                           [llvm_i32_ty], [llvm_i64_ty, llvm_i64_ty],
 193                           [IntrNoMem]>;
 194 //
 195 // DEF_FUNCTION_TYPE_2(DI_ftype_DIDI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG) ->
 196 // Hexagon_di_didi_Intrinsic<string GCCIntSuffix>
 197 //
 198 class Hexagon_di_didi_Intrinsic<string GCCIntSuffix>
 199   : Hexagon_Intrinsic<GCCIntSuffix,
 200                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
 201                           [IntrNoMem]>;
 202 //
 203 // DEF_FUNCTION_TYPE_2(UDI_ftype_DIDI,BT_ULONGLONG,BT_LONGLONG,BT_LONGLONG) ->
 204 // Hexagon_udi_didi_Intrinsic<string GCCIntSuffix>
 205 //
 206 class Hexagon_udi_didi_Intrinsic<string GCCIntSuffix>
 207   : Hexagon_Intrinsic<GCCIntSuffix,
 208                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
 209                           [IntrNoMem]>;
 210 //
 211 // DEF_FUNCTION_TYPE_2(SI_ftype_DISI,BT_INT,BT_LONGLONG,BT_INT) ->
 212 // Hexagon_si_disi_Intrinsic<string GCCIntSuffix>
 213 //
 214 class Hexagon_si_disi_Intrinsic<string GCCIntSuffix>
 215   : Hexagon_Intrinsic<GCCIntSuffix,
 216                           [llvm_i32_ty], [llvm_i64_ty, llvm_i32_ty],
 217                           [IntrNoMem]>;
 218 //
 219 // DEF_FUNCTION_TYPE_2(QI_ftype_DIDI,BT_BOOL,BT_LONGLONG,BT_LONGLONG) ->
 220 // Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
 221 //
 222 class Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
 223   : Hexagon_Intrinsic<GCCIntSuffix,
 224                           [llvm_i1_ty], [llvm_i64_ty, llvm_i64_ty],
 225                           [IntrNoMem]>;
 226 //
 227 // DEF_FUNCTION_TYPE_2(QI_ftype_SIDI,BT_BOOL,BT_INT,BT_LONGLONG) ->
 228 // Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
 229 //
 230 class Hexagon_qi_sidi_Intrinsic<string GCCIntSuffix>
 231   : Hexagon_Intrinsic<GCCIntSuffix,
 232                           [llvm_i1_ty], [llvm_i32_ty, llvm_i64_ty],
 233                           [IntrNoMem]>;
 234 //
 235 // DEF_FUNCTION_TYPE_2(QI_ftype_DISI,BT_BOOL,BT_LONGLONG,BT_INT) ->
 236 // Hexagon_qi_disi_Intrinsic<string GCCIntSuffix>
 237 //
 238 class Hexagon_qi_disi_Intrinsic<string GCCIntSuffix>
 239   : Hexagon_Intrinsic<GCCIntSuffix,
 240                           [llvm_i1_ty], [llvm_i64_ty, llvm_i32_ty],
 241                           [IntrNoMem]>;
 242 //
 243 // DEF_FUNCTION_TYPE_2(QI_ftype_QIQI,BT_BOOL,BT_BOOL,BT_BOOL) ->
 244 // Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix>
 245 //
 246 class Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix>
 247   : Hexagon_Intrinsic<GCCIntSuffix,
 248                           [llvm_i1_ty], [llvm_i32_ty, llvm_i32_ty],
 249                           [IntrNoMem]>;
 250 //
 251 // DEF_FUNCTION_TYPE_2(QI_ftype_QIQIQI,BT_BOOL,BT_BOOL,BT_BOOL) ->
 252 // Hexagon_qi_qiqiqi_Intrinsic<string GCCIntSuffix>
 253 //
 254 class Hexagon_qi_qiqiqi_Intrinsic<string GCCIntSuffix>
 255   : Hexagon_Intrinsic<GCCIntSuffix,
 256                           [llvm_i1_ty], [llvm_i1_ty, llvm_i1_ty, llvm_i1_ty],
 257                           [IntrNoMem]>;
 258 //
 259 // DEF_FUNCTION_TYPE_2(SI_ftype_QIQI,BT_INT,BT_BOOL,BT_BOOL) ->
 260 // Hexagon_si_qiqi_Intrinsic<string GCCIntSuffix>
 261 //
 262 class Hexagon_si_qiqi_Intrinsic<string GCCIntSuffix>
 263   : Hexagon_Intrinsic<GCCIntSuffix,
 264                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 265                           [IntrNoMem]>;
 266 //
 267 // DEF_FUNCTION_TYPE_2(SI_ftype_QISI,BT_INT,BT_BOOL,BT_INT) ->
 268 // Hexagon_si_qisi_Intrinsic<string GCCIntSuffix>
 269 //
 270 class Hexagon_si_qisi_Intrinsic<string GCCIntSuffix>
 271   : Hexagon_Intrinsic<GCCIntSuffix,
 272                           [llvm_i32_ty], [llvm_i1_ty, llvm_i32_ty],
 273                           [IntrNoMem]>;
 274 //
 275 // DEF_FUNCTION_TYPE_3(void_ftype_SISISI,BT_VOID,BT_INT,BT_INT,BT_INT) ->
 276 // Hexagon_void_sisisi_Intrinsic<string GCCIntSuffix>
 277 //
 278 class Hexagon_void_sisisi_Intrinsic<string GCCIntSuffix>
 279   : Hexagon_Intrinsic<GCCIntSuffix,
 280                           [llvm_void_ty], [llvm_i32_ty, llvm_i32_ty,
 281                            llvm_i32_ty],
 282                           [IntrNoMem]>;
 283 //
 284 // DEF_FUNCTION_TYPE_3(SI_ftype_SISISI,BT_INT,BT_INT,BT_INT,BT_INT) ->
 285 // Hexagon_si_sisisi_Intrinsic<string GCCIntSuffix>
 286 //
 287 class Hexagon_si_sisisi_Intrinsic<string GCCIntSuffix>
 288   : Hexagon_Intrinsic<GCCIntSuffix,
 289                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
 290                            llvm_i32_ty],
 291                           [IntrNoMem]>;
 292 //
 293 // DEF_FUNCTION_TYPE_3(DI_ftype_SISISI,BT_LONGLONG,BT_INT,BT_INT,BT_INT) ->
 294 // Hexagon_di_sisisi_Intrinsic<string GCCIntSuffix>
 295 //
 296 class Hexagon_di_sisisi_Intrinsic<string GCCIntSuffix>
 297   : Hexagon_Intrinsic<GCCIntSuffix,
 298                           [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty,
 299                            llvm_i32_ty],
 300                           [IntrNoMem]>;
 301 //
 302 // DEF_FUNCTION_TYPE_3(SI_ftype_DISISI,BT_INT,BT_LONGLONG,BT_INT,BT_INT) ->
 303 // Hexagon_si_disisi_Intrinsic<string GCCIntSuffix>
 304 //
 305 class Hexagon_si_disisi_Intrinsic<string GCCIntSuffix>
 306   : Hexagon_Intrinsic<GCCIntSuffix,
 307                           [llvm_i32_ty], [llvm_i64_ty, llvm_i32_ty,
 308                            llvm_i32_ty],
 309                           [IntrNoMem]>;
 310 //
 311 // DEF_FUNCTION_TYPE_3(DI_ftype_DISISI,BT_LONGLONG,BT_LONGLONG,BT_INT,BT_INT) ->
 312 // Hexagon_di_disisi_Intrinsic<string GCCIntSuffix>
 313 //
 314 class Hexagon_di_disisi_Intrinsic<string GCCIntSuffix>
 315   : Hexagon_Intrinsic<GCCIntSuffix,
 316                           [llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty,
 317                            llvm_i32_ty],
 318                           [IntrNoMem]>;
 319 //
 320 // DEF_FUNCTION_TYPE_3(SI_ftype_SIDISI,BT_INT,BT_INT,BT_LONGLONG,BT_INT) ->
 321 // Hexagon_si_sidisi_Intrinsic<string GCCIntSuffix>
 322 //
 323 class Hexagon_si_sidisi_Intrinsic<string GCCIntSuffix>
 324   : Hexagon_Intrinsic<GCCIntSuffix,
 325                           [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty,
 326                            llvm_i32_ty],
 327                           [IntrNoMem]>;
 328 //
 329 // DEF_FUNCTION_TYPE_3(DI_ftype_DIDISI,BT_LONGLONG,BT_LONGLONG,
 330 //                     BT_LONGLONG,BT_INT) ->
 331 // Hexagon_di_didisi_Intrinsic<string GCCIntSuffix>
 332 //
 333 class Hexagon_di_didisi_Intrinsic<string GCCIntSuffix>
 334   : Hexagon_Intrinsic<GCCIntSuffix,
 335                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 336                            llvm_i32_ty],
 337                           [IntrNoMem]>;
 338 //
 339 // DEF_FUNCTION_TYPE_3(SI_ftype_SIDIDI,BT_INT,BT_INT,BT_LONGLONG,BT_LONGLONG) ->
 340 // Hexagon_si_sididi_Intrinsic<string GCCIntSuffix>
 341 //
 342 class Hexagon_si_sididi_Intrinsic<string GCCIntSuffix>
 343   : Hexagon_Intrinsic<GCCIntSuffix,
 344                           [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty,
 345                            llvm_i64_ty],
 346                           [IntrNoMem]>;
 347 //
 348 // DEF_FUNCTION_TYPE_3(DI_ftype_DIDIDI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG,
 349 //                     BT_LONGLONG) ->
 350 // Hexagon_di_dididi_Intrinsic<string GCCIntSuffix>
 351 //
 352 class Hexagon_di_dididi_Intrinsic<string GCCIntSuffix>
 353   : Hexagon_Intrinsic<GCCIntSuffix,
 354                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 355                            llvm_i64_ty],
 356                           [IntrNoMem]>;
 357 //
 358 // DEF_FUNCTION_TYPE_3(SI_ftype_SISIDI,BT_INT,BT_INT,BT_INT,BT_LONGLONG) ->
 359 // Hexagon_si_sisidi_Intrinsic<string GCCIntSuffix>
 360 //
 361 class Hexagon_si_sisidi_Intrinsic<string GCCIntSuffix>
 362   : Hexagon_Intrinsic<GCCIntSuffix,
 363                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
 364                            llvm_i64_ty],
 365                           [IntrNoMem]>;
 366 //
 367 // DEF_FUNCTION_TYPE_3(SI_ftype_QISISI,BT_INT,BT_BOOL,BT_INT,BT_INT) ->
 368 // Hexagon_si_qisisi_Intrinsic<string GCCIntSuffix>
 369 //
 370 class Hexagon_si_qisisi_Intrinsic<string GCCIntSuffix>
 371   : Hexagon_Intrinsic<GCCIntSuffix,
 372                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
 373                            llvm_i32_ty],
 374                           [IntrNoMem]>;
 375 //
 376 // DEF_FUNCTION_TYPE_3(DI_ftype_QISISI,BT_LONGLONG,BT_BOOL,BT_INT,BT_INT) ->
 377 // Hexagon_di_qisisi_Intrinsic<string GCCIntSuffix>
 378 //
 379 class Hexagon_di_qisisi_Intrinsic<string GCCIntSuffix>
 380   : Hexagon_Intrinsic<GCCIntSuffix,
 381                           [llvm_i64_ty], [llvm_i1_ty, llvm_i32_ty,
 382                            llvm_i32_ty],
 383                           [IntrNoMem]>;
 384 //
 385 // DEF_FUNCTION_TYPE_3(DI_ftype_QIDIDI,BT_LONGLONG,BT_BOOL,BT_LONGLONG,
 386 //                     BT_LONGLONG) ->
 387 // Hexagon_di_qididi_Intrinsic<string GCCIntSuffix>
 388 //
 389 class Hexagon_di_qididi_Intrinsic<string GCCIntSuffix>
 390   : Hexagon_Intrinsic<GCCIntSuffix,
 391                           [llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty,
 392                            llvm_i64_ty],
 393                           [IntrNoMem]>;
 394 //
 395 // DEF_FUNCTION_TYPE_3(DI_ftype_DIDIQI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG,
 396 //                     BT_BOOL) ->
 397 // Hexagon_di_didiqi_Intrinsic<string GCCIntSuffix>
 398 //
 399 class Hexagon_di_didiqi_Intrinsic<string GCCIntSuffix>
 400   : Hexagon_Intrinsic<GCCIntSuffix,
 401                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 402                            llvm_i32_ty],
 403                           [IntrNoMem]>;
 404 //
 405 // DEF_FUNCTION_TYPE_4(SI_ftype_SISISISI,BT_INT,BT_INT,BT_INT,BT_INT,BT_INT) ->
 406 // Hexagon_si_sisisisi_Intrinsic<string GCCIntSuffix>
 407 //
 408 class Hexagon_si_sisisisi_Intrinsic<string GCCIntSuffix>
 409   : Hexagon_Intrinsic<GCCIntSuffix,
 410                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
 411                            llvm_i32_ty, llvm_i32_ty],
 412                           [IntrNoMem]>;
 413 //
 414 // DEF_FUNCTION_TYPE_4(DI_ftype_DIDISISI,BT_LONGLONG,BT_LONGLONG,
 415 //                     BT_LONGLONG,BT_INT,BT_INT) ->
 416 // Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix>
 417 //
 418 class Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix>
 419   : Hexagon_Intrinsic<GCCIntSuffix,
 420                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 421                            llvm_i32_ty, llvm_i32_ty],
 422                           [IntrNoMem]>;
 423
 424 class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
 425   : Hexagon_Intrinsic<GCCIntSuffix,
 426                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
 427                            llvm_i32_ty],
 428                           [IntrArgMemOnly]>;
 429
 430 class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix>
 431   : Hexagon_Intrinsic<GCCIntSuffix,
 432                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
 433                            llvm_i32_ty],
 434                           [IntrWriteMem]>;
 435
 436 class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix>
 437   : Hexagon_Intrinsic<GCCIntSuffix,
 438                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
 439                            llvm_i32_ty],
 440                           [IntrWriteMem]>;
 441
 442 class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
 443   : Hexagon_Intrinsic<GCCIntSuffix,
 444                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
 445                            llvm_i32_ty, llvm_i32_ty],
 446                           [IntrArgMemOnly]>;
 447
 448 class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix>
 449   : Hexagon_Intrinsic<GCCIntSuffix,
 450                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
 451                            llvm_i32_ty, llvm_i32_ty],
 452                           [IntrWriteMem]>;
 453
 454 class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix>
 455   : Hexagon_Intrinsic<GCCIntSuffix,
 456                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
 457                            llvm_i32_ty, llvm_i32_ty],
 458                           [IntrWriteMem]>;
 459
 460 class Hexagon_v256_v256v256_Intrinsic<string GCCIntSuffix>
 461   : Hexagon_Intrinsic<GCCIntSuffix,
 462                           [llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
 463                           [IntrArgMemOnly]>;
 464
 465 //
 466 // Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
 467 //
 468 class Hexagon_sf_si_Intrinsic<string GCCIntSuffix>
 469   : Hexagon_Intrinsic<GCCIntSuffix,
 470                           [llvm_float_ty], [llvm_i32_ty],
 471                           [IntrNoMem, Throws]>;
 472 //
 473 // Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
 474 //
 475 class Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
 476   : Hexagon_Intrinsic<GCCIntSuffix,
 477                           [llvm_float_ty], [llvm_double_ty],
 478                           [IntrNoMem]>;
 479 //
 480 // Hexagon_sf_di_Intrinsic<string GCCIntSuffix>
 481 //
 482 class Hexagon_sf_di_Intrinsic<string GCCIntSuffix>
 483   : Hexagon_Intrinsic<GCCIntSuffix,
 484                           [llvm_float_ty], [llvm_i64_ty],
 485                           [IntrNoMem]>;
 486 //
 487 // Hexagon_df_sf_Intrinsic<string GCCIntSuffix>
 488 //
 489 class Hexagon_df_sf_Intrinsic<string GCCIntSuffix>
 490   : Hexagon_Intrinsic<GCCIntSuffix,
 491                           [llvm_double_ty], [llvm_float_ty],
 492                           [IntrNoMem]>;
 493 //
 494 // Hexagon_di_sf_Intrinsic<string GCCIntSuffix>
 495 //
 496 class Hexagon_di_sf_Intrinsic<string GCCIntSuffix>
 497   : Hexagon_Intrinsic<GCCIntSuffix,
 498                           [llvm_i64_ty], [llvm_float_ty],
 499                           [IntrNoMem]>;
 500 //
 501 // Hexagon_sf_sf_Intrinsic<string GCCIntSuffix>
 502 //
 503 class Hexagon_sf_sf_Intrinsic<string GCCIntSuffix>
 504   : Hexagon_Intrinsic<GCCIntSuffix,
 505                           [llvm_float_ty], [llvm_float_ty],
 506                           [IntrNoMem]>;
 507 //
 508 // Hexagon_si_sf_Intrinsic<string GCCIntSuffix>
 509 //
 510 class Hexagon_si_sf_Intrinsic<string GCCIntSuffix>
 511   : Hexagon_Intrinsic<GCCIntSuffix,
 512                           [llvm_i32_ty], [llvm_float_ty],
 513                           [IntrNoMem]>;
 514 //
 515 // Hexagon_si_df_Intrinsic<string GCCIntSuffix>
 516 //
 517 class Hexagon_si_df_Intrinsic<string GCCIntSuffix>
 518   : Hexagon_Intrinsic<GCCIntSuffix,
 519                           [llvm_i32_ty], [llvm_double_ty],
 520                           [IntrNoMem]>;
 521 //
 522 // Hexagon_sf_sfsf_Intrinsic<string GCCIntSuffix>
 523 //
 524 class Hexagon_sf_sfsf_Intrinsic<string GCCIntSuffix>
 525   : Hexagon_Intrinsic<GCCIntSuffix,
 526                           [llvm_float_ty], [llvm_float_ty, llvm_float_ty],
 527                           [IntrNoMem, Throws]>;
 528 //
 529 // Hexagon_si_sfsf_Intrinsic<string GCCIntSuffix>
 530 //
 531 class Hexagon_si_sfsf_Intrinsic<string GCCIntSuffix>
 532   : Hexagon_Intrinsic<GCCIntSuffix,
 533                           [llvm_i32_ty], [llvm_float_ty, llvm_float_ty],
 534                           [IntrNoMem, Throws]>;
 535 //
 536 // Hexagon_si_sfsi_Intrinsic<string GCCIntSuffix>
 537 //
 538 class Hexagon_si_sfsi_Intrinsic<string GCCIntSuffix>
 539   : Hexagon_Intrinsic<GCCIntSuffix,
 540                           [llvm_i32_ty], [llvm_float_ty, llvm_i32_ty],
 541                           [IntrNoMem, Throws]>;
 542 //
 543 // Hexagon_qi_sfqi_Intrinsic<string GCCIntSuffix>
 544 //
 545 class Hexagon_qi_sfqi_Intrinsic<string GCCIntSuffix>
 546   : Hexagon_Intrinsic<GCCIntSuffix,
 547                           [llvm_i1_ty], [llvm_float_ty, llvm_i32_ty],
 548                           [IntrNoMem]>;
 549 //
 550 // Hexagon_sf_sfsfsf_Intrinsic<string GCCIntSuffix>
 551 //
 552 class Hexagon_sf_sfsfsf_Intrinsic<string GCCIntSuffix>
 553   : Hexagon_Intrinsic<GCCIntSuffix,
 554                           [llvm_float_ty], [llvm_float_ty, llvm_float_ty,
 555                                             llvm_float_ty],
 556                           [IntrNoMem, Throws]>;
 557 //
 558 // Hexagon_sf_sfsfsfqi_Intrinsic<string GCCIntSuffix>
 559 //
 560 class Hexagon_sf_sfsfsfqi_Intrinsic<string GCCIntSuffix>
 561   : Hexagon_Intrinsic<GCCIntSuffix,
 562                           [llvm_float_ty], [llvm_float_ty, llvm_float_ty,
 563                                             llvm_float_ty,
 564                            llvm_i32_ty],
 565                           [IntrNoMem, Throws]>;
 566 //
 567 // Hexagon_di_dididi_Intrinsic<string GCCIntSuffix>
 568 //
 569 class Hexagon_di_dididisi_Intrinsic<string GCCIntSuffix>
 570   : Hexagon_Intrinsic<GCCIntSuffix,
 571                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 572                            llvm_i64_ty, llvm_i32_ty],
 573                           [IntrNoMem]>;
 574 //
 575 // Hexagon_df_si_Intrinsic<string GCCIntSuffix>
 576 //
 577 class Hexagon_df_si_Intrinsic<string GCCIntSuffix>
 578   : Hexagon_Intrinsic<GCCIntSuffix,
 579                           [llvm_double_ty], [llvm_i32_ty],
 580                           [IntrNoMem, Throws]>;
 581 //
 582 // Hexagon_df_di_Intrinsic<string GCCIntSuffix>
 583 //
 584 class Hexagon_df_di_Intrinsic<string GCCIntSuffix>
 585   : Hexagon_Intrinsic<GCCIntSuffix,
 586                           [llvm_double_ty], [llvm_i64_ty],
 587                           [IntrNoMem]>;
 588 //
 589 // Hexagon_di_df_Intrinsic<string GCCIntSuffix>
 590 //
 591 class Hexagon_di_df_Intrinsic<string GCCIntSuffix>
 592   : Hexagon_Intrinsic<GCCIntSuffix,
 593                           [llvm_i64_ty], [llvm_double_ty],
 594                           [IntrNoMem]>;
 595 //
 596 // Hexagon_df_df_Intrinsic<string GCCIntSuffix>
 597 //
 598 class Hexagon_df_df_Intrinsic<string GCCIntSuffix>
 599   : Hexagon_Intrinsic<GCCIntSuffix,
 600                           [llvm_double_ty], [llvm_double_ty],
 601                           [IntrNoMem]>;
 602 //
 603 // Hexagon_df_dfdf_Intrinsic<string GCCIntSuffix>
 604 //
 605 class Hexagon_df_dfdf_Intrinsic<string GCCIntSuffix>
 606   : Hexagon_Intrinsic<GCCIntSuffix,
 607                           [llvm_double_ty], [llvm_double_ty, llvm_double_ty],
 608                           [IntrNoMem, Throws]>;
 609 //
 610 // Hexagon_si_dfdf_Intrinsic<string GCCIntSuffix>
 611 //
 612 class Hexagon_si_dfdf_Intrinsic<string GCCIntSuffix>
 613   : Hexagon_Intrinsic<GCCIntSuffix,
 614                           [llvm_i32_ty], [llvm_double_ty, llvm_double_ty],
 615                           [IntrNoMem, Throws]>;
 616 //
 617 // Hexagon_si_dfsi_Intrinsic<string GCCIntSuffix>
 618 //
 619 class Hexagon_si_dfsi_Intrinsic<string GCCIntSuffix>
 620   : Hexagon_Intrinsic<GCCIntSuffix,
 621                           [llvm_i32_ty], [llvm_double_ty, llvm_i32_ty],
 622                           [IntrNoMem, Throws]>;
 623 //
 624 //
 625 // Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
 626 //
 627 class Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
 628   : Hexagon_Intrinsic<GCCIntSuffix,
 629                           [llvm_double_ty], [llvm_double_ty, llvm_double_ty,
 630                                              llvm_double_ty],
 631                           [IntrNoMem, Throws]>;
 632 //
 633 // Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
 634 //
 635 class Hexagon_df_dfdfdfqi_Intrinsic<string GCCIntSuffix>
 636   : Hexagon_Intrinsic<GCCIntSuffix,
 637                           [llvm_double_ty], [llvm_double_ty, llvm_double_ty,
 638                                              llvm_double_ty,
 639                           llvm_i32_ty],
 640                           [IntrNoMem, Throws]>;
 641
 642
 643 // This one below will not be auto-generated,
 644 // so make sure, you don't overwrite this one.
 645 //
 646 // BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
 647 //
 648 def int_hexagon_circ_ldd :
 649 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
 650 //
 651 // BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4)
 652 //
 653 def int_hexagon_circ_ldw :
 654 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">;
 655 //
 656 // BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4)
 657 //
 658 def int_hexagon_circ_ldh :
 659 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">;
 660 //
 661 // BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4)
 662 //
 663 def int_hexagon_circ_lduh :
 664 Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">;
 665 //
 666 // BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4)
 667 //
 668 def int_hexagon_circ_ldb :
 669 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">;
 670 //
 671 // BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4)
 672 //
 673 def int_hexagon_circ_ldub :
 674 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">;
 675
 676 //
 677 // BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4)
 678 //
 679 def int_hexagon_circ_std :
 680 Hexagon_mem_memdisisi_Intrinsic<"circ_std">;
 681 //
 682 // BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4)
 683 //
 684 def int_hexagon_circ_stw :
 685 Hexagon_mem_memsisisi_Intrinsic<"circ_stw">;
 686 //
 687 // BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4)
 688 //
 689 def int_hexagon_circ_sth :
 690 Hexagon_mem_memsisisi_Intrinsic<"circ_sth">;
 691 //
 692 // BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4)
 693 //
 694 def int_hexagon_circ_sthhi :
 695 Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">;
 696 //
 697 // BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4)
 698 //
 699 def int_hexagon_circ_stb :
 700 Hexagon_mem_memsisisi_Intrinsic<"circ_stb">;
 701
 702
 703 def int_hexagon_mm256i_vaddw :
 704 Hexagon_v256_v256v256_Intrinsic<"_mm256i_vaddw">;
 705
 706
 707 // This one above will not be auto-generated,
 708 // so make sure, you don't overwrite this one.
 709 //
 710 // BUILTIN_INFO(HEXAGON.C2_cmpeq,QI_ftype_SISI,2)
 711 //
 712 def int_hexagon_C2_cmpeq :
 713 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpeq">;
 714 //
 715 // BUILTIN_INFO(HEXAGON.C2_cmpgt,QI_ftype_SISI,2)
 716 //
 717 def int_hexagon_C2_cmpgt :
 718 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgt">;
 719 //
 720 // BUILTIN_INFO(HEXAGON.C2_cmpgtu,QI_ftype_SISI,2)
 721 //
 722 def int_hexagon_C2_cmpgtu :
 723 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgtu">;
 724 //
 725 // BUILTIN_INFO(HEXAGON.C2_cmpeqp,QI_ftype_DIDI,2)
 726 //
 727 def int_hexagon_C2_cmpeqp :
 728 Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpeqp">;
 729 //
 730 // BUILTIN_INFO(HEXAGON.C2_cmpgtp,QI_ftype_DIDI,2)
 731 //
 732 def int_hexagon_C2_cmpgtp :
 733 Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpgtp">;
 734 //
 735 // BUILTIN_INFO(HEXAGON.C2_cmpgtup,QI_ftype_DIDI,2)
 736 //
 737 def int_hexagon_C2_cmpgtup :
 738 Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpgtup">;
 739 //
 740 // BUILTIN_INFO(HEXAGON.A4_rcmpeqi,SI_ftype_SISI,2)
 741 //
 742 def int_hexagon_A4_rcmpeqi :
 743 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpeqi">;
 744 //
 745 // BUILTIN_INFO(HEXAGON.A4_rcmpneqi,SI_ftype_SISI,2)
 746 //
 747 def int_hexagon_A4_rcmpneqi :
 748 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneqi">;
 749 //
 750 // BUILTIN_INFO(HEXAGON.A4_rcmpeq,SI_ftype_SISI,2)
 751 //
 752 def int_hexagon_A4_rcmpeq :
 753 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpeq">;
 754 //
 755 // BUILTIN_INFO(HEXAGON.A4_rcmpneq,SI_ftype_SISI,2)
 756 //
 757 def int_hexagon_A4_rcmpneq :
 758 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneq">;
 759 //
 760 // BUILTIN_INFO(HEXAGON.C2_bitsset,QI_ftype_SISI,2)
 761 //
 762 def int_hexagon_C2_bitsset :
 763 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsset">;
 764 //
 765 // BUILTIN_INFO(HEXAGON.C2_bitsclr,QI_ftype_SISI,2)
 766 //
 767 def int_hexagon_C2_bitsclr :
 768 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsclr">;
 769 //
 770 // BUILTIN_INFO(HEXAGON.C4_nbitsset,QI_ftype_SISI,2)
 771 //
 772 def int_hexagon_C4_nbitsset :
 773 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsset">;
 774 //
 775 // BUILTIN_INFO(HEXAGON.C4_nbitsclr,QI_ftype_SISI,2)
 776 //
 777 def int_hexagon_C4_nbitsclr :
 778 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsclr">;
 779 //
 780 // BUILTIN_INFO(HEXAGON.C2_cmpeqi,QI_ftype_SISI,2)
 781 //
 782 def int_hexagon_C2_cmpeqi :
 783 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpeqi">;
 784 //
 785 // BUILTIN_INFO(HEXAGON.C2_cmpgti,QI_ftype_SISI,2)
 786 //
 787 def int_hexagon_C2_cmpgti :
 788 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgti">;
 789 //
 790 // BUILTIN_INFO(HEXAGON.C2_cmpgtui,QI_ftype_SISI,2)
 791 //
 792 def int_hexagon_C2_cmpgtui :
 793 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgtui">;
 794 //
 795 // BUILTIN_INFO(HEXAGON.C2_cmpgei,QI_ftype_SISI,2)
 796 //
 797 def int_hexagon_C2_cmpgei :
 798 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgei">;
 799 //
 800 // BUILTIN_INFO(HEXAGON.C2_cmpgeui,QI_ftype_SISI,2)
 801 //
 802 def int_hexagon_C2_cmpgeui :
 803 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgeui">;
 804 //
 805 // BUILTIN_INFO(HEXAGON.C2_cmplt,QI_ftype_SISI,2)
 806 //
 807 def int_hexagon_C2_cmplt :
 808 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmplt">;
 809 //
 810 // BUILTIN_INFO(HEXAGON.C2_cmpltu,QI_ftype_SISI,2)
 811 //
 812 def int_hexagon_C2_cmpltu :
 813 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpltu">;
 814 //
 815 // BUILTIN_INFO(HEXAGON.C2_bitsclri,QI_ftype_SISI,2)
 816 //
 817 def int_hexagon_C2_bitsclri :
 818 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsclri">;
 819 //
 820 // BUILTIN_INFO(HEXAGON.C4_nbitsclri,QI_ftype_SISI,2)
 821 //
 822 def int_hexagon_C4_nbitsclri :
 823 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsclri">;
 824 //
 825 // BUILTIN_INFO(HEXAGON.C4_cmpneqi,QI_ftype_SISI,2)
 826 //
 827 def int_hexagon_C4_cmpneqi :
 828 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpneqi">;
 829 //
 830 // BUILTIN_INFO(HEXAGON.C4_cmpltei,QI_ftype_SISI,2)
 831 //
 832 def int_hexagon_C4_cmpltei :
 833 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpltei">;
 834 //
 835 // BUILTIN_INFO(HEXAGON.C4_cmplteui,QI_ftype_SISI,2)
 836 //
 837 def int_hexagon_C4_cmplteui :
 838 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplteui">;
 839 //
 840 // BUILTIN_INFO(HEXAGON.C4_cmpneq,QI_ftype_SISI,2)
 841 //
 842 def int_hexagon_C4_cmpneq :
 843 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpneq">;
 844 //
 845 // BUILTIN_INFO(HEXAGON.C4_cmplte,QI_ftype_SISI,2)
 846 //
 847 def int_hexagon_C4_cmplte :
 848 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplte">;
 849 //
 850 // BUILTIN_INFO(HEXAGON.C4_cmplteu,QI_ftype_SISI,2)
 851 //
 852 def int_hexagon_C4_cmplteu :
 853 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplteu">;
 854 //
 855 // BUILTIN_INFO(HEXAGON.C2_and,QI_ftype_QIQI,2)
 856 //
 857 def int_hexagon_C2_and :
 858 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_and">;
 859 //
 860 // BUILTIN_INFO(HEXAGON.C2_or,QI_ftype_QIQI,2)
 861 //
 862 def int_hexagon_C2_or :
 863 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_or">;
 864 //
 865 // BUILTIN_INFO(HEXAGON.C2_xor,QI_ftype_QIQI,2)
 866 //
 867 def int_hexagon_C2_xor :
 868 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_xor">;
 869 //
 870 // BUILTIN_INFO(HEXAGON.C2_andn,QI_ftype_QIQI,2)
 871 //
 872 def int_hexagon_C2_andn :
 873 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_andn">;
 874 //
 875 // BUILTIN_INFO(HEXAGON.C2_not,QI_ftype_QI,1)
 876 //
 877 def int_hexagon_C2_not :
 878 Hexagon_si_si_Intrinsic<"HEXAGON_C2_not">;
 879 //
 880 // BUILTIN_INFO(HEXAGON.C2_orn,QI_ftype_QIQI,2)
 881 //
 882 def int_hexagon_C2_orn :
 883 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_orn">;
 884 //
 885 // BUILTIN_INFO(HEXAGON.C4_and_and,QI_ftype_QIQIQI,3)
 886 //
 887 def int_hexagon_C4_and_and :
 888 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_and">;
 889 //
 890 // BUILTIN_INFO(HEXAGON.C4_and_or,QI_ftype_QIQIQI,3)
 891 //
 892 def int_hexagon_C4_and_or :
 893 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_or">;
 894 //
 895 // BUILTIN_INFO(HEXAGON.C4_or_and,QI_ftype_QIQIQI,3)
 896 //
 897 def int_hexagon_C4_or_and :
 898 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_and">;
 899 //
 900 // BUILTIN_INFO(HEXAGON.C4_or_or,QI_ftype_QIQIQI,3)
 901 //
 902 def int_hexagon_C4_or_or :
 903 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_or">;
 904 //
 905 // BUILTIN_INFO(HEXAGON.C4_and_andn,QI_ftype_QIQIQI,3)
 906 //
 907 def int_hexagon_C4_and_andn :
 908 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_andn">;
 909 //
 910 // BUILTIN_INFO(HEXAGON.C4_and_orn,QI_ftype_QIQIQI,3)
 911 //
 912 def int_hexagon_C4_and_orn :
 913 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_orn">;
 914 //
 915 // BUILTIN_INFO(HEXAGON.C4_or_andn,QI_ftype_QIQIQI,3)
 916 //
 917 def int_hexagon_C4_or_andn :
 918 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_andn">;
 919 //
 920 // BUILTIN_INFO(HEXAGON.C4_or_orn,QI_ftype_QIQIQI,3)
 921 //
 922 def int_hexagon_C4_or_orn :
 923 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_orn">;
 924 //
 925 // BUILTIN_INFO(HEXAGON.C2_pxfer_map,QI_ftype_QI,1)
 926 //
 927 def int_hexagon_C2_pxfer_map :
 928 Hexagon_si_qi_Intrinsic<"HEXAGON_C2_pxfer_map">;
 929 //
 930 // BUILTIN_INFO(HEXAGON.C2_any8,QI_ftype_QI,1)
 931 //
 932 def int_hexagon_C2_any8 :
 933 Hexagon_si_qi_Intrinsic<"HEXAGON_C2_any8">;
 934 //
 935 // BUILTIN_INFO(HEXAGON.C2_all8,QI_ftype_QI,1)
 936 //
 937 def int_hexagon_C2_all8 :
 938 Hexagon_si_qi_Intrinsic<"HEXAGON_C2_all8">;
 939 //
 940 // BUILTIN_INFO(HEXAGON.C2_vitpack,SI_ftype_QIQI,2)
 941 //
 942 def int_hexagon_C2_vitpack :
 943 Hexagon_si_qiqi_Intrinsic<"HEXAGON_C2_vitpack">;
 944 //
 945 // BUILTIN_INFO(HEXAGON.C2_mux,SI_ftype_QISISI,3)
 946 //
 947 def int_hexagon_C2_mux :
 948 Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_mux">;
 949 //
 950 // BUILTIN_INFO(HEXAGON.C2_muxii,SI_ftype_QISISI,3)
 951 //
 952 def int_hexagon_C2_muxii :
 953 Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxii">;
 954 //
 955 // BUILTIN_INFO(HEXAGON.C2_muxir,SI_ftype_QISISI,3)
 956 //
 957 def int_hexagon_C2_muxir :
 958 Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxir">;
 959 //
 960 // BUILTIN_INFO(HEXAGON.C2_muxri,SI_ftype_QISISI,3)
 961 //
 962 def int_hexagon_C2_muxri :
 963 Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxri">;
 964 //
 965 // BUILTIN_INFO(HEXAGON.C2_vmux,DI_ftype_QIDIDI,3)
 966 //
 967 def int_hexagon_C2_vmux :
 968 Hexagon_di_qididi_Intrinsic<"HEXAGON_C2_vmux">;
 969 //
 970 // BUILTIN_INFO(HEXAGON.C2_mask,DI_ftype_QI,1)
 971 //
 972 def int_hexagon_C2_mask :
 973 Hexagon_di_qi_Intrinsic<"HEXAGON_C2_mask">;
 974 //
 975 // BUILTIN_INFO(HEXAGON.A2_vcmpbeq,QI_ftype_DIDI,2)
 976 //
 977 def int_hexagon_A2_vcmpbeq :
 978 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpbeq">;
 979 //
 980 // BUILTIN_INFO(HEXAGON.A4_vcmpbeqi,QI_ftype_DISI,2)
 981 //
 982 def int_hexagon_A4_vcmpbeqi :
 983 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbeqi">;
 984 //
 985 // BUILTIN_INFO(HEXAGON.A4_vcmpbeq_any,QI_ftype_DIDI,2)
 986 //
 987 def int_hexagon_A4_vcmpbeq_any :
 988 Hexagon_si_didi_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;
 989 //
 990 // BUILTIN_INFO(HEXAGON.A2_vcmpbgtu,QI_ftype_DIDI,2)
 991 //
 992 def int_hexagon_A2_vcmpbgtu :
 993 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpbgtu">;
 994 //
 995 // BUILTIN_INFO(HEXAGON.A4_vcmpbgtui,QI_ftype_DISI,2)
 996 //
 997 def int_hexagon_A4_vcmpbgtui :
 998 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbgtui">;
 999 //
1000 // BUILTIN_INFO(HEXAGON.A4_vcmpbgt,QI_ftype_DIDI,2)
1001 //
1002 def int_hexagon_A4_vcmpbgt :
1003 Hexagon_si_didi_Intrinsic<"HEXAGON_A4_vcmpbgt">;
1004 //
1005 // BUILTIN_INFO(HEXAGON.A4_vcmpbgti,QI_ftype_DISI,2)
1006 //
1007 def int_hexagon_A4_vcmpbgti :
1008 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbgti">;
1009 //
1010 // BUILTIN_INFO(HEXAGON.A4_cmpbeq,QI_ftype_SISI,2)
1011 //
1012 def int_hexagon_A4_cmpbeq :
1013 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbeq">;
1014 //
1015 // BUILTIN_INFO(HEXAGON.A4_cmpbeqi,QI_ftype_SISI,2)
1016 //
1017 def int_hexagon_A4_cmpbeqi :
1018 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbeqi">;
1019 //
1020 // BUILTIN_INFO(HEXAGON.A4_cmpbgtu,QI_ftype_SISI,2)
1021 //
1022 def int_hexagon_A4_cmpbgtu :
1023 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgtu">;
1024 //
1025 // BUILTIN_INFO(HEXAGON.A4_cmpbgtui,QI_ftype_SISI,2)
1026 //
1027 def int_hexagon_A4_cmpbgtui :
1028 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgtui">;
1029 //
1030 // BUILTIN_INFO(HEXAGON.A4_cmpbgt,QI_ftype_SISI,2)
1031 //
1032 def int_hexagon_A4_cmpbgt :
1033 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgt">;
1034 //
1035 // BUILTIN_INFO(HEXAGON.A4_cmpbgti,QI_ftype_SISI,2)
1036 //
1037 def int_hexagon_A4_cmpbgti :
1038 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgti">;
1039 //
1040 // BUILTIN_INFO(HEXAGON.A2_vcmpheq,QI_ftype_DIDI,2)
1041 //
1042 def int_hexagon_A2_vcmpheq :
1043 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpheq">;
1044 //
1045 // BUILTIN_INFO(HEXAGON.A2_vcmphgt,QI_ftype_DIDI,2)
1046 //
1047 def int_hexagon_A2_vcmphgt :
1048 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmphgt">;
1049 //
1050 // BUILTIN_INFO(HEXAGON.A2_vcmphgtu,QI_ftype_DIDI,2)
1051 //
1052 def int_hexagon_A2_vcmphgtu :
1053 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmphgtu">;
1054 //
1055 // BUILTIN_INFO(HEXAGON.A4_vcmpheqi,QI_ftype_DISI,2)
1056 //
1057 def int_hexagon_A4_vcmpheqi :
1058 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpheqi">;
1059 //
1060 // BUILTIN_INFO(HEXAGON.A4_vcmphgti,QI_ftype_DISI,2)
1061 //
1062 def int_hexagon_A4_vcmphgti :
1063 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmphgti">;
1064 //
1065 // BUILTIN_INFO(HEXAGON.A4_vcmphgtui,QI_ftype_DISI,2)
1066 //
1067 def int_hexagon_A4_vcmphgtui :
1068 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmphgtui">;
1069 //
1070 // BUILTIN_INFO(HEXAGON.A4_cmpheq,QI_ftype_SISI,2)
1071 //
1072 def int_hexagon_A4_cmpheq :
1073 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpheq">;
1074 //
1075 // BUILTIN_INFO(HEXAGON.A4_cmphgt,QI_ftype_SISI,2)
1076 //
1077 def int_hexagon_A4_cmphgt :
1078 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgt">;
1079 //
1080 // BUILTIN_INFO(HEXAGON.A4_cmphgtu,QI_ftype_SISI,2)
1081 //
1082 def int_hexagon_A4_cmphgtu :
1083 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgtu">;
1084 //
1085 // BUILTIN_INFO(HEXAGON.A4_cmpheqi,QI_ftype_SISI,2)
1086 //
1087 def int_hexagon_A4_cmpheqi :
1088 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpheqi">;
1089 //
1090 // BUILTIN_INFO(HEXAGON.A4_cmphgti,QI_ftype_SISI,2)
1091 //
1092 def int_hexagon_A4_cmphgti :
1093 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgti">;
1094 //
1095 // BUILTIN_INFO(HEXAGON.A4_cmphgtui,QI_ftype_SISI,2)
1096 //
1097 def int_hexagon_A4_cmphgtui :
1098 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgtui">;
1099 //
1100 // BUILTIN_INFO(HEXAGON.A2_vcmpweq,QI_ftype_DIDI,2)
1101 //
1102 def int_hexagon_A2_vcmpweq :
1103 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpweq">;
1104 //
1105 // BUILTIN_INFO(HEXAGON.A2_vcmpwgt,QI_ftype_DIDI,2)
1106 //
1107 def int_hexagon_A2_vcmpwgt :
1108 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpwgt">;
1109 //
1110 // BUILTIN_INFO(HEXAGON.A2_vcmpwgtu,QI_ftype_DIDI,2)
1111 //
1112 def int_hexagon_A2_vcmpwgtu :
1113 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpwgtu">;
1114 //
1115 // BUILTIN_INFO(HEXAGON.A4_vcmpweqi,QI_ftype_DISI,2)
1116 //
1117 def int_hexagon_A4_vcmpweqi :
1118 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpweqi">;
1119 //
1120 // BUILTIN_INFO(HEXAGON.A4_vcmpwgti,QI_ftype_DISI,2)
1121 //
1122 def int_hexagon_A4_vcmpwgti :
1123 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpwgti">;
1124 //
1125 // BUILTIN_INFO(HEXAGON.A4_vcmpwgtui,QI_ftype_DISI,2)
1126 //
1127 def int_hexagon_A4_vcmpwgtui :
1128 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpwgtui">;
1129 //
1130 // BUILTIN_INFO(HEXAGON.A4_boundscheck,QI_ftype_SIDI,2)
1131 //
1132 def int_hexagon_A4_boundscheck :
1133 Hexagon_si_sidi_Intrinsic<"HEXAGON_A4_boundscheck">;
1134 //
1135 // BUILTIN_INFO(HEXAGON.A4_tlbmatch,QI_ftype_DISI,2)
1136 //
1137 def int_hexagon_A4_tlbmatch :
1138 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_tlbmatch">;
1139 //
1140 // BUILTIN_INFO(HEXAGON.C2_tfrpr,SI_ftype_QI,1)
1141 //
1142 def int_hexagon_C2_tfrpr :
1143 Hexagon_si_qi_Intrinsic<"HEXAGON_C2_tfrpr">;
1144 //
1145 // BUILTIN_INFO(HEXAGON.C2_tfrrp,QI_ftype_SI,1)
1146 //
1147 def int_hexagon_C2_tfrrp :
1148 Hexagon_si_si_Intrinsic<"HEXAGON_C2_tfrrp">;
1149 //
1150 // BUILTIN_INFO(HEXAGON.C4_fastcorner9,QI_ftype_QIQI,2)
1151 //
1152 def int_hexagon_C4_fastcorner9 :
1153 Hexagon_si_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9">;
1154 //
1155 // BUILTIN_INFO(HEXAGON.C4_fastcorner9_not,QI_ftype_QIQI,2)
1156 //
1157 def int_hexagon_C4_fastcorner9_not :
1158 Hexagon_si_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9_not">;
1159 //
1160 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s0,SI_ftype_SISISI,3)
1161 //
1162 def int_hexagon_M2_mpy_acc_hh_s0 :
1163 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;
1164 //
1165 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s1,SI_ftype_SISISI,3)
1166 //
1167 def int_hexagon_M2_mpy_acc_hh_s1 :
1168 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;
1169 //
1170 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s0,SI_ftype_SISISI,3)
1171 //
1172 def int_hexagon_M2_mpy_acc_hl_s0 :
1173 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;
1174 //
1175 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s1,SI_ftype_SISISI,3)
1176 //
1177 def int_hexagon_M2_mpy_acc_hl_s1 :
1178 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;
1179 //
1180 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s0,SI_ftype_SISISI,3)
1181 //
1182 def int_hexagon_M2_mpy_acc_lh_s0 :
1183 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;
1184 //
1185 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s1,SI_ftype_SISISI,3)
1186 //
1187 def int_hexagon_M2_mpy_acc_lh_s1 :
1188 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;
1189 //
1190 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s0,SI_ftype_SISISI,3)
1191 //
1192 def int_hexagon_M2_mpy_acc_ll_s0 :
1193 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;
1194 //
1195 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s1,SI_ftype_SISISI,3)
1196 //
1197 def int_hexagon_M2_mpy_acc_ll_s1 :
1198 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;
1199 //
1200 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s0,SI_ftype_SISISI,3)
1201 //
1202 def int_hexagon_M2_mpy_nac_hh_s0 :
1203 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;
1204 //
1205 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s1,SI_ftype_SISISI,3)
1206 //
1207 def int_hexagon_M2_mpy_nac_hh_s1 :
1208 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;
1209 //
1210 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s0,SI_ftype_SISISI,3)
1211 //
1212 def int_hexagon_M2_mpy_nac_hl_s0 :
1213 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;
1214 //
1215 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s1,SI_ftype_SISISI,3)
1216 //
1217 def int_hexagon_M2_mpy_nac_hl_s1 :
1218 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;
1219 //
1220 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s0,SI_ftype_SISISI,3)
1221 //
1222 def int_hexagon_M2_mpy_nac_lh_s0 :
1223 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">;
1224 //
1225 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s1,SI_ftype_SISISI,3)
1226 //
1227 def int_hexagon_M2_mpy_nac_lh_s1 :
1228 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">;
1229 //
1230 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s0,SI_ftype_SISISI,3)
1231 //
1232 def int_hexagon_M2_mpy_nac_ll_s0 :
1233 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">;
1234 //
1235 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s1,SI_ftype_SISISI,3)
1236 //
1237 def int_hexagon_M2_mpy_nac_ll_s1 :
1238 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">;
1239 //
1240 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s0,SI_ftype_SISISI,3)
1241 //
1242 def int_hexagon_M2_mpy_acc_sat_hh_s0 :
1243 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;
1244 //
1245 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s1,SI_ftype_SISISI,3)
1246 //
1247 def int_hexagon_M2_mpy_acc_sat_hh_s1 :
1248 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;
1249 //
1250 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s0,SI_ftype_SISISI,3)
1251 //
1252 def int_hexagon_M2_mpy_acc_sat_hl_s0 :
1253 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;
1254 //
1255 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s1,SI_ftype_SISISI,3)
1256 //
1257 def int_hexagon_M2_mpy_acc_sat_hl_s1 :
1258 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;
1259 //
1260 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s0,SI_ftype_SISISI,3)
1261 //
1262 def int_hexagon_M2_mpy_acc_sat_lh_s0 :
1263 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;
1264 //
1265 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s1,SI_ftype_SISISI,3)
1266 //
1267 def int_hexagon_M2_mpy_acc_sat_lh_s1 :
1268 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;
1269 //
1270 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s0,SI_ftype_SISISI,3)
1271 //
1272 def int_hexagon_M2_mpy_acc_sat_ll_s0 :
1273 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">;
1274 //
1275 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s1,SI_ftype_SISISI,3)
1276 //
1277 def int_hexagon_M2_mpy_acc_sat_ll_s1 :
1278 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">;
1279 //
1280 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s0,SI_ftype_SISISI,3)
1281 //
1282 def int_hexagon_M2_mpy_nac_sat_hh_s0 :
1283 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;
1284 //
1285 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s1,SI_ftype_SISISI,3)
1286 //
1287 def int_hexagon_M2_mpy_nac_sat_hh_s1 :
1288 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;
1289 //
1290 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s0,SI_ftype_SISISI,3)
1291 //
1292 def int_hexagon_M2_mpy_nac_sat_hl_s0 :
1293 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;
1294 //
1295 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s1,SI_ftype_SISISI,3)
1296 //
1297 def int_hexagon_M2_mpy_nac_sat_hl_s1 :
1298 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;
1299 //
1300 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s0,SI_ftype_SISISI,3)
1301 //
1302 def int_hexagon_M2_mpy_nac_sat_lh_s0 :
1303 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;
1304 //
1305 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s1,SI_ftype_SISISI,3)
1306 //
1307 def int_hexagon_M2_mpy_nac_sat_lh_s1 :
1308 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;
1309 //
1310 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s0,SI_ftype_SISISI,3)
1311 //
1312 def int_hexagon_M2_mpy_nac_sat_ll_s0 :
1313 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;
1314 //
1315 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s1,SI_ftype_SISISI,3)
1316 //
1317 def int_hexagon_M2_mpy_nac_sat_ll_s1 :
1318 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;
1319 //
1320 // BUILTIN_INFO(HEXAGON.M2_mpy_hh_s0,SI_ftype_SISI,2)
1321 //
1322 def int_hexagon_M2_mpy_hh_s0 :
1323 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;
1324 //
1325 // BUILTIN_INFO(HEXAGON.M2_mpy_hh_s1,SI_ftype_SISI,2)
1326 //
1327 def int_hexagon_M2_mpy_hh_s1 :
1328 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;
1329 //
1330 // BUILTIN_INFO(HEXAGON.M2_mpy_hl_s0,SI_ftype_SISI,2)
1331 //
1332 def int_hexagon_M2_mpy_hl_s0 :
1333 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;
1334 //
1335 // BUILTIN_INFO(HEXAGON.M2_mpy_hl_s1,SI_ftype_SISI,2)
1336 //
1337 def int_hexagon_M2_mpy_hl_s1 :
1338 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;
1339 //
1340 // BUILTIN_INFO(HEXAGON.M2_mpy_lh_s0,SI_ftype_SISI,2)
1341 //
1342 def int_hexagon_M2_mpy_lh_s0 :
1343 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;
1344 //
1345 // BUILTIN_INFO(HEXAGON.M2_mpy_lh_s1,SI_ftype_SISI,2)
1346 //
1347 def int_hexagon_M2_mpy_lh_s1 :
1348 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;
1349 //
1350 // BUILTIN_INFO(HEXAGON.M2_mpy_ll_s0,SI_ftype_SISI,2)
1351 //
1352 def int_hexagon_M2_mpy_ll_s0 :
1353 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;
1354 //
1355 // BUILTIN_INFO(HEXAGON.M2_mpy_ll_s1,SI_ftype_SISI,2)
1356 //
1357 def int_hexagon_M2_mpy_ll_s1 :
1358 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;
1359 //
1360 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s0,SI_ftype_SISI,2)
1361 //
1362 def int_hexagon_M2_mpy_sat_hh_s0 :
1363 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;
1364 //
1365 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s1,SI_ftype_SISI,2)
1366 //
1367 def int_hexagon_M2_mpy_sat_hh_s1 :
1368 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;
1369 //
1370 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s0,SI_ftype_SISI,2)
1371 //
1372 def int_hexagon_M2_mpy_sat_hl_s0 :
1373 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;
1374 //
1375 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s1,SI_ftype_SISI,2)
1376 //
1377 def int_hexagon_M2_mpy_sat_hl_s1 :
1378 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;
1379 //
1380 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s0,SI_ftype_SISI,2)
1381 //
1382 def int_hexagon_M2_mpy_sat_lh_s0 :
1383 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">;
1384 //
1385 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s1,SI_ftype_SISI,2)
1386 //
1387 def int_hexagon_M2_mpy_sat_lh_s1 :
1388 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;
1389 //
1390 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s0,SI_ftype_SISI,2)
1391 //
1392 def int_hexagon_M2_mpy_sat_ll_s0 :
1393 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;
1394 //
1395 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s1,SI_ftype_SISI,2)
1396 //
1397 def int_hexagon_M2_mpy_sat_ll_s1 :
1398 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;
1399 //
1400 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s0,SI_ftype_SISI,2)
1401 //
1402 def int_hexagon_M2_mpy_rnd_hh_s0 :
1403 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;
1404 //
1405 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s1,SI_ftype_SISI,2)
1406 //
1407 def int_hexagon_M2_mpy_rnd_hh_s1 :
1408 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;
1409 //
1410 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s0,SI_ftype_SISI,2)
1411 //
1412 def int_hexagon_M2_mpy_rnd_hl_s0 :
1413 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;
1414 //
1415 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s1,SI_ftype_SISI,2)
1416 //
1417 def int_hexagon_M2_mpy_rnd_hl_s1 :
1418 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;
1419 //
1420 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s0,SI_ftype_SISI,2)
1421 //
1422 def int_hexagon_M2_mpy_rnd_lh_s0 :
1423 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;
1424 //
1425 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s1,SI_ftype_SISI,2)
1426 //
1427 def int_hexagon_M2_mpy_rnd_lh_s1 :
1428 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;
1429 //
1430 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s0,SI_ftype_SISI,2)
1431 //
1432 def int_hexagon_M2_mpy_rnd_ll_s0 :
1433 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;
1434 //
1435 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s1,SI_ftype_SISI,2)
1436 //
1437 def int_hexagon_M2_mpy_rnd_ll_s1 :
1438 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;
1439 //
1440 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s0,SI_ftype_SISI,2)
1441 //
1442 def int_hexagon_M2_mpy_sat_rnd_hh_s0 :
1443 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;
1444 //
1445 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s1,SI_ftype_SISI,2)
1446 //
1447 def int_hexagon_M2_mpy_sat_rnd_hh_s1 :
1448 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;
1449 //
1450 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s0,SI_ftype_SISI,2)
1451 //
1452 def int_hexagon_M2_mpy_sat_rnd_hl_s0 :
1453 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;
1454 //
1455 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s1,SI_ftype_SISI,2)
1456 //
1457 def int_hexagon_M2_mpy_sat_rnd_hl_s1 :
1458 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;
1459 //
1460 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s0,SI_ftype_SISI,2)
1461 //
1462 def int_hexagon_M2_mpy_sat_rnd_lh_s0 :
1463 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;
1464 //
1465 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s1,SI_ftype_SISI,2)
1466 //
1467 def int_hexagon_M2_mpy_sat_rnd_lh_s1 :
1468 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;
1469 //
1470 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s0,SI_ftype_SISI,2)
1471 //
1472 def int_hexagon_M2_mpy_sat_rnd_ll_s0 :
1473 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;
1474 //
1475 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s1,SI_ftype_SISI,2)
1476 //
1477 def int_hexagon_M2_mpy_sat_rnd_ll_s1 :
1478 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;
1479 //
1480 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s0,DI_ftype_DISISI,3)
1481 //
1482 def int_hexagon_M2_mpyd_acc_hh_s0 :
1483 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;
1484 //
1485 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s1,DI_ftype_DISISI,3)
1486 //
1487 def int_hexagon_M2_mpyd_acc_hh_s1 :
1488 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;
1489 //
1490 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s0,DI_ftype_DISISI,3)
1491 //
1492 def int_hexagon_M2_mpyd_acc_hl_s0 :
1493 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;
1494 //
1495 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s1,DI_ftype_DISISI,3)
1496 //
1497 def int_hexagon_M2_mpyd_acc_hl_s1 :
1498 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;
1499 //
1500 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s0,DI_ftype_DISISI,3)
1501 //
1502 def int_hexagon_M2_mpyd_acc_lh_s0 :
1503 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;
1504 //
1505 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s1,DI_ftype_DISISI,3)
1506 //
1507 def int_hexagon_M2_mpyd_acc_lh_s1 :
1508 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;
1509 //
1510 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s0,DI_ftype_DISISI,3)
1511 //
1512 def int_hexagon_M2_mpyd_acc_ll_s0 :
1513 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;
1514 //
1515 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s1,DI_ftype_DISISI,3)
1516 //
1517 def int_hexagon_M2_mpyd_acc_ll_s1 :
1518 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;
1519 //
1520 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s0,DI_ftype_DISISI,3)
1521 //
1522 def int_hexagon_M2_mpyd_nac_hh_s0 :
1523 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;
1524 //
1525 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s1,DI_ftype_DISISI,3)
1526 //
1527 def int_hexagon_M2_mpyd_nac_hh_s1 :
1528 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;
1529 //
1530 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s0,DI_ftype_DISISI,3)
1531 //
1532 def int_hexagon_M2_mpyd_nac_hl_s0 :
1533 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">;
1534 //
1535 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s1,DI_ftype_DISISI,3)
1536 //
1537 def int_hexagon_M2_mpyd_nac_hl_s1 :
1538 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">;
1539 //
1540 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s0,DI_ftype_DISISI,3)
1541 //
1542 def int_hexagon_M2_mpyd_nac_lh_s0 :
1543 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;
1544 //
1545 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s1,DI_ftype_DISISI,3)
1546 //
1547 def int_hexagon_M2_mpyd_nac_lh_s1 :
1548 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;
1549 //
1550 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s0,DI_ftype_DISISI,3)
1551 //
1552 def int_hexagon_M2_mpyd_nac_ll_s0 :
1553 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;
1554 //
1555 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s1,DI_ftype_DISISI,3)
1556 //
1557 def int_hexagon_M2_mpyd_nac_ll_s1 :
1558 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;
1559 //
1560 // BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s0,DI_ftype_SISI,2)
1561 //
1562 def int_hexagon_M2_mpyd_hh_s0 :
1563 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;
1564 //
1565 // BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s1,DI_ftype_SISI,2)
1566 //
1567 def int_hexagon_M2_mpyd_hh_s1 :
1568 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;
1569 //
1570 // BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s0,DI_ftype_SISI,2)
1571 //
1572 def int_hexagon_M2_mpyd_hl_s0 :
1573 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;
1574 //
1575 // BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s1,DI_ftype_SISI,2)
1576 //
1577 def int_hexagon_M2_mpyd_hl_s1 :
1578 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;
1579 //
1580 // BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s0,DI_ftype_SISI,2)
1581 //
1582 def int_hexagon_M2_mpyd_lh_s0 :
1583 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;
1584 //
1585 // BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s1,DI_ftype_SISI,2)
1586 //
1587 def int_hexagon_M2_mpyd_lh_s1 :
1588 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;
1589 //
1590 // BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s0,DI_ftype_SISI,2)
1591 //
1592 def int_hexagon_M2_mpyd_ll_s0 :
1593 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;
1594 //
1595 // BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s1,DI_ftype_SISI,2)
1596 //
1597 def int_hexagon_M2_mpyd_ll_s1 :
1598 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;
1599 //
1600 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s0,DI_ftype_SISI,2)
1601 //
1602 def int_hexagon_M2_mpyd_rnd_hh_s0 :
1603 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">;
1604 //
1605 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s1,DI_ftype_SISI,2)
1606 //
1607 def int_hexagon_M2_mpyd_rnd_hh_s1 :
1608 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;
1609 //
1610 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s0,DI_ftype_SISI,2)
1611 //
1612 def int_hexagon_M2_mpyd_rnd_hl_s0 :
1613 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">;
1614 //
1615 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s1,DI_ftype_SISI,2)
1616 //
1617 def int_hexagon_M2_mpyd_rnd_hl_s1 :
1618 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">;
1619 //
1620 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s0,DI_ftype_SISI,2)
1621 //
1622 def int_hexagon_M2_mpyd_rnd_lh_s0 :
1623 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;
1624 //
1625 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s1,DI_ftype_SISI,2)
1626 //
1627 def int_hexagon_M2_mpyd_rnd_lh_s1 :
1628 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;
1629 //
1630 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s0,DI_ftype_SISI,2)
1631 //
1632 def int_hexagon_M2_mpyd_rnd_ll_s0 :
1633 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;
1634 //
1635 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s1,DI_ftype_SISI,2)
1636 //
1637 def int_hexagon_M2_mpyd_rnd_ll_s1 :
1638 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;
1639 //
1640 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s0,SI_ftype_SISISI,3)
1641 //
1642 def int_hexagon_M2_mpyu_acc_hh_s0 :
1643 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;
1644 //
1645 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s1,SI_ftype_SISISI,3)
1646 //
1647 def int_hexagon_M2_mpyu_acc_hh_s1 :
1648 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;
1649 //
1650 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s0,SI_ftype_SISISI,3)
1651 //
1652 def int_hexagon_M2_mpyu_acc_hl_s0 :
1653 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">;
1654 //
1655 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s1,SI_ftype_SISISI,3)
1656 //
1657 def int_hexagon_M2_mpyu_acc_hl_s1 :
1658 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">;
1659 //
1660 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s0,SI_ftype_SISISI,3)
1661 //
1662 def int_hexagon_M2_mpyu_acc_lh_s0 :
1663 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;
1664 //
1665 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s1,SI_ftype_SISISI,3)
1666 //
1667 def int_hexagon_M2_mpyu_acc_lh_s1 :
1668 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;
1669 //
1670 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s0,SI_ftype_SISISI,3)
1671 //
1672 def int_hexagon_M2_mpyu_acc_ll_s0 :
1673 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">;
1674 //
1675 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s1,SI_ftype_SISISI,3)
1676 //
1677 def int_hexagon_M2_mpyu_acc_ll_s1 :
1678 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;
1679 //
1680 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s0,SI_ftype_SISISI,3)
1681 //
1682 def int_hexagon_M2_mpyu_nac_hh_s0 :
1683 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;
1684 //
1685 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s1,SI_ftype_SISISI,3)
1686 //
1687 def int_hexagon_M2_mpyu_nac_hh_s1 :
1688 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;
1689 //
1690 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s0,SI_ftype_SISISI,3)
1691 //
1692 def int_hexagon_M2_mpyu_nac_hl_s0 :
1693 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;
1694 //
1695 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s1,SI_ftype_SISISI,3)
1696 //
1697 def int_hexagon_M2_mpyu_nac_hl_s1 :
1698 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;
1699 //
1700 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s0,SI_ftype_SISISI,3)
1701 //
1702 def int_hexagon_M2_mpyu_nac_lh_s0 :
1703 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;
1704 //
1705 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s1,SI_ftype_SISISI,3)
1706 //
1707 def int_hexagon_M2_mpyu_nac_lh_s1 :
1708 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;
1709 //
1710 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s0,SI_ftype_SISISI,3)
1711 //
1712 def int_hexagon_M2_mpyu_nac_ll_s0 :
1713 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;
1714 //
1715 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s1,SI_ftype_SISISI,3)
1716 //
1717 def int_hexagon_M2_mpyu_nac_ll_s1 :
1718 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;
1719 //
1720 // BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s0,USI_ftype_SISI,2)
1721 //
1722 def int_hexagon_M2_mpyu_hh_s0 :
1723 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;
1724 //
1725 // BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s1,USI_ftype_SISI,2)
1726 //
1727 def int_hexagon_M2_mpyu_hh_s1 :
1728 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;
1729 //
1730 // BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s0,USI_ftype_SISI,2)
1731 //
1732 def int_hexagon_M2_mpyu_hl_s0 :
1733 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;
1734 //
1735 // BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s1,USI_ftype_SISI,2)
1736 //
1737 def int_hexagon_M2_mpyu_hl_s1 :
1738 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;
1739 //
1740 // BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s0,USI_ftype_SISI,2)
1741 //
1742 def int_hexagon_M2_mpyu_lh_s0 :
1743 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;
1744 //
1745 // BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s1,USI_ftype_SISI,2)
1746 //
1747 def int_hexagon_M2_mpyu_lh_s1 :
1748 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;
1749 //
1750 // BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s0,USI_ftype_SISI,2)
1751 //
1752 def int_hexagon_M2_mpyu_ll_s0 :
1753 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;
1754 //
1755 // BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s1,USI_ftype_SISI,2)
1756 //
1757 def int_hexagon_M2_mpyu_ll_s1 :
1758 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;
1759 //
1760 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s0,DI_ftype_DISISI,3)
1761 //
1762 def int_hexagon_M2_mpyud_acc_hh_s0 :
1763 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;
1764 //
1765 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s1,DI_ftype_DISISI,3)
1766 //
1767 def int_hexagon_M2_mpyud_acc_hh_s1 :
1768 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;
1769 //
1770 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s0,DI_ftype_DISISI,3)
1771 //
1772 def int_hexagon_M2_mpyud_acc_hl_s0 :
1773 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;
1774 //
1775 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s1,DI_ftype_DISISI,3)
1776 //
1777 def int_hexagon_M2_mpyud_acc_hl_s1 :
1778 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;
1779 //
1780 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s0,DI_ftype_DISISI,3)
1781 //
1782 def int_hexagon_M2_mpyud_acc_lh_s0 :
1783 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;
1784 //
1785 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s1,DI_ftype_DISISI,3)
1786 //
1787 def int_hexagon_M2_mpyud_acc_lh_s1 :
1788 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;
1789 //
1790 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s0,DI_ftype_DISISI,3)
1791 //
1792 def int_hexagon_M2_mpyud_acc_ll_s0 :
1793 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;
1794 //
1795 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s1,DI_ftype_DISISI,3)
1796 //
1797 def int_hexagon_M2_mpyud_acc_ll_s1 :
1798 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;
1799 //
1800 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s0,DI_ftype_DISISI,3)
1801 //
1802 def int_hexagon_M2_mpyud_nac_hh_s0 :
1803 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;
1804 //
1805 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s1,DI_ftype_DISISI,3)
1806 //
1807 def int_hexagon_M2_mpyud_nac_hh_s1 :
1808 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;
1809 //
1810 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s0,DI_ftype_DISISI,3)
1811 //
1812 def int_hexagon_M2_mpyud_nac_hl_s0 :
1813 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;
1814 //
1815 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s1,DI_ftype_DISISI,3)
1816 //
1817 def int_hexagon_M2_mpyud_nac_hl_s1 :
1818 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;
1819 //
1820 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s0,DI_ftype_DISISI,3)
1821 //
1822 def int_hexagon_M2_mpyud_nac_lh_s0 :
1823 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;
1824 //
1825 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s1,DI_ftype_DISISI,3)
1826 //
1827 def int_hexagon_M2_mpyud_nac_lh_s1 :
1828 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;
1829 //
1830 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s0,DI_ftype_DISISI,3)
1831 //
1832 def int_hexagon_M2_mpyud_nac_ll_s0 :
1833 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">;
1834 //
1835 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s1,DI_ftype_DISISI,3)
1836 //
1837 def int_hexagon_M2_mpyud_nac_ll_s1 :
1838 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">;
1839 //
1840 // BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s0,UDI_ftype_SISI,2)
1841 //
1842 def int_hexagon_M2_mpyud_hh_s0 :
1843 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;
1844 //
1845 // BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s1,UDI_ftype_SISI,2)
1846 //
1847 def int_hexagon_M2_mpyud_hh_s1 :
1848 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">;
1849 //
1850 // BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s0,UDI_ftype_SISI,2)
1851 //
1852 def int_hexagon_M2_mpyud_hl_s0 :
1853 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;
1854 //
1855 // BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s1,UDI_ftype_SISI,2)
1856 //
1857 def int_hexagon_M2_mpyud_hl_s1 :
1858 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;
1859 //
1860 // BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s0,UDI_ftype_SISI,2)
1861 //
1862 def int_hexagon_M2_mpyud_lh_s0 :
1863 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">;
1864 //
1865 // BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s1,UDI_ftype_SISI,2)
1866 //
1867 def int_hexagon_M2_mpyud_lh_s1 :
1868 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;
1869 //
1870 // BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s0,UDI_ftype_SISI,2)
1871 //
1872 def int_hexagon_M2_mpyud_ll_s0 :
1873 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">;
1874 //
1875 // BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s1,UDI_ftype_SISI,2)
1876 //
1877 def int_hexagon_M2_mpyud_ll_s1 :
1878 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">;
1879 //
1880 // BUILTIN_INFO(HEXAGON.M2_mpysmi,SI_ftype_SISI,2)
1881 //
1882 def int_hexagon_M2_mpysmi :
1883 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpysmi">;
1884 //
1885 // BUILTIN_INFO(HEXAGON.M2_macsip,SI_ftype_SISISI,3)
1886 //
1887 def int_hexagon_M2_macsip :
1888 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_macsip">;
1889 //
1890 // BUILTIN_INFO(HEXAGON.M2_macsin,SI_ftype_SISISI,3)
1891 //
1892 def int_hexagon_M2_macsin :
1893 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_macsin">;
1894 //
1895 // BUILTIN_INFO(HEXAGON.M2_dpmpyss_s0,DI_ftype_SISI,2)
1896 //
1897 def int_hexagon_M2_dpmpyss_s0 :
1898 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;
1899 //
1900 // BUILTIN_INFO(HEXAGON.M2_dpmpyss_acc_s0,DI_ftype_DISISI,3)
1901 //
1902 def int_hexagon_M2_dpmpyss_acc_s0 :
1903 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;
1904 //
1905 // BUILTIN_INFO(HEXAGON.M2_dpmpyss_nac_s0,DI_ftype_DISISI,3)
1906 //
1907 def int_hexagon_M2_dpmpyss_nac_s0 :
1908 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;
1909 //
1910 // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_s0,UDI_ftype_SISI,2)
1911 //
1912 def int_hexagon_M2_dpmpyuu_s0 :
1913 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">;
1914 //
1915 // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_acc_s0,DI_ftype_DISISI,3)
1916 //
1917 def int_hexagon_M2_dpmpyuu_acc_s0 :
1918 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;
1919 //
1920 // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_nac_s0,DI_ftype_DISISI,3)
1921 //
1922 def int_hexagon_M2_dpmpyuu_nac_s0 :
1923 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;
1924 //
1925 // BUILTIN_INFO(HEXAGON.M2_mpy_up,SI_ftype_SISI,2)
1926 //
1927 def int_hexagon_M2_mpy_up :
1928 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up">;
1929 //
1930 // BUILTIN_INFO(HEXAGON.M2_mpy_up_s1,SI_ftype_SISI,2)
1931 //
1932 def int_hexagon_M2_mpy_up_s1 :
1933 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up_s1">;
1934 //
1935 // BUILTIN_INFO(HEXAGON.M2_mpy_up_s1_sat,SI_ftype_SISI,2)
1936 //
1937 def int_hexagon_M2_mpy_up_s1_sat :
1938 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;
1939 //
1940 // BUILTIN_INFO(HEXAGON.M2_mpyu_up,USI_ftype_SISI,2)
1941 //
1942 def int_hexagon_M2_mpyu_up :
1943 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_up">;
1944 //
1945 // BUILTIN_INFO(HEXAGON.M2_mpysu_up,SI_ftype_SISI,2)
1946 //
1947 def int_hexagon_M2_mpysu_up :
1948 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpysu_up">;
1949 //
1950 // BUILTIN_INFO(HEXAGON.M2_dpmpyss_rnd_s0,SI_ftype_SISI,2)
1951 //
1952 def int_hexagon_M2_dpmpyss_rnd_s0 :
1953 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;
1954 //
1955 // BUILTIN_INFO(HEXAGON.M4_mac_up_s1_sat,SI_ftype_SISISI,3)
1956 //
1957 def int_hexagon_M4_mac_up_s1_sat :
1958 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;
1959 //
1960 // BUILTIN_INFO(HEXAGON.M4_nac_up_s1_sat,SI_ftype_SISISI,3)
1961 //
1962 def int_hexagon_M4_nac_up_s1_sat :
1963 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">;
1964 //
1965 // BUILTIN_INFO(HEXAGON.M2_mpyi,SI_ftype_SISI,2)
1966 //
1967 def int_hexagon_M2_mpyi :
1968 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyi">;
1969 //
1970 // BUILTIN_INFO(HEXAGON.M2_mpyui,SI_ftype_SISI,2)
1971 //
1972 def int_hexagon_M2_mpyui :
1973 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyui">;
1974 //
1975 // BUILTIN_INFO(HEXAGON.M2_maci,SI_ftype_SISISI,3)
1976 //
1977 def int_hexagon_M2_maci :
1978 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_maci">;
1979 //
1980 // BUILTIN_INFO(HEXAGON.M2_acci,SI_ftype_SISISI,3)
1981 //
1982 def int_hexagon_M2_acci :
1983 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_acci">;
1984 //
1985 // BUILTIN_INFO(HEXAGON.M2_accii,SI_ftype_SISISI,3)
1986 //
1987 def int_hexagon_M2_accii :
1988 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_accii">;
1989 //
1990 // BUILTIN_INFO(HEXAGON.M2_nacci,SI_ftype_SISISI,3)
1991 //
1992 def int_hexagon_M2_nacci :
1993 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_nacci">;
1994 //
1995 // BUILTIN_INFO(HEXAGON.M2_naccii,SI_ftype_SISISI,3)
1996 //
1997 def int_hexagon_M2_naccii :
1998 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_naccii">;
1999 //
2000 // BUILTIN_INFO(HEXAGON.M2_subacc,SI_ftype_SISISI,3)
2001 //
2002 def int_hexagon_M2_subacc :
2003 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_subacc">;
2004 //
2005 // BUILTIN_INFO(HEXAGON.M4_mpyrr_addr,SI_ftype_SISISI,3)
2006 //
2007 def int_hexagon_M4_mpyrr_addr :
2008 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyrr_addr">;
2009 //
2010 // BUILTIN_INFO(HEXAGON.M4_mpyri_addr_u2,SI_ftype_SISISI,3)
2011 //
2012 def int_hexagon_M4_mpyri_addr_u2 :
2013 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addr_u2">;
2014 //
2015 // BUILTIN_INFO(HEXAGON.M4_mpyri_addr,SI_ftype_SISISI,3)
2016 //
2017 def int_hexagon_M4_mpyri_addr :
2018 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addr">;
2019 //
2020 // BUILTIN_INFO(HEXAGON.M4_mpyri_addi,SI_ftype_SISISI,3)
2021 //
2022 def int_hexagon_M4_mpyri_addi :
2023 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addi">;
2024 //
2025 // BUILTIN_INFO(HEXAGON.M4_mpyrr_addi,SI_ftype_SISISI,3)
2026 //
2027 def int_hexagon_M4_mpyrr_addi :
2028 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyrr_addi">;
2029 //
2030 // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0,DI_ftype_SISI,2)
2031 //
2032 def int_hexagon_M2_vmpy2s_s0 :
2033 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;
2034 //
2035 // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1,DI_ftype_SISI,2)
2036 //
2037 def int_hexagon_M2_vmpy2s_s1 :
2038 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;
2039 //
2040 // BUILTIN_INFO(HEXAGON.M2_vmac2s_s0,DI_ftype_DISISI,3)
2041 //
2042 def int_hexagon_M2_vmac2s_s0 :
2043 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2s_s0">;
2044 //
2045 // BUILTIN_INFO(HEXAGON.M2_vmac2s_s1,DI_ftype_DISISI,3)
2046 //
2047 def int_hexagon_M2_vmac2s_s1 :
2048 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2s_s1">;
2049 //
2050 // BUILTIN_INFO(HEXAGON.M2_vmpy2su_s0,DI_ftype_SISI,2)
2051 //
2052 def int_hexagon_M2_vmpy2su_s0 :
2053 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;
2054 //
2055 // BUILTIN_INFO(HEXAGON.M2_vmpy2su_s1,DI_ftype_SISI,2)
2056 //
2057 def int_hexagon_M2_vmpy2su_s1 :
2058 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;
2059 //
2060 // BUILTIN_INFO(HEXAGON.M2_vmac2su_s0,DI_ftype_DISISI,3)
2061 //
2062 def int_hexagon_M2_vmac2su_s0 :
2063 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2su_s0">;
2064 //
2065 // BUILTIN_INFO(HEXAGON.M2_vmac2su_s1,DI_ftype_DISISI,3)
2066 //
2067 def int_hexagon_M2_vmac2su_s1 :
2068 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2su_s1">;
2069 //
2070 // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0pack,SI_ftype_SISI,2)
2071 //
2072 def int_hexagon_M2_vmpy2s_s0pack :
2073 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;
2074 //
2075 // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1pack,SI_ftype_SISI,2)
2076 //
2077 def int_hexagon_M2_vmpy2s_s1pack :
2078 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;
2079 //
2080 // BUILTIN_INFO(HEXAGON.M2_vmac2,DI_ftype_DISISI,3)
2081 //
2082 def int_hexagon_M2_vmac2 :
2083 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2">;
2084 //
2085 // BUILTIN_INFO(HEXAGON.M2_vmpy2es_s0,DI_ftype_DIDI,2)
2086 //
2087 def int_hexagon_M2_vmpy2es_s0 :
2088 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vmpy2es_s0">;
2089 //
2090 // BUILTIN_INFO(HEXAGON.M2_vmpy2es_s1,DI_ftype_DIDI,2)
2091 //
2092 def int_hexagon_M2_vmpy2es_s1 :
2093 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vmpy2es_s1">;
2094 //
2095 // BUILTIN_INFO(HEXAGON.M2_vmac2es_s0,DI_ftype_DIDIDI,3)
2096 //
2097 def int_hexagon_M2_vmac2es_s0 :
2098 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es_s0">;
2099 //
2100 // BUILTIN_INFO(HEXAGON.M2_vmac2es_s1,DI_ftype_DIDIDI,3)
2101 //
2102 def int_hexagon_M2_vmac2es_s1 :
2103 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es_s1">;
2104 //
2105 // BUILTIN_INFO(HEXAGON.M2_vmac2es,DI_ftype_DIDIDI,3)
2106 //
2107 def int_hexagon_M2_vmac2es :
2108 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es">;
2109 //
2110 // BUILTIN_INFO(HEXAGON.M2_vrmac_s0,DI_ftype_DIDIDI,3)
2111 //
2112 def int_hexagon_M2_vrmac_s0 :
2113 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrmac_s0">;
2114 //
2115 // BUILTIN_INFO(HEXAGON.M2_vrmpy_s0,DI_ftype_DIDI,2)
2116 //
2117 def int_hexagon_M2_vrmpy_s0 :
2118 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrmpy_s0">;
2119 //
2120 // BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s0,SI_ftype_DIDI,2)
2121 //
2122 def int_hexagon_M2_vdmpyrs_s0 :
2123 Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;
2124 //
2125 // BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s1,SI_ftype_DIDI,2)
2126 //
2127 def int_hexagon_M2_vdmpyrs_s1 :
2128 Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;
2129 //
2130 // BUILTIN_INFO(HEXAGON.M5_vrmpybuu,DI_ftype_DIDI,2)
2131 //
2132 def int_hexagon_M5_vrmpybuu :
2133 Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vrmpybuu">;
2134 //
2135 // BUILTIN_INFO(HEXAGON.M5_vrmacbuu,DI_ftype_DIDIDI,3)
2136 //
2137 def int_hexagon_M5_vrmacbuu :
2138 Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vrmacbuu">;
2139 //
2140 // BUILTIN_INFO(HEXAGON.M5_vrmpybsu,DI_ftype_DIDI,2)
2141 //
2142 def int_hexagon_M5_vrmpybsu :
2143 Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vrmpybsu">;
2144 //
2145 // BUILTIN_INFO(HEXAGON.M5_vrmacbsu,DI_ftype_DIDIDI,3)
2146 //
2147 def int_hexagon_M5_vrmacbsu :
2148 Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vrmacbsu">;
2149 //
2150 // BUILTIN_INFO(HEXAGON.M5_vmpybuu,DI_ftype_SISI,2)
2151 //
2152 def int_hexagon_M5_vmpybuu :
2153 Hexagon_di_sisi_Intrinsic<"HEXAGON_M5_vmpybuu">;
2154 //
2155 // BUILTIN_INFO(HEXAGON.M5_vmpybsu,DI_ftype_SISI,2)
2156 //
2157 def int_hexagon_M5_vmpybsu :
2158 Hexagon_di_sisi_Intrinsic<"HEXAGON_M5_vmpybsu">;
2159 //
2160 // BUILTIN_INFO(HEXAGON.M5_vmacbuu,DI_ftype_DISISI,3)
2161 //
2162 def int_hexagon_M5_vmacbuu :
2163 Hexagon_di_disisi_Intrinsic<"HEXAGON_M5_vmacbuu">;
2164 //
2165 // BUILTIN_INFO(HEXAGON.M5_vmacbsu,DI_ftype_DISISI,3)
2166 //
2167 def int_hexagon_M5_vmacbsu :
2168 Hexagon_di_disisi_Intrinsic<"HEXAGON_M5_vmacbsu">;
2169 //
2170 // BUILTIN_INFO(HEXAGON.M5_vdmpybsu,DI_ftype_DIDI,2)
2171 //
2172 def int_hexagon_M5_vdmpybsu :
2173 Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vdmpybsu">;
2174 //
2175 // BUILTIN_INFO(HEXAGON.M5_vdmacbsu,DI_ftype_DIDIDI,3)
2176 //
2177 def int_hexagon_M5_vdmacbsu :
2178 Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vdmacbsu">;
2179 //
2180 // BUILTIN_INFO(HEXAGON.M2_vdmacs_s0,DI_ftype_DIDIDI,3)
2181 //
2182 def int_hexagon_M2_vdmacs_s0 :
2183 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vdmacs_s0">;
2184 //
2185 // BUILTIN_INFO(HEXAGON.M2_vdmacs_s1,DI_ftype_DIDIDI,3)
2186 //
2187 def int_hexagon_M2_vdmacs_s1 :
2188 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vdmacs_s1">;
2189 //
2190 // BUILTIN_INFO(HEXAGON.M2_vdmpys_s0,DI_ftype_DIDI,2)
2191 //
2192 def int_hexagon_M2_vdmpys_s0 :
2193 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vdmpys_s0">;
2194 //
2195 // BUILTIN_INFO(HEXAGON.M2_vdmpys_s1,DI_ftype_DIDI,2)
2196 //
2197 def int_hexagon_M2_vdmpys_s1 :
2198 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vdmpys_s1">;
2199 //
2200 // BUILTIN_INFO(HEXAGON.M2_cmpyrs_s0,SI_ftype_SISI,2)
2201 //
2202 def int_hexagon_M2_cmpyrs_s0 :
2203 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;
2204 //
2205 // BUILTIN_INFO(HEXAGON.M2_cmpyrs_s1,SI_ftype_SISI,2)
2206 //
2207 def int_hexagon_M2_cmpyrs_s1 :
2208 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;
2209 //
2210 // BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s0,SI_ftype_SISI,2)
2211 //
2212 def int_hexagon_M2_cmpyrsc_s0 :
2213 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;
2214 //
2215 // BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s1,SI_ftype_SISI,2)
2216 //
2217 def int_hexagon_M2_cmpyrsc_s1 :
2218 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;
2219 //
2220 // BUILTIN_INFO(HEXAGON.M2_cmacs_s0,DI_ftype_DISISI,3)
2221 //
2222 def int_hexagon_M2_cmacs_s0 :
2223 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacs_s0">;
2224 //
2225 // BUILTIN_INFO(HEXAGON.M2_cmacs_s1,DI_ftype_DISISI,3)
2226 //
2227 def int_hexagon_M2_cmacs_s1 :
2228 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacs_s1">;
2229 //
2230 // BUILTIN_INFO(HEXAGON.M2_cmacsc_s0,DI_ftype_DISISI,3)
2231 //
2232 def int_hexagon_M2_cmacsc_s0 :
2233 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacsc_s0">;
2234 //
2235 // BUILTIN_INFO(HEXAGON.M2_cmacsc_s1,DI_ftype_DISISI,3)
2236 //
2237 def int_hexagon_M2_cmacsc_s1 :
2238 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacsc_s1">;
2239 //
2240 // BUILTIN_INFO(HEXAGON.M2_cmpys_s0,DI_ftype_SISI,2)
2241 //
2242 def int_hexagon_M2_cmpys_s0 :
2243 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpys_s0">;
2244 //
2245 // BUILTIN_INFO(HEXAGON.M2_cmpys_s1,DI_ftype_SISI,2)
2246 //
2247 def int_hexagon_M2_cmpys_s1 :
2248 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpys_s1">;
2249 //
2250 // BUILTIN_INFO(HEXAGON.M2_cmpysc_s0,DI_ftype_SISI,2)
2251 //
2252 def int_hexagon_M2_cmpysc_s0 :
2253 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpysc_s0">;
2254 //
2255 // BUILTIN_INFO(HEXAGON.M2_cmpysc_s1,DI_ftype_SISI,2)
2256 //
2257 def int_hexagon_M2_cmpysc_s1 :
2258 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpysc_s1">;
2259 //
2260 // BUILTIN_INFO(HEXAGON.M2_cnacs_s0,DI_ftype_DISISI,3)
2261 //
2262 def int_hexagon_M2_cnacs_s0 :
2263 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacs_s0">;
2264 //
2265 // BUILTIN_INFO(HEXAGON.M2_cnacs_s1,DI_ftype_DISISI,3)
2266 //
2267 def int_hexagon_M2_cnacs_s1 :
2268 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacs_s1">;
2269 //
2270 // BUILTIN_INFO(HEXAGON.M2_cnacsc_s0,DI_ftype_DISISI,3)
2271 //
2272 def int_hexagon_M2_cnacsc_s0 :
2273 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacsc_s0">;
2274 //
2275 // BUILTIN_INFO(HEXAGON.M2_cnacsc_s1,DI_ftype_DISISI,3)
2276 //
2277 def int_hexagon_M2_cnacsc_s1 :
2278 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacsc_s1">;
2279 //
2280 // BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1,DI_ftype_DISI,2)
2281 //
2282 def int_hexagon_M2_vrcmpys_s1 :
2283 Hexagon_di_disi_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;
2284 //
2285 // BUILTIN_INFO(HEXAGON.M2_vrcmpys_acc_s1,DI_ftype_DIDISI,3)
2286 //
2287 def int_hexagon_M2_vrcmpys_acc_s1 :
2288 Hexagon_di_didisi_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;
2289 //
2290 // BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1rp,SI_ftype_DISI,2)
2291 //
2292 def int_hexagon_M2_vrcmpys_s1rp :
2293 Hexagon_si_disi_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;
2294 //
2295 // BUILTIN_INFO(HEXAGON.M2_mmacls_s0,DI_ftype_DIDIDI,3)
2296 //
2297 def int_hexagon_M2_mmacls_s0 :
2298 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_s0">;
2299 //
2300 // BUILTIN_INFO(HEXAGON.M2_mmacls_s1,DI_ftype_DIDIDI,3)
2301 //
2302 def int_hexagon_M2_mmacls_s1 :
2303 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_s1">;
2304 //
2305 // BUILTIN_INFO(HEXAGON.M2_mmachs_s0,DI_ftype_DIDIDI,3)
2306 //
2307 def int_hexagon_M2_mmachs_s0 :
2308 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_s0">;
2309 //
2310 // BUILTIN_INFO(HEXAGON.M2_mmachs_s1,DI_ftype_DIDIDI,3)
2311 //
2312 def int_hexagon_M2_mmachs_s1 :
2313 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_s1">;
2314 //
2315 // BUILTIN_INFO(HEXAGON.M2_mmpyl_s0,DI_ftype_DIDI,2)
2316 //
2317 def int_hexagon_M2_mmpyl_s0 :
2318 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_s0">;
2319 //
2320 // BUILTIN_INFO(HEXAGON.M2_mmpyl_s1,DI_ftype_DIDI,2)
2321 //
2322 def int_hexagon_M2_mmpyl_s1 :
2323 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_s1">;
2324 //
2325 // BUILTIN_INFO(HEXAGON.M2_mmpyh_s0,DI_ftype_DIDI,2)
2326 //
2327 def int_hexagon_M2_mmpyh_s0 :
2328 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_s0">;
2329 //
2330 // BUILTIN_INFO(HEXAGON.M2_mmpyh_s1,DI_ftype_DIDI,2)
2331 //
2332 def int_hexagon_M2_mmpyh_s1 :
2333 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_s1">;
2334 //
2335 // BUILTIN_INFO(HEXAGON.M2_mmacls_rs0,DI_ftype_DIDIDI,3)
2336 //
2337 def int_hexagon_M2_mmacls_rs0 :
2338 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_rs0">;
2339 //
2340 // BUILTIN_INFO(HEXAGON.M2_mmacls_rs1,DI_ftype_DIDIDI,3)
2341 //
2342 def int_hexagon_M2_mmacls_rs1 :
2343 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_rs1">;
2344 //
2345 // BUILTIN_INFO(HEXAGON.M2_mmachs_rs0,DI_ftype_DIDIDI,3)
2346 //
2347 def int_hexagon_M2_mmachs_rs0 :
2348 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_rs0">;
2349 //
2350 // BUILTIN_INFO(HEXAGON.M2_mmachs_rs1,DI_ftype_DIDIDI,3)
2351 //
2352 def int_hexagon_M2_mmachs_rs1 :
2353 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_rs1">;
2354 //
2355 // BUILTIN_INFO(HEXAGON.M2_mmpyl_rs0,DI_ftype_DIDI,2)
2356 //
2357 def int_hexagon_M2_mmpyl_rs0 :
2358 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_rs0">;
2359 //
2360 // BUILTIN_INFO(HEXAGON.M2_mmpyl_rs1,DI_ftype_DIDI,2)
2361 //
2362 def int_hexagon_M2_mmpyl_rs1 :
2363 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;
2364 //
2365 // BUILTIN_INFO(HEXAGON.M2_mmpyh_rs0,DI_ftype_DIDI,2)
2366 //
2367 def int_hexagon_M2_mmpyh_rs0 :
2368 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;
2369 //
2370 // BUILTIN_INFO(HEXAGON.M2_mmpyh_rs1,DI_ftype_DIDI,2)
2371 //
2372 def int_hexagon_M2_mmpyh_rs1 :
2373 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;
2374 //
2375 // BUILTIN_INFO(HEXAGON.M4_vrmpyeh_s0,DI_ftype_DIDI,2)
2376 //
2377 def int_hexagon_M4_vrmpyeh_s0 :
2378 Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">;
2379 //
2380 // BUILTIN_INFO(HEXAGON.M4_vrmpyeh_s1,DI_ftype_DIDI,2)
2381 //
2382 def int_hexagon_M4_vrmpyeh_s1 :
2383 Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">;
2384 //
2385 // BUILTIN_INFO(HEXAGON.M4_vrmpyeh_acc_s0,DI_ftype_DIDIDI,3)
2386 //
2387 def int_hexagon_M4_vrmpyeh_acc_s0 :
2388 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;
2389 //
2390 // BUILTIN_INFO(HEXAGON.M4_vrmpyeh_acc_s1,DI_ftype_DIDIDI,3)
2391 //
2392 def int_hexagon_M4_vrmpyeh_acc_s1 :
2393 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;
2394 //
2395 // BUILTIN_INFO(HEXAGON.M4_vrmpyoh_s0,DI_ftype_DIDI,2)
2396 //
2397 def int_hexagon_M4_vrmpyoh_s0 :
2398 Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;
2399 //
2400 // BUILTIN_INFO(HEXAGON.M4_vrmpyoh_s1,DI_ftype_DIDI,2)
2401 //
2402 def int_hexagon_M4_vrmpyoh_s1 :
2403 Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;
2404 //
2405 // BUILTIN_INFO(HEXAGON.M4_vrmpyoh_acc_s0,DI_ftype_DIDIDI,3)
2406 //
2407 def int_hexagon_M4_vrmpyoh_acc_s0 :
2408 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;
2409 //
2410 // BUILTIN_INFO(HEXAGON.M4_vrmpyoh_acc_s1,DI_ftype_DIDIDI,3)
2411 //
2412 def int_hexagon_M4_vrmpyoh_acc_s1 :
2413 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;
2414 //
2415 // BUILTIN_INFO(HEXAGON.M2_hmmpyl_rs1,SI_ftype_SISI,2)
2416 //
2417 def int_hexagon_M2_hmmpyl_rs1 :
2418 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;
2419 //
2420 // BUILTIN_INFO(HEXAGON.M2_hmmpyh_rs1,SI_ftype_SISI,2)
2421 //
2422 def int_hexagon_M2_hmmpyh_rs1 :
2423 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;
2424 //
2425 // BUILTIN_INFO(HEXAGON.M2_hmmpyl_s1,SI_ftype_SISI,2)
2426 //
2427 def int_hexagon_M2_hmmpyl_s1 :
2428 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;
2429 //
2430 // BUILTIN_INFO(HEXAGON.M2_hmmpyh_s1,SI_ftype_SISI,2)
2431 //
2432 def int_hexagon_M2_hmmpyh_s1 :
2433 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;
2434 //
2435 // BUILTIN_INFO(HEXAGON.M2_mmaculs_s0,DI_ftype_DIDIDI,3)
2436 //
2437 def int_hexagon_M2_mmaculs_s0 :
2438 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_s0">;
2439 //
2440 // BUILTIN_INFO(HEXAGON.M2_mmaculs_s1,DI_ftype_DIDIDI,3)
2441 //
2442 def int_hexagon_M2_mmaculs_s1 :
2443 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_s1">;
2444 //
2445 // BUILTIN_INFO(HEXAGON.M2_mmacuhs_s0,DI_ftype_DIDIDI,3)
2446 //
2447 def int_hexagon_M2_mmacuhs_s0 :
2448 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;
2449 //
2450 // BUILTIN_INFO(HEXAGON.M2_mmacuhs_s1,DI_ftype_DIDIDI,3)
2451 //
2452 def int_hexagon_M2_mmacuhs_s1 :
2453 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;
2454 //
2455 // BUILTIN_INFO(HEXAGON.M2_mmpyul_s0,DI_ftype_DIDI,2)
2456 //
2457 def int_hexagon_M2_mmpyul_s0 :
2458 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_s0">;
2459 //
2460 // BUILTIN_INFO(HEXAGON.M2_mmpyul_s1,DI_ftype_DIDI,2)
2461 //
2462 def int_hexagon_M2_mmpyul_s1 :
2463 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_s1">;
2464 //
2465 // BUILTIN_INFO(HEXAGON.M2_mmpyuh_s0,DI_ftype_DIDI,2)
2466 //
2467 def int_hexagon_M2_mmpyuh_s0 :
2468 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;
2469 //
2470 // BUILTIN_INFO(HEXAGON.M2_mmpyuh_s1,DI_ftype_DIDI,2)
2471 //
2472 def int_hexagon_M2_mmpyuh_s1 :
2473 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;
2474 //
2475 // BUILTIN_INFO(HEXAGON.M2_mmaculs_rs0,DI_ftype_DIDIDI,3)
2476 //
2477 def int_hexagon_M2_mmaculs_rs0 :
2478 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;
2479 //
2480 // BUILTIN_INFO(HEXAGON.M2_mmaculs_rs1,DI_ftype_DIDIDI,3)
2481 //
2482 def int_hexagon_M2_mmaculs_rs1 :
2483 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;
2484 //
2485 // BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs0,DI_ftype_DIDIDI,3)
2486 //
2487 def int_hexagon_M2_mmacuhs_rs0 :
2488 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;
2489 //
2490 // BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs1,DI_ftype_DIDIDI,3)
2491 //
2492 def int_hexagon_M2_mmacuhs_rs1 :
2493 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;
2494 //
2495 // BUILTIN_INFO(HEXAGON.M2_mmpyul_rs0,DI_ftype_DIDI,2)
2496 //
2497 def int_hexagon_M2_mmpyul_rs0 :
2498 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;
2499 //
2500 // BUILTIN_INFO(HEXAGON.M2_mmpyul_rs1,DI_ftype_DIDI,2)
2501 //
2502 def int_hexagon_M2_mmpyul_rs1 :
2503 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;
2504 //
2505 // BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs0,DI_ftype_DIDI,2)
2506 //
2507 def int_hexagon_M2_mmpyuh_rs0 :
2508 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;
2509 //
2510 // BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs1,DI_ftype_DIDI,2)
2511 //
2512 def int_hexagon_M2_mmpyuh_rs1 :
2513 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;
2514 //
2515 // BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0,DI_ftype_DIDIDI,3)
2516 //
2517 def int_hexagon_M2_vrcmaci_s0 :
2518 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmaci_s0">;
2519 //
2520 // BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0,DI_ftype_DIDIDI,3)
2521 //
2522 def int_hexagon_M2_vrcmacr_s0 :
2523 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;
2524 //
2525 // BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0c,DI_ftype_DIDIDI,3)
2526 //
2527 def int_hexagon_M2_vrcmaci_s0c :
2528 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;
2529 //
2530 // BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0c,DI_ftype_DIDIDI,3)
2531 //
2532 def int_hexagon_M2_vrcmacr_s0c :
2533 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;
2534 //
2535 // BUILTIN_INFO(HEXAGON.M2_cmaci_s0,DI_ftype_DISISI,3)
2536 //
2537 def int_hexagon_M2_cmaci_s0 :
2538 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmaci_s0">;
2539 //
2540 // BUILTIN_INFO(HEXAGON.M2_cmacr_s0,DI_ftype_DISISI,3)
2541 //
2542 def int_hexagon_M2_cmacr_s0 :
2543 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacr_s0">;
2544 //
2545 // BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0,DI_ftype_DIDI,2)
2546 //
2547 def int_hexagon_M2_vrcmpyi_s0 :
2548 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;
2549 //
2550 // BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0,DI_ftype_DIDI,2)
2551 //
2552 def int_hexagon_M2_vrcmpyr_s0 :
2553 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">;
2554 //
2555 // BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0c,DI_ftype_DIDI,2)
2556 //
2557 def int_hexagon_M2_vrcmpyi_s0c :
2558 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;
2559 //
2560 // BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0c,DI_ftype_DIDI,2)
2561 //
2562 def int_hexagon_M2_vrcmpyr_s0c :
2563 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;
2564 //
2565 // BUILTIN_INFO(HEXAGON.M2_cmpyi_s0,DI_ftype_SISI,2)
2566 //
2567 def int_hexagon_M2_cmpyi_s0 :
2568 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpyi_s0">;
2569 //
2570 // BUILTIN_INFO(HEXAGON.M2_cmpyr_s0,DI_ftype_SISI,2)
2571 //
2572 def int_hexagon_M2_cmpyr_s0 :
2573 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpyr_s0">;
2574 //
2575 // BUILTIN_INFO(HEXAGON.M4_cmpyi_wh,SI_ftype_DISI,2)
2576 //
2577 def int_hexagon_M4_cmpyi_wh :
2578 Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyi_wh">;
2579 //
2580 // BUILTIN_INFO(HEXAGON.M4_cmpyr_wh,SI_ftype_DISI,2)
2581 //
2582 def int_hexagon_M4_cmpyr_wh :
2583 Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyr_wh">;
2584 //
2585 // BUILTIN_INFO(HEXAGON.M4_cmpyi_whc,SI_ftype_DISI,2)
2586 //
2587 def int_hexagon_M4_cmpyi_whc :
2588 Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyi_whc">;
2589 //
2590 // BUILTIN_INFO(HEXAGON.M4_cmpyr_whc,SI_ftype_DISI,2)
2591 //
2592 def int_hexagon_M4_cmpyr_whc :
2593 Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyr_whc">;
2594 //
2595 // BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_i,DI_ftype_DIDI,2)
2596 //
2597 def int_hexagon_M2_vcmpy_s0_sat_i :
2598 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;
2599 //
2600 // BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_r,DI_ftype_DIDI,2)
2601 //
2602 def int_hexagon_M2_vcmpy_s0_sat_r :
2603 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;
2604 //
2605 // BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_i,DI_ftype_DIDI,2)
2606 //
2607 def int_hexagon_M2_vcmpy_s1_sat_i :
2608 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;
2609 //
2610 // BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_r,DI_ftype_DIDI,2)
2611 //
2612 def int_hexagon_M2_vcmpy_s1_sat_r :
2613 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;
2614 //
2615 // BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_i,DI_ftype_DIDIDI,3)
2616 //
2617 def int_hexagon_M2_vcmac_s0_sat_i :
2618 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">;
2619 //
2620 // BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_r,DI_ftype_DIDIDI,3)
2621 //
2622 def int_hexagon_M2_vcmac_s0_sat_r :
2623 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;
2624 //
2625 // BUILTIN_INFO(HEXAGON.S2_vcrotate,DI_ftype_DISI,2)
2626 //
2627 def int_hexagon_S2_vcrotate :
2628 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_vcrotate">;
2629 //
2630 // BUILTIN_INFO(HEXAGON.S4_vrcrotate_acc,DI_ftype_DIDISISI,4)
2631 //
2632 def int_hexagon_S4_vrcrotate_acc :
2633 Hexagon_di_didisisi_Intrinsic<"HEXAGON_S4_vrcrotate_acc">;
2634 //
2635 // BUILTIN_INFO(HEXAGON.S4_vrcrotate,DI_ftype_DISISI,3)
2636 //
2637 def int_hexagon_S4_vrcrotate :
2638 Hexagon_di_disisi_Intrinsic<"HEXAGON_S4_vrcrotate">;
2639 //
2640 // BUILTIN_INFO(HEXAGON.S2_vcnegh,DI_ftype_DISI,2)
2641 //
2642 def int_hexagon_S2_vcnegh :
2643 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_vcnegh">;
2644 //
2645 // BUILTIN_INFO(HEXAGON.S2_vrcnegh,DI_ftype_DIDISI,3)
2646 //
2647 def int_hexagon_S2_vrcnegh :
2648 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_vrcnegh">;
2649 //
2650 // BUILTIN_INFO(HEXAGON.M4_pmpyw,DI_ftype_SISI,2)
2651 //
2652 def int_hexagon_M4_pmpyw :
2653 Hexagon_di_sisi_Intrinsic<"HEXAGON_M4_pmpyw">;
2654 //
2655 // BUILTIN_INFO(HEXAGON.M4_vpmpyh,DI_ftype_SISI,2)
2656 //
2657 def int_hexagon_M4_vpmpyh :
2658 Hexagon_di_sisi_Intrinsic<"HEXAGON_M4_vpmpyh">;
2659 //
2660 // BUILTIN_INFO(HEXAGON.M4_pmpyw_acc,DI_ftype_DISISI,3)
2661 //
2662 def int_hexagon_M4_pmpyw_acc :
2663 Hexagon_di_disisi_Intrinsic<"HEXAGON_M4_pmpyw_acc">;
2664 //
2665 // BUILTIN_INFO(HEXAGON.M4_vpmpyh_acc,DI_ftype_DISISI,3)
2666 //
2667 def int_hexagon_M4_vpmpyh_acc :
2668 Hexagon_di_disisi_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;
2669 //
2670 // BUILTIN_INFO(HEXAGON.A2_add,SI_ftype_SISI,2)
2671 //
2672 def int_hexagon_A2_add :
2673 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_add">;
2674 //
2675 // BUILTIN_INFO(HEXAGON.A2_sub,SI_ftype_SISI,2)
2676 //
2677 def int_hexagon_A2_sub :
2678 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_sub">;
2679 //
2680 // BUILTIN_INFO(HEXAGON.A2_addsat,SI_ftype_SISI,2)
2681 //
2682 def int_hexagon_A2_addsat :
2683 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addsat">;
2684 //
2685 // BUILTIN_INFO(HEXAGON.A2_subsat,SI_ftype_SISI,2)
2686 //
2687 def int_hexagon_A2_subsat :
2688 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subsat">;
2689 //
2690 // BUILTIN_INFO(HEXAGON.A2_addi,SI_ftype_SISI,2)
2691 //
2692 def int_hexagon_A2_addi :
2693 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addi">;
2694 //
2695 // BUILTIN_INFO(HEXAGON.A2_addh_l16_ll,SI_ftype_SISI,2)
2696 //
2697 def int_hexagon_A2_addh_l16_ll :
2698 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_ll">;
2699 //
2700 // BUILTIN_INFO(HEXAGON.A2_addh_l16_hl,SI_ftype_SISI,2)
2701 //
2702 def int_hexagon_A2_addh_l16_hl :
2703 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_hl">;
2704 //
2705 // BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_ll,SI_ftype_SISI,2)
2706 //
2707 def int_hexagon_A2_addh_l16_sat_ll :
2708 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;
2709 //
2710 // BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_hl,SI_ftype_SISI,2)
2711 //
2712 def int_hexagon_A2_addh_l16_sat_hl :
2713 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;
2714 //
2715 // BUILTIN_INFO(HEXAGON.A2_subh_l16_ll,SI_ftype_SISI,2)
2716 //
2717 def int_hexagon_A2_subh_l16_ll :
2718 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_ll">;
2719 //
2720 // BUILTIN_INFO(HEXAGON.A2_subh_l16_hl,SI_ftype_SISI,2)
2721 //
2722 def int_hexagon_A2_subh_l16_hl :
2723 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_hl">;
2724 //
2725 // BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_ll,SI_ftype_SISI,2)
2726 //
2727 def int_hexagon_A2_subh_l16_sat_ll :
2728 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">;
2729 //
2730 // BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_hl,SI_ftype_SISI,2)
2731 //
2732 def int_hexagon_A2_subh_l16_sat_hl :
2733 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;
2734 //
2735 // BUILTIN_INFO(HEXAGON.A2_addh_h16_ll,SI_ftype_SISI,2)
2736 //
2737 def int_hexagon_A2_addh_h16_ll :
2738 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_ll">;
2739 //
2740 // BUILTIN_INFO(HEXAGON.A2_addh_h16_lh,SI_ftype_SISI,2)
2741 //
2742 def int_hexagon_A2_addh_h16_lh :
2743 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_lh">;
2744 //
2745 // BUILTIN_INFO(HEXAGON.A2_addh_h16_hl,SI_ftype_SISI,2)
2746 //
2747 def int_hexagon_A2_addh_h16_hl :
2748 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_hl">;
2749 //
2750 // BUILTIN_INFO(HEXAGON.A2_addh_h16_hh,SI_ftype_SISI,2)
2751 //
2752 def int_hexagon_A2_addh_h16_hh :
2753 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_hh">;
2754 //
2755 // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_ll,SI_ftype_SISI,2)
2756 //
2757 def int_hexagon_A2_addh_h16_sat_ll :
2758 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">;
2759 //
2760 // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_lh,SI_ftype_SISI,2)
2761 //
2762 def int_hexagon_A2_addh_h16_sat_lh :
2763 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">;
2764 //
2765 // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hl,SI_ftype_SISI,2)
2766 //
2767 def int_hexagon_A2_addh_h16_sat_hl :
2768 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;
2769 //
2770 // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hh,SI_ftype_SISI,2)
2771 //
2772 def int_hexagon_A2_addh_h16_sat_hh :
2773 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;
2774 //
2775 // BUILTIN_INFO(HEXAGON.A2_subh_h16_ll,SI_ftype_SISI,2)
2776 //
2777 def int_hexagon_A2_subh_h16_ll :
2778 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_ll">;
2779 //
2780 // BUILTIN_INFO(HEXAGON.A2_subh_h16_lh,SI_ftype_SISI,2)
2781 //
2782 def int_hexagon_A2_subh_h16_lh :
2783 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_lh">;
2784 //
2785 // BUILTIN_INFO(HEXAGON.A2_subh_h16_hl,SI_ftype_SISI,2)
2786 //
2787 def int_hexagon_A2_subh_h16_hl :
2788 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_hl">;
2789 //
2790 // BUILTIN_INFO(HEXAGON.A2_subh_h16_hh,SI_ftype_SISI,2)
2791 //
2792 def int_hexagon_A2_subh_h16_hh :
2793 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_hh">;
2794 //
2795 // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_ll,SI_ftype_SISI,2)
2796 //
2797 def int_hexagon_A2_subh_h16_sat_ll :
2798 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;
2799 //
2800 // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_lh,SI_ftype_SISI,2)
2801 //
2802 def int_hexagon_A2_subh_h16_sat_lh :
2803 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;
2804 //
2805 // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hl,SI_ftype_SISI,2)
2806 //
2807 def int_hexagon_A2_subh_h16_sat_hl :
2808 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;
2809 //
2810 // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hh,SI_ftype_SISI,2)
2811 //
2812 def int_hexagon_A2_subh_h16_sat_hh :
2813 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;
2814 //
2815 // BUILTIN_INFO(HEXAGON.A2_aslh,SI_ftype_SI,1)
2816 //
2817 def int_hexagon_A2_aslh :
2818 Hexagon_si_si_Intrinsic<"HEXAGON_A2_aslh">;
2819 //
2820 // BUILTIN_INFO(HEXAGON.A2_asrh,SI_ftype_SI,1)
2821 //
2822 def int_hexagon_A2_asrh :
2823 Hexagon_si_si_Intrinsic<"HEXAGON_A2_asrh">;
2824 //
2825 // BUILTIN_INFO(HEXAGON.A2_addp,DI_ftype_DIDI,2)
2826 //
2827 def int_hexagon_A2_addp :
2828 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_addp">;
2829 //
2830 // BUILTIN_INFO(HEXAGON.A2_addpsat,DI_ftype_DIDI,2)
2831 //
2832 def int_hexagon_A2_addpsat :
2833 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_addpsat">;
2834 //
2835 // BUILTIN_INFO(HEXAGON.A2_addsp,DI_ftype_SIDI,2)
2836 //
2837 def int_hexagon_A2_addsp :
2838 Hexagon_di_sidi_Intrinsic<"HEXAGON_A2_addsp">;
2839 //
2840 // BUILTIN_INFO(HEXAGON.A2_subp,DI_ftype_DIDI,2)
2841 //
2842 def int_hexagon_A2_subp :
2843 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_subp">;
2844 //
2845 // BUILTIN_INFO(HEXAGON.A2_neg,SI_ftype_SI,1)
2846 //
2847 def int_hexagon_A2_neg :
2848 Hexagon_si_si_Intrinsic<"HEXAGON_A2_neg">;
2849 //
2850 // BUILTIN_INFO(HEXAGON.A2_negsat,SI_ftype_SI,1)
2851 //
2852 def int_hexagon_A2_negsat :
2853 Hexagon_si_si_Intrinsic<"HEXAGON_A2_negsat">;
2854 //
2855 // BUILTIN_INFO(HEXAGON.A2_abs,SI_ftype_SI,1)
2856 //
2857 def int_hexagon_A2_abs :
2858 Hexagon_si_si_Intrinsic<"HEXAGON_A2_abs">;
2859 //
2860 // BUILTIN_INFO(HEXAGON.A2_abssat,SI_ftype_SI,1)
2861 //
2862 def int_hexagon_A2_abssat :
2863 Hexagon_si_si_Intrinsic<"HEXAGON_A2_abssat">;
2864 //
2865 // BUILTIN_INFO(HEXAGON.A2_vconj,DI_ftype_DI,1)
2866 //
2867 def int_hexagon_A2_vconj :
2868 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vconj">;
2869 //
2870 // BUILTIN_INFO(HEXAGON.A2_negp,DI_ftype_DI,1)
2871 //
2872 def int_hexagon_A2_negp :
2873 Hexagon_di_di_Intrinsic<"HEXAGON_A2_negp">;
2874 //
2875 // BUILTIN_INFO(HEXAGON.A2_absp,DI_ftype_DI,1)
2876 //
2877 def int_hexagon_A2_absp :
2878 Hexagon_di_di_Intrinsic<"HEXAGON_A2_absp">;
2879 //
2880 // BUILTIN_INFO(HEXAGON.A2_max,SI_ftype_SISI,2)
2881 //
2882 def int_hexagon_A2_max :
2883 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_max">;
2884 //
2885 // BUILTIN_INFO(HEXAGON.A2_maxu,USI_ftype_SISI,2)
2886 //
2887 def int_hexagon_A2_maxu :
2888 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_maxu">;
2889 //
2890 // BUILTIN_INFO(HEXAGON.A2_min,SI_ftype_SISI,2)
2891 //
2892 def int_hexagon_A2_min :
2893 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_min">;
2894 //
2895 // BUILTIN_INFO(HEXAGON.A2_minu,USI_ftype_SISI,2)
2896 //
2897 def int_hexagon_A2_minu :
2898 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_minu">;
2899 //
2900 // BUILTIN_INFO(HEXAGON.A2_maxp,DI_ftype_DIDI,2)
2901 //
2902 def int_hexagon_A2_maxp :
2903 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_maxp">;
2904 //
2905 // BUILTIN_INFO(HEXAGON.A2_maxup,UDI_ftype_DIDI,2)
2906 //
2907 def int_hexagon_A2_maxup :
2908 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_maxup">;
2909 //
2910 // BUILTIN_INFO(HEXAGON.A2_minp,DI_ftype_DIDI,2)
2911 //
2912 def int_hexagon_A2_minp :
2913 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_minp">;
2914 //
2915 // BUILTIN_INFO(HEXAGON.A2_minup,UDI_ftype_DIDI,2)
2916 //
2917 def int_hexagon_A2_minup :
2918 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_minup">;
2919 //
2920 // BUILTIN_INFO(HEXAGON.A2_tfr,SI_ftype_SI,1)
2921 //
2922 def int_hexagon_A2_tfr :
2923 Hexagon_si_si_Intrinsic<"HEXAGON_A2_tfr">;
2924 //
2925 // BUILTIN_INFO(HEXAGON.A2_tfrsi,SI_ftype_SI,1)
2926 //
2927 def int_hexagon_A2_tfrsi :
2928 Hexagon_si_si_Intrinsic<"HEXAGON_A2_tfrsi">;
2929 //
2930 // BUILTIN_INFO(HEXAGON.A2_tfrp,DI_ftype_DI,1)
2931 //
2932 def int_hexagon_A2_tfrp :
2933 Hexagon_di_di_Intrinsic<"HEXAGON_A2_tfrp">;
2934 //
2935 // BUILTIN_INFO(HEXAGON.A2_tfrpi,DI_ftype_SI,1)
2936 //
2937 def int_hexagon_A2_tfrpi :
2938 Hexagon_di_si_Intrinsic<"HEXAGON_A2_tfrpi">;
2939 //
2940 // BUILTIN_INFO(HEXAGON.A2_zxtb,SI_ftype_SI,1)
2941 //
2942 def int_hexagon_A2_zxtb :
2943 Hexagon_si_si_Intrinsic<"HEXAGON_A2_zxtb">;
2944 //
2945 // BUILTIN_INFO(HEXAGON.A2_sxtb,SI_ftype_SI,1)
2946 //
2947 def int_hexagon_A2_sxtb :
2948 Hexagon_si_si_Intrinsic<"HEXAGON_A2_sxtb">;
2949 //
2950 // BUILTIN_INFO(HEXAGON.A2_zxth,SI_ftype_SI,1)
2951 //
2952 def int_hexagon_A2_zxth :
2953 Hexagon_si_si_Intrinsic<"HEXAGON_A2_zxth">;
2954 //
2955 // BUILTIN_INFO(HEXAGON.A2_sxth,SI_ftype_SI,1)
2956 //
2957 def int_hexagon_A2_sxth :
2958 Hexagon_si_si_Intrinsic<"HEXAGON_A2_sxth">;
2959 //
2960 // BUILTIN_INFO(HEXAGON.A2_combinew,DI_ftype_SISI,2)
2961 //
2962 def int_hexagon_A2_combinew :
2963 Hexagon_di_sisi_Intrinsic<"HEXAGON_A2_combinew">;
2964 //
2965 // BUILTIN_INFO(HEXAGON.A4_combineri,DI_ftype_SISI,2)
2966 //
2967 def int_hexagon_A4_combineri :
2968 Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_combineri">;
2969 //
2970 // BUILTIN_INFO(HEXAGON.A4_combineir,DI_ftype_SISI,2)
2971 //
2972 def int_hexagon_A4_combineir :
2973 Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_combineir">;
2974 //
2975 // BUILTIN_INFO(HEXAGON.A2_combineii,DI_ftype_SISI,2)
2976 //
2977 def int_hexagon_A2_combineii :
2978 Hexagon_di_sisi_Intrinsic<"HEXAGON_A2_combineii">;
2979 //
2980 // BUILTIN_INFO(HEXAGON.A2_combine_hh,SI_ftype_SISI,2)
2981 //
2982 def int_hexagon_A2_combine_hh :
2983 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_hh">;
2984 //
2985 // BUILTIN_INFO(HEXAGON.A2_combine_hl,SI_ftype_SISI,2)
2986 //
2987 def int_hexagon_A2_combine_hl :
2988 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_hl">;
2989 //
2990 // BUILTIN_INFO(HEXAGON.A2_combine_lh,SI_ftype_SISI,2)
2991 //
2992 def int_hexagon_A2_combine_lh :
2993 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_lh">;
2994 //
2995 // BUILTIN_INFO(HEXAGON.A2_combine_ll,SI_ftype_SISI,2)
2996 //
2997 def int_hexagon_A2_combine_ll :
2998 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_ll">;
2999 //
3000 // BUILTIN_INFO(HEXAGON.A2_tfril,SI_ftype_SISI,2)
3001 //
3002 def int_hexagon_A2_tfril :
3003 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_tfril">;
3004 //
3005 // BUILTIN_INFO(HEXAGON.A2_tfrih,SI_ftype_SISI,2)
3006 //
3007 def int_hexagon_A2_tfrih :
3008 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_tfrih">;
3009 //
3010 // BUILTIN_INFO(HEXAGON.A2_and,SI_ftype_SISI,2)
3011 //
3012 def int_hexagon_A2_and :
3013 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_and">;
3014 //
3015 // BUILTIN_INFO(HEXAGON.A2_or,SI_ftype_SISI,2)
3016 //
3017 def int_hexagon_A2_or :
3018 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_or">;
3019 //
3020 // BUILTIN_INFO(HEXAGON.A2_xor,SI_ftype_SISI,2)
3021 //
3022 def int_hexagon_A2_xor :
3023 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_xor">;
3024 //
3025 // BUILTIN_INFO(HEXAGON.A2_not,SI_ftype_SI,1)
3026 //
3027 def int_hexagon_A2_not :
3028 Hexagon_si_si_Intrinsic<"HEXAGON_A2_not">;
3029 //
3030 // BUILTIN_INFO(HEXAGON.M2_xor_xacc,SI_ftype_SISISI,3)
3031 //
3032 def int_hexagon_M2_xor_xacc :
3033 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_xor_xacc">;
3034 //
3035 // BUILTIN_INFO(HEXAGON.M4_xor_xacc,DI_ftype_DIDIDI,3)
3036 //
3037 def int_hexagon_M4_xor_xacc :
3038 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_xor_xacc">;
3039 //
3040 // BUILTIN_INFO(HEXAGON.A4_andn,SI_ftype_SISI,2)
3041 //
3042 def int_hexagon_A4_andn :
3043 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_andn">;
3044 //
3045 // BUILTIN_INFO(HEXAGON.A4_orn,SI_ftype_SISI,2)
3046 //
3047 def int_hexagon_A4_orn :
3048 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_orn">;
3049 //
3050 // BUILTIN_INFO(HEXAGON.A4_andnp,DI_ftype_DIDI,2)
3051 //
3052 def int_hexagon_A4_andnp :
3053 Hexagon_di_didi_Intrinsic<"HEXAGON_A4_andnp">;
3054 //
3055 // BUILTIN_INFO(HEXAGON.A4_ornp,DI_ftype_DIDI,2)
3056 //
3057 def int_hexagon_A4_ornp :
3058 Hexagon_di_didi_Intrinsic<"HEXAGON_A4_ornp">;
3059 //
3060 // BUILTIN_INFO(HEXAGON.S4_addaddi,SI_ftype_SISISI,3)
3061 //
3062 def int_hexagon_S4_addaddi :
3063 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addaddi">;
3064 //
3065 // BUILTIN_INFO(HEXAGON.S4_subaddi,SI_ftype_SISISI,3)
3066 //
3067 def int_hexagon_S4_subaddi :
3068 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subaddi">;
3069 //
3070 // BUILTIN_INFO(HEXAGON.M4_and_and,SI_ftype_SISISI,3)
3071 //
3072 def int_hexagon_M4_and_and :
3073 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_and">;
3074 //
3075 // BUILTIN_INFO(HEXAGON.M4_and_andn,SI_ftype_SISISI,3)
3076 //
3077 def int_hexagon_M4_and_andn :
3078 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_andn">;
3079 //
3080 // BUILTIN_INFO(HEXAGON.M4_and_or,SI_ftype_SISISI,3)
3081 //
3082 def int_hexagon_M4_and_or :
3083 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_or">;
3084 //
3085 // BUILTIN_INFO(HEXAGON.M4_and_xor,SI_ftype_SISISI,3)
3086 //
3087 def int_hexagon_M4_and_xor :
3088 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_xor">;
3089 //
3090 // BUILTIN_INFO(HEXAGON.M4_or_and,SI_ftype_SISISI,3)
3091 //
3092 def int_hexagon_M4_or_and :
3093 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_and">;
3094 //
3095 // BUILTIN_INFO(HEXAGON.M4_or_andn,SI_ftype_SISISI,3)
3096 //
3097 def int_hexagon_M4_or_andn :
3098 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_andn">;
3099 //
3100 // BUILTIN_INFO(HEXAGON.M4_or_or,SI_ftype_SISISI,3)
3101 //
3102 def int_hexagon_M4_or_or :
3103 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_or">;
3104 //
3105 // BUILTIN_INFO(HEXAGON.M4_or_xor,SI_ftype_SISISI,3)
3106 //
3107 def int_hexagon_M4_or_xor :
3108 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_xor">;
3109 //
3110 // BUILTIN_INFO(HEXAGON.S4_or_andix,SI_ftype_SISISI,3)
3111 //
3112 def int_hexagon_S4_or_andix :
3113 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_andix">;
3114 //
3115 // BUILTIN_INFO(HEXAGON.S4_or_andi,SI_ftype_SISISI,3)
3116 //
3117 def int_hexagon_S4_or_andi :
3118 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_andi">;
3119 //
3120 // BUILTIN_INFO(HEXAGON.S4_or_ori,SI_ftype_SISISI,3)
3121 //
3122 def int_hexagon_S4_or_ori :
3123 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_ori">;
3124 //
3125 // BUILTIN_INFO(HEXAGON.M4_xor_and,SI_ftype_SISISI,3)
3126 //
3127 def int_hexagon_M4_xor_and :
3128 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_and">;
3129 //
3130 // BUILTIN_INFO(HEXAGON.M4_xor_or,SI_ftype_SISISI,3)
3131 //
3132 def int_hexagon_M4_xor_or :
3133 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_or">;
3134 //
3135 // BUILTIN_INFO(HEXAGON.M4_xor_andn,SI_ftype_SISISI,3)
3136 //
3137 def int_hexagon_M4_xor_andn :
3138 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_andn">;
3139 //
3140 // BUILTIN_INFO(HEXAGON.A2_subri,SI_ftype_SISI,2)
3141 //
3142 def int_hexagon_A2_subri :
3143 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subri">;
3144 //
3145 // BUILTIN_INFO(HEXAGON.A2_andir,SI_ftype_SISI,2)
3146 //
3147 def int_hexagon_A2_andir :
3148 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_andir">;
3149 //
3150 // BUILTIN_INFO(HEXAGON.A2_orir,SI_ftype_SISI,2)
3151 //
3152 def int_hexagon_A2_orir :
3153 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_orir">;
3154 //
3155 // BUILTIN_INFO(HEXAGON.A2_andp,DI_ftype_DIDI,2)
3156 //
3157 def int_hexagon_A2_andp :
3158 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_andp">;
3159 //
3160 // BUILTIN_INFO(HEXAGON.A2_orp,DI_ftype_DIDI,2)
3161 //
3162 def int_hexagon_A2_orp :
3163 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_orp">;
3164 //
3165 // BUILTIN_INFO(HEXAGON.A2_xorp,DI_ftype_DIDI,2)
3166 //
3167 def int_hexagon_A2_xorp :
3168 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_xorp">;
3169 //
3170 // BUILTIN_INFO(HEXAGON.A2_notp,DI_ftype_DI,1)
3171 //
3172 def int_hexagon_A2_notp :
3173 Hexagon_di_di_Intrinsic<"HEXAGON_A2_notp">;
3174 //
3175 // BUILTIN_INFO(HEXAGON.A2_sxtw,DI_ftype_SI,1)
3176 //
3177 def int_hexagon_A2_sxtw :
3178 Hexagon_di_si_Intrinsic<"HEXAGON_A2_sxtw">;
3179 //
3180 // BUILTIN_INFO(HEXAGON.A2_sat,SI_ftype_DI,1)
3181 //
3182 def int_hexagon_A2_sat :
3183 Hexagon_si_di_Intrinsic<"HEXAGON_A2_sat">;
3184 //
3185 // BUILTIN_INFO(HEXAGON.A2_roundsat,SI_ftype_DI,1)
3186 //
3187 def int_hexagon_A2_roundsat :
3188 Hexagon_si_di_Intrinsic<"HEXAGON_A2_roundsat">;
3189 //
3190 // BUILTIN_INFO(HEXAGON.A2_sath,SI_ftype_SI,1)
3191 //
3192 def int_hexagon_A2_sath :
3193 Hexagon_si_si_Intrinsic<"HEXAGON_A2_sath">;
3194 //
3195 // BUILTIN_INFO(HEXAGON.A2_satuh,SI_ftype_SI,1)
3196 //
3197 def int_hexagon_A2_satuh :
3198 Hexagon_si_si_Intrinsic<"HEXAGON_A2_satuh">;
3199 //
3200 // BUILTIN_INFO(HEXAGON.A2_satub,SI_ftype_SI,1)
3201 //
3202 def int_hexagon_A2_satub :
3203 Hexagon_si_si_Intrinsic<"HEXAGON_A2_satub">;
3204 //
3205 // BUILTIN_INFO(HEXAGON.A2_satb,SI_ftype_SI,1)
3206 //
3207 def int_hexagon_A2_satb :
3208 Hexagon_si_si_Intrinsic<"HEXAGON_A2_satb">;
3209 //
3210 // BUILTIN_INFO(HEXAGON.A2_vaddub,DI_ftype_DIDI,2)
3211 //
3212 def int_hexagon_A2_vaddub :
3213 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddub">;
3214 //
3215 // BUILTIN_INFO(HEXAGON.A2_vaddb_map,DI_ftype_DIDI,2)
3216 //
3217 def int_hexagon_A2_vaddb_map :
3218 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddb_map">;
3219 //
3220 // BUILTIN_INFO(HEXAGON.A2_vaddubs,DI_ftype_DIDI,2)
3221 //
3222 def int_hexagon_A2_vaddubs :
3223 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddubs">;
3224 //
3225 // BUILTIN_INFO(HEXAGON.A2_vaddh,DI_ftype_DIDI,2)
3226 //
3227 def int_hexagon_A2_vaddh :
3228 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddh">;
3229 //
3230 // BUILTIN_INFO(HEXAGON.A2_vaddhs,DI_ftype_DIDI,2)
3231 //
3232 def int_hexagon_A2_vaddhs :
3233 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddhs">;
3234 //
3235 // BUILTIN_INFO(HEXAGON.A2_vadduhs,DI_ftype_DIDI,2)
3236 //
3237 def int_hexagon_A2_vadduhs :
3238 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vadduhs">;
3239 //
3240 // BUILTIN_INFO(HEXAGON.A5_vaddhubs,SI_ftype_DIDI,2)
3241 //
3242 def int_hexagon_A5_vaddhubs :
3243 Hexagon_si_didi_Intrinsic<"HEXAGON_A5_vaddhubs">;
3244 //
3245 // BUILTIN_INFO(HEXAGON.A2_vaddw,DI_ftype_DIDI,2)
3246 //
3247 def int_hexagon_A2_vaddw :
3248 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddw">;
3249 //
3250 // BUILTIN_INFO(HEXAGON.A2_vaddws,DI_ftype_DIDI,2)
3251 //
3252 def int_hexagon_A2_vaddws :
3253 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddws">;
3254 //
3255 // BUILTIN_INFO(HEXAGON.S4_vxaddsubw,DI_ftype_DIDI,2)
3256 //
3257 def int_hexagon_S4_vxaddsubw :
3258 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubw">;
3259 //
3260 // BUILTIN_INFO(HEXAGON.S4_vxsubaddw,DI_ftype_DIDI,2)
3261 //
3262 def int_hexagon_S4_vxsubaddw :
3263 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddw">;
3264 //
3265 // BUILTIN_INFO(HEXAGON.S4_vxaddsubh,DI_ftype_DIDI,2)
3266 //
3267 def int_hexagon_S4_vxaddsubh :
3268 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubh">;
3269 //
3270 // BUILTIN_INFO(HEXAGON.S4_vxsubaddh,DI_ftype_DIDI,2)
3271 //
3272 def int_hexagon_S4_vxsubaddh :
3273 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddh">;
3274 //
3275 // BUILTIN_INFO(HEXAGON.S4_vxaddsubhr,DI_ftype_DIDI,2)
3276 //
3277 def int_hexagon_S4_vxaddsubhr :
3278 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubhr">;
3279 //
3280 // BUILTIN_INFO(HEXAGON.S4_vxsubaddhr,DI_ftype_DIDI,2)
3281 //
3282 def int_hexagon_S4_vxsubaddhr :
3283 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddhr">;
3284 //
3285 // BUILTIN_INFO(HEXAGON.A2_svavgh,SI_ftype_SISI,2)
3286 //
3287 def int_hexagon_A2_svavgh :
3288 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svavgh">;
3289 //
3290 // BUILTIN_INFO(HEXAGON.A2_svavghs,SI_ftype_SISI,2)
3291 //
3292 def int_hexagon_A2_svavghs :
3293 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svavghs">;
3294 //
3295 // BUILTIN_INFO(HEXAGON.A2_svnavgh,SI_ftype_SISI,2)
3296 //
3297 def int_hexagon_A2_svnavgh :
3298 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svnavgh">;
3299 //
3300 // BUILTIN_INFO(HEXAGON.A2_svaddh,SI_ftype_SISI,2)
3301 //
3302 def int_hexagon_A2_svaddh :
3303 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svaddh">;
3304 //
3305 // BUILTIN_INFO(HEXAGON.A2_svaddhs,SI_ftype_SISI,2)
3306 //
3307 def int_hexagon_A2_svaddhs :
3308 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svaddhs">;
3309 //
3310 // BUILTIN_INFO(HEXAGON.A2_svadduhs,SI_ftype_SISI,2)
3311 //
3312 def int_hexagon_A2_svadduhs :
3313 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svadduhs">;
3314 //
3315 // BUILTIN_INFO(HEXAGON.A2_svsubh,SI_ftype_SISI,2)
3316 //
3317 def int_hexagon_A2_svsubh :
3318 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubh">;
3319 //
3320 // BUILTIN_INFO(HEXAGON.A2_svsubhs,SI_ftype_SISI,2)
3321 //
3322 def int_hexagon_A2_svsubhs :
3323 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubhs">;
3324 //
3325 // BUILTIN_INFO(HEXAGON.A2_svsubuhs,SI_ftype_SISI,2)
3326 //
3327 def int_hexagon_A2_svsubuhs :
3328 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubuhs">;
3329 //
3330 // BUILTIN_INFO(HEXAGON.A2_vraddub,DI_ftype_DIDI,2)
3331 //
3332 def int_hexagon_A2_vraddub :
3333 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vraddub">;
3334 //
3335 // BUILTIN_INFO(HEXAGON.A2_vraddub_acc,DI_ftype_DIDIDI,3)
3336 //
3337 def int_hexagon_A2_vraddub_acc :
3338 Hexagon_di_dididi_Intrinsic<"HEXAGON_A2_vraddub_acc">;
3339 //
3340 // BUILTIN_INFO(HEXAGON.M2_vraddh,SI_ftype_DIDI,2)
3341 //
3342 def int_hexagon_M2_vraddh :
3343 Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vraddh">;
3344 //
3345 // BUILTIN_INFO(HEXAGON.M2_vradduh,SI_ftype_DIDI,2)
3346 //
3347 def int_hexagon_M2_vradduh :
3348 Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vradduh">;
3349 //
3350 // BUILTIN_INFO(HEXAGON.A2_vsubub,DI_ftype_DIDI,2)
3351 //
3352 def int_hexagon_A2_vsubub :
3353 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubub">;
3354 //
3355 // BUILTIN_INFO(HEXAGON.A2_vsubb_map,DI_ftype_DIDI,2)
3356 //
3357 def int_hexagon_A2_vsubb_map :
3358 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubb_map">;
3359 //
3360 // BUILTIN_INFO(HEXAGON.A2_vsububs,DI_ftype_DIDI,2)
3361 //
3362 def int_hexagon_A2_vsububs :
3363 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsububs">;
3364 //
3365 // BUILTIN_INFO(HEXAGON.A2_vsubh,DI_ftype_DIDI,2)
3366 //
3367 def int_hexagon_A2_vsubh :
3368 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubh">;
3369 //
3370 // BUILTIN_INFO(HEXAGON.A2_vsubhs,DI_ftype_DIDI,2)
3371 //
3372 def int_hexagon_A2_vsubhs :
3373 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubhs">;
3374 //
3375 // BUILTIN_INFO(HEXAGON.A2_vsubuhs,DI_ftype_DIDI,2)
3376 //
3377 def int_hexagon_A2_vsubuhs :
3378 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubuhs">;
3379 //
3380 // BUILTIN_INFO(HEXAGON.A2_vsubw,DI_ftype_DIDI,2)
3381 //
3382 def int_hexagon_A2_vsubw :
3383 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubw">;
3384 //
3385 // BUILTIN_INFO(HEXAGON.A2_vsubws,DI_ftype_DIDI,2)
3386 //
3387 def int_hexagon_A2_vsubws :
3388 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubws">;
3389 //
3390 // BUILTIN_INFO(HEXAGON.A2_vabsh,DI_ftype_DI,1)
3391 //
3392 def int_hexagon_A2_vabsh :
3393 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabsh">;
3394 //
3395 // BUILTIN_INFO(HEXAGON.A2_vabshsat,DI_ftype_DI,1)
3396 //
3397 def int_hexagon_A2_vabshsat :
3398 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabshsat">;
3399 //
3400 // BUILTIN_INFO(HEXAGON.A2_vabsw,DI_ftype_DI,1)
3401 //
3402 def int_hexagon_A2_vabsw :
3403 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabsw">;
3404 //
3405 // BUILTIN_INFO(HEXAGON.A2_vabswsat,DI_ftype_DI,1)
3406 //
3407 def int_hexagon_A2_vabswsat :
3408 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabswsat">;
3409 //
3410 // BUILTIN_INFO(HEXAGON.M2_vabsdiffw,DI_ftype_DIDI,2)
3411 //
3412 def int_hexagon_M2_vabsdiffw :
3413 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vabsdiffw">;
3414 //
3415 // BUILTIN_INFO(HEXAGON.M2_vabsdiffh,DI_ftype_DIDI,2)
3416 //
3417 def int_hexagon_M2_vabsdiffh :
3418 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vabsdiffh">;
3419 //
3420 // BUILTIN_INFO(HEXAGON.A2_vrsadub,DI_ftype_DIDI,2)
3421 //
3422 def int_hexagon_A2_vrsadub :
3423 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vrsadub">;
3424 //
3425 // BUILTIN_INFO(HEXAGON.A2_vrsadub_acc,DI_ftype_DIDIDI,3)
3426 //
3427 def int_hexagon_A2_vrsadub_acc :
3428 Hexagon_di_dididi_Intrinsic<"HEXAGON_A2_vrsadub_acc">;
3429 //
3430 // BUILTIN_INFO(HEXAGON.A2_vavgub,DI_ftype_DIDI,2)
3431 //
3432 def int_hexagon_A2_vavgub :
3433 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgub">;
3434 //
3435 // BUILTIN_INFO(HEXAGON.A2_vavguh,DI_ftype_DIDI,2)
3436 //
3437 def int_hexagon_A2_vavguh :
3438 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguh">;
3439 //
3440 // BUILTIN_INFO(HEXAGON.A2_vavgh,DI_ftype_DIDI,2)
3441 //
3442 def int_hexagon_A2_vavgh :
3443 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgh">;
3444 //
3445 // BUILTIN_INFO(HEXAGON.A2_vnavgh,DI_ftype_DIDI,2)
3446 //
3447 def int_hexagon_A2_vnavgh :
3448 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgh">;
3449 //
3450 // BUILTIN_INFO(HEXAGON.A2_vavgw,DI_ftype_DIDI,2)
3451 //
3452 def int_hexagon_A2_vavgw :
3453 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgw">;
3454 //
3455 // BUILTIN_INFO(HEXAGON.A2_vnavgw,DI_ftype_DIDI,2)
3456 //
3457 def int_hexagon_A2_vnavgw :
3458 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgw">;
3459 //
3460 // BUILTIN_INFO(HEXAGON.A2_vavgwr,DI_ftype_DIDI,2)
3461 //
3462 def int_hexagon_A2_vavgwr :
3463 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgwr">;
3464 //
3465 // BUILTIN_INFO(HEXAGON.A2_vnavgwr,DI_ftype_DIDI,2)
3466 //
3467 def int_hexagon_A2_vnavgwr :
3468 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgwr">;
3469 //
3470 // BUILTIN_INFO(HEXAGON.A2_vavgwcr,DI_ftype_DIDI,2)
3471 //
3472 def int_hexagon_A2_vavgwcr :
3473 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgwcr">;
3474 //
3475 // BUILTIN_INFO(HEXAGON.A2_vnavgwcr,DI_ftype_DIDI,2)
3476 //
3477 def int_hexagon_A2_vnavgwcr :
3478 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgwcr">;
3479 //
3480 // BUILTIN_INFO(HEXAGON.A2_vavghcr,DI_ftype_DIDI,2)
3481 //
3482 def int_hexagon_A2_vavghcr :
3483 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavghcr">;
3484 //
3485 // BUILTIN_INFO(HEXAGON.A2_vnavghcr,DI_ftype_DIDI,2)
3486 //
3487 def int_hexagon_A2_vnavghcr :
3488 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavghcr">;
3489 //
3490 // BUILTIN_INFO(HEXAGON.A2_vavguw,DI_ftype_DIDI,2)
3491 //
3492 def int_hexagon_A2_vavguw :
3493 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguw">;
3494 //
3495 // BUILTIN_INFO(HEXAGON.A2_vavguwr,DI_ftype_DIDI,2)
3496 //
3497 def int_hexagon_A2_vavguwr :
3498 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguwr">;
3499 //
3500 // BUILTIN_INFO(HEXAGON.A2_vavgubr,DI_ftype_DIDI,2)
3501 //
3502 def int_hexagon_A2_vavgubr :
3503 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgubr">;
3504 //
3505 // BUILTIN_INFO(HEXAGON.A2_vavguhr,DI_ftype_DIDI,2)
3506 //
3507 def int_hexagon_A2_vavguhr :
3508 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguhr">;
3509 //
3510 // BUILTIN_INFO(HEXAGON.A2_vavghr,DI_ftype_DIDI,2)
3511 //
3512 def int_hexagon_A2_vavghr :
3513 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavghr">;
3514 //
3515 // BUILTIN_INFO(HEXAGON.A2_vnavghr,DI_ftype_DIDI,2)
3516 //
3517 def int_hexagon_A2_vnavghr :
3518 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavghr">;
3519 //
3520 // BUILTIN_INFO(HEXAGON.A4_round_ri,SI_ftype_SISI,2)
3521 //
3522 def int_hexagon_A4_round_ri :
3523 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_ri">;
3524 //
3525 // BUILTIN_INFO(HEXAGON.A4_round_rr,SI_ftype_SISI,2)
3526 //
3527 def int_hexagon_A4_round_rr :
3528 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_rr">;
3529 //
3530 // BUILTIN_INFO(HEXAGON.A4_round_ri_sat,SI_ftype_SISI,2)
3531 //
3532 def int_hexagon_A4_round_ri_sat :
3533 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_ri_sat">;
3534 //
3535 // BUILTIN_INFO(HEXAGON.A4_round_rr_sat,SI_ftype_SISI,2)
3536 //
3537 def int_hexagon_A4_round_rr_sat :
3538 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_rr_sat">;
3539 //
3540 // BUILTIN_INFO(HEXAGON.A4_cround_ri,SI_ftype_SISI,2)
3541 //
3542 def int_hexagon_A4_cround_ri :
3543 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cround_ri">;
3544 //
3545 // BUILTIN_INFO(HEXAGON.A4_cround_rr,SI_ftype_SISI,2)
3546 //
3547 def int_hexagon_A4_cround_rr :
3548 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cround_rr">;
3549 //
3550 // BUILTIN_INFO(HEXAGON.A4_vrminh,DI_ftype_DIDISI,3)
3551 //
3552 def int_hexagon_A4_vrminh :
3553 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminh">;
3554 //
3555 // BUILTIN_INFO(HEXAGON.A4_vrmaxh,DI_ftype_DIDISI,3)
3556 //
3557 def int_hexagon_A4_vrmaxh :
3558 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxh">;
3559 //
3560 // BUILTIN_INFO(HEXAGON.A4_vrminuh,DI_ftype_DIDISI,3)
3561 //
3562 def int_hexagon_A4_vrminuh :
3563 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminuh">;
3564 //
3565 // BUILTIN_INFO(HEXAGON.A4_vrmaxuh,DI_ftype_DIDISI,3)
3566 //
3567 def int_hexagon_A4_vrmaxuh :
3568 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxuh">;
3569 //
3570 // BUILTIN_INFO(HEXAGON.A4_vrminw,DI_ftype_DIDISI,3)
3571 //
3572 def int_hexagon_A4_vrminw :
3573 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminw">;
3574 //
3575 // BUILTIN_INFO(HEXAGON.A4_vrmaxw,DI_ftype_DIDISI,3)
3576 //
3577 def int_hexagon_A4_vrmaxw :
3578 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxw">;
3579 //
3580 // BUILTIN_INFO(HEXAGON.A4_vrminuw,DI_ftype_DIDISI,3)
3581 //
3582 def int_hexagon_A4_vrminuw :
3583 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminuw">;
3584 //
3585 // BUILTIN_INFO(HEXAGON.A4_vrmaxuw,DI_ftype_DIDISI,3)
3586 //
3587 def int_hexagon_A4_vrmaxuw :
3588 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxuw">;
3589 //
3590 // BUILTIN_INFO(HEXAGON.A2_vminb,DI_ftype_DIDI,2)
3591 //
3592 def int_hexagon_A2_vminb :
3593 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminb">;
3594 //
3595 // BUILTIN_INFO(HEXAGON.A2_vmaxb,DI_ftype_DIDI,2)
3596 //
3597 def int_hexagon_A2_vmaxb :
3598 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxb">;
3599 //
3600 // BUILTIN_INFO(HEXAGON.A2_vminub,DI_ftype_DIDI,2)
3601 //
3602 def int_hexagon_A2_vminub :
3603 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminub">;
3604 //
3605 // BUILTIN_INFO(HEXAGON.A2_vmaxub,DI_ftype_DIDI,2)
3606 //
3607 def int_hexagon_A2_vmaxub :
3608 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxub">;
3609 //
3610 // BUILTIN_INFO(HEXAGON.A2_vminh,DI_ftype_DIDI,2)
3611 //
3612 def int_hexagon_A2_vminh :
3613 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminh">;
3614 //
3615 // BUILTIN_INFO(HEXAGON.A2_vmaxh,DI_ftype_DIDI,2)
3616 //
3617 def int_hexagon_A2_vmaxh :
3618 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxh">;
3619 //
3620 // BUILTIN_INFO(HEXAGON.A2_vminuh,DI_ftype_DIDI,2)
3621 //
3622 def int_hexagon_A2_vminuh :
3623 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminuh">;
3624 //
3625 // BUILTIN_INFO(HEXAGON.A2_vmaxuh,DI_ftype_DIDI,2)
3626 //
3627 def int_hexagon_A2_vmaxuh :
3628 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxuh">;
3629 //
3630 // BUILTIN_INFO(HEXAGON.A2_vminw,DI_ftype_DIDI,2)
3631 //
3632 def int_hexagon_A2_vminw :
3633 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminw">;
3634 //
3635 // BUILTIN_INFO(HEXAGON.A2_vmaxw,DI_ftype_DIDI,2)
3636 //
3637 def int_hexagon_A2_vmaxw :
3638 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxw">;
3639 //
3640 // BUILTIN_INFO(HEXAGON.A2_vminuw,DI_ftype_DIDI,2)
3641 //
3642 def int_hexagon_A2_vminuw :
3643 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminuw">;
3644 //
3645 // BUILTIN_INFO(HEXAGON.A2_vmaxuw,DI_ftype_DIDI,2)
3646 //
3647 def int_hexagon_A2_vmaxuw :
3648 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxuw">;
3649 //
3650 // BUILTIN_INFO(HEXAGON.A4_modwrapu,SI_ftype_SISI,2)
3651 //
3652 def int_hexagon_A4_modwrapu :
3653 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_modwrapu">;
3654 //
3655 // BUILTIN_INFO(HEXAGON.F2_sfadd,SF_ftype_SFSF,2)
3656 //
3657 def int_hexagon_F2_sfadd :
3658 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfadd">;
3659 //
3660 // BUILTIN_INFO(HEXAGON.F2_sfsub,SF_ftype_SFSF,2)
3661 //
3662 def int_hexagon_F2_sfsub :
3663 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfsub">;
3664 //
3665 // BUILTIN_INFO(HEXAGON.F2_sfmpy,SF_ftype_SFSF,2)
3666 //
3667 def int_hexagon_F2_sfmpy :
3668 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmpy">;
3669 //
3670 // BUILTIN_INFO(HEXAGON.F2_sffma,SF_ftype_SFSFSF,3)
3671 //
3672 def int_hexagon_F2_sffma :
3673 Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffma">;
3674 //
3675 // BUILTIN_INFO(HEXAGON.F2_sffma_sc,SF_ftype_SFSFSFQI,4)
3676 //
3677 def int_hexagon_F2_sffma_sc :
3678 Hexagon_sf_sfsfsfqi_Intrinsic<"HEXAGON_F2_sffma_sc">;
3679 //
3680 // BUILTIN_INFO(HEXAGON.F2_sffms,SF_ftype_SFSFSF,3)
3681 //
3682 def int_hexagon_F2_sffms :
3683 Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms">;
3684 //
3685 // BUILTIN_INFO(HEXAGON.F2_sffma_lib,SF_ftype_SFSFSF,3)
3686 //
3687 def int_hexagon_F2_sffma_lib :
3688 Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffma_lib">;
3689 //
3690 // BUILTIN_INFO(HEXAGON.F2_sffms_lib,SF_ftype_SFSFSF,3)
3691 //
3692 def int_hexagon_F2_sffms_lib :
3693 Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms_lib">;
3694 //
3695 // BUILTIN_INFO(HEXAGON.F2_sfcmpeq,QI_ftype_SFSF,2)
3696 //
3697 def int_hexagon_F2_sfcmpeq :
3698 Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpeq">;
3699 //
3700 // BUILTIN_INFO(HEXAGON.F2_sfcmpgt,QI_ftype_SFSF,2)
3701 //
3702 def int_hexagon_F2_sfcmpgt :
3703 Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpgt">;
3704 //
3705 // BUILTIN_INFO(HEXAGON.F2_sfcmpge,QI_ftype_SFSF,2)
3706 //
3707 def int_hexagon_F2_sfcmpge :
3708 Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpge">;
3709 //
3710 // BUILTIN_INFO(HEXAGON.F2_sfcmpuo,QI_ftype_SFSF,2)
3711 //
3712 def int_hexagon_F2_sfcmpuo :
3713 Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpuo">;
3714 //
3715 // BUILTIN_INFO(HEXAGON.F2_sfmax,SF_ftype_SFSF,2)
3716 //
3717 def int_hexagon_F2_sfmax :
3718 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmax">;
3719 //
3720 // BUILTIN_INFO(HEXAGON.F2_sfmin,SF_ftype_SFSF,2)
3721 //
3722 def int_hexagon_F2_sfmin :
3723 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmin">;
3724 //
3725 // BUILTIN_INFO(HEXAGON.F2_sfclass,QI_ftype_SFSI,2)
3726 //
3727 def int_hexagon_F2_sfclass :
3728 Hexagon_si_sfsi_Intrinsic<"HEXAGON_F2_sfclass">;
3729 //
3730 // BUILTIN_INFO(HEXAGON.F2_sfimm_p,SF_ftype_SI,1)
3731 //
3732 def int_hexagon_F2_sfimm_p :
3733 Hexagon_sf_si_Intrinsic<"HEXAGON_F2_sfimm_p">;
3734 //
3735 // BUILTIN_INFO(HEXAGON.F2_sfimm_n,SF_ftype_SI,1)
3736 //
3737 def int_hexagon_F2_sfimm_n :
3738 Hexagon_sf_si_Intrinsic<"HEXAGON_F2_sfimm_n">;
3739 //
3740 // BUILTIN_INFO(HEXAGON.F2_sffixupn,SF_ftype_SFSF,2)
3741 //
3742 def int_hexagon_F2_sffixupn :
3743 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sffixupn">;
3744 //
3745 // BUILTIN_INFO(HEXAGON.F2_sffixupd,SF_ftype_SFSF,2)
3746 //
3747 def int_hexagon_F2_sffixupd :
3748 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sffixupd">;
3749 //
3750 // BUILTIN_INFO(HEXAGON.F2_sffixupr,SF_ftype_SF,1)
3751 //
3752 def int_hexagon_F2_sffixupr :
3753 Hexagon_sf_sf_Intrinsic<"HEXAGON_F2_sffixupr">;
3754 //
3755 // BUILTIN_INFO(HEXAGON.F2_dfcmpeq,QI_ftype_DFDF,2)
3756 //
3757 def int_hexagon_F2_dfcmpeq :
3758 Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpeq">;
3759 //
3760 // BUILTIN_INFO(HEXAGON.F2_dfcmpgt,QI_ftype_DFDF,2)
3761 //
3762 def int_hexagon_F2_dfcmpgt :
3763 Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpgt">;
3764 //
3765 // BUILTIN_INFO(HEXAGON.F2_dfcmpge,QI_ftype_DFDF,2)
3766 //
3767 def int_hexagon_F2_dfcmpge :
3768 Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpge">;
3769 //
3770 // BUILTIN_INFO(HEXAGON.F2_dfcmpuo,QI_ftype_DFDF,2)
3771 //
3772 def int_hexagon_F2_dfcmpuo :
3773 Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpuo">;
3774 //
3775 // BUILTIN_INFO(HEXAGON.F2_dfclass,QI_ftype_DFSI,2)
3776 //
3777 def int_hexagon_F2_dfclass :
3778 Hexagon_si_dfsi_Intrinsic<"HEXAGON_F2_dfclass">;
3779 //
3780 // BUILTIN_INFO(HEXAGON.F2_dfimm_p,DF_ftype_SI,1)
3781 //
3782 def int_hexagon_F2_dfimm_p :
3783 Hexagon_df_si_Intrinsic<"HEXAGON_F2_dfimm_p">;
3784 //
3785 // BUILTIN_INFO(HEXAGON.F2_dfimm_n,DF_ftype_SI,1)
3786 //
3787 def int_hexagon_F2_dfimm_n :
3788 Hexagon_df_si_Intrinsic<"HEXAGON_F2_dfimm_n">;
3789 //
3790 // BUILTIN_INFO(HEXAGON.F2_conv_sf2df,DF_ftype_SF,1)
3791 //
3792 def int_hexagon_F2_conv_sf2df :
3793 Hexagon_df_sf_Intrinsic<"HEXAGON_F2_conv_sf2df">;
3794 //
3795 // BUILTIN_INFO(HEXAGON.F2_conv_df2sf,SF_ftype_DF,1)
3796 //
3797 def int_hexagon_F2_conv_df2sf :
3798 Hexagon_sf_df_Intrinsic<"HEXAGON_F2_conv_df2sf">;
3799 //
3800 // BUILTIN_INFO(HEXAGON.F2_conv_uw2sf,SF_ftype_SI,1)
3801 //
3802 def int_hexagon_F2_conv_uw2sf :
3803 Hexagon_sf_si_Intrinsic<"HEXAGON_F2_conv_uw2sf">;
3804 //
3805 // BUILTIN_INFO(HEXAGON.F2_conv_uw2df,DF_ftype_SI,1)
3806 //
3807 def int_hexagon_F2_conv_uw2df :
3808 Hexagon_df_si_Intrinsic<"HEXAGON_F2_conv_uw2df">;
3809 //
3810 // BUILTIN_INFO(HEXAGON.F2_conv_w2sf,SF_ftype_SI,1)
3811 //
3812 def int_hexagon_F2_conv_w2sf :
3813 Hexagon_sf_si_Intrinsic<"HEXAGON_F2_conv_w2sf">;
3814 //
3815 // BUILTIN_INFO(HEXAGON.F2_conv_w2df,DF_ftype_SI,1)
3816 //
3817 def int_hexagon_F2_conv_w2df :
3818 Hexagon_df_si_Intrinsic<"HEXAGON_F2_conv_w2df">;
3819 //
3820 // BUILTIN_INFO(HEXAGON.F2_conv_ud2sf,SF_ftype_DI,1)
3821 //
3822 def int_hexagon_F2_conv_ud2sf :
3823 Hexagon_sf_di_Intrinsic<"HEXAGON_F2_conv_ud2sf">;
3824 //
3825 // BUILTIN_INFO(HEXAGON.F2_conv_ud2df,DF_ftype_DI,1)
3826 //
3827 def int_hexagon_F2_conv_ud2df :
3828 Hexagon_df_di_Intrinsic<"HEXAGON_F2_conv_ud2df">;
3829 //
3830 // BUILTIN_INFO(HEXAGON.F2_conv_d2sf,SF_ftype_DI,1)
3831 //
3832 def int_hexagon_F2_conv_d2sf :
3833 Hexagon_sf_di_Intrinsic<"HEXAGON_F2_conv_d2sf">;
3834 //
3835 // BUILTIN_INFO(HEXAGON.F2_conv_d2df,DF_ftype_DI,1)
3836 //
3837 def int_hexagon_F2_conv_d2df :
3838 Hexagon_df_di_Intrinsic<"HEXAGON_F2_conv_d2df">;
3839 //
3840 // BUILTIN_INFO(HEXAGON.F2_conv_sf2uw,SI_ftype_SF,1)
3841 //
3842 def int_hexagon_F2_conv_sf2uw :
3843 Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2uw">;
3844 //
3845 // BUILTIN_INFO(HEXAGON.F2_conv_sf2w,SI_ftype_SF,1)
3846 //
3847 def int_hexagon_F2_conv_sf2w :
3848 Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2w">;
3849 //
3850 // BUILTIN_INFO(HEXAGON.F2_conv_sf2ud,DI_ftype_SF,1)
3851 //
3852 def int_hexagon_F2_conv_sf2ud :
3853 Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2ud">;
3854 //
3855 // BUILTIN_INFO(HEXAGON.F2_conv_sf2d,DI_ftype_SF,1)
3856 //
3857 def int_hexagon_F2_conv_sf2d :
3858 Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2d">;
3859 //
3860 // BUILTIN_INFO(HEXAGON.F2_conv_df2uw,SI_ftype_DF,1)
3861 //
3862 def int_hexagon_F2_conv_df2uw :
3863 Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2uw">;
3864 //
3865 // BUILTIN_INFO(HEXAGON.F2_conv_df2w,SI_ftype_DF,1)
3866 //
3867 def int_hexagon_F2_conv_df2w :
3868 Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2w">;
3869 //
3870 // BUILTIN_INFO(HEXAGON.F2_conv_df2ud,DI_ftype_DF,1)
3871 //
3872 def int_hexagon_F2_conv_df2ud :
3873 Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2ud">;
3874 //
3875 // BUILTIN_INFO(HEXAGON.F2_conv_df2d,DI_ftype_DF,1)
3876 //
3877 def int_hexagon_F2_conv_df2d :
3878 Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2d">;
3879 //
3880 // BUILTIN_INFO(HEXAGON.F2_conv_sf2uw_chop,SI_ftype_SF,1)
3881 //
3882 def int_hexagon_F2_conv_sf2uw_chop :
3883 Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">;
3884 //
3885 // BUILTIN_INFO(HEXAGON.F2_conv_sf2w_chop,SI_ftype_SF,1)
3886 //
3887 def int_hexagon_F2_conv_sf2w_chop :
3888 Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">;
3889 //
3890 // BUILTIN_INFO(HEXAGON.F2_conv_sf2ud_chop,DI_ftype_SF,1)
3891 //
3892 def int_hexagon_F2_conv_sf2ud_chop :
3893 Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;
3894 //
3895 // BUILTIN_INFO(HEXAGON.F2_conv_sf2d_chop,DI_ftype_SF,1)
3896 //
3897 def int_hexagon_F2_conv_sf2d_chop :
3898 Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">;
3899 //
3900 // BUILTIN_INFO(HEXAGON.F2_conv_df2uw_chop,SI_ftype_DF,1)
3901 //
3902 def int_hexagon_F2_conv_df2uw_chop :
3903 Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;
3904 //
3905 // BUILTIN_INFO(HEXAGON.F2_conv_df2w_chop,SI_ftype_DF,1)
3906 //
3907 def int_hexagon_F2_conv_df2w_chop :
3908 Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2w_chop">;
3909 //
3910 // BUILTIN_INFO(HEXAGON.F2_conv_df2ud_chop,DI_ftype_DF,1)
3911 //
3912 def int_hexagon_F2_conv_df2ud_chop :
3913 Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;
3914 //
3915 // BUILTIN_INFO(HEXAGON.F2_conv_df2d_chop,DI_ftype_DF,1)
3916 //
3917 def int_hexagon_F2_conv_df2d_chop :
3918 Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;
3919 //
3920 // BUILTIN_INFO(HEXAGON.S2_asr_r_r,SI_ftype_SISI,2)
3921 //
3922 def int_hexagon_S2_asr_r_r :
3923 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_r_r">;
3924 //
3925 // BUILTIN_INFO(HEXAGON.S2_asl_r_r,SI_ftype_SISI,2)
3926 //
3927 def int_hexagon_S2_asl_r_r :
3928 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_r_r">;
3929 //
3930 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r,SI_ftype_SISI,2)
3931 //
3932 def int_hexagon_S2_lsr_r_r :
3933 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsr_r_r">;
3934 //
3935 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r,SI_ftype_SISI,2)
3936 //
3937 def int_hexagon_S2_lsl_r_r :
3938 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsl_r_r">;
3939 //
3940 // BUILTIN_INFO(HEXAGON.S2_asr_r_p,DI_ftype_DISI,2)
3941 //
3942 def int_hexagon_S2_asr_r_p :
3943 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_p">;
3944 //
3945 // BUILTIN_INFO(HEXAGON.S2_asl_r_p,DI_ftype_DISI,2)
3946 //
3947 def int_hexagon_S2_asl_r_p :
3948 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_p">;
3949 //
3950 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p,DI_ftype_DISI,2)
3951 //
3952 def int_hexagon_S2_lsr_r_p :
3953 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_p">;
3954 //
3955 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p,DI_ftype_DISI,2)
3956 //
3957 def int_hexagon_S2_lsl_r_p :
3958 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_p">;
3959 //
3960 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_acc,SI_ftype_SISISI,3)
3961 //
3962 def int_hexagon_S2_asr_r_r_acc :
3963 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;
3964 //
3965 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_acc,SI_ftype_SISISI,3)
3966 //
3967 def int_hexagon_S2_asl_r_r_acc :
3968 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;
3969 //
3970 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_acc,SI_ftype_SISISI,3)
3971 //
3972 def int_hexagon_S2_lsr_r_r_acc :
3973 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;
3974 //
3975 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_acc,SI_ftype_SISISI,3)
3976 //
3977 def int_hexagon_S2_lsl_r_r_acc :
3978 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;
3979 //
3980 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_acc,DI_ftype_DIDISI,3)
3981 //
3982 def int_hexagon_S2_asr_r_p_acc :
3983 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_acc">;
3984 //
3985 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_acc,DI_ftype_DIDISI,3)
3986 //
3987 def int_hexagon_S2_asl_r_p_acc :
3988 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;
3989 //
3990 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_acc,DI_ftype_DIDISI,3)
3991 //
3992 def int_hexagon_S2_lsr_r_p_acc :
3993 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;
3994 //
3995 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_acc,DI_ftype_DIDISI,3)
3996 //
3997 def int_hexagon_S2_lsl_r_p_acc :
3998 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;
3999 //
4000 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_nac,SI_ftype_SISISI,3)
4001 //
4002 def int_hexagon_S2_asr_r_r_nac :
4003 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;
4004 //
4005 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_nac,SI_ftype_SISISI,3)
4006 //
4007 def int_hexagon_S2_asl_r_r_nac :
4008 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;
4009 //
4010 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_nac,SI_ftype_SISISI,3)
4011 //
4012 def int_hexagon_S2_lsr_r_r_nac :
4013 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;
4014 //
4015 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_nac,SI_ftype_SISISI,3)
4016 //
4017 def int_hexagon_S2_lsl_r_r_nac :
4018 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;
4019 //
4020 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_nac,DI_ftype_DIDISI,3)
4021 //
4022 def int_hexagon_S2_asr_r_p_nac :
4023 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;
4024 //
4025 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_nac,DI_ftype_DIDISI,3)
4026 //
4027 def int_hexagon_S2_asl_r_p_nac :
4028 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;
4029 //
4030 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_nac,DI_ftype_DIDISI,3)
4031 //
4032 def int_hexagon_S2_lsr_r_p_nac :
4033 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;
4034 //
4035 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_nac,DI_ftype_DIDISI,3)
4036 //
4037 def int_hexagon_S2_lsl_r_p_nac :
4038 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;
4039 //
4040 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_and,SI_ftype_SISISI,3)
4041 //
4042 def int_hexagon_S2_asr_r_r_and :
4043 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_and">;
4044 //
4045 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_and,SI_ftype_SISISI,3)
4046 //
4047 def int_hexagon_S2_asl_r_r_and :
4048 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_and">;
4049 //
4050 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_and,SI_ftype_SISISI,3)
4051 //
4052 def int_hexagon_S2_lsr_r_r_and :
4053 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;
4054 //
4055 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_and,SI_ftype_SISISI,3)
4056 //
4057 def int_hexagon_S2_lsl_r_r_and :
4058 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;
4059 //
4060 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_or,SI_ftype_SISISI,3)
4061 //
4062 def int_hexagon_S2_asr_r_r_or :
4063 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_or">;
4064 //
4065 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_or,SI_ftype_SISISI,3)
4066 //
4067 def int_hexagon_S2_asl_r_r_or :
4068 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_or">;
4069 //
4070 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_or,SI_ftype_SISISI,3)
4071 //
4072 def int_hexagon_S2_lsr_r_r_or :
4073 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;
4074 //
4075 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_or,SI_ftype_SISISI,3)
4076 //
4077 def int_hexagon_S2_lsl_r_r_or :
4078 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;
4079 //
4080 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_and,DI_ftype_DIDISI,3)
4081 //
4082 def int_hexagon_S2_asr_r_p_and :
4083 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_and">;
4084 //
4085 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_and,DI_ftype_DIDISI,3)
4086 //
4087 def int_hexagon_S2_asl_r_p_and :
4088 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_and">;
4089 //
4090 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_and,DI_ftype_DIDISI,3)
4091 //
4092 def int_hexagon_S2_lsr_r_p_and :
4093 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_and">;
4094 //
4095 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_and,DI_ftype_DIDISI,3)
4096 //
4097 def int_hexagon_S2_lsl_r_p_and :
4098 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;
4099 //
4100 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_or,DI_ftype_DIDISI,3)
4101 //
4102 def int_hexagon_S2_asr_r_p_or :
4103 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_or">;
4104 //
4105 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_or,DI_ftype_DIDISI,3)
4106 //
4107 def int_hexagon_S2_asl_r_p_or :
4108 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_or">;
4109 //
4110 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_or,DI_ftype_DIDISI,3)
4111 //
4112 def int_hexagon_S2_lsr_r_p_or :
4113 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;
4114 //
4115 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_or,DI_ftype_DIDISI,3)
4116 //
4117 def int_hexagon_S2_lsl_r_p_or :
4118 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;
4119 //
4120 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_xor,DI_ftype_DIDISI,3)
4121 //
4122 def int_hexagon_S2_asr_r_p_xor :
4123 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;
4124 //
4125 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_xor,DI_ftype_DIDISI,3)
4126 //
4127 def int_hexagon_S2_asl_r_p_xor :
4128 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;
4129 //
4130 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_xor,DI_ftype_DIDISI,3)
4131 //
4132 def int_hexagon_S2_lsr_r_p_xor :
4133 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;
4134 //
4135 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_xor,DI_ftype_DIDISI,3)
4136 //
4137 def int_hexagon_S2_lsl_r_p_xor :
4138 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;
4139 //
4140 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_sat,SI_ftype_SISI,2)
4141 //
4142 def int_hexagon_S2_asr_r_r_sat :
4143 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;
4144 //
4145 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_sat,SI_ftype_SISI,2)
4146 //
4147 def int_hexagon_S2_asl_r_r_sat :
4148 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_r_r_sat">;
4149 //
4150 // BUILTIN_INFO(HEXAGON.S2_asr_i_r,SI_ftype_SISI,2)
4151 //
4152 def int_hexagon_S2_asr_i_r :
4153 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r">;
4154 //
4155 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r,SI_ftype_SISI,2)
4156 //
4157 def int_hexagon_S2_lsr_i_r :
4158 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsr_i_r">;
4159 //
4160 // BUILTIN_INFO(HEXAGON.S2_asl_i_r,SI_ftype_SISI,2)
4161 //
4162 def int_hexagon_S2_asl_i_r :
4163 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_i_r">;
4164 //
4165 // BUILTIN_INFO(HEXAGON.S2_asr_i_p,DI_ftype_DISI,2)
4166 //
4167 def int_hexagon_S2_asr_i_p :
4168 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p">;
4169 //
4170 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p,DI_ftype_DISI,2)
4171 //
4172 def int_hexagon_S2_lsr_i_p :
4173 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_p">;
4174 //
4175 // BUILTIN_INFO(HEXAGON.S2_asl_i_p,DI_ftype_DISI,2)
4176 //
4177 def int_hexagon_S2_asl_i_p :
4178 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_p">;
4179 //
4180 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_acc,SI_ftype_SISISI,3)
4181 //
4182 def int_hexagon_S2_asr_i_r_acc :
4183 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_acc">;
4184 //
4185 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_acc,SI_ftype_SISISI,3)
4186 //
4187 def int_hexagon_S2_lsr_i_r_acc :
4188 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_acc">;
4189 //
4190 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_acc,SI_ftype_SISISI,3)
4191 //
4192 def int_hexagon_S2_asl_i_r_acc :
4193 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_acc">;
4194 //
4195 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_acc,DI_ftype_DIDISI,3)
4196 //
4197 def int_hexagon_S2_asr_i_p_acc :
4198 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_acc">;
4199 //
4200 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_acc,DI_ftype_DIDISI,3)
4201 //
4202 def int_hexagon_S2_lsr_i_p_acc :
4203 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_acc">;
4204 //
4205 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_acc,DI_ftype_DIDISI,3)
4206 //
4207 def int_hexagon_S2_asl_i_p_acc :
4208 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_acc">;
4209 //
4210 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_nac,SI_ftype_SISISI,3)
4211 //
4212 def int_hexagon_S2_asr_i_r_nac :
4213 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_nac">;
4214 //
4215 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_nac,SI_ftype_SISISI,3)
4216 //
4217 def int_hexagon_S2_lsr_i_r_nac :
4218 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_nac">;
4219 //
4220 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_nac,SI_ftype_SISISI,3)
4221 //
4222 def int_hexagon_S2_asl_i_r_nac :
4223 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_nac">;
4224 //
4225 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_nac,DI_ftype_DIDISI,3)
4226 //
4227 def int_hexagon_S2_asr_i_p_nac :
4228 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_nac">;
4229 //
4230 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_nac,DI_ftype_DIDISI,3)
4231 //
4232 def int_hexagon_S2_lsr_i_p_nac :
4233 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_nac">;
4234 //
4235 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_nac,DI_ftype_DIDISI,3)
4236 //
4237 def int_hexagon_S2_asl_i_p_nac :
4238 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_nac">;
4239 //
4240 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_xacc,SI_ftype_SISISI,3)
4241 //
4242 def int_hexagon_S2_lsr_i_r_xacc :
4243 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc">;
4244 //
4245 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_xacc,SI_ftype_SISISI,3)
4246 //
4247 def int_hexagon_S2_asl_i_r_xacc :
4248 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_xacc">;
4249 //
4250 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_xacc,DI_ftype_DIDISI,3)
4251 //
4252 def int_hexagon_S2_lsr_i_p_xacc :
4253 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc">;
4254 //
4255 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_xacc,DI_ftype_DIDISI,3)
4256 //
4257 def int_hexagon_S2_asl_i_p_xacc :
4258 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_xacc">;
4259 //
4260 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_and,SI_ftype_SISISI,3)
4261 //
4262 def int_hexagon_S2_asr_i_r_and :
4263 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_and">;
4264 //
4265 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_and,SI_ftype_SISISI,3)
4266 //
4267 def int_hexagon_S2_lsr_i_r_and :
4268 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_and">;
4269 //
4270 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_and,SI_ftype_SISISI,3)
4271 //
4272 def int_hexagon_S2_asl_i_r_and :
4273 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_and">;
4274 //
4275 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_or,SI_ftype_SISISI,3)
4276 //
4277 def int_hexagon_S2_asr_i_r_or :
4278 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_or">;
4279 //
4280 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_or,SI_ftype_SISISI,3)
4281 //
4282 def int_hexagon_S2_lsr_i_r_or :
4283 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_or">;
4284 //
4285 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_or,SI_ftype_SISISI,3)
4286 //
4287 def int_hexagon_S2_asl_i_r_or :
4288 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_or">;
4289 //
4290 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_and,DI_ftype_DIDISI,3)
4291 //
4292 def int_hexagon_S2_asr_i_p_and :
4293 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_and">;
4294 //
4295 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_and,DI_ftype_DIDISI,3)
4296 //
4297 def int_hexagon_S2_lsr_i_p_and :
4298 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_and">;
4299 //
4300 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_and,DI_ftype_DIDISI,3)
4301 //
4302 def int_hexagon_S2_asl_i_p_and :
4303 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_and">;
4304 //
4305 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_or,DI_ftype_DIDISI,3)
4306 //
4307 def int_hexagon_S2_asr_i_p_or :
4308 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_or">;
4309 //
4310 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_or,DI_ftype_DIDISI,3)
4311 //
4312 def int_hexagon_S2_lsr_i_p_or :
4313 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_or">;
4314 //
4315 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_or,DI_ftype_DIDISI,3)
4316 //
4317 def int_hexagon_S2_asl_i_p_or :
4318 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_or">;
4319 //
4320 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_sat,SI_ftype_SISI,2)
4321 //
4322 def int_hexagon_S2_asl_i_r_sat :
4323 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_i_r_sat">;
4324 //
4325 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd,SI_ftype_SISI,2)
4326 //
4327 def int_hexagon_S2_asr_i_r_rnd :
4328 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r_rnd">;
4329 //
4330 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd_goodsyntax,SI_ftype_SISI,2)
4331 //
4332 def int_hexagon_S2_asr_i_r_rnd_goodsyntax :
4333 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax">;
4334 //
4335 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_rnd,DI_ftype_DISI,2)
4336 //
4337 def int_hexagon_S2_asr_i_p_rnd :
4338 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p_rnd">;
4339 //
4340 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_rnd_goodsyntax,DI_ftype_DISI,2)
4341 //
4342 def int_hexagon_S2_asr_i_p_rnd_goodsyntax :
4343 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax">;
4344 //
4345 // BUILTIN_INFO(HEXAGON.S4_lsli,SI_ftype_SISI,2)
4346 //
4347 def int_hexagon_S4_lsli :
4348 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_lsli">;
4349 //
4350 // BUILTIN_INFO(HEXAGON.S2_addasl_rrri,SI_ftype_SISISI,3)
4351 //
4352 def int_hexagon_S2_addasl_rrri :
4353 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_addasl_rrri">;
4354 //
4355 // BUILTIN_INFO(HEXAGON.S4_andi_asl_ri,SI_ftype_SISISI,3)
4356 //
4357 def int_hexagon_S4_andi_asl_ri :
4358 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_andi_asl_ri">;
4359 //
4360 // BUILTIN_INFO(HEXAGON.S4_ori_asl_ri,SI_ftype_SISISI,3)
4361 //
4362 def int_hexagon_S4_ori_asl_ri :
4363 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_ori_asl_ri">;
4364 //
4365 // BUILTIN_INFO(HEXAGON.S4_addi_asl_ri,SI_ftype_SISISI,3)
4366 //
4367 def int_hexagon_S4_addi_asl_ri :
4368 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addi_asl_ri">;
4369 //
4370 // BUILTIN_INFO(HEXAGON.S4_subi_asl_ri,SI_ftype_SISISI,3)
4371 //
4372 def int_hexagon_S4_subi_asl_ri :
4373 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subi_asl_ri">;
4374 //
4375 // BUILTIN_INFO(HEXAGON.S4_andi_lsr_ri,SI_ftype_SISISI,3)
4376 //
4377 def int_hexagon_S4_andi_lsr_ri :
4378 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_andi_lsr_ri">;
4379 //
4380 // BUILTIN_INFO(HEXAGON.S4_ori_lsr_ri,SI_ftype_SISISI,3)
4381 //
4382 def int_hexagon_S4_ori_lsr_ri :
4383 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_ori_lsr_ri">;
4384 //
4385 // BUILTIN_INFO(HEXAGON.S4_addi_lsr_ri,SI_ftype_SISISI,3)
4386 //
4387 def int_hexagon_S4_addi_lsr_ri :
4388 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addi_lsr_ri">;
4389 //
4390 // BUILTIN_INFO(HEXAGON.S4_subi_lsr_ri,SI_ftype_SISISI,3)
4391 //
4392 def int_hexagon_S4_subi_lsr_ri :
4393 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subi_lsr_ri">;
4394 //
4395 // BUILTIN_INFO(HEXAGON.S2_valignib,DI_ftype_DIDISI,3)
4396 //
4397 def int_hexagon_S2_valignib :
4398 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_valignib">;
4399 //
4400 // BUILTIN_INFO(HEXAGON.S2_valignrb,DI_ftype_DIDIQI,3)
4401 //
4402 def int_hexagon_S2_valignrb :
4403 Hexagon_di_didiqi_Intrinsic<"HEXAGON_S2_valignrb">;
4404 //
4405 // BUILTIN_INFO(HEXAGON.S2_vspliceib,DI_ftype_DIDISI,3)
4406 //
4407 def int_hexagon_S2_vspliceib :
4408 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_vspliceib">;
4409 //
4410 // BUILTIN_INFO(HEXAGON.S2_vsplicerb,DI_ftype_DIDIQI,3)
4411 //
4412 def int_hexagon_S2_vsplicerb :
4413 Hexagon_di_didiqi_Intrinsic<"HEXAGON_S2_vsplicerb">;
4414 //
4415 // BUILTIN_INFO(HEXAGON.S2_vsplatrh,DI_ftype_SI,1)
4416 //
4417 def int_hexagon_S2_vsplatrh :
4418 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsplatrh">;
4419 //
4420 // BUILTIN_INFO(HEXAGON.S2_vsplatrb,SI_ftype_SI,1)
4421 //
4422 def int_hexagon_S2_vsplatrb :
4423 Hexagon_si_si_Intrinsic<"HEXAGON_S2_vsplatrb">;
4424 //
4425 // BUILTIN_INFO(HEXAGON.S2_insert,SI_ftype_SISISISI,4)
4426 //
4427 def int_hexagon_S2_insert :
4428 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_insert">;
4429 //
4430 // BUILTIN_INFO(HEXAGON.S2_tableidxb_goodsyntax,SI_ftype_SISISISI,4)
4431 //
4432 def int_hexagon_S2_tableidxb_goodsyntax :
4433 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">;
4434 //
4435 // BUILTIN_INFO(HEXAGON.S2_tableidxh_goodsyntax,SI_ftype_SISISISI,4)
4436 //
4437 def int_hexagon_S2_tableidxh_goodsyntax :
4438 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">;
4439 //
4440 // BUILTIN_INFO(HEXAGON.S2_tableidxw_goodsyntax,SI_ftype_SISISISI,4)
4441 //
4442 def int_hexagon_S2_tableidxw_goodsyntax :
4443 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">;
4444 //
4445 // BUILTIN_INFO(HEXAGON.S2_tableidxd_goodsyntax,SI_ftype_SISISISI,4)
4446 //
4447 def int_hexagon_S2_tableidxd_goodsyntax :
4448 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">;
4449 //
4450 // BUILTIN_INFO(HEXAGON.A4_bitspliti,DI_ftype_SISI,2)
4451 //
4452 def int_hexagon_A4_bitspliti :
4453 Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_bitspliti">;
4454 //
4455 // BUILTIN_INFO(HEXAGON.A4_bitsplit,DI_ftype_SISI,2)
4456 //
4457 def int_hexagon_A4_bitsplit :
4458 Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_bitsplit">;
4459 //
4460 // BUILTIN_INFO(HEXAGON.S4_extract,SI_ftype_SISISI,3)
4461 //
4462 def int_hexagon_S4_extract :
4463 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_extract">;
4464 //
4465 // BUILTIN_INFO(HEXAGON.S2_extractu,SI_ftype_SISISI,3)
4466 //
4467 def int_hexagon_S2_extractu :
4468 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_extractu">;
4469 //
4470 // BUILTIN_INFO(HEXAGON.S2_insertp,DI_ftype_DIDISISI,4)
4471 //
4472 def int_hexagon_S2_insertp :
4473 Hexagon_di_didisisi_Intrinsic<"HEXAGON_S2_insertp">;
4474 //
4475 // BUILTIN_INFO(HEXAGON.S4_extractp,DI_ftype_DISISI,3)
4476 //
4477 def int_hexagon_S4_extractp :
4478 Hexagon_di_disisi_Intrinsic<"HEXAGON_S4_extractp">;
4479 //
4480 // BUILTIN_INFO(HEXAGON.S2_extractup,DI_ftype_DISISI,3)
4481 //
4482 def int_hexagon_S2_extractup :
4483 Hexagon_di_disisi_Intrinsic<"HEXAGON_S2_extractup">;
4484 //
4485 // BUILTIN_INFO(HEXAGON.S2_insert_rp,SI_ftype_SISIDI,3)
4486 //
4487 def int_hexagon_S2_insert_rp :
4488 Hexagon_si_sisidi_Intrinsic<"HEXAGON_S2_insert_rp">;
4489 //
4490 // BUILTIN_INFO(HEXAGON.S4_extract_rp,SI_ftype_SIDI,2)
4491 //
4492 def int_hexagon_S4_extract_rp :
4493 Hexagon_si_sidi_Intrinsic<"HEXAGON_S4_extract_rp">;
4494 //
4495 // BUILTIN_INFO(HEXAGON.S2_extractu_rp,SI_ftype_SIDI,2)
4496 //
4497 def int_hexagon_S2_extractu_rp :
4498 Hexagon_si_sidi_Intrinsic<"HEXAGON_S2_extractu_rp">;
4499 //
4500 // BUILTIN_INFO(HEXAGON.S2_insertp_rp,DI_ftype_DIDIDI,3)
4501 //
4502 def int_hexagon_S2_insertp_rp :
4503 Hexagon_di_dididi_Intrinsic<"HEXAGON_S2_insertp_rp">;
4504 //
4505 // BUILTIN_INFO(HEXAGON.S4_extractp_rp,DI_ftype_DIDI,2)
4506 //
4507 def int_hexagon_S4_extractp_rp :
4508 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_extractp_rp">;
4509 //
4510 // BUILTIN_INFO(HEXAGON.S2_extractup_rp,DI_ftype_DIDI,2)
4511 //
4512 def int_hexagon_S2_extractup_rp :
4513 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_extractup_rp">;
4514 //
4515 // BUILTIN_INFO(HEXAGON.S2_tstbit_i,QI_ftype_SISI,2)
4516 //
4517 def int_hexagon_S2_tstbit_i :
4518 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_tstbit_i">;
4519 //
4520 // BUILTIN_INFO(HEXAGON.S4_ntstbit_i,QI_ftype_SISI,2)
4521 //
4522 def int_hexagon_S4_ntstbit_i :
4523 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_ntstbit_i">;
4524 //
4525 // BUILTIN_INFO(HEXAGON.S2_setbit_i,SI_ftype_SISI,2)
4526 //
4527 def int_hexagon_S2_setbit_i :
4528 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_setbit_i">;
4529 //
4530 // BUILTIN_INFO(HEXAGON.S2_togglebit_i,SI_ftype_SISI,2)
4531 //
4532 def int_hexagon_S2_togglebit_i :
4533 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_togglebit_i">;
4534 //
4535 // BUILTIN_INFO(HEXAGON.S2_clrbit_i,SI_ftype_SISI,2)
4536 //
4537 def int_hexagon_S2_clrbit_i :
4538 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_i">;
4539 //
4540 // BUILTIN_INFO(HEXAGON.S2_tstbit_r,QI_ftype_SISI,2)
4541 //
4542 def int_hexagon_S2_tstbit_r :
4543 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_tstbit_r">;
4544 //
4545 // BUILTIN_INFO(HEXAGON.S4_ntstbit_r,QI_ftype_SISI,2)
4546 //
4547 def int_hexagon_S4_ntstbit_r :
4548 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_ntstbit_r">;
4549 //
4550 // BUILTIN_INFO(HEXAGON.S2_setbit_r,SI_ftype_SISI,2)
4551 //
4552 def int_hexagon_S2_setbit_r :
4553 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_setbit_r">;
4554 //
4555 // BUILTIN_INFO(HEXAGON.S2_togglebit_r,SI_ftype_SISI,2)
4556 //
4557 def int_hexagon_S2_togglebit_r :
4558 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_togglebit_r">;
4559 //
4560 // BUILTIN_INFO(HEXAGON.S2_clrbit_r,SI_ftype_SISI,2)
4561 //
4562 def int_hexagon_S2_clrbit_r :
4563 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_r">;
4564 //
4565 // BUILTIN_INFO(HEXAGON.S2_asr_i_vh,DI_ftype_DISI,2)
4566 //
4567 def int_hexagon_S2_asr_i_vh :
4568 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_vh">;
4569 //
4570 // BUILTIN_INFO(HEXAGON.S2_lsr_i_vh,DI_ftype_DISI,2)
4571 //
4572 def int_hexagon_S2_lsr_i_vh :
4573 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_vh">;
4574 //
4575 // BUILTIN_INFO(HEXAGON.S2_asl_i_vh,DI_ftype_DISI,2)
4576 //
4577 def int_hexagon_S2_asl_i_vh :
4578 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_vh">;
4579 //
4580 // BUILTIN_INFO(HEXAGON.S2_asr_r_vh,DI_ftype_DISI,2)
4581 //
4582 def int_hexagon_S2_asr_r_vh :
4583 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_vh">;
4584 //
4585 // BUILTIN_INFO(HEXAGON.S5_asrhub_rnd_sat_goodsyntax,SI_ftype_DISI,2)
4586 //
4587 def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :
4588 Hexagon_si_disi_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax">;
4589 //
4590 // BUILTIN_INFO(HEXAGON.S5_asrhub_sat,SI_ftype_DISI,2)
4591 //
4592 def int_hexagon_S5_asrhub_sat :
4593 Hexagon_si_disi_Intrinsic<"HEXAGON_S5_asrhub_sat">;
4594 //
4595 // BUILTIN_INFO(HEXAGON.S5_vasrhrnd_goodsyntax,DI_ftype_DISI,2)
4596 //
4597 def int_hexagon_S5_vasrhrnd_goodsyntax :
4598 Hexagon_di_disi_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax">;
4599 //
4600 // BUILTIN_INFO(HEXAGON.S2_asl_r_vh,DI_ftype_DISI,2)
4601 //
4602 def int_hexagon_S2_asl_r_vh :
4603 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_vh">;
4604 //
4605 // BUILTIN_INFO(HEXAGON.S2_lsr_r_vh,DI_ftype_DISI,2)
4606 //
4607 def int_hexagon_S2_lsr_r_vh :
4608 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_vh">;
4609 //
4610 // BUILTIN_INFO(HEXAGON.S2_lsl_r_vh,DI_ftype_DISI,2)
4611 //
4612 def int_hexagon_S2_lsl_r_vh :
4613 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_vh">;
4614 //
4615 // BUILTIN_INFO(HEXAGON.S2_asr_i_vw,DI_ftype_DISI,2)
4616 //
4617 def int_hexagon_S2_asr_i_vw :
4618 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_vw">;
4619 //
4620 // BUILTIN_INFO(HEXAGON.S2_asr_i_svw_trun,SI_ftype_DISI,2)
4621 //
4622 def int_hexagon_S2_asr_i_svw_trun :
4623 Hexagon_si_disi_Intrinsic<"HEXAGON_S2_asr_i_svw_trun">;
4624 //
4625 // BUILTIN_INFO(HEXAGON.S2_asr_r_svw_trun,SI_ftype_DISI,2)
4626 //
4627 def int_hexagon_S2_asr_r_svw_trun :
4628 Hexagon_si_disi_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">;
4629 //
4630 // BUILTIN_INFO(HEXAGON.S2_lsr_i_vw,DI_ftype_DISI,2)
4631 //
4632 def int_hexagon_S2_lsr_i_vw :
4633 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_vw">;
4634 //
4635 // BUILTIN_INFO(HEXAGON.S2_asl_i_vw,DI_ftype_DISI,2)
4636 //
4637 def int_hexagon_S2_asl_i_vw :
4638 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_vw">;
4639 //
4640 // BUILTIN_INFO(HEXAGON.S2_asr_r_vw,DI_ftype_DISI,2)
4641 //
4642 def int_hexagon_S2_asr_r_vw :
4643 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_vw">;
4644 //
4645 // BUILTIN_INFO(HEXAGON.S2_asl_r_vw,DI_ftype_DISI,2)
4646 //
4647 def int_hexagon_S2_asl_r_vw :
4648 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_vw">;
4649 //
4650 // BUILTIN_INFO(HEXAGON.S2_lsr_r_vw,DI_ftype_DISI,2)
4651 //
4652 def int_hexagon_S2_lsr_r_vw :
4653 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_vw">;
4654 //
4655 // BUILTIN_INFO(HEXAGON.S2_lsl_r_vw,DI_ftype_DISI,2)
4656 //
4657 def int_hexagon_S2_lsl_r_vw :
4658 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_vw">;
4659 //
4660 // BUILTIN_INFO(HEXAGON.S2_vrndpackwh,SI_ftype_DI,1)
4661 //
4662 def int_hexagon_S2_vrndpackwh :
4663 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vrndpackwh">;
4664 //
4665 // BUILTIN_INFO(HEXAGON.S2_vrndpackwhs,SI_ftype_DI,1)
4666 //
4667 def int_hexagon_S2_vrndpackwhs :
4668 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vrndpackwhs">;
4669 //
4670 // BUILTIN_INFO(HEXAGON.S2_vsxtbh,DI_ftype_SI,1)
4671 //
4672 def int_hexagon_S2_vsxtbh :
4673 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsxtbh">;
4674 //
4675 // BUILTIN_INFO(HEXAGON.S2_vzxtbh,DI_ftype_SI,1)
4676 //
4677 def int_hexagon_S2_vzxtbh :
4678 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vzxtbh">;
4679 //
4680 // BUILTIN_INFO(HEXAGON.S2_vsathub,SI_ftype_DI,1)
4681 //
4682 def int_hexagon_S2_vsathub :
4683 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsathub">;
4684 //
4685 // BUILTIN_INFO(HEXAGON.S2_svsathub,SI_ftype_SI,1)
4686 //
4687 def int_hexagon_S2_svsathub :
4688 Hexagon_si_si_Intrinsic<"HEXAGON_S2_svsathub">;
4689 //
4690 // BUILTIN_INFO(HEXAGON.S2_svsathb,SI_ftype_SI,1)
4691 //
4692 def int_hexagon_S2_svsathb :
4693 Hexagon_si_si_Intrinsic<"HEXAGON_S2_svsathb">;
4694 //
4695 // BUILTIN_INFO(HEXAGON.S2_vsathb,SI_ftype_DI,1)
4696 //
4697 def int_hexagon_S2_vsathb :
4698 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsathb">;
4699 //
4700 // BUILTIN_INFO(HEXAGON.S2_vtrunohb,SI_ftype_DI,1)
4701 //
4702 def int_hexagon_S2_vtrunohb :
4703 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vtrunohb">;
4704 //
4705 // BUILTIN_INFO(HEXAGON.S2_vtrunewh,DI_ftype_DIDI,2)
4706 //
4707 def int_hexagon_S2_vtrunewh :
4708 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_vtrunewh">;
4709 //
4710 // BUILTIN_INFO(HEXAGON.S2_vtrunowh,DI_ftype_DIDI,2)
4711 //
4712 def int_hexagon_S2_vtrunowh :
4713 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_vtrunowh">;
4714 //
4715 // BUILTIN_INFO(HEXAGON.S2_vtrunehb,SI_ftype_DI,1)
4716 //
4717 def int_hexagon_S2_vtrunehb :
4718 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vtrunehb">;
4719 //
4720 // BUILTIN_INFO(HEXAGON.S2_vsxthw,DI_ftype_SI,1)
4721 //
4722 def int_hexagon_S2_vsxthw :
4723 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsxthw">;
4724 //
4725 // BUILTIN_INFO(HEXAGON.S2_vzxthw,DI_ftype_SI,1)
4726 //
4727 def int_hexagon_S2_vzxthw :
4728 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vzxthw">;
4729 //
4730 // BUILTIN_INFO(HEXAGON.S2_vsatwh,SI_ftype_DI,1)
4731 //
4732 def int_hexagon_S2_vsatwh :
4733 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsatwh">;
4734 //
4735 // BUILTIN_INFO(HEXAGON.S2_vsatwuh,SI_ftype_DI,1)
4736 //
4737 def int_hexagon_S2_vsatwuh :
4738 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsatwuh">;
4739 //
4740 // BUILTIN_INFO(HEXAGON.S2_packhl,DI_ftype_SISI,2)
4741 //
4742 def int_hexagon_S2_packhl :
4743 Hexagon_di_sisi_Intrinsic<"HEXAGON_S2_packhl">;
4744 //
4745 // BUILTIN_INFO(HEXAGON.A2_swiz,SI_ftype_SI,1)
4746 //
4747 def int_hexagon_A2_swiz :
4748 Hexagon_si_si_Intrinsic<"HEXAGON_A2_swiz">;
4749 //
4750 // BUILTIN_INFO(HEXAGON.S2_vsathub_nopack,DI_ftype_DI,1)
4751 //
4752 def int_hexagon_S2_vsathub_nopack :
4753 Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsathub_nopack">;
4754 //
4755 // BUILTIN_INFO(HEXAGON.S2_vsathb_nopack,DI_ftype_DI,1)
4756 //
4757 def int_hexagon_S2_vsathb_nopack :
4758 Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsathb_nopack">;
4759 //
4760 // BUILTIN_INFO(HEXAGON.S2_vsatwh_nopack,DI_ftype_DI,1)
4761 //
4762 def int_hexagon_S2_vsatwh_nopack :
4763 Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;
4764 //
4765 // BUILTIN_INFO(HEXAGON.S2_vsatwuh_nopack,DI_ftype_DI,1)
4766 //
4767 def int_hexagon_S2_vsatwuh_nopack :
4768 Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">;
4769 //
4770 // BUILTIN_INFO(HEXAGON.S2_shuffob,DI_ftype_DIDI,2)
4771 //
4772 def int_hexagon_S2_shuffob :
4773 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffob">;
4774 //
4775 // BUILTIN_INFO(HEXAGON.S2_shuffeb,DI_ftype_DIDI,2)
4776 //
4777 def int_hexagon_S2_shuffeb :
4778 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffeb">;
4779 //
4780 // BUILTIN_INFO(HEXAGON.S2_shuffoh,DI_ftype_DIDI,2)
4781 //
4782 def int_hexagon_S2_shuffoh :
4783 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffoh">;
4784 //
4785 // BUILTIN_INFO(HEXAGON.S2_shuffeh,DI_ftype_DIDI,2)
4786 //
4787 def int_hexagon_S2_shuffeh :
4788 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffeh">;
4789 //
4790 // BUILTIN_INFO(HEXAGON.S5_popcountp,SI_ftype_DI,1)
4791 //
4792 def int_hexagon_S5_popcountp :
4793 Hexagon_si_di_Intrinsic<"HEXAGON_S5_popcountp">;
4794 //
4795 // BUILTIN_INFO(HEXAGON.S4_parity,SI_ftype_SISI,2)
4796 //
4797 def int_hexagon_S4_parity :
4798 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_parity">;
4799 //
4800 // BUILTIN_INFO(HEXAGON.S2_parityp,SI_ftype_DIDI,2)
4801 //
4802 def int_hexagon_S2_parityp :
4803 Hexagon_si_didi_Intrinsic<"HEXAGON_S2_parityp">;
4804 //
4805 // BUILTIN_INFO(HEXAGON.S2_lfsp,DI_ftype_DIDI,2)
4806 //
4807 def int_hexagon_S2_lfsp :
4808 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_lfsp">;
4809 //
4810 // BUILTIN_INFO(HEXAGON.S2_clbnorm,SI_ftype_SI,1)
4811 //
4812 def int_hexagon_S2_clbnorm :
4813 Hexagon_si_si_Intrinsic<"HEXAGON_S2_clbnorm">;
4814 //
4815 // BUILTIN_INFO(HEXAGON.S4_clbaddi,SI_ftype_SISI,2)
4816 //
4817 def int_hexagon_S4_clbaddi :
4818 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_clbaddi">;
4819 //
4820 // BUILTIN_INFO(HEXAGON.S4_clbpnorm,SI_ftype_DI,1)
4821 //
4822 def int_hexagon_S4_clbpnorm :
4823 Hexagon_si_di_Intrinsic<"HEXAGON_S4_clbpnorm">;
4824 //
4825 // BUILTIN_INFO(HEXAGON.S4_clbpaddi,SI_ftype_DISI,2)
4826 //
4827 def int_hexagon_S4_clbpaddi :
4828 Hexagon_si_disi_Intrinsic<"HEXAGON_S4_clbpaddi">;
4829 //
4830 // BUILTIN_INFO(HEXAGON.S2_clb,SI_ftype_SI,1)
4831 //
4832 def int_hexagon_S2_clb :
4833 Hexagon_si_si_Intrinsic<"HEXAGON_S2_clb">;
4834 //
4835 // BUILTIN_INFO(HEXAGON.S2_cl0,SI_ftype_SI,1)
4836 //
4837 def int_hexagon_S2_cl0 :
4838 Hexagon_si_si_Intrinsic<"HEXAGON_S2_cl0">;
4839 //
4840 // BUILTIN_INFO(HEXAGON.S2_cl1,SI_ftype_SI,1)
4841 //
4842 def int_hexagon_S2_cl1 :
4843 Hexagon_si_si_Intrinsic<"HEXAGON_S2_cl1">;
4844 //
4845 // BUILTIN_INFO(HEXAGON.S2_clbp,SI_ftype_DI,1)
4846 //
4847 def int_hexagon_S2_clbp :
4848 Hexagon_si_di_Intrinsic<"HEXAGON_S2_clbp">;
4849 //
4850 // BUILTIN_INFO(HEXAGON.S2_cl0p,SI_ftype_DI,1)
4851 //
4852 def int_hexagon_S2_cl0p :
4853 Hexagon_si_di_Intrinsic<"HEXAGON_S2_cl0p">;
4854 //
4855 // BUILTIN_INFO(HEXAGON.S2_cl1p,SI_ftype_DI,1)
4856 //
4857 def int_hexagon_S2_cl1p :
4858 Hexagon_si_di_Intrinsic<"HEXAGON_S2_cl1p">;
4859 //
4860 // BUILTIN_INFO(HEXAGON.S2_brev,SI_ftype_SI,1)
4861 //
4862 def int_hexagon_S2_brev :
4863 Hexagon_si_si_Intrinsic<"HEXAGON_S2_brev">;
4864 //
4865 // BUILTIN_INFO(HEXAGON.S2_brevp,DI_ftype_DI,1)
4866 //
4867 def int_hexagon_S2_brevp :
4868 Hexagon_di_di_Intrinsic<"HEXAGON_S2_brevp">;
4869 //
4870 // BUILTIN_INFO(HEXAGON.S2_ct0,SI_ftype_SI,1)
4871 //
4872 def int_hexagon_S2_ct0 :
4873 Hexagon_si_si_Intrinsic<"HEXAGON_S2_ct0">;
4874 //
4875 // BUILTIN_INFO(HEXAGON.S2_ct1,SI_ftype_SI,1)
4876 //
4877 def int_hexagon_S2_ct1 :
4878 Hexagon_si_si_Intrinsic<"HEXAGON_S2_ct1">;
4879 //
4880 // BUILTIN_INFO(HEXAGON.S2_ct0p,SI_ftype_DI,1)
4881 //
4882 def int_hexagon_S2_ct0p :
4883 Hexagon_si_di_Intrinsic<"HEXAGON_S2_ct0p">;
4884 //
4885 // BUILTIN_INFO(HEXAGON.S2_ct1p,SI_ftype_DI,1)
4886 //
4887 def int_hexagon_S2_ct1p :
4888 Hexagon_si_di_Intrinsic<"HEXAGON_S2_ct1p">;
4889 //
4890 // BUILTIN_INFO(HEXAGON.S2_interleave,DI_ftype_DI,1)
4891 //
4892 def int_hexagon_S2_interleave :
4893 Hexagon_di_di_Intrinsic<"HEXAGON_S2_interleave">;
4894 //
4895 // BUILTIN_INFO(HEXAGON.S2_deinterleave,DI_ftype_DI,1)
4896 //
4897 def int_hexagon_S2_deinterleave :
4898 Hexagon_di_di_Intrinsic<"HEXAGON_S2_deinterleave">;
4899
4900 //
4901 // BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1)
4902 //
4903 def int_hexagon_prefetch :
4904 Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>;
4905 def int_hexagon_Y2_dccleana :
4906 Hexagon_Intrinsic<"HEXAGON_Y2_dccleana", [], [llvm_ptr_ty], []>;
4907 def int_hexagon_Y2_dccleaninva :
4908 Hexagon_Intrinsic<"HEXAGON_Y2_dccleaninva", [], [llvm_ptr_ty], []>;
4909 def int_hexagon_Y2_dcinva :
4910 Hexagon_Intrinsic<"HEXAGON_Y2_dcinva", [], [llvm_ptr_ty], []>;
4911 def int_hexagon_Y2_dczeroa :
4912 Hexagon_Intrinsic<"HEXAGON_Y2_dczeroa", [], [llvm_ptr_ty],
4913       [IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects]>;
4914 def int_hexagon_Y4_l2fetch :
4915 Hexagon_Intrinsic<"HEXAGON_Y4_l2fetch", [], [llvm_ptr_ty, llvm_i32_ty], []>;
4916 def int_hexagon_Y5_l2fetch :
4917 Hexagon_Intrinsic<"HEXAGON_Y5_l2fetch", [], [llvm_ptr_ty, llvm_i64_ty], []>;
4918
4919 def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;
4920 def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
4921
4922 // Mark locked loads as read/write to prevent any accidental reordering.
4923 def int_hexagon_L2_loadw_locked :
4924 Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
4925       [IntrArgMemOnly, NoCapture<0>]>;
4926 def int_hexagon_L4_loadd_locked :
4927 Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
4928       [IntrArgMemOnly, NoCapture<0>]>;
4929
4930 def int_hexagon_S2_storew_locked :
4931 Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
4932       [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<0>]>;
4933 def int_hexagon_S4_stored_locked :
4934 Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
4935       [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<0>]>;
4936
4937 // V60
4938
4939 class Hexagon_v2048v2048_Intrinsic_T<string GCCIntSuffix>
4940  : Hexagon_Intrinsic<GCCIntSuffix,
4941                           [llvm_v64i32_ty], [llvm_v64i32_ty],
4942                           [IntrNoMem]>;
4943
4944 // tag : V6_hi_W
4945 // tag : V6_lo_W
4946 class Hexagon_v512v1024_Intrinsic_T<string GCCIntSuffix>
4947  : Hexagon_Intrinsic<GCCIntSuffix,
4948                           [llvm_v16i32_ty], [llvm_v32i32_ty],
4949                           [IntrNoMem]>;
4950
4951 // tag : V6_hi_W_128B
4952 // tag : V6_lo_W_128B
4953 class Hexagon_v1024v2048_Intrinsic_T<string GCCIntSuffix>
4954  : Hexagon_Intrinsic<GCCIntSuffix,
4955                           [llvm_v32i32_ty], [llvm_v64i32_ty],
4956                           [IntrNoMem]>;
4957
4958 class Hexagon_v1024v1024_Intrinsic_T<string GCCIntSuffix>
4959  : Hexagon_Intrinsic<GCCIntSuffix,
4960                           [llvm_v32i32_ty], [llvm_v32i32_ty],
4961                           [IntrNoMem]>;
4962
4963 // BUILTIN_INFO(HEXAGON.V6_hi_W,VI_ftype_VI,1)
4964 // tag : V6_hi
4965 def int_hexagon_V6_hi :
4966 Hexagon_v512v1024_Intrinsic_T<"HEXAGON_V6_hi">;
4967
4968 // BUILTIN_INFO(HEXAGON.V6_lo_W,VI_ftype_VI,1)
4969 // tag : V6_lo
4970 def int_hexagon_V6_lo :
4971 Hexagon_v512v1024_Intrinsic_T<"HEXAGON_V6_lo">;
4972
4973 // BUILTIN_INFO(HEXAGON.V6_hi_W,VI_ftype_VI,1)
4974 // tag : V6_hi_128B
4975 def int_hexagon_V6_hi_128B :
4976 Hexagon_v1024v2048_Intrinsic_T<"HEXAGON_V6_hi_128B">;
4977
4978 // BUILTIN_INFO(HEXAGON.V6_lo_W,VI_ftype_VI,1)
4979 // tag : V6_lo_128B
4980 def int_hexagon_V6_lo_128B :
4981 Hexagon_v1024v2048_Intrinsic_T<"HEXAGON_V6_lo_128B">;
4982
4983 // BUILTIN_INFO(HEXAGON.V6_vassignp,VI_ftype_VI,1)
4984 // tag : V6_vassignp
4985 def int_hexagon_V6_vassignp :
4986 Hexagon_v1024v1024_Intrinsic_T<"HEXAGON_V6_vassignp">;
4987
4988 // BUILTIN_INFO(HEXAGON.V6_vassignp,VI_ftype_VI,1)
4989 // tag : V6_vassignp_128B
4990 def int_hexagon_V6_vassignp_128B :
4991 Hexagon_v2048v2048_Intrinsic_T<"HEXAGON_V6_vassignp_128B">;
4992
4993
4994 //
4995 // Hexagon_iii_Intrinsic<string GCCIntSuffix>
4996 // tag : S6_rol_i_r
4997 class Hexagon_iii_Intrinsic<string GCCIntSuffix>
4998  : Hexagon_Intrinsic<GCCIntSuffix,
4999                           [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],
5000                           [IntrNoMem]>;
5001
5002 //
5003 // Hexagon_LLiLLii_Intrinsic<string GCCIntSuffix>
5004 // tag : S6_rol_i_p
5005 class Hexagon_LLiLLii_Intrinsic<string GCCIntSuffix>
5006  : Hexagon_Intrinsic<GCCIntSuffix,
5007                           [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],
5008                           [IntrNoMem]>;
5009
5010 //
5011 // Hexagon_iiii_Intrinsic<string GCCIntSuffix>
5012 // tag : S6_rol_i_r_acc
5013 class Hexagon_iiii_Intrinsic<string GCCIntSuffix>
5014  : Hexagon_Intrinsic<GCCIntSuffix,
5015                           [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
5016                           [IntrNoMem]>;
5017
5018 //
5019 // Hexagon_LLiLLiLLii_Intrinsic<string GCCIntSuffix>
5020 // tag : S6_rol_i_p_acc
5021 class Hexagon_LLiLLiLLii_Intrinsic<string GCCIntSuffix>
5022  : Hexagon_Intrinsic<GCCIntSuffix,
5023                           [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
5024                           [IntrNoMem]>;
5025
5026 //
5027 // Hexagon_v512v512v512i_Intrinsic<string GCCIntSuffix>
5028 // tag : V6_valignb
5029 class Hexagon_v512v512v512i_Intrinsic<string GCCIntSuffix>
5030  : Hexagon_Intrinsic<GCCIntSuffix,
5031                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5032                           [IntrNoMem]>;
5033
5034 //
5035 // Hexagon_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
5036 // tag : V6_valignb_128B
5037 class Hexagon_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
5038  : Hexagon_Intrinsic<GCCIntSuffix,
5039                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5040                           [IntrNoMem]>;
5041
5042 //
5043 // Hexagon_v512v512i_Intrinsic<string GCCIntSuffix>
5044 // tag : V6_vror
5045 class Hexagon_v512v512i_Intrinsic<string GCCIntSuffix>
5046  : Hexagon_Intrinsic<GCCIntSuffix,
5047                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
5048                           [IntrNoMem]>;
5049
5050 //
5051 // Hexagon_v1024v1024i_Intrinsic<string GCCIntSuffix>
5052 // tag : V6_vror_128B
5053 class Hexagon_v1024v1024i_Intrinsic<string GCCIntSuffix>
5054  : Hexagon_Intrinsic<GCCIntSuffix,
5055                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
5056                           [IntrNoMem]>;
5057
5058 //
5059 // Hexagon_v1024v512_Intrinsic<string GCCIntSuffix>
5060 // tag : V6_vunpackub
5061 class Hexagon_v1024v512_Intrinsic<string GCCIntSuffix>
5062  : Hexagon_Intrinsic<GCCIntSuffix,
5063                           [llvm_v32i32_ty], [llvm_v16i32_ty],
5064                           [IntrNoMem]>;
5065
5066 //
5067 // Hexagon_v2048v1024_Intrinsic<string GCCIntSuffix>
5068 // tag : V6_vunpackub_128B
5069 class Hexagon_v2048v1024_Intrinsic<string GCCIntSuffix>
5070  : Hexagon_Intrinsic<GCCIntSuffix,
5071                           [llvm_v64i32_ty], [llvm_v32i32_ty],
5072                           [IntrNoMem]>;
5073
5074 //
5075 // Hexagon_v1024v1024v512_Intrinsic<string GCCIntSuffix>
5076 // tag : V6_vunpackob
5077 class Hexagon_v1024v1024v512_Intrinsic<string GCCIntSuffix>
5078  : Hexagon_Intrinsic<GCCIntSuffix,
5079                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],
5080                           [IntrNoMem]>;
5081
5082 //
5083 // Hexagon_v2048v2048v1024_Intrinsic<string GCCIntSuffix>
5084 // tag : V6_vunpackob_128B
5085 class Hexagon_v2048v2048v1024_Intrinsic<string GCCIntSuffix>
5086  : Hexagon_Intrinsic<GCCIntSuffix,
5087                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],
5088                           [IntrNoMem]>;
5089
5090 //
5091 // Hexagon_v512v512v512_Intrinsic<string GCCIntSuffix>
5092 // tag : V6_vpackeb
5093 class Hexagon_v512v512v512_Intrinsic<string GCCIntSuffix>
5094  : Hexagon_Intrinsic<GCCIntSuffix,
5095                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
5096                           [IntrNoMem]>;
5097
5098 //
5099 // Hexagon_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
5100 // tag : V6_vpackeb_128B
5101 class Hexagon_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
5102  : Hexagon_Intrinsic<GCCIntSuffix,
5103                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
5104                           [IntrNoMem]>;
5105
5106 //
5107 // Hexagon_v2048v2048i_Intrinsic<string GCCIntSuffix>
5108 // tag : V6_vdmpybus_dv_128B
5109 class Hexagon_v2048v2048i_Intrinsic<string GCCIntSuffix>
5110  : Hexagon_Intrinsic<GCCIntSuffix,
5111                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
5112                           [IntrNoMem]>;
5113
5114 //
5115 // Hexagon_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
5116 // tag : V6_vdmpybus_dv_acc_128B
5117 class Hexagon_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
5118  : Hexagon_Intrinsic<GCCIntSuffix,
5119                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
5120                           [IntrNoMem]>;
5121
5122 //
5123 // Hexagon_v512v512v512v512_Intrinsic<string GCCIntSuffix>
5124 // tag : V6_vdmpyhvsat_acc
5125 class Hexagon_v512v512v512v512_Intrinsic<string GCCIntSuffix>
5126  : Hexagon_Intrinsic<GCCIntSuffix,
5127                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5128                           [IntrNoMem]>;
5129
5130 //
5131 // Hexagon_v1024v1024v1024v1024_Intrinsic<string GCCIntSuffix>
5132 // tag : V6_vdmpyhvsat_acc_128B
5133 class Hexagon_v1024v1024v1024v1024_Intrinsic<string GCCIntSuffix>
5134  : Hexagon_Intrinsic<GCCIntSuffix,
5135                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5136                           [IntrNoMem]>;
5137
5138 //
5139 // Hexagon_v512v1024i_Intrinsic<string GCCIntSuffix>
5140 // tag : V6_vdmpyhisat
5141 class Hexagon_v512v1024i_Intrinsic<string GCCIntSuffix>
5142  : Hexagon_Intrinsic<GCCIntSuffix,
5143                           [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
5144                           [IntrNoMem]>;
5145
5146 //
5147 // Hexagon_v1024v2048i_Intrinsic<string GCCIntSuffix>
5148 // tag : V6_vdmpyhisat_128B
5149 class Hexagon_v1024v2048i_Intrinsic<string GCCIntSuffix>
5150  : Hexagon_Intrinsic<GCCIntSuffix,
5151                           [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
5152                           [IntrNoMem]>;
5153
5154 //
5155 // Hexagon_v512v512v1024i_Intrinsic<string GCCIntSuffix>
5156 // tag : V6_vdmpyhisat_acc
5157 class Hexagon_v512v512v1024i_Intrinsic<string GCCIntSuffix>
5158  : Hexagon_Intrinsic<GCCIntSuffix,
5159                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5160                           [IntrNoMem]>;
5161
5162 //
5163 // Hexagon_v1024v1024v2048i_Intrinsic<string GCCIntSuffix>
5164 // tag : V6_vdmpyhisat_acc_128B
5165 class Hexagon_v1024v1024v2048i_Intrinsic<string GCCIntSuffix>
5166  : Hexagon_Intrinsic<GCCIntSuffix,
5167                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty],
5168                           [IntrNoMem]>;
5169
5170 //
5171 // Hexagon_v1024v1024ii_Intrinsic<string GCCIntSuffix>
5172 // tag : V6_vrmpyubi
5173 class Hexagon_v1024v1024ii_Intrinsic<string GCCIntSuffix>
5174  : Hexagon_Intrinsic<GCCIntSuffix,
5175                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
5176                           [IntrNoMem]>;
5177
5178 //
5179 // Hexagon_v2048v2048ii_Intrinsic<string GCCIntSuffix>
5180 // tag : V6_vrmpyubi_128B
5181 class Hexagon_v2048v2048ii_Intrinsic<string GCCIntSuffix>
5182  : Hexagon_Intrinsic<GCCIntSuffix,
5183                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
5184                           [IntrNoMem]>;
5185
5186 //
5187 // Hexagon_v1024v1024v1024ii_Intrinsic<string GCCIntSuffix>
5188 // tag : V6_vrmpyubi_acc
5189 class Hexagon_v1024v1024v1024ii_Intrinsic<string GCCIntSuffix>
5190  : Hexagon_Intrinsic<GCCIntSuffix,
5191                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
5192                           [IntrNoMem]>;
5193
5194 //
5195 // Hexagon_v2048v2048v2048ii_Intrinsic<string GCCIntSuffix>
5196 // tag : V6_vrmpyubi_acc_128B
5197 class Hexagon_v2048v2048v2048ii_Intrinsic<string GCCIntSuffix>
5198  : Hexagon_Intrinsic<GCCIntSuffix,
5199                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
5200                           [IntrNoMem]>;
5201
5202 //
5203 // Hexagon_v2048v2048v2048_Intrinsic<string GCCIntSuffix>
5204 // tag : V6_vaddb_dv_128B
5205 class Hexagon_v2048v2048v2048_Intrinsic<string GCCIntSuffix>
5206  : Hexagon_Intrinsic<GCCIntSuffix,
5207                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
5208                           [IntrNoMem]>;
5209
5210 //
5211 // Hexagon_v1024v512v512_Intrinsic<string GCCIntSuffix>
5212 // tag : V6_vaddubh
5213 class Hexagon_v1024v512v512_Intrinsic<string GCCIntSuffix>
5214  : Hexagon_Intrinsic<GCCIntSuffix,
5215                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
5216                           [IntrNoMem]>;
5217
5218 //
5219 // Hexagon_v2048v1024v1024_Intrinsic<string GCCIntSuffix>
5220 // tag : V6_vaddubh_128B
5221 class Hexagon_v2048v1024v1024_Intrinsic<string GCCIntSuffix>
5222  : Hexagon_Intrinsic<GCCIntSuffix,
5223                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
5224                           [IntrNoMem]>;
5225
5226 //
5227 // Hexagon_v512_Intrinsic<string GCCIntSuffix>
5228 // tag : V6_vd0
5229 class Hexagon_v512_Intrinsic<string GCCIntSuffix>
5230  : Hexagon_Intrinsic<GCCIntSuffix,
5231                           [llvm_v16i32_ty], [],
5232                           [IntrNoMem]>;
5233
5234 //
5235 // Hexagon_v1024_Intrinsic<string GCCIntSuffix>
5236 // tag : V6_vd0_128B
5237 class Hexagon_v1024_Intrinsic<string GCCIntSuffix>
5238  : Hexagon_Intrinsic<GCCIntSuffix,
5239                           [llvm_v32i32_ty], [],
5240                           [IntrNoMem]>;
5241
5242 //
5243 // Hexagon_v512v64iv512v512_Intrinsic<string GCCIntSuffix>
5244 // tag : V6_vaddbq
5245 class Hexagon_v512v64iv512v512_Intrinsic<string GCCIntSuffix>
5246  : Hexagon_Intrinsic<GCCIntSuffix,
5247                           [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5248                           [IntrNoMem]>;
5249
5250 //
5251 // Hexagon_v1024v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5252 // tag : V6_vaddbq_128B
5253 class Hexagon_v1024v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5254  : Hexagon_Intrinsic<GCCIntSuffix,
5255                           [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5256                           [IntrNoMem]>;
5257
5258 //
5259 // Hexagon_v512v512_Intrinsic<string GCCIntSuffix>
5260 // tag : V6_vabsh
5261 class Hexagon_v512v512_Intrinsic<string GCCIntSuffix>
5262  : Hexagon_Intrinsic<GCCIntSuffix,
5263                           [llvm_v16i32_ty], [llvm_v16i32_ty],
5264                           [IntrNoMem]>;
5265
5266 //
5267 // Hexagon_v1024v1024_Intrinsic<string GCCIntSuffix>
5268 // tag : V6_vabsh_128B
5269 class Hexagon_v1024v1024_Intrinsic<string GCCIntSuffix>
5270  : Hexagon_Intrinsic<GCCIntSuffix,
5271                           [llvm_v32i32_ty], [llvm_v32i32_ty],
5272                           [IntrNoMem]>;
5273
5274 //
5275 // Hexagon_v1024v1024v512v512_Intrinsic<string GCCIntSuffix>
5276 // tag : V6_vmpybv_acc
5277 class Hexagon_v1024v1024v512v512_Intrinsic<string GCCIntSuffix>
5278  : Hexagon_Intrinsic<GCCIntSuffix,
5279                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5280                           [IntrNoMem]>;
5281
5282 //
5283 // Hexagon_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix>
5284 // tag : V6_vmpybv_acc_128B
5285 class Hexagon_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix>
5286  : Hexagon_Intrinsic<GCCIntSuffix,
5287                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5288                           [IntrNoMem]>;
5289
5290 //
5291 // Hexagon_v1024v512i_Intrinsic<string GCCIntSuffix>
5292 // tag : V6_vmpyub
5293 class Hexagon_v1024v512i_Intrinsic<string GCCIntSuffix>
5294  : Hexagon_Intrinsic<GCCIntSuffix,
5295                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
5296                           [IntrNoMem]>;
5297
5298 //
5299 // Hexagon_v2048v1024i_Intrinsic<string GCCIntSuffix>
5300 // tag : V6_vmpyub_128B
5301 class Hexagon_v2048v1024i_Intrinsic<string GCCIntSuffix>
5302  : Hexagon_Intrinsic<GCCIntSuffix,
5303                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
5304                           [IntrNoMem]>;
5305
5306 //
5307 // Hexagon_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
5308 // tag : V6_vmpyub_acc
5309 class Hexagon_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
5310  : Hexagon_Intrinsic<GCCIntSuffix,
5311                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5312                           [IntrNoMem]>;
5313
5314 //
5315 // Hexagon_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
5316 // tag : V6_vmpyub_acc_128B
5317 class Hexagon_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
5318  : Hexagon_Intrinsic<GCCIntSuffix,
5319                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5320                           [IntrNoMem]>;
5321
5322 //
5323 // Hexagon_v512v64ii_Intrinsic<string GCCIntSuffix>
5324 // tag : V6_vandqrt
5325 class Hexagon_v512v64ii_Intrinsic<string GCCIntSuffix>
5326  : Hexagon_Intrinsic<GCCIntSuffix,
5327                           [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],
5328                           [IntrNoMem]>;
5329
5330 //
5331 // Hexagon_v1024v128ii_Intrinsic<string GCCIntSuffix>
5332 // tag : V6_vandqrt_128B
5333 class Hexagon_v1024v128ii_Intrinsic<string GCCIntSuffix>
5334  : Hexagon_Intrinsic<GCCIntSuffix,
5335                           [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],
5336                           [IntrNoMem]>;
5337
5338 //
5339 // Hexagon_v512v512v64ii_Intrinsic<string GCCIntSuffix>
5340 // tag : V6_vandqrt_acc
5341 class Hexagon_v512v512v64ii_Intrinsic<string GCCIntSuffix>
5342  : Hexagon_Intrinsic<GCCIntSuffix,
5343                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],
5344                           [IntrNoMem]>;
5345
5346 //
5347 // Hexagon_v1024v1024v128ii_Intrinsic<string GCCIntSuffix>
5348 // tag : V6_vandqrt_acc_128B
5349 class Hexagon_v1024v1024v128ii_Intrinsic<string GCCIntSuffix>
5350  : Hexagon_Intrinsic<GCCIntSuffix,
5351                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],
5352                           [IntrNoMem]>;
5353
5354 //
5355 // Hexagon_v64iv512i_Intrinsic<string GCCIntSuffix>
5356 // tag : V6_vandvrt
5357 class Hexagon_v64iv512i_Intrinsic<string GCCIntSuffix>
5358  : Hexagon_Intrinsic<GCCIntSuffix,
5359                           [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty],
5360                           [IntrNoMem]>;
5361
5362 //
5363 // Hexagon_v128iv1024i_Intrinsic<string GCCIntSuffix>
5364 // tag : V6_vandvrt_128B
5365 class Hexagon_v128iv1024i_Intrinsic<string GCCIntSuffix>
5366  : Hexagon_Intrinsic<GCCIntSuffix,
5367                           [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty],
5368                           [IntrNoMem]>;
5369
5370 //
5371 // Hexagon_v64iv64iv512i_Intrinsic<string GCCIntSuffix>
5372 // tag : V6_vandvrt_acc
5373 class Hexagon_v64iv64iv512i_Intrinsic<string GCCIntSuffix>
5374  : Hexagon_Intrinsic<GCCIntSuffix,
5375                           [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty],
5376                           [IntrNoMem]>;
5377
5378 //
5379 // Hexagon_v128iv128iv1024i_Intrinsic<string GCCIntSuffix>
5380 // tag : V6_vandvrt_acc_128B
5381 class Hexagon_v128iv128iv1024i_Intrinsic<string GCCIntSuffix>
5382  : Hexagon_Intrinsic<GCCIntSuffix,
5383                           [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty],
5384                           [IntrNoMem]>;
5385
5386 //
5387 // Hexagon_v64iv512v512_Intrinsic<string GCCIntSuffix>
5388 // tag : V6_vgtw
5389 class Hexagon_v64iv512v512_Intrinsic<string GCCIntSuffix>
5390  : Hexagon_Intrinsic<GCCIntSuffix,
5391                           [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
5392                           [IntrNoMem]>;
5393
5394 //
5395 // Hexagon_v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5396 // tag : V6_vgtw_128B
5397 class Hexagon_v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5398  : Hexagon_Intrinsic<GCCIntSuffix,
5399                           [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
5400                           [IntrNoMem]>;
5401
5402 //
5403 // Hexagon_v64iv64iv512v512_Intrinsic<string GCCIntSuffix>
5404 // tag : V6_vgtw_and
5405 class Hexagon_v64iv64iv512v512_Intrinsic<string GCCIntSuffix>
5406  : Hexagon_Intrinsic<GCCIntSuffix,
5407                           [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5408                           [IntrNoMem]>;
5409
5410 //
5411 // Hexagon_v128iv128iv1024v1024_Intrinsic<string GCCIntSuffix>
5412 // tag : V6_vgtw_and_128B
5413 class Hexagon_v128iv128iv1024v1024_Intrinsic<string GCCIntSuffix>
5414  : Hexagon_Intrinsic<GCCIntSuffix,
5415                           [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5416                           [IntrNoMem]>;
5417
5418 //
5419 // Hexagon_v64iv64iv64i_Intrinsic<string GCCIntSuffix>
5420 // tag : V6_pred_or
5421 class Hexagon_v64iv64iv64i_Intrinsic<string GCCIntSuffix>
5422  : Hexagon_Intrinsic<GCCIntSuffix,
5423                           [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],
5424                           [IntrNoMem]>;
5425
5426 //
5427 // Hexagon_v128iv128iv128i_Intrinsic<string GCCIntSuffix>
5428 // tag : V6_pred_or_128B
5429 class Hexagon_v128iv128iv128i_Intrinsic<string GCCIntSuffix>
5430  : Hexagon_Intrinsic<GCCIntSuffix,
5431                           [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],
5432                           [IntrNoMem]>;
5433
5434 //
5435 // Hexagon_v64iv64i_Intrinsic<string GCCIntSuffix>
5436 // tag : V6_pred_not
5437 class Hexagon_v64iv64i_Intrinsic<string GCCIntSuffix>
5438  : Hexagon_Intrinsic<GCCIntSuffix,
5439                           [llvm_v512i1_ty], [llvm_v512i1_ty],
5440                           [IntrNoMem]>;
5441
5442 //
5443 // Hexagon_v128iv128i_Intrinsic<string GCCIntSuffix>
5444 // tag : V6_pred_not_128B
5445 class Hexagon_v128iv128i_Intrinsic<string GCCIntSuffix>
5446  : Hexagon_Intrinsic<GCCIntSuffix,
5447                           [llvm_v1024i1_ty], [llvm_v1024i1_ty],
5448                           [IntrNoMem]>;
5449
5450 //
5451 // Hexagon_v64ii_Intrinsic<string GCCIntSuffix>
5452 // tag : V6_pred_scalar2
5453 class Hexagon_v64ii_Intrinsic<string GCCIntSuffix>
5454  : Hexagon_Intrinsic<GCCIntSuffix,
5455                           [llvm_v512i1_ty], [llvm_i32_ty],
5456                           [IntrNoMem]>;
5457
5458 //
5459 // Hexagon_v128ii_Intrinsic<string GCCIntSuffix>
5460 // tag : V6_pred_scalar2_128B
5461 class Hexagon_v128ii_Intrinsic<string GCCIntSuffix>
5462  : Hexagon_Intrinsic<GCCIntSuffix,
5463                           [llvm_v1024i1_ty], [llvm_i32_ty],
5464                           [IntrNoMem]>;
5465
5466 //
5467 // Hexagon_v1024v64iv512v512_Intrinsic<string GCCIntSuffix>
5468 // tag : V6_vswap
5469 class Hexagon_v1024v64iv512v512_Intrinsic<string GCCIntSuffix>
5470  : Hexagon_Intrinsic<GCCIntSuffix,
5471                           [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5472                           [IntrNoMem]>;
5473
5474 //
5475 // Hexagon_v2048v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5476 // tag : V6_vswap_128B
5477 class Hexagon_v2048v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5478  : Hexagon_Intrinsic<GCCIntSuffix,
5479                           [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5480                           [IntrNoMem]>;
5481
5482 //
5483 // Hexagon_v1024v512v512i_Intrinsic<string GCCIntSuffix>
5484 // tag : V6_vshuffvdd
5485 class Hexagon_v1024v512v512i_Intrinsic<string GCCIntSuffix>
5486  : Hexagon_Intrinsic<GCCIntSuffix,
5487                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5488                           [IntrNoMem]>;
5489
5490 //
5491 // Hexagon_v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
5492 // tag : V6_vshuffvdd_128B
5493 class Hexagon_v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
5494  : Hexagon_Intrinsic<GCCIntSuffix,
5495                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5496                           [IntrNoMem]>;
5497
5498
5499 //
5500 // Hexagon_iv512i_Intrinsic<string GCCIntSuffix>
5501 // tag : V6_extractw
5502 class Hexagon_iv512i_Intrinsic<string GCCIntSuffix>
5503  : Hexagon_Intrinsic<GCCIntSuffix,
5504                           [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
5505                           [IntrNoMem]>;
5506
5507 //
5508 // Hexagon_iv1024i_Intrinsic<string GCCIntSuffix>
5509 // tag : V6_extractw_128B
5510 class Hexagon_iv1024i_Intrinsic<string GCCIntSuffix>
5511  : Hexagon_Intrinsic<GCCIntSuffix,
5512                           [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
5513                           [IntrNoMem]>;
5514
5515 //
5516 // Hexagon_v512i_Intrinsic<string GCCIntSuffix>
5517 // tag : V6_lvsplatw
5518 class Hexagon_v512i_Intrinsic<string GCCIntSuffix>
5519  : Hexagon_Intrinsic<GCCIntSuffix,
5520                           [llvm_v16i32_ty], [llvm_i32_ty],
5521                           [IntrNoMem]>;
5522
5523 //
5524 // Hexagon_v1024i_Intrinsic<string GCCIntSuffix>
5525 // tag : V6_lvsplatw_128B
5526 class Hexagon_v1024i_Intrinsic<string GCCIntSuffix>
5527  : Hexagon_Intrinsic<GCCIntSuffix,
5528                           [llvm_v32i32_ty], [llvm_i32_ty],
5529                           [IntrNoMem]>;
5530
5531 //
5532 // Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
5533 // tag : V6_vlutvvb_oracc
5534 class Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
5535  : Hexagon_Intrinsic<GCCIntSuffix,
5536                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5537                           [IntrNoMem]>;
5538
5539 //
5540 // Hexagon_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
5541 // tag : V6_vlutvvb_oracc_128B
5542 class Hexagon_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
5543  : Hexagon_Intrinsic<GCCIntSuffix,
5544                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5545                           [IntrNoMem]>;
5546
5547 //
5548 // Hexagon_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix>
5549 // tag : V6_vlutvwh_oracc
5550 class Hexagon_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix>
5551  : Hexagon_Intrinsic<GCCIntSuffix,
5552                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5553                           [IntrNoMem]>;
5554
5555 //
5556 // Hexagon_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
5557 // tag : V6_vlutvwh_oracc_128B
5558 class Hexagon_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
5559  : Hexagon_Intrinsic<GCCIntSuffix,
5560                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5561                           [IntrNoMem]>;
5562
5563 //
5564 // Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
5565 // tag: V6_vS32b_qpred_ai
5566 class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
5567  : Hexagon_Intrinsic<GCCIntSuffix,
5568                           [], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty],
5569                           [IntrArgMemOnly]>;
5570
5571 //
5572 // Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
5573 // tag: V6_vS32b_qpred_ai_128B
5574 class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
5575  : Hexagon_Intrinsic<GCCIntSuffix,
5576                           [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty],
5577                           [IntrArgMemOnly]>;
5578
5579 //
5580 // BUILTIN_INFO(HEXAGON.S6_rol_i_r,SI_ftype_SISI,2)
5581 // tag : S6_rol_i_r
5582 def int_hexagon_S6_rol_i_r :
5583 Hexagon_iii_Intrinsic<"HEXAGON_S6_rol_i_r">;
5584
5585 //
5586 // BUILTIN_INFO(HEXAGON.S6_rol_i_p,DI_ftype_DISI,2)
5587 // tag : S6_rol_i_p
5588 def int_hexagon_S6_rol_i_p :
5589 Hexagon_LLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p">;
5590
5591 //
5592 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_acc,SI_ftype_SISISI,3)
5593 // tag : S6_rol_i_r_acc
5594 def int_hexagon_S6_rol_i_r_acc :
5595 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_acc">;
5596
5597 //
5598 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_acc,DI_ftype_DIDISI,3)
5599 // tag : S6_rol_i_p_acc
5600 def int_hexagon_S6_rol_i_p_acc :
5601 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_acc">;
5602
5603 //
5604 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_nac,SI_ftype_SISISI,3)
5605 // tag : S6_rol_i_r_nac
5606 def int_hexagon_S6_rol_i_r_nac :
5607 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_nac">;
5608
5609 //
5610 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_nac,DI_ftype_DIDISI,3)
5611 // tag : S6_rol_i_p_nac
5612 def int_hexagon_S6_rol_i_p_nac :
5613 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_nac">;
5614
5615 //
5616 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_xacc,SI_ftype_SISISI,3)
5617 // tag : S6_rol_i_r_xacc
5618 def int_hexagon_S6_rol_i_r_xacc :
5619 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_xacc">;
5620
5621 //
5622 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_xacc,DI_ftype_DIDISI,3)
5623 // tag : S6_rol_i_p_xacc
5624 def int_hexagon_S6_rol_i_p_xacc :
5625 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_xacc">;
5626
5627 //
5628 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_and,SI_ftype_SISISI,3)
5629 // tag : S6_rol_i_r_and
5630 def int_hexagon_S6_rol_i_r_and :
5631 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_and">;
5632
5633 //
5634 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_or,SI_ftype_SISISI,3)
5635 // tag : S6_rol_i_r_or
5636 def int_hexagon_S6_rol_i_r_or :
5637 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_or">;
5638
5639 //
5640 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_and,DI_ftype_DIDISI,3)
5641 // tag : S6_rol_i_p_and
5642 def int_hexagon_S6_rol_i_p_and :
5643 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_and">;
5644
5645 //
5646 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_or,DI_ftype_DIDISI,3)
5647 // tag : S6_rol_i_p_or
5648 def int_hexagon_S6_rol_i_p_or :
5649 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_or">;
5650
5651 //
5652 // BUILTIN_INFO(HEXAGON.S2_cabacencbin,DI_ftype_DIDIQI,3)
5653 // tag : S2_cabacencbin
5654 def int_hexagon_S2_cabacencbin :
5655 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S2_cabacencbin">;
5656
5657 //
5658 // BUILTIN_INFO(HEXAGON.V6_valignb,VI_ftype_VIVISI,3)
5659 // tag : V6_valignb
5660 def int_hexagon_V6_valignb :
5661 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_valignb">;
5662
5663 //
5664 // BUILTIN_INFO(HEXAGON.V6_valignb_128B,VI_ftype_VIVISI,3)
5665 // tag : V6_valignb_128B
5666 def int_hexagon_V6_valignb_128B :
5667 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_valignb_128B">;
5668
5669 //
5670 // BUILTIN_INFO(HEXAGON.V6_vlalignb,VI_ftype_VIVISI,3)
5671 // tag : V6_vlalignb
5672 def int_hexagon_V6_vlalignb :
5673 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlalignb">;
5674
5675 //
5676 // BUILTIN_INFO(HEXAGON.V6_vlalignb_128B,VI_ftype_VIVISI,3)
5677 // tag : V6_vlalignb_128B
5678 def int_hexagon_V6_vlalignb_128B :
5679 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlalignb_128B">;
5680
5681 //
5682 // BUILTIN_INFO(HEXAGON.V6_valignbi,VI_ftype_VIVISI,3)
5683 // tag : V6_valignbi
5684 def int_hexagon_V6_valignbi :
5685 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_valignbi">;
5686
5687 //
5688 // BUILTIN_INFO(HEXAGON.V6_valignbi_128B,VI_ftype_VIVISI,3)
5689 // tag : V6_valignbi_128B
5690 def int_hexagon_V6_valignbi_128B :
5691 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_valignbi_128B">;
5692
5693 //
5694 // BUILTIN_INFO(HEXAGON.V6_vlalignbi,VI_ftype_VIVISI,3)
5695 // tag : V6_vlalignbi
5696 def int_hexagon_V6_vlalignbi :
5697 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlalignbi">;
5698
5699 //
5700 // BUILTIN_INFO(HEXAGON.V6_vlalignbi_128B,VI_ftype_VIVISI,3)
5701 // tag : V6_vlalignbi_128B
5702 def int_hexagon_V6_vlalignbi_128B :
5703 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlalignbi_128B">;
5704
5705 //
5706 // BUILTIN_INFO(HEXAGON.V6_vror,VI_ftype_VISI,2)
5707 // tag : V6_vror
5708 def int_hexagon_V6_vror :
5709 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vror">;
5710
5711 //
5712 // BUILTIN_INFO(HEXAGON.V6_vror_128B,VI_ftype_VISI,2)
5713 // tag : V6_vror_128B
5714 def int_hexagon_V6_vror_128B :
5715 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vror_128B">;
5716
5717 //
5718 // BUILTIN_INFO(HEXAGON.V6_vunpackub,VD_ftype_VI,1)
5719 // tag : V6_vunpackub
5720 def int_hexagon_V6_vunpackub :
5721 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackub">;
5722
5723 //
5724 // BUILTIN_INFO(HEXAGON.V6_vunpackub_128B,VD_ftype_VI,1)
5725 // tag : V6_vunpackub_128B
5726 def int_hexagon_V6_vunpackub_128B :
5727 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackub_128B">;
5728
5729 //
5730 // BUILTIN_INFO(HEXAGON.V6_vunpackb,VD_ftype_VI,1)
5731 // tag : V6_vunpackb
5732 def int_hexagon_V6_vunpackb :
5733 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackb">;
5734
5735 //
5736 // BUILTIN_INFO(HEXAGON.V6_vunpackb_128B,VD_ftype_VI,1)
5737 // tag : V6_vunpackb_128B
5738 def int_hexagon_V6_vunpackb_128B :
5739 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackb_128B">;
5740
5741 //
5742 // BUILTIN_INFO(HEXAGON.V6_vunpackuh,VD_ftype_VI,1)
5743 // tag : V6_vunpackuh
5744 def int_hexagon_V6_vunpackuh :
5745 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackuh">;
5746
5747 //
5748 // BUILTIN_INFO(HEXAGON.V6_vunpackuh_128B,VD_ftype_VI,1)
5749 // tag : V6_vunpackuh_128B
5750 def int_hexagon_V6_vunpackuh_128B :
5751 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackuh_128B">;
5752
5753 //
5754 // BUILTIN_INFO(HEXAGON.V6_vunpackh,VD_ftype_VI,1)
5755 // tag : V6_vunpackh
5756 def int_hexagon_V6_vunpackh :
5757 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackh">;
5758
5759 //
5760 // BUILTIN_INFO(HEXAGON.V6_vunpackh_128B,VD_ftype_VI,1)
5761 // tag : V6_vunpackh_128B
5762 def int_hexagon_V6_vunpackh_128B :
5763 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackh_128B">;
5764
5765 //
5766 // BUILTIN_INFO(HEXAGON.V6_vunpackob,VD_ftype_VDVI,2)
5767 // tag : V6_vunpackob
5768 def int_hexagon_V6_vunpackob :
5769 Hexagon_v1024v1024v512_Intrinsic<"HEXAGON_V6_vunpackob">;
5770
5771 //
5772 // BUILTIN_INFO(HEXAGON.V6_vunpackob_128B,VD_ftype_VDVI,2)
5773 // tag : V6_vunpackob_128B
5774 def int_hexagon_V6_vunpackob_128B :
5775 Hexagon_v2048v2048v1024_Intrinsic<"HEXAGON_V6_vunpackob_128B">;
5776
5777 //
5778 // BUILTIN_INFO(HEXAGON.V6_vunpackoh,VD_ftype_VDVI,2)
5779 // tag : V6_vunpackoh
5780 def int_hexagon_V6_vunpackoh :
5781 Hexagon_v1024v1024v512_Intrinsic<"HEXAGON_V6_vunpackoh">;
5782
5783 //
5784 // BUILTIN_INFO(HEXAGON.V6_vunpackoh_128B,VD_ftype_VDVI,2)
5785 // tag : V6_vunpackoh_128B
5786 def int_hexagon_V6_vunpackoh_128B :
5787 Hexagon_v2048v2048v1024_Intrinsic<"HEXAGON_V6_vunpackoh_128B">;
5788
5789 //
5790 // BUILTIN_INFO(HEXAGON.V6_vpackeb,VI_ftype_VIVI,2)
5791 // tag : V6_vpackeb
5792 def int_hexagon_V6_vpackeb :
5793 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackeb">;
5794
5795 //
5796 // BUILTIN_INFO(HEXAGON.V6_vpackeb_128B,VI_ftype_VIVI,2)
5797 // tag : V6_vpackeb_128B
5798 def int_hexagon_V6_vpackeb_128B :
5799 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackeb_128B">;
5800
5801 //
5802 // BUILTIN_INFO(HEXAGON.V6_vpackeh,VI_ftype_VIVI,2)
5803 // tag : V6_vpackeh
5804 def int_hexagon_V6_vpackeh :
5805 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackeh">;
5806
5807 //
5808 // BUILTIN_INFO(HEXAGON.V6_vpackeh_128B,VI_ftype_VIVI,2)
5809 // tag : V6_vpackeh_128B
5810 def int_hexagon_V6_vpackeh_128B :
5811 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackeh_128B">;
5812
5813 //
5814 // BUILTIN_INFO(HEXAGON.V6_vpackob,VI_ftype_VIVI,2)
5815 // tag : V6_vpackob
5816 def int_hexagon_V6_vpackob :
5817 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackob">;
5818
5819 //
5820 // BUILTIN_INFO(HEXAGON.V6_vpackob_128B,VI_ftype_VIVI,2)
5821 // tag : V6_vpackob_128B
5822 def int_hexagon_V6_vpackob_128B :
5823 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackob_128B">;
5824
5825 //
5826 // BUILTIN_INFO(HEXAGON.V6_vpackoh,VI_ftype_VIVI,2)
5827 // tag : V6_vpackoh
5828 def int_hexagon_V6_vpackoh :
5829 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackoh">;
5830
5831 //
5832 // BUILTIN_INFO(HEXAGON.V6_vpackoh_128B,VI_ftype_VIVI,2)
5833 // tag : V6_vpackoh_128B
5834 def int_hexagon_V6_vpackoh_128B :
5835 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackoh_128B">;
5836
5837 //
5838 // BUILTIN_INFO(HEXAGON.V6_vpackhub_sat,VI_ftype_VIVI,2)
5839 // tag : V6_vpackhub_sat
5840 def int_hexagon_V6_vpackhub_sat :
5841 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackhub_sat">;
5842
5843 //
5844 // BUILTIN_INFO(HEXAGON.V6_vpackhub_sat_128B,VI_ftype_VIVI,2)
5845 // tag : V6_vpackhub_sat_128B
5846 def int_hexagon_V6_vpackhub_sat_128B :
5847 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">;
5848
5849 //
5850 // BUILTIN_INFO(HEXAGON.V6_vpackhb_sat,VI_ftype_VIVI,2)
5851 // tag : V6_vpackhb_sat
5852 def int_hexagon_V6_vpackhb_sat :
5853 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackhb_sat">;
5854
5855 //
5856 // BUILTIN_INFO(HEXAGON.V6_vpackhb_sat_128B,VI_ftype_VIVI,2)
5857 // tag : V6_vpackhb_sat_128B
5858 def int_hexagon_V6_vpackhb_sat_128B :
5859 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">;
5860
5861 //
5862 // BUILTIN_INFO(HEXAGON.V6_vpackwuh_sat,VI_ftype_VIVI,2)
5863 // tag : V6_vpackwuh_sat
5864 def int_hexagon_V6_vpackwuh_sat :
5865 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackwuh_sat">;
5866
5867 //
5868 // BUILTIN_INFO(HEXAGON.V6_vpackwuh_sat_128B,VI_ftype_VIVI,2)
5869 // tag : V6_vpackwuh_sat_128B
5870 def int_hexagon_V6_vpackwuh_sat_128B :
5871 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">;
5872
5873 //
5874 // BUILTIN_INFO(HEXAGON.V6_vpackwh_sat,VI_ftype_VIVI,2)
5875 // tag : V6_vpackwh_sat
5876 def int_hexagon_V6_vpackwh_sat :
5877 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackwh_sat">;
5878
5879 //
5880 // BUILTIN_INFO(HEXAGON.V6_vpackwh_sat_128B,VI_ftype_VIVI,2)
5881 // tag : V6_vpackwh_sat_128B
5882 def int_hexagon_V6_vpackwh_sat_128B :
5883 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">;
5884
5885 //
5886 // BUILTIN_INFO(HEXAGON.V6_vzb,VD_ftype_VI,1)
5887 // tag : V6_vzb
5888 def int_hexagon_V6_vzb :
5889 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vzb">;
5890
5891 //
5892 // BUILTIN_INFO(HEXAGON.V6_vzb_128B,VD_ftype_VI,1)
5893 // tag : V6_vzb_128B
5894 def int_hexagon_V6_vzb_128B :
5895 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vzb_128B">;
5896
5897 //
5898 // BUILTIN_INFO(HEXAGON.V6_vsb,VD_ftype_VI,1)
5899 // tag : V6_vsb
5900 def int_hexagon_V6_vsb :
5901 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vsb">;
5902
5903 //
5904 // BUILTIN_INFO(HEXAGON.V6_vsb_128B,VD_ftype_VI,1)
5905 // tag : V6_vsb_128B
5906 def int_hexagon_V6_vsb_128B :
5907 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vsb_128B">;
5908
5909 //
5910 // BUILTIN_INFO(HEXAGON.V6_vzh,VD_ftype_VI,1)
5911 // tag : V6_vzh
5912 def int_hexagon_V6_vzh :
5913 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vzh">;
5914
5915 //
5916 // BUILTIN_INFO(HEXAGON.V6_vzh_128B,VD_ftype_VI,1)
5917 // tag : V6_vzh_128B
5918 def int_hexagon_V6_vzh_128B :
5919 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vzh_128B">;
5920
5921 //
5922 // BUILTIN_INFO(HEXAGON.V6_vsh,VD_ftype_VI,1)
5923 // tag : V6_vsh
5924 def int_hexagon_V6_vsh :
5925 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vsh">;
5926
5927 //
5928 // BUILTIN_INFO(HEXAGON.V6_vsh_128B,VD_ftype_VI,1)
5929 // tag : V6_vsh_128B
5930 def int_hexagon_V6_vsh_128B :
5931 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vsh_128B">;
5932
5933 //
5934 // BUILTIN_INFO(HEXAGON.V6_vdmpybus,VI_ftype_VISI,2)
5935 // tag : V6_vdmpybus
5936 def int_hexagon_V6_vdmpybus :
5937 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpybus">;
5938
5939 //
5940 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_128B,VI_ftype_VISI,2)
5941 // tag : V6_vdmpybus_128B
5942 def int_hexagon_V6_vdmpybus_128B :
5943 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_128B">;
5944
5945 //
5946 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_acc,VI_ftype_VIVISI,3)
5947 // tag : V6_vdmpybus_acc
5948 def int_hexagon_V6_vdmpybus_acc :
5949 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpybus_acc">;
5950
5951 //
5952 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_acc_128B,VI_ftype_VIVISI,3)
5953 // tag : V6_vdmpybus_acc_128B
5954 def int_hexagon_V6_vdmpybus_acc_128B :
5955 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">;
5956
5957 //
5958 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv,VD_ftype_VDSI,2)
5959 // tag : V6_vdmpybus_dv
5960 def int_hexagon_V6_vdmpybus_dv :
5961 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_dv">;
5962
5963 //
5964 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_128B,VD_ftype_VDSI,2)
5965 // tag : V6_vdmpybus_dv_128B
5966 def int_hexagon_V6_vdmpybus_dv_128B :
5967 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">;
5968
5969 //
5970 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_acc,VD_ftype_VDVDSI,3)
5971 // tag : V6_vdmpybus_dv_acc
5972 def int_hexagon_V6_vdmpybus_dv_acc :
5973 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">;
5974
5975 //
5976 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_acc_128B,VD_ftype_VDVDSI,3)
5977 // tag : V6_vdmpybus_dv_acc_128B
5978 def int_hexagon_V6_vdmpybus_dv_acc_128B :
5979 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">;
5980
5981 //
5982 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb,VI_ftype_VISI,2)
5983 // tag : V6_vdmpyhb
5984 def int_hexagon_V6_vdmpyhb :
5985 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhb">;
5986
5987 //
5988 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_128B,VI_ftype_VISI,2)
5989 // tag : V6_vdmpyhb_128B
5990 def int_hexagon_V6_vdmpyhb_128B :
5991 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">;
5992
5993 //
5994 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_acc,VI_ftype_VIVISI,3)
5995 // tag : V6_vdmpyhb_acc
5996 def int_hexagon_V6_vdmpyhb_acc :
5997 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">;
5998
5999 //
6000 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_acc_128B,VI_ftype_VIVISI,3)
6001 // tag : V6_vdmpyhb_acc_128B
6002 def int_hexagon_V6_vdmpyhb_acc_128B :
6003 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">;
6004
6005 //
6006 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv,VD_ftype_VDSI,2)
6007 // tag : V6_vdmpyhb_dv
6008 def int_hexagon_V6_vdmpyhb_dv :
6009 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">;
6010
6011 //
6012 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_128B,VD_ftype_VDSI,2)
6013 // tag : V6_vdmpyhb_dv_128B
6014 def int_hexagon_V6_vdmpyhb_dv_128B :
6015 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">;
6016
6017 //
6018 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_acc,VD_ftype_VDVDSI,3)
6019 // tag : V6_vdmpyhb_dv_acc
6020 def int_hexagon_V6_vdmpyhb_dv_acc :
6021 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">;
6022
6023 //
6024 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_acc_128B,VD_ftype_VDVDSI,3)
6025 // tag : V6_vdmpyhb_dv_acc_128B
6026 def int_hexagon_V6_vdmpyhb_dv_acc_128B :
6027 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">;
6028
6029 //
6030 // BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat,VI_ftype_VIVI,2)
6031 // tag : V6_vdmpyhvsat
6032 def int_hexagon_V6_vdmpyhvsat :
6033 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdmpyhvsat">;
6034
6035 //
6036 // BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_128B,VI_ftype_VIVI,2)
6037 // tag : V6_vdmpyhvsat_128B
6038 def int_hexagon_V6_vdmpyhvsat_128B :
6039 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">;
6040
6041 //
6042 // BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_acc,VI_ftype_VIVIVI,3)
6043 // tag : V6_vdmpyhvsat_acc
6044 def int_hexagon_V6_vdmpyhvsat_acc :
6045 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">;
6046
6047 //
6048 // BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_acc_128B,VI_ftype_VIVIVI,3)
6049 // tag : V6_vdmpyhvsat_acc_128B
6050 def int_hexagon_V6_vdmpyhvsat_acc_128B :
6051 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">;
6052
6053 //
6054 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsat,VI_ftype_VISI,2)
6055 // tag : V6_vdmpyhsat
6056 def int_hexagon_V6_vdmpyhsat :
6057 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsat">;
6058
6059 //
6060 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_128B,VI_ftype_VISI,2)
6061 // tag : V6_vdmpyhsat_128B
6062 def int_hexagon_V6_vdmpyhsat_128B :
6063 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">;
6064
6065 //
6066 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_acc,VI_ftype_VIVISI,3)
6067 // tag : V6_vdmpyhsat_acc
6068 def int_hexagon_V6_vdmpyhsat_acc :
6069 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">;
6070
6071 //
6072 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_acc_128B,VI_ftype_VIVISI,3)
6073 // tag : V6_vdmpyhsat_acc_128B
6074 def int_hexagon_V6_vdmpyhsat_acc_128B :
6075 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">;
6076
6077 //
6078 // BUILTIN_INFO(HEXAGON.V6_vdmpyhisat,VI_ftype_VDSI,2)
6079 // tag : V6_vdmpyhisat
6080 def int_hexagon_V6_vdmpyhisat :
6081 Hexagon_v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhisat">;
6082
6083 //
6084 // BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_128B,VI_ftype_VDSI,2)
6085 // tag : V6_vdmpyhisat_128B
6086 def int_hexagon_V6_vdmpyhisat_128B :
6087 Hexagon_v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">;
6088
6089 //
6090 // BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_acc,VI_ftype_VIVDSI,3)
6091 // tag : V6_vdmpyhisat_acc
6092 def int_hexagon_V6_vdmpyhisat_acc :
6093 Hexagon_v512v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">;
6094
6095 //
6096 // BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_acc_128B,VI_ftype_VIVDSI,3)
6097 // tag : V6_vdmpyhisat_acc_128B
6098 def int_hexagon_V6_vdmpyhisat_acc_128B :
6099 Hexagon_v1024v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">;
6100
6101 //
6102 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat,VI_ftype_VISI,2)
6103 // tag : V6_vdmpyhsusat
6104 def int_hexagon_V6_vdmpyhsusat :
6105 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsusat">;
6106
6107 //
6108 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_128B,VI_ftype_VISI,2)
6109 // tag : V6_vdmpyhsusat_128B
6110 def int_hexagon_V6_vdmpyhsusat_128B :
6111 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">;
6112
6113 //
6114 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_acc,VI_ftype_VIVISI,3)
6115 // tag : V6_vdmpyhsusat_acc
6116 def int_hexagon_V6_vdmpyhsusat_acc :
6117 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">;
6118
6119 //
6120 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_acc_128B,VI_ftype_VIVISI,3)
6121 // tag : V6_vdmpyhsusat_acc_128B
6122 def int_hexagon_V6_vdmpyhsusat_acc_128B :
6123 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">;
6124
6125 //
6126 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat,VI_ftype_VDSI,2)
6127 // tag : V6_vdmpyhsuisat
6128 def int_hexagon_V6_vdmpyhsuisat :
6129 Hexagon_v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">;
6130
6131 //
6132 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_128B,VI_ftype_VDSI,2)
6133 // tag : V6_vdmpyhsuisat_128B
6134 def int_hexagon_V6_vdmpyhsuisat_128B :
6135 Hexagon_v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">;
6136
6137 //
6138 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_acc,VI_ftype_VIVDSI,3)
6139 // tag : V6_vdmpyhsuisat_acc
6140 def int_hexagon_V6_vdmpyhsuisat_acc :
6141 Hexagon_v512v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">;
6142
6143 //
6144 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_acc_128B,VI_ftype_VIVDSI,3)
6145 // tag : V6_vdmpyhsuisat_acc_128B
6146 def int_hexagon_V6_vdmpyhsuisat_acc_128B :
6147 Hexagon_v1024v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">;
6148
6149 //
6150 // BUILTIN_INFO(HEXAGON.V6_vtmpyb,VD_ftype_VDSI,2)
6151 // tag : V6_vtmpyb
6152 def int_hexagon_V6_vtmpyb :
6153 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyb">;
6154
6155 //
6156 // BUILTIN_INFO(HEXAGON.V6_vtmpyb_128B,VD_ftype_VDSI,2)
6157 // tag : V6_vtmpyb_128B
6158 def int_hexagon_V6_vtmpyb_128B :
6159 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyb_128B">;
6160
6161 //
6162 // BUILTIN_INFO(HEXAGON.V6_vtmpyb_acc,VD_ftype_VDVDSI,3)
6163 // tag : V6_vtmpyb_acc
6164 def int_hexagon_V6_vtmpyb_acc :
6165 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyb_acc">;
6166
6167 //
6168 // BUILTIN_INFO(HEXAGON.V6_vtmpyb_acc_128B,VD_ftype_VDVDSI,3)
6169 // tag : V6_vtmpyb_acc_128B
6170 def int_hexagon_V6_vtmpyb_acc_128B :
6171 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">;
6172
6173 //
6174 // BUILTIN_INFO(HEXAGON.V6_vtmpybus,VD_ftype_VDSI,2)
6175 // tag : V6_vtmpybus
6176 def int_hexagon_V6_vtmpybus :
6177 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpybus">;
6178
6179 //
6180 // BUILTIN_INFO(HEXAGON.V6_vtmpybus_128B,VD_ftype_VDSI,2)
6181 // tag : V6_vtmpybus_128B
6182 def int_hexagon_V6_vtmpybus_128B :
6183 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpybus_128B">;
6184
6185 //
6186 // BUILTIN_INFO(HEXAGON.V6_vtmpybus_acc,VD_ftype_VDVDSI,3)
6187 // tag : V6_vtmpybus_acc
6188 def int_hexagon_V6_vtmpybus_acc :
6189 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpybus_acc">;
6190
6191 //
6192 // BUILTIN_INFO(HEXAGON.V6_vtmpybus_acc_128B,VD_ftype_VDVDSI,3)
6193 // tag : V6_vtmpybus_acc_128B
6194 def int_hexagon_V6_vtmpybus_acc_128B :
6195 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">;
6196
6197 //
6198 // BUILTIN_INFO(HEXAGON.V6_vtmpyhb,VD_ftype_VDSI,2)
6199 // tag : V6_vtmpyhb
6200 def int_hexagon_V6_vtmpyhb :
6201 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyhb">;
6202
6203 //
6204 // BUILTIN_INFO(HEXAGON.V6_vtmpyhb_128B,VD_ftype_VDSI,2)
6205 // tag : V6_vtmpyhb_128B
6206 def int_hexagon_V6_vtmpyhb_128B :
6207 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">;
6208
6209 //
6210 // BUILTIN_INFO(HEXAGON.V6_vtmpyhb_acc,VD_ftype_VDVDSI,3)
6211 // tag : V6_vtmpyhb_acc
6212 def int_hexagon_V6_vtmpyhb_acc :
6213 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">;
6214
6215 //
6216 // BUILTIN_INFO(HEXAGON.V6_vtmpyhb_acc_128B,VD_ftype_VDVDSI,3)
6217 // tag : V6_vtmpyhb_acc_128B
6218 def int_hexagon_V6_vtmpyhb_acc_128B :
6219 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">;
6220
6221 //
6222 // BUILTIN_INFO(HEXAGON.V6_vrmpyub,VI_ftype_VISI,2)
6223 // tag : V6_vrmpyub
6224 def int_hexagon_V6_vrmpyub :
6225 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vrmpyub">;
6226
6227 //
6228 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_128B,VI_ftype_VISI,2)
6229 // tag : V6_vrmpyub_128B
6230 def int_hexagon_V6_vrmpyub_128B :
6231 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpyub_128B">;
6232
6233 //
6234 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_acc,VI_ftype_VIVISI,3)
6235 // tag : V6_vrmpyub_acc
6236 def int_hexagon_V6_vrmpyub_acc :
6237 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vrmpyub_acc">;
6238
6239 //
6240 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_acc_128B,VI_ftype_VIVISI,3)
6241 // tag : V6_vrmpyub_acc_128B
6242 def int_hexagon_V6_vrmpyub_acc_128B :
6243 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">;
6244
6245 //
6246 // BUILTIN_INFO(HEXAGON.V6_vrmpyubv,VI_ftype_VIVI,2)
6247 // tag : V6_vrmpyubv
6248 def int_hexagon_V6_vrmpyubv :
6249 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpyubv">;
6250
6251 //
6252 // BUILTIN_INFO(HEXAGON.V6_vrmpyubv_128B,VI_ftype_VIVI,2)
6253 // tag : V6_vrmpyubv_128B
6254 def int_hexagon_V6_vrmpyubv_128B :
6255 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">;
6256
6257 //
6258 // BUILTIN_INFO(HEXAGON.V6_vrmpyubv_acc,VI_ftype_VIVIVI,3)
6259 // tag : V6_vrmpyubv_acc
6260 def int_hexagon_V6_vrmpyubv_acc :
6261 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">;
6262
6263 //
6264 // BUILTIN_INFO(HEXAGON.V6_vrmpyubv_acc_128B,VI_ftype_VIVIVI,3)
6265 // tag : V6_vrmpyubv_acc_128B
6266 def int_hexagon_V6_vrmpyubv_acc_128B :
6267 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">;
6268
6269 //
6270 // BUILTIN_INFO(HEXAGON.V6_vrmpybv,VI_ftype_VIVI,2)
6271 // tag : V6_vrmpybv
6272 def int_hexagon_V6_vrmpybv :
6273 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybv">;
6274
6275 //
6276 // BUILTIN_INFO(HEXAGON.V6_vrmpybv_128B,VI_ftype_VIVI,2)
6277 // tag : V6_vrmpybv_128B
6278 def int_hexagon_V6_vrmpybv_128B :
6279 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybv_128B">;
6280
6281 //
6282 // BUILTIN_INFO(HEXAGON.V6_vrmpybv_acc,VI_ftype_VIVIVI,3)
6283 // tag : V6_vrmpybv_acc
6284 def int_hexagon_V6_vrmpybv_acc :
6285 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybv_acc">;
6286
6287 //
6288 // BUILTIN_INFO(HEXAGON.V6_vrmpybv_acc_128B,VI_ftype_VIVIVI,3)
6289 // tag : V6_vrmpybv_acc_128B
6290 def int_hexagon_V6_vrmpybv_acc_128B :
6291 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">;
6292
6293 //
6294 // BUILTIN_INFO(HEXAGON.V6_vrmpyubi,VD_ftype_VDSISI,3)
6295 // tag : V6_vrmpyubi
6296 def int_hexagon_V6_vrmpyubi :
6297 Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpyubi">;
6298
6299 //
6300 // BUILTIN_INFO(HEXAGON.V6_vrmpyubi_128B,VD_ftype_VDSISI,3)
6301 // tag : V6_vrmpyubi_128B
6302 def int_hexagon_V6_vrmpyubi_128B :
6303 Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpyubi_128B">;
6304
6305 //
6306 // BUILTIN_INFO(HEXAGON.V6_vrmpyubi_acc,VD_ftype_VDVDSISI,4)
6307 // tag : V6_vrmpyubi_acc
6308 def int_hexagon_V6_vrmpyubi_acc :
6309 Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpyubi_acc">;
6310
6311 //
6312 // BUILTIN_INFO(HEXAGON.V6_vrmpyubi_acc_128B,VD_ftype_VDVDSISI,4)
6313 // tag : V6_vrmpyubi_acc_128B
6314 def int_hexagon_V6_vrmpyubi_acc_128B :
6315 Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B">;
6316
6317 //
6318 // BUILTIN_INFO(HEXAGON.V6_vrmpybus,VI_ftype_VISI,2)
6319 // tag : V6_vrmpybus
6320 def int_hexagon_V6_vrmpybus :
6321 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vrmpybus">;
6322
6323 //
6324 // BUILTIN_INFO(HEXAGON.V6_vrmpybus_128B,VI_ftype_VISI,2)
6325 // tag : V6_vrmpybus_128B
6326 def int_hexagon_V6_vrmpybus_128B :
6327 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpybus_128B">;
6328
6329 //
6330 // BUILTIN_INFO(HEXAGON.V6_vrmpybus_acc,VI_ftype_VIVISI,3)
6331 // tag : V6_vrmpybus_acc
6332 def int_hexagon_V6_vrmpybus_acc :
6333 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vrmpybus_acc">;
6334
6335 //
6336 // BUILTIN_INFO(HEXAGON.V6_vrmpybus_acc_128B,VI_ftype_VIVISI,3)
6337 // tag : V6_vrmpybus_acc_128B
6338 def int_hexagon_V6_vrmpybus_acc_128B :
6339 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">;
6340
6341 //
6342 // BUILTIN_INFO(HEXAGON.V6_vrmpybusi,VD_ftype_VDSISI,3)
6343 // tag : V6_vrmpybusi
6344 def int_hexagon_V6_vrmpybusi :
6345 Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpybusi">;
6346
6347 //
6348 // BUILTIN_INFO(HEXAGON.V6_vrmpybusi_128B,VD_ftype_VDSISI,3)
6349 // tag : V6_vrmpybusi_128B
6350 def int_hexagon_V6_vrmpybusi_128B :
6351 Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpybusi_128B">;
6352
6353 //
6354 // BUILTIN_INFO(HEXAGON.V6_vrmpybusi_acc,VD_ftype_VDVDSISI,4)
6355 // tag : V6_vrmpybusi_acc
6356 def int_hexagon_V6_vrmpybusi_acc :
6357 Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpybusi_acc">;
6358
6359 //
6360 // BUILTIN_INFO(HEXAGON.V6_vrmpybusi_acc_128B,VD_ftype_VDVDSISI,4)
6361 // tag : V6_vrmpybusi_acc_128B
6362 def int_hexagon_V6_vrmpybusi_acc_128B :
6363 Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B">;
6364
6365 //
6366 // BUILTIN_INFO(HEXAGON.V6_vrmpybusv,VI_ftype_VIVI,2)
6367 // tag : V6_vrmpybusv
6368 def int_hexagon_V6_vrmpybusv :
6369 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybusv">;
6370
6371 //
6372 // BUILTIN_INFO(HEXAGON.V6_vrmpybusv_128B,VI_ftype_VIVI,2)
6373 // tag : V6_vrmpybusv_128B
6374 def int_hexagon_V6_vrmpybusv_128B :
6375 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">;
6376
6377 //
6378 // BUILTIN_INFO(HEXAGON.V6_vrmpybusv_acc,VI_ftype_VIVIVI,3)
6379 // tag : V6_vrmpybusv_acc
6380 def int_hexagon_V6_vrmpybusv_acc :
6381 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">;
6382
6383 //
6384 // BUILTIN_INFO(HEXAGON.V6_vrmpybusv_acc_128B,VI_ftype_VIVIVI,3)
6385 // tag : V6_vrmpybusv_acc_128B
6386 def int_hexagon_V6_vrmpybusv_acc_128B :
6387 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">;
6388
6389 //
6390 // BUILTIN_INFO(HEXAGON.V6_vdsaduh,VD_ftype_VDSI,2)
6391 // tag : V6_vdsaduh
6392 def int_hexagon_V6_vdsaduh :
6393 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdsaduh">;
6394
6395 //
6396 // BUILTIN_INFO(HEXAGON.V6_vdsaduh_128B,VD_ftype_VDSI,2)
6397 // tag : V6_vdsaduh_128B
6398 def int_hexagon_V6_vdsaduh_128B :
6399 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdsaduh_128B">;
6400
6401 //
6402 // BUILTIN_INFO(HEXAGON.V6_vdsaduh_acc,VD_ftype_VDVDSI,3)
6403 // tag : V6_vdsaduh_acc
6404 def int_hexagon_V6_vdsaduh_acc :
6405 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdsaduh_acc">;
6406
6407 //
6408 // BUILTIN_INFO(HEXAGON.V6_vdsaduh_acc_128B,VD_ftype_VDVDSI,3)
6409 // tag : V6_vdsaduh_acc_128B
6410 def int_hexagon_V6_vdsaduh_acc_128B :
6411 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">;
6412
6413 //
6414 // BUILTIN_INFO(HEXAGON.V6_vrsadubi,VD_ftype_VDSISI,3)
6415 // tag : V6_vrsadubi
6416 def int_hexagon_V6_vrsadubi :
6417 Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrsadubi">;
6418
6419 //
6420 // BUILTIN_INFO(HEXAGON.V6_vrsadubi_128B,VD_ftype_VDSISI,3)
6421 // tag : V6_vrsadubi_128B
6422 def int_hexagon_V6_vrsadubi_128B :
6423 Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrsadubi_128B">;
6424
6425 //
6426 // BUILTIN_INFO(HEXAGON.V6_vrsadubi_acc,VD_ftype_VDVDSISI,4)
6427 // tag : V6_vrsadubi_acc
6428 def int_hexagon_V6_vrsadubi_acc :
6429 Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrsadubi_acc">;
6430
6431 //
6432 // BUILTIN_INFO(HEXAGON.V6_vrsadubi_acc_128B,VD_ftype_VDVDSISI,4)
6433 // tag : V6_vrsadubi_acc_128B
6434 def int_hexagon_V6_vrsadubi_acc_128B :
6435 Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B">;
6436
6437 //
6438 // BUILTIN_INFO(HEXAGON.V6_vasrw,VI_ftype_VISI,2)
6439 // tag : V6_vasrw
6440 def int_hexagon_V6_vasrw :
6441 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vasrw">;
6442
6443 //
6444 // BUILTIN_INFO(HEXAGON.V6_vasrw_128B,VI_ftype_VISI,2)
6445 // tag : V6_vasrw_128B
6446 def int_hexagon_V6_vasrw_128B :
6447 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vasrw_128B">;
6448
6449
6450 //
6451 // BUILTIN_INFO(HEXAGON.V6_vaslw,VI_ftype_VISI,2)
6452 // tag : V6_vaslw
6453 def int_hexagon_V6_vaslw :
6454 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vaslw">;
6455
6456 //
6457 // BUILTIN_INFO(HEXAGON.V6_vaslw_128B,VI_ftype_VISI,2)
6458 // tag : V6_vaslw_128B
6459 def int_hexagon_V6_vaslw_128B :
6460 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vaslw_128B">;
6461
6462 //
6463 // BUILTIN_INFO(HEXAGON.V6_vlsrw,VI_ftype_VISI,2)
6464 // tag : V6_vlsrw
6465 def int_hexagon_V6_vlsrw :
6466 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vlsrw">;
6467
6468 //
6469 // BUILTIN_INFO(HEXAGON.V6_vlsrw_128B,VI_ftype_VISI,2)
6470 // tag : V6_vlsrw_128B
6471 def int_hexagon_V6_vlsrw_128B :
6472 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrw_128B">;
6473
6474 //
6475 // BUILTIN_INFO(HEXAGON.V6_vasrwv,VI_ftype_VIVI,2)
6476 // tag : V6_vasrwv
6477 def int_hexagon_V6_vasrwv :
6478 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vasrwv">;
6479
6480 //
6481 // BUILTIN_INFO(HEXAGON.V6_vasrwv_128B,VI_ftype_VIVI,2)
6482 // tag : V6_vasrwv_128B
6483 def int_hexagon_V6_vasrwv_128B :
6484 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vasrwv_128B">;
6485
6486 //
6487 // BUILTIN_INFO(HEXAGON.V6_vaslwv,VI_ftype_VIVI,2)
6488 // tag : V6_vaslwv
6489 def int_hexagon_V6_vaslwv :
6490 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaslwv">;
6491
6492 //
6493 // BUILTIN_INFO(HEXAGON.V6_vaslwv_128B,VI_ftype_VIVI,2)
6494 // tag : V6_vaslwv_128B
6495 def int_hexagon_V6_vaslwv_128B :
6496 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaslwv_128B">;
6497
6498 //
6499 // BUILTIN_INFO(HEXAGON.V6_vlsrwv,VI_ftype_VIVI,2)
6500 // tag : V6_vlsrwv
6501 def int_hexagon_V6_vlsrwv :
6502 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vlsrwv">;
6503
6504 //
6505 // BUILTIN_INFO(HEXAGON.V6_vlsrwv_128B,VI_ftype_VIVI,2)
6506 // tag : V6_vlsrwv_128B
6507 def int_hexagon_V6_vlsrwv_128B :
6508 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vlsrwv_128B">;
6509
6510 //
6511 // BUILTIN_INFO(HEXAGON.V6_vasrh,VI_ftype_VISI,2)
6512 // tag : V6_vasrh
6513 def int_hexagon_V6_vasrh :
6514 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vasrh">;
6515
6516 //
6517 // BUILTIN_INFO(HEXAGON.V6_vasrh_128B,VI_ftype_VISI,2)
6518 // tag : V6_vasrh_128B
6519 def int_hexagon_V6_vasrh_128B :
6520 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_128B">;
6521
6522 //
6523 // BUILTIN_INFO(HEXAGON.V6_vaslh,VI_ftype_VISI,2)
6524 // tag : V6_vaslh
6525 def int_hexagon_V6_vaslh :
6526 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vaslh">;
6527
6528 //
6529 // BUILTIN_INFO(HEXAGON.V6_vaslh_128B,VI_ftype_VISI,2)
6530 // tag : V6_vaslh_128B
6531 def int_hexagon_V6_vaslh_128B :
6532 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_128B">;
6533
6534 //
6535 // BUILTIN_INFO(HEXAGON.V6_vlsrh,VI_ftype_VISI,2)
6536 // tag : V6_vlsrh
6537 def int_hexagon_V6_vlsrh :
6538 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vlsrh">;
6539
6540 //
6541 // BUILTIN_INFO(HEXAGON.V6_vlsrh_128B,VI_ftype_VISI,2)
6542 // tag : V6_vlsrh_128B
6543 def int_hexagon_V6_vlsrh_128B :
6544 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrh_128B">;
6545
6546 //
6547 // BUILTIN_INFO(HEXAGON.V6_vasrhv,VI_ftype_VIVI,2)
6548 // tag : V6_vasrhv
6549 def int_hexagon_V6_vasrhv :
6550 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vasrhv">;
6551
6552 //
6553 // BUILTIN_INFO(HEXAGON.V6_vasrhv_128B,VI_ftype_VIVI,2)
6554 // tag : V6_vasrhv_128B
6555 def int_hexagon_V6_vasrhv_128B :
6556 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vasrhv_128B">;
6557
6558 //
6559 // BUILTIN_INFO(HEXAGON.V6_vaslhv,VI_ftype_VIVI,2)
6560 // tag : V6_vaslhv
6561 def int_hexagon_V6_vaslhv :
6562 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaslhv">;
6563
6564 //
6565 // BUILTIN_INFO(HEXAGON.V6_vaslhv_128B,VI_ftype_VIVI,2)
6566 // tag : V6_vaslhv_128B
6567 def int_hexagon_V6_vaslhv_128B :
6568 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaslhv_128B">;
6569
6570 //
6571 // BUILTIN_INFO(HEXAGON.V6_vlsrhv,VI_ftype_VIVI,2)
6572 // tag : V6_vlsrhv
6573 def int_hexagon_V6_vlsrhv :
6574 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vlsrhv">;
6575
6576 //
6577 // BUILTIN_INFO(HEXAGON.V6_vlsrhv_128B,VI_ftype_VIVI,2)
6578 // tag : V6_vlsrhv_128B
6579 def int_hexagon_V6_vlsrhv_128B :
6580 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vlsrhv_128B">;
6581
6582 //
6583 // BUILTIN_INFO(HEXAGON.V6_vasrwh,VI_ftype_VIVISI,3)
6584 // tag : V6_vasrwh
6585 def int_hexagon_V6_vasrwh :
6586 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwh">;
6587
6588 //
6589 // BUILTIN_INFO(HEXAGON.V6_vasrwh_128B,VI_ftype_VIVISI,3)
6590 // tag : V6_vasrwh_128B
6591 def int_hexagon_V6_vasrwh_128B :
6592 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwh_128B">;
6593
6594 //
6595 // BUILTIN_INFO(HEXAGON.V6_vasrwhsat,VI_ftype_VIVISI,3)
6596 // tag : V6_vasrwhsat
6597 def int_hexagon_V6_vasrwhsat :
6598 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwhsat">;
6599
6600 //
6601 // BUILTIN_INFO(HEXAGON.V6_vasrwhsat_128B,VI_ftype_VIVISI,3)
6602 // tag : V6_vasrwhsat_128B
6603 def int_hexagon_V6_vasrwhsat_128B :
6604 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">;
6605
6606 //
6607 // BUILTIN_INFO(HEXAGON.V6_vasrwhrndsat,VI_ftype_VIVISI,3)
6608 // tag : V6_vasrwhrndsat
6609 def int_hexagon_V6_vasrwhrndsat :
6610 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwhrndsat">;
6611
6612 //
6613 // BUILTIN_INFO(HEXAGON.V6_vasrwhrndsat_128B,VI_ftype_VIVISI,3)
6614 // tag : V6_vasrwhrndsat_128B
6615 def int_hexagon_V6_vasrwhrndsat_128B :
6616 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">;
6617
6618 //
6619 // BUILTIN_INFO(HEXAGON.V6_vasrwuhsat,VI_ftype_VIVISI,3)
6620 // tag : V6_vasrwuhsat
6621 def int_hexagon_V6_vasrwuhsat :
6622 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwuhsat">;
6623
6624 //
6625 // BUILTIN_INFO(HEXAGON.V6_vasrwuhsat_128B,VI_ftype_VIVISI,3)
6626 // tag : V6_vasrwuhsat_128B
6627 def int_hexagon_V6_vasrwuhsat_128B :
6628 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">;
6629
6630 //
6631 // BUILTIN_INFO(HEXAGON.V6_vroundwh,VI_ftype_VIVI,2)
6632 // tag : V6_vroundwh
6633 def int_hexagon_V6_vroundwh :
6634 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundwh">;
6635
6636 //
6637 // BUILTIN_INFO(HEXAGON.V6_vroundwh_128B,VI_ftype_VIVI,2)
6638 // tag : V6_vroundwh_128B
6639 def int_hexagon_V6_vroundwh_128B :
6640 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundwh_128B">;
6641
6642 //
6643 // BUILTIN_INFO(HEXAGON.V6_vroundwuh,VI_ftype_VIVI,2)
6644 // tag : V6_vroundwuh
6645 def int_hexagon_V6_vroundwuh :
6646 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundwuh">;
6647
6648 //
6649 // BUILTIN_INFO(HEXAGON.V6_vroundwuh_128B,VI_ftype_VIVI,2)
6650 // tag : V6_vroundwuh_128B
6651 def int_hexagon_V6_vroundwuh_128B :
6652 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundwuh_128B">;
6653
6654 //
6655 // BUILTIN_INFO(HEXAGON.V6_vasrhubsat,VI_ftype_VIVISI,3)
6656 // tag : V6_vasrhubsat
6657 def int_hexagon_V6_vasrhubsat :
6658 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhubsat">;
6659
6660 //
6661 // BUILTIN_INFO(HEXAGON.V6_vasrhubsat_128B,VI_ftype_VIVISI,3)
6662 // tag : V6_vasrhubsat_128B
6663 def int_hexagon_V6_vasrhubsat_128B :
6664 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">;
6665
6666 //
6667 // BUILTIN_INFO(HEXAGON.V6_vasrhubrndsat,VI_ftype_VIVISI,3)
6668 // tag : V6_vasrhubrndsat
6669 def int_hexagon_V6_vasrhubrndsat :
6670 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhubrndsat">;
6671
6672 //
6673 // BUILTIN_INFO(HEXAGON.V6_vasrhubrndsat_128B,VI_ftype_VIVISI,3)
6674 // tag : V6_vasrhubrndsat_128B
6675 def int_hexagon_V6_vasrhubrndsat_128B :
6676 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">;
6677
6678 //
6679 // BUILTIN_INFO(HEXAGON.V6_vasrhbrndsat,VI_ftype_VIVISI,3)
6680 // tag : V6_vasrhbrndsat
6681 def int_hexagon_V6_vasrhbrndsat :
6682 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhbrndsat">;
6683
6684 //
6685 // BUILTIN_INFO(HEXAGON.V6_vasrhbrndsat_128B,VI_ftype_VIVISI,3)
6686 // tag : V6_vasrhbrndsat_128B
6687 def int_hexagon_V6_vasrhbrndsat_128B :
6688 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">;
6689
6690 //
6691 // BUILTIN_INFO(HEXAGON.V6_vroundhb,VI_ftype_VIVI,2)
6692 // tag : V6_vroundhb
6693 def int_hexagon_V6_vroundhb :
6694 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundhb">;
6695
6696 //
6697 // BUILTIN_INFO(HEXAGON.V6_vroundhb_128B,VI_ftype_VIVI,2)
6698 // tag : V6_vroundhb_128B
6699 def int_hexagon_V6_vroundhb_128B :
6700 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundhb_128B">;
6701
6702 //
6703 // BUILTIN_INFO(HEXAGON.V6_vroundhub,VI_ftype_VIVI,2)
6704 // tag : V6_vroundhub
6705 def int_hexagon_V6_vroundhub :
6706 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundhub">;
6707
6708 //
6709 // BUILTIN_INFO(HEXAGON.V6_vroundhub_128B,VI_ftype_VIVI,2)
6710 // tag : V6_vroundhub_128B
6711 def int_hexagon_V6_vroundhub_128B :
6712 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundhub_128B">;
6713
6714 //
6715 // BUILTIN_INFO(HEXAGON.V6_vaslw_acc,VI_ftype_VIVISI,3)
6716 // tag : V6_vaslw_acc
6717 def int_hexagon_V6_vaslw_acc :
6718 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslw_acc">;
6719
6720 //
6721 // BUILTIN_INFO(HEXAGON.V6_vaslw_acc_128B,VI_ftype_VIVISI,3)
6722 // tag : V6_vaslw_acc_128B
6723 def int_hexagon_V6_vaslw_acc_128B :
6724 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">;
6725
6726 //
6727 // BUILTIN_INFO(HEXAGON.V6_vasrw_acc,VI_ftype_VIVISI,3)
6728 // tag : V6_vasrw_acc
6729 def int_hexagon_V6_vasrw_acc :
6730 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrw_acc">;
6731
6732 //
6733 // BUILTIN_INFO(HEXAGON.V6_vasrw_acc_128B,VI_ftype_VIVISI,3)
6734 // tag : V6_vasrw_acc_128B
6735 def int_hexagon_V6_vasrw_acc_128B :
6736 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">;
6737
6738 //
6739 // BUILTIN_INFO(HEXAGON.V6_vaddb,VI_ftype_VIVI,2)
6740 // tag : V6_vaddb
6741 def int_hexagon_V6_vaddb :
6742 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddb">;
6743
6744 //
6745 // BUILTIN_INFO(HEXAGON.V6_vaddb_128B,VI_ftype_VIVI,2)
6746 // tag : V6_vaddb_128B
6747 def int_hexagon_V6_vaddb_128B :
6748 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddb_128B">;
6749
6750 //
6751 // BUILTIN_INFO(HEXAGON.V6_vsubb,VI_ftype_VIVI,2)
6752 // tag : V6_vsubb
6753 def int_hexagon_V6_vsubb :
6754 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubb">;
6755
6756 //
6757 // BUILTIN_INFO(HEXAGON.V6_vsubb_128B,VI_ftype_VIVI,2)
6758 // tag : V6_vsubb_128B
6759 def int_hexagon_V6_vsubb_128B :
6760 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubb_128B">;
6761
6762 //
6763 // BUILTIN_INFO(HEXAGON.V6_vaddb_dv,VD_ftype_VDVD,2)
6764 // tag : V6_vaddb_dv
6765 def int_hexagon_V6_vaddb_dv :
6766 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddb_dv">;
6767
6768 //
6769 // BUILTIN_INFO(HEXAGON.V6_vaddb_dv_128B,VD_ftype_VDVD,2)
6770 // tag : V6_vaddb_dv_128B
6771 def int_hexagon_V6_vaddb_dv_128B :
6772 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">;
6773
6774 //
6775 // BUILTIN_INFO(HEXAGON.V6_vsubb_dv,VD_ftype_VDVD,2)
6776 // tag : V6_vsubb_dv
6777 def int_hexagon_V6_vsubb_dv :
6778 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubb_dv">;
6779
6780 //
6781 // BUILTIN_INFO(HEXAGON.V6_vsubb_dv_128B,VD_ftype_VDVD,2)
6782 // tag : V6_vsubb_dv_128B
6783 def int_hexagon_V6_vsubb_dv_128B :
6784 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">;
6785
6786 //
6787 // BUILTIN_INFO(HEXAGON.V6_vaddh,VI_ftype_VIVI,2)
6788 // tag : V6_vaddh
6789 def int_hexagon_V6_vaddh :
6790 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddh">;
6791
6792 //
6793 // BUILTIN_INFO(HEXAGON.V6_vaddh_128B,VI_ftype_VIVI,2)
6794 // tag : V6_vaddh_128B
6795 def int_hexagon_V6_vaddh_128B :
6796 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddh_128B">;
6797
6798 //
6799 // BUILTIN_INFO(HEXAGON.V6_vsubh,VI_ftype_VIVI,2)
6800 // tag : V6_vsubh
6801 def int_hexagon_V6_vsubh :
6802 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubh">;
6803
6804 //
6805 // BUILTIN_INFO(HEXAGON.V6_vsubh_128B,VI_ftype_VIVI,2)
6806 // tag : V6_vsubh_128B
6807 def int_hexagon_V6_vsubh_128B :
6808 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubh_128B">;
6809
6810 //
6811 // BUILTIN_INFO(HEXAGON.V6_vaddh_dv,VD_ftype_VDVD,2)
6812 // tag : V6_vaddh_dv
6813 def int_hexagon_V6_vaddh_dv :
6814 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddh_dv">;
6815
6816 //
6817 // BUILTIN_INFO(HEXAGON.V6_vaddh_dv_128B,VD_ftype_VDVD,2)
6818 // tag : V6_vaddh_dv_128B
6819 def int_hexagon_V6_vaddh_dv_128B :
6820 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">;
6821
6822 //
6823 // BUILTIN_INFO(HEXAGON.V6_vsubh_dv,VD_ftype_VDVD,2)
6824 // tag : V6_vsubh_dv
6825 def int_hexagon_V6_vsubh_dv :
6826 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubh_dv">;
6827
6828 //
6829 // BUILTIN_INFO(HEXAGON.V6_vsubh_dv_128B,VD_ftype_VDVD,2)
6830 // tag : V6_vsubh_dv_128B
6831 def int_hexagon_V6_vsubh_dv_128B :
6832 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">;
6833
6834 //
6835 // BUILTIN_INFO(HEXAGON.V6_vaddw,VI_ftype_VIVI,2)
6836 // tag : V6_vaddw
6837 def int_hexagon_V6_vaddw :
6838 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddw">;
6839
6840 //
6841 // BUILTIN_INFO(HEXAGON.V6_vaddw_128B,VI_ftype_VIVI,2)
6842 // tag : V6_vaddw_128B
6843 def int_hexagon_V6_vaddw_128B :
6844 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddw_128B">;
6845
6846 //
6847 // BUILTIN_INFO(HEXAGON.V6_vsubw,VI_ftype_VIVI,2)
6848 // tag : V6_vsubw
6849 def int_hexagon_V6_vsubw :
6850 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubw">;
6851
6852 //
6853 // BUILTIN_INFO(HEXAGON.V6_vsubw_128B,VI_ftype_VIVI,2)
6854 // tag : V6_vsubw_128B
6855 def int_hexagon_V6_vsubw_128B :
6856 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubw_128B">;
6857
6858 //
6859 // BUILTIN_INFO(HEXAGON.V6_vaddw_dv,VD_ftype_VDVD,2)
6860 // tag : V6_vaddw_dv
6861 def int_hexagon_V6_vaddw_dv :
6862 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddw_dv">;
6863
6864 //
6865 // BUILTIN_INFO(HEXAGON.V6_vaddw_dv_128B,VD_ftype_VDVD,2)
6866 // tag : V6_vaddw_dv_128B
6867 def int_hexagon_V6_vaddw_dv_128B :
6868 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">;
6869
6870 //
6871 // BUILTIN_INFO(HEXAGON.V6_vsubw_dv,VD_ftype_VDVD,2)
6872 // tag : V6_vsubw_dv
6873 def int_hexagon_V6_vsubw_dv :
6874 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubw_dv">;
6875
6876 //
6877 // BUILTIN_INFO(HEXAGON.V6_vsubw_dv_128B,VD_ftype_VDVD,2)
6878 // tag : V6_vsubw_dv_128B
6879 def int_hexagon_V6_vsubw_dv_128B :
6880 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">;
6881
6882 //
6883 // BUILTIN_INFO(HEXAGON.V6_vaddubsat,VI_ftype_VIVI,2)
6884 // tag : V6_vaddubsat
6885 def int_hexagon_V6_vaddubsat :
6886 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddubsat">;
6887
6888 //
6889 // BUILTIN_INFO(HEXAGON.V6_vaddubsat_128B,VI_ftype_VIVI,2)
6890 // tag : V6_vaddubsat_128B
6891 def int_hexagon_V6_vaddubsat_128B :
6892 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddubsat_128B">;
6893
6894 //
6895 // BUILTIN_INFO(HEXAGON.V6_vaddubsat_dv,VD_ftype_VDVD,2)
6896 // tag : V6_vaddubsat_dv
6897 def int_hexagon_V6_vaddubsat_dv :
6898 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddubsat_dv">;
6899
6900 //
6901 // BUILTIN_INFO(HEXAGON.V6_vaddubsat_dv_128B,VD_ftype_VDVD,2)
6902 // tag : V6_vaddubsat_dv_128B
6903 def int_hexagon_V6_vaddubsat_dv_128B :
6904 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">;
6905
6906 //
6907 // BUILTIN_INFO(HEXAGON.V6_vsububsat,VI_ftype_VIVI,2)
6908 // tag : V6_vsububsat
6909 def int_hexagon_V6_vsububsat :
6910 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsububsat">;
6911
6912 //
6913 // BUILTIN_INFO(HEXAGON.V6_vsububsat_128B,VI_ftype_VIVI,2)
6914 // tag : V6_vsububsat_128B
6915 def int_hexagon_V6_vsububsat_128B :
6916 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsububsat_128B">;
6917
6918 //
6919 // BUILTIN_INFO(HEXAGON.V6_vsububsat_dv,VD_ftype_VDVD,2)
6920 // tag : V6_vsububsat_dv
6921 def int_hexagon_V6_vsububsat_dv :
6922 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsububsat_dv">;
6923
6924 //
6925 // BUILTIN_INFO(HEXAGON.V6_vsububsat_dv_128B,VD_ftype_VDVD,2)
6926 // tag : V6_vsububsat_dv_128B
6927 def int_hexagon_V6_vsububsat_dv_128B :
6928 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">;
6929
6930 //
6931 // BUILTIN_INFO(HEXAGON.V6_vadduhsat,VI_ftype_VIVI,2)
6932 // tag : V6_vadduhsat
6933 def int_hexagon_V6_vadduhsat :
6934 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vadduhsat">;
6935
6936 //
6937 // BUILTIN_INFO(HEXAGON.V6_vadduhsat_128B,VI_ftype_VIVI,2)
6938 // tag : V6_vadduhsat_128B
6939 def int_hexagon_V6_vadduhsat_128B :
6940 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduhsat_128B">;
6941
6942 //
6943 // BUILTIN_INFO(HEXAGON.V6_vadduhsat_dv,VD_ftype_VDVD,2)
6944 // tag : V6_vadduhsat_dv
6945 def int_hexagon_V6_vadduhsat_dv :
6946 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduhsat_dv">;
6947
6948 //
6949 // BUILTIN_INFO(HEXAGON.V6_vadduhsat_dv_128B,VD_ftype_VDVD,2)
6950 // tag : V6_vadduhsat_dv_128B
6951 def int_hexagon_V6_vadduhsat_dv_128B :
6952 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">;
6953
6954 //
6955 // BUILTIN_INFO(HEXAGON.V6_vsubuhsat,VI_ftype_VIVI,2)
6956 // tag : V6_vsubuhsat
6957 def int_hexagon_V6_vsubuhsat :
6958 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubuhsat">;
6959
6960 //
6961 // BUILTIN_INFO(HEXAGON.V6_vsubuhsat_128B,VI_ftype_VIVI,2)
6962 // tag : V6_vsubuhsat_128B
6963 def int_hexagon_V6_vsubuhsat_128B :
6964 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">;
6965
6966 //
6967 // BUILTIN_INFO(HEXAGON.V6_vsubuhsat_dv,VD_ftype_VDVD,2)
6968 // tag : V6_vsubuhsat_dv
6969 def int_hexagon_V6_vsubuhsat_dv :
6970 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">;
6971
6972 //
6973 // BUILTIN_INFO(HEXAGON.V6_vsubuhsat_dv_128B,VD_ftype_VDVD,2)
6974 // tag : V6_vsubuhsat_dv_128B
6975 def int_hexagon_V6_vsubuhsat_dv_128B :
6976 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">;
6977
6978 //
6979 // BUILTIN_INFO(HEXAGON.V6_vaddhsat,VI_ftype_VIVI,2)
6980 // tag : V6_vaddhsat
6981 def int_hexagon_V6_vaddhsat :
6982 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddhsat">;
6983
6984 //
6985 // BUILTIN_INFO(HEXAGON.V6_vaddhsat_128B,VI_ftype_VIVI,2)
6986 // tag : V6_vaddhsat_128B
6987 def int_hexagon_V6_vaddhsat_128B :
6988 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddhsat_128B">;
6989
6990 //
6991 // BUILTIN_INFO(HEXAGON.V6_vaddhsat_dv,VD_ftype_VDVD,2)
6992 // tag : V6_vaddhsat_dv
6993 def int_hexagon_V6_vaddhsat_dv :
6994 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddhsat_dv">;
6995
6996 //
6997 // BUILTIN_INFO(HEXAGON.V6_vaddhsat_dv_128B,VD_ftype_VDVD,2)
6998 // tag : V6_vaddhsat_dv_128B
6999 def int_hexagon_V6_vaddhsat_dv_128B :
7000 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">;
7001
7002 //
7003 // BUILTIN_INFO(HEXAGON.V6_vsubhsat,VI_ftype_VIVI,2)
7004 // tag : V6_vsubhsat
7005 def int_hexagon_V6_vsubhsat :
7006 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubhsat">;
7007
7008 //
7009 // BUILTIN_INFO(HEXAGON.V6_vsubhsat_128B,VI_ftype_VIVI,2)
7010 // tag : V6_vsubhsat_128B
7011 def int_hexagon_V6_vsubhsat_128B :
7012 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubhsat_128B">;
7013
7014 //
7015 // BUILTIN_INFO(HEXAGON.V6_vsubhsat_dv,VD_ftype_VDVD,2)
7016 // tag : V6_vsubhsat_dv
7017 def int_hexagon_V6_vsubhsat_dv :
7018 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubhsat_dv">;
7019
7020 //
7021 // BUILTIN_INFO(HEXAGON.V6_vsubhsat_dv_128B,VD_ftype_VDVD,2)
7022 // tag : V6_vsubhsat_dv_128B
7023 def int_hexagon_V6_vsubhsat_dv_128B :
7024 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">;
7025
7026 //
7027 // BUILTIN_INFO(HEXAGON.V6_vaddwsat,VI_ftype_VIVI,2)
7028 // tag : V6_vaddwsat
7029 def int_hexagon_V6_vaddwsat :
7030 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddwsat">;
7031
7032 //
7033 // BUILTIN_INFO(HEXAGON.V6_vaddwsat_128B,VI_ftype_VIVI,2)
7034 // tag : V6_vaddwsat_128B
7035 def int_hexagon_V6_vaddwsat_128B :
7036 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddwsat_128B">;
7037
7038 //
7039 // BUILTIN_INFO(HEXAGON.V6_vaddwsat_dv,VD_ftype_VDVD,2)
7040 // tag : V6_vaddwsat_dv
7041 def int_hexagon_V6_vaddwsat_dv :
7042 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddwsat_dv">;
7043
7044 //
7045 // BUILTIN_INFO(HEXAGON.V6_vaddwsat_dv_128B,VD_ftype_VDVD,2)
7046 // tag : V6_vaddwsat_dv_128B
7047 def int_hexagon_V6_vaddwsat_dv_128B :
7048 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">;
7049
7050 //
7051 // BUILTIN_INFO(HEXAGON.V6_vsubwsat,VI_ftype_VIVI,2)
7052 // tag : V6_vsubwsat
7053 def int_hexagon_V6_vsubwsat :
7054 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubwsat">;
7055
7056 //
7057 // BUILTIN_INFO(HEXAGON.V6_vsubwsat_128B,VI_ftype_VIVI,2)
7058 // tag : V6_vsubwsat_128B
7059 def int_hexagon_V6_vsubwsat_128B :
7060 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubwsat_128B">;
7061
7062 //
7063 // BUILTIN_INFO(HEXAGON.V6_vsubwsat_dv,VD_ftype_VDVD,2)
7064 // tag : V6_vsubwsat_dv
7065 def int_hexagon_V6_vsubwsat_dv :
7066 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubwsat_dv">;
7067
7068 //
7069 // BUILTIN_INFO(HEXAGON.V6_vsubwsat_dv_128B,VD_ftype_VDVD,2)
7070 // tag : V6_vsubwsat_dv_128B
7071 def int_hexagon_V6_vsubwsat_dv_128B :
7072 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">;
7073
7074 //
7075 // BUILTIN_INFO(HEXAGON.V6_vavgub,VI_ftype_VIVI,2)
7076 // tag : V6_vavgub
7077 def int_hexagon_V6_vavgub :
7078 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgub">;
7079
7080 //
7081 // BUILTIN_INFO(HEXAGON.V6_vavgub_128B,VI_ftype_VIVI,2)
7082 // tag : V6_vavgub_128B
7083 def int_hexagon_V6_vavgub_128B :
7084 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgub_128B">;
7085
7086 //
7087 // BUILTIN_INFO(HEXAGON.V6_vavgubrnd,VI_ftype_VIVI,2)
7088 // tag : V6_vavgubrnd
7089 def int_hexagon_V6_vavgubrnd :
7090 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgubrnd">;
7091
7092 //
7093 // BUILTIN_INFO(HEXAGON.V6_vavgubrnd_128B,VI_ftype_VIVI,2)
7094 // tag : V6_vavgubrnd_128B
7095 def int_hexagon_V6_vavgubrnd_128B :
7096 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">;
7097
7098 //
7099 // BUILTIN_INFO(HEXAGON.V6_vavguh,VI_ftype_VIVI,2)
7100 // tag : V6_vavguh
7101 def int_hexagon_V6_vavguh :
7102 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavguh">;
7103
7104 //
7105 // BUILTIN_INFO(HEXAGON.V6_vavguh_128B,VI_ftype_VIVI,2)
7106 // tag : V6_vavguh_128B
7107 def int_hexagon_V6_vavguh_128B :
7108 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguh_128B">;
7109
7110 //
7111 // BUILTIN_INFO(HEXAGON.V6_vavguhrnd,VI_ftype_VIVI,2)
7112 // tag : V6_vavguhrnd
7113 def int_hexagon_V6_vavguhrnd :
7114 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavguhrnd">;
7115
7116 //
7117 // BUILTIN_INFO(HEXAGON.V6_vavguhrnd_128B,VI_ftype_VIVI,2)
7118 // tag : V6_vavguhrnd_128B
7119 def int_hexagon_V6_vavguhrnd_128B :
7120 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">;
7121
7122 //
7123 // BUILTIN_INFO(HEXAGON.V6_vavgh,VI_ftype_VIVI,2)
7124 // tag : V6_vavgh
7125 def int_hexagon_V6_vavgh :
7126 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgh">;
7127
7128 //
7129 // BUILTIN_INFO(HEXAGON.V6_vavgh_128B,VI_ftype_VIVI,2)
7130 // tag : V6_vavgh_128B
7131 def int_hexagon_V6_vavgh_128B :
7132 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgh_128B">;
7133
7134 //
7135 // BUILTIN_INFO(HEXAGON.V6_vavghrnd,VI_ftype_VIVI,2)
7136 // tag : V6_vavghrnd
7137 def int_hexagon_V6_vavghrnd :
7138 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavghrnd">;
7139
7140 //
7141 // BUILTIN_INFO(HEXAGON.V6_vavghrnd_128B,VI_ftype_VIVI,2)
7142 // tag : V6_vavghrnd_128B
7143 def int_hexagon_V6_vavghrnd_128B :
7144 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavghrnd_128B">;
7145
7146 //
7147 // BUILTIN_INFO(HEXAGON.V6_vnavgh,VI_ftype_VIVI,2)
7148 // tag : V6_vnavgh
7149 def int_hexagon_V6_vnavgh :
7150 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgh">;
7151
7152 //
7153 // BUILTIN_INFO(HEXAGON.V6_vnavgh_128B,VI_ftype_VIVI,2)
7154 // tag : V6_vnavgh_128B
7155 def int_hexagon_V6_vnavgh_128B :
7156 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgh_128B">;
7157
7158 //
7159 // BUILTIN_INFO(HEXAGON.V6_vavgw,VI_ftype_VIVI,2)
7160 // tag : V6_vavgw
7161 def int_hexagon_V6_vavgw :
7162 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgw">;
7163
7164 //
7165 // BUILTIN_INFO(HEXAGON.V6_vavgw_128B,VI_ftype_VIVI,2)
7166 // tag : V6_vavgw_128B
7167 def int_hexagon_V6_vavgw_128B :
7168 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgw_128B">;
7169
7170 //
7171 // BUILTIN_INFO(HEXAGON.V6_vavgwrnd,VI_ftype_VIVI,2)
7172 // tag : V6_vavgwrnd
7173 def int_hexagon_V6_vavgwrnd :
7174 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgwrnd">;
7175
7176 //
7177 // BUILTIN_INFO(HEXAGON.V6_vavgwrnd_128B,VI_ftype_VIVI,2)
7178 // tag : V6_vavgwrnd_128B
7179 def int_hexagon_V6_vavgwrnd_128B :
7180 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">;
7181
7182 //
7183 // BUILTIN_INFO(HEXAGON.V6_vnavgw,VI_ftype_VIVI,2)
7184 // tag : V6_vnavgw
7185 def int_hexagon_V6_vnavgw :
7186 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgw">;
7187
7188 //
7189 // BUILTIN_INFO(HEXAGON.V6_vnavgw_128B,VI_ftype_VIVI,2)
7190 // tag : V6_vnavgw_128B
7191 def int_hexagon_V6_vnavgw_128B :
7192 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgw_128B">;
7193
7194 //
7195 // BUILTIN_INFO(HEXAGON.V6_vabsdiffub,VI_ftype_VIVI,2)
7196 // tag : V6_vabsdiffub
7197 def int_hexagon_V6_vabsdiffub :
7198 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffub">;
7199
7200 //
7201 // BUILTIN_INFO(HEXAGON.V6_vabsdiffub_128B,VI_ftype_VIVI,2)
7202 // tag : V6_vabsdiffub_128B
7203 def int_hexagon_V6_vabsdiffub_128B :
7204 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">;
7205
7206 //
7207 // BUILTIN_INFO(HEXAGON.V6_vabsdiffuh,VI_ftype_VIVI,2)
7208 // tag : V6_vabsdiffuh
7209 def int_hexagon_V6_vabsdiffuh :
7210 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffuh">;
7211
7212 //
7213 // BUILTIN_INFO(HEXAGON.V6_vabsdiffuh_128B,VI_ftype_VIVI,2)
7214 // tag : V6_vabsdiffuh_128B
7215 def int_hexagon_V6_vabsdiffuh_128B :
7216 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">;
7217
7218 //
7219 // BUILTIN_INFO(HEXAGON.V6_vabsdiffh,VI_ftype_VIVI,2)
7220 // tag : V6_vabsdiffh
7221 def int_hexagon_V6_vabsdiffh :
7222 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffh">;
7223
7224 //
7225 // BUILTIN_INFO(HEXAGON.V6_vabsdiffh_128B,VI_ftype_VIVI,2)
7226 // tag : V6_vabsdiffh_128B
7227 def int_hexagon_V6_vabsdiffh_128B :
7228 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">;
7229
7230 //
7231 // BUILTIN_INFO(HEXAGON.V6_vabsdiffw,VI_ftype_VIVI,2)
7232 // tag : V6_vabsdiffw
7233 def int_hexagon_V6_vabsdiffw :
7234 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffw">;
7235
7236 //
7237 // BUILTIN_INFO(HEXAGON.V6_vabsdiffw_128B,VI_ftype_VIVI,2)
7238 // tag : V6_vabsdiffw_128B
7239 def int_hexagon_V6_vabsdiffw_128B :
7240 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">;
7241
7242 //
7243 // BUILTIN_INFO(HEXAGON.V6_vnavgub,VI_ftype_VIVI,2)
7244 // tag : V6_vnavgub
7245 def int_hexagon_V6_vnavgub :
7246 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgub">;
7247
7248 //
7249 // BUILTIN_INFO(HEXAGON.V6_vnavgub_128B,VI_ftype_VIVI,2)
7250 // tag : V6_vnavgub_128B
7251 def int_hexagon_V6_vnavgub_128B :
7252 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgub_128B">;
7253
7254 //
7255 // BUILTIN_INFO(HEXAGON.V6_vaddubh,VD_ftype_VIVI,2)
7256 // tag : V6_vaddubh
7257 def int_hexagon_V6_vaddubh :
7258 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vaddubh">;
7259
7260 //
7261 // BUILTIN_INFO(HEXAGON.V6_vaddubh_128B,VD_ftype_VIVI,2)
7262 // tag : V6_vaddubh_128B
7263 def int_hexagon_V6_vaddubh_128B :
7264 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddubh_128B">;
7265
7266 //
7267 // BUILTIN_INFO(HEXAGON.V6_vsububh,VD_ftype_VIVI,2)
7268 // tag : V6_vsububh
7269 def int_hexagon_V6_vsububh :
7270 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsububh">;
7271
7272 //
7273 // BUILTIN_INFO(HEXAGON.V6_vsububh_128B,VD_ftype_VIVI,2)
7274 // tag : V6_vsububh_128B
7275 def int_hexagon_V6_vsububh_128B :
7276 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsububh_128B">;
7277
7278 //
7279 // BUILTIN_INFO(HEXAGON.V6_vaddhw,VD_ftype_VIVI,2)
7280 // tag : V6_vaddhw
7281 def int_hexagon_V6_vaddhw :
7282 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vaddhw">;
7283
7284 //
7285 // BUILTIN_INFO(HEXAGON.V6_vaddhw_128B,VD_ftype_VIVI,2)
7286 // tag : V6_vaddhw_128B
7287 def int_hexagon_V6_vaddhw_128B :
7288 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddhw_128B">;
7289
7290 //
7291 // BUILTIN_INFO(HEXAGON.V6_vsubhw,VD_ftype_VIVI,2)
7292 // tag : V6_vsubhw
7293 def int_hexagon_V6_vsubhw :
7294 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsubhw">;
7295
7296 //
7297 // BUILTIN_INFO(HEXAGON.V6_vsubhw_128B,VD_ftype_VIVI,2)
7298 // tag : V6_vsubhw_128B
7299 def int_hexagon_V6_vsubhw_128B :
7300 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsubhw_128B">;
7301
7302 //
7303 // BUILTIN_INFO(HEXAGON.V6_vadduhw,VD_ftype_VIVI,2)
7304 // tag : V6_vadduhw
7305 def int_hexagon_V6_vadduhw :
7306 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vadduhw">;
7307
7308 //
7309 // BUILTIN_INFO(HEXAGON.V6_vadduhw_128B,VD_ftype_VIVI,2)
7310 // tag : V6_vadduhw_128B
7311 def int_hexagon_V6_vadduhw_128B :
7312 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vadduhw_128B">;
7313
7314 //
7315 // BUILTIN_INFO(HEXAGON.V6_vsubuhw,VD_ftype_VIVI,2)
7316 // tag : V6_vsubuhw
7317 def int_hexagon_V6_vsubuhw :
7318 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsubuhw">;
7319
7320 //
7321 // BUILTIN_INFO(HEXAGON.V6_vsubuhw_128B,VD_ftype_VIVI,2)
7322 // tag : V6_vsubuhw_128B
7323 def int_hexagon_V6_vsubuhw_128B :
7324 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhw_128B">;
7325
7326 //
7327 // BUILTIN_INFO(HEXAGON.V6_vd0,VI_ftype_,0)
7328 // tag : V6_vd0
7329 def int_hexagon_V6_vd0 :
7330 Hexagon_v512_Intrinsic<"HEXAGON_V6_vd0">;
7331
7332 //
7333 // BUILTIN_INFO(HEXAGON.V6_vd0_128B,VI_ftype_,0)
7334 // tag : V6_vd0_128B
7335 def int_hexagon_V6_vd0_128B :
7336 Hexagon_v1024_Intrinsic<"HEXAGON_V6_vd0_128B">;
7337
7338 //
7339 // BUILTIN_INFO(HEXAGON.V6_vaddbq,VI_ftype_QVVIVI,3)
7340 // tag : V6_vaddbq
7341 def int_hexagon_V6_vaddbq :
7342 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddbq">;
7343
7344 //
7345 // BUILTIN_INFO(HEXAGON.V6_vaddbq_128B,VI_ftype_QVVIVI,3)
7346 // tag : V6_vaddbq_128B
7347 def int_hexagon_V6_vaddbq_128B :
7348 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddbq_128B">;
7349
7350
7351 //
7352 // BUILTIN_INFO(HEXAGON.V6_vsubbq,VI_ftype_QVVIVI,3)
7353 // tag : V6_vsubbq
7354 def int_hexagon_V6_vsubbq :
7355 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubbq">;
7356
7357 //
7358 // BUILTIN_INFO(HEXAGON.V6_vsubbq_128B,VI_ftype_QVVIVI,3)
7359 // tag : V6_vsubbq_128B
7360 def int_hexagon_V6_vsubbq_128B :
7361 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubbq_128B">;
7362
7363 //
7364 // BUILTIN_INFO(HEXAGON.V6_vaddbnq,VI_ftype_QVVIVI,3)
7365 // tag : V6_vaddbnq
7366 def int_hexagon_V6_vaddbnq :
7367 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddbnq">;
7368
7369 //
7370 // BUILTIN_INFO(HEXAGON.V6_vaddbnq_128B,VI_ftype_QVVIVI,3)
7371 // tag : V6_vaddbnq_128B
7372 def int_hexagon_V6_vaddbnq_128B :
7373 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddbnq_128B">;
7374
7375 //
7376 // BUILTIN_INFO(HEXAGON.V6_vsubbnq,VI_ftype_QVVIVI,3)
7377 // tag : V6_vsubbnq
7378 def int_hexagon_V6_vsubbnq :
7379 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubbnq">;
7380
7381 //
7382 // BUILTIN_INFO(HEXAGON.V6_vsubbnq_128B,VI_ftype_QVVIVI,3)
7383 // tag : V6_vsubbnq_128B
7384 def int_hexagon_V6_vsubbnq_128B :
7385 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubbnq_128B">;
7386
7387 //
7388 // BUILTIN_INFO(HEXAGON.V6_vaddhq,VI_ftype_QVVIVI,3)
7389 // tag : V6_vaddhq
7390 def int_hexagon_V6_vaddhq :
7391 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddhq">;
7392
7393 //
7394 // BUILTIN_INFO(HEXAGON.V6_vaddhq_128B,VI_ftype_QVVIVI,3)
7395 // tag : V6_vaddhq_128B
7396 def int_hexagon_V6_vaddhq_128B :
7397 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddhq_128B">;
7398
7399 //
7400 // BUILTIN_INFO(HEXAGON.V6_vsubhq,VI_ftype_QVVIVI,3)
7401 // tag : V6_vsubhq
7402 def int_hexagon_V6_vsubhq :
7403 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubhq">;
7404
7405 //
7406 // BUILTIN_INFO(HEXAGON.V6_vsubhq_128B,VI_ftype_QVVIVI,3)
7407 // tag : V6_vsubhq_128B
7408 def int_hexagon_V6_vsubhq_128B :
7409 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubhq_128B">;
7410
7411 //
7412 // BUILTIN_INFO(HEXAGON.V6_vaddhnq,VI_ftype_QVVIVI,3)
7413 // tag : V6_vaddhnq
7414 def int_hexagon_V6_vaddhnq :
7415 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddhnq">;
7416
7417 //
7418 // BUILTIN_INFO(HEXAGON.V6_vaddhnq_128B,VI_ftype_QVVIVI,3)
7419 // tag : V6_vaddhnq_128B
7420 def int_hexagon_V6_vaddhnq_128B :
7421 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddhnq_128B">;
7422
7423 //
7424 // BUILTIN_INFO(HEXAGON.V6_vsubhnq,VI_ftype_QVVIVI,3)
7425 // tag : V6_vsubhnq
7426 def int_hexagon_V6_vsubhnq :
7427 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubhnq">;
7428
7429 //
7430 // BUILTIN_INFO(HEXAGON.V6_vsubhnq_128B,VI_ftype_QVVIVI,3)
7431 // tag : V6_vsubhnq_128B
7432 def int_hexagon_V6_vsubhnq_128B :
7433 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubhnq_128B">;
7434
7435 //
7436 // BUILTIN_INFO(HEXAGON.V6_vaddwq,VI_ftype_QVVIVI,3)
7437 // tag : V6_vaddwq
7438 def int_hexagon_V6_vaddwq :
7439 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddwq">;
7440
7441 //
7442 // BUILTIN_INFO(HEXAGON.V6_vaddwq_128B,VI_ftype_QVVIVI,3)
7443 // tag : V6_vaddwq_128B
7444 def int_hexagon_V6_vaddwq_128B :
7445 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddwq_128B">;
7446
7447 //
7448 // BUILTIN_INFO(HEXAGON.V6_vsubwq,VI_ftype_QVVIVI,3)
7449 // tag : V6_vsubwq
7450 def int_hexagon_V6_vsubwq :
7451 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubwq">;
7452
7453 //
7454 // BUILTIN_INFO(HEXAGON.V6_vsubwq_128B,VI_ftype_QVVIVI,3)
7455 // tag : V6_vsubwq_128B
7456 def int_hexagon_V6_vsubwq_128B :
7457 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubwq_128B">;
7458
7459 //
7460 // BUILTIN_INFO(HEXAGON.V6_vaddwnq,VI_ftype_QVVIVI,3)
7461 // tag : V6_vaddwnq
7462 def int_hexagon_V6_vaddwnq :
7463 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddwnq">;
7464
7465 //
7466 // BUILTIN_INFO(HEXAGON.V6_vaddwnq_128B,VI_ftype_QVVIVI,3)
7467 // tag : V6_vaddwnq_128B
7468 def int_hexagon_V6_vaddwnq_128B :
7469 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddwnq_128B">;
7470
7471 //
7472 // BUILTIN_INFO(HEXAGON.V6_vsubwnq,VI_ftype_QVVIVI,3)
7473 // tag : V6_vsubwnq
7474 def int_hexagon_V6_vsubwnq :
7475 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubwnq">;
7476
7477 //
7478 // BUILTIN_INFO(HEXAGON.V6_vsubwnq_128B,VI_ftype_QVVIVI,3)
7479 // tag : V6_vsubwnq_128B
7480 def int_hexagon_V6_vsubwnq_128B :
7481 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubwnq_128B">;
7482
7483 //
7484 // BUILTIN_INFO(HEXAGON.V6_vabsh,VI_ftype_VI,1)
7485 // tag : V6_vabsh
7486 def int_hexagon_V6_vabsh :
7487 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsh">;
7488
7489 //
7490 // BUILTIN_INFO(HEXAGON.V6_vabsh_128B,VI_ftype_VI,1)
7491 // tag : V6_vabsh_128B
7492 def int_hexagon_V6_vabsh_128B :
7493 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsh_128B">;
7494
7495 //
7496 // BUILTIN_INFO(HEXAGON.V6_vabsh_sat,VI_ftype_VI,1)
7497 // tag : V6_vabsh_sat
7498 def int_hexagon_V6_vabsh_sat :
7499 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsh_sat">;
7500
7501 //
7502 // BUILTIN_INFO(HEXAGON.V6_vabsh_sat_128B,VI_ftype_VI,1)
7503 // tag : V6_vabsh_sat_128B
7504 def int_hexagon_V6_vabsh_sat_128B :
7505 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">;
7506
7507 //
7508 // BUILTIN_INFO(HEXAGON.V6_vabsw,VI_ftype_VI,1)
7509 // tag : V6_vabsw
7510 def int_hexagon_V6_vabsw :
7511 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsw">;
7512
7513 //
7514 // BUILTIN_INFO(HEXAGON.V6_vabsw_128B,VI_ftype_VI,1)
7515 // tag : V6_vabsw_128B
7516 def int_hexagon_V6_vabsw_128B :
7517 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsw_128B">;
7518
7519 //
7520 // BUILTIN_INFO(HEXAGON.V6_vabsw_sat,VI_ftype_VI,1)
7521 // tag : V6_vabsw_sat
7522 def int_hexagon_V6_vabsw_sat :
7523 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsw_sat">;
7524
7525 //
7526 // BUILTIN_INFO(HEXAGON.V6_vabsw_sat_128B,VI_ftype_VI,1)
7527 // tag : V6_vabsw_sat_128B
7528 def int_hexagon_V6_vabsw_sat_128B :
7529 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">;
7530
7531 //
7532 // BUILTIN_INFO(HEXAGON.V6_vmpybv,VD_ftype_VIVI,2)
7533 // tag : V6_vmpybv
7534 def int_hexagon_V6_vmpybv :
7535 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybv">;
7536
7537 //
7538 // BUILTIN_INFO(HEXAGON.V6_vmpybv_128B,VD_ftype_VIVI,2)
7539 // tag : V6_vmpybv_128B
7540 def int_hexagon_V6_vmpybv_128B :
7541 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybv_128B">;
7542
7543 //
7544 // BUILTIN_INFO(HEXAGON.V6_vmpybv_acc,VD_ftype_VDVIVI,3)
7545 // tag : V6_vmpybv_acc
7546 def int_hexagon_V6_vmpybv_acc :
7547 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybv_acc">;
7548
7549 //
7550 // BUILTIN_INFO(HEXAGON.V6_vmpybv_acc_128B,VD_ftype_VDVIVI,3)
7551 // tag : V6_vmpybv_acc_128B
7552 def int_hexagon_V6_vmpybv_acc_128B :
7553 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">;
7554
7555 //
7556 // BUILTIN_INFO(HEXAGON.V6_vmpyubv,VD_ftype_VIVI,2)
7557 // tag : V6_vmpyubv
7558 def int_hexagon_V6_vmpyubv :
7559 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyubv">;
7560
7561 //
7562 // BUILTIN_INFO(HEXAGON.V6_vmpyubv_128B,VD_ftype_VIVI,2)
7563 // tag : V6_vmpyubv_128B
7564 def int_hexagon_V6_vmpyubv_128B :
7565 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyubv_128B">;
7566
7567 //
7568 // BUILTIN_INFO(HEXAGON.V6_vmpyubv_acc,VD_ftype_VDVIVI,3)
7569 // tag : V6_vmpyubv_acc
7570 def int_hexagon_V6_vmpyubv_acc :
7571 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyubv_acc">;
7572
7573 //
7574 // BUILTIN_INFO(HEXAGON.V6_vmpyubv_acc_128B,VD_ftype_VDVIVI,3)
7575 // tag : V6_vmpyubv_acc_128B
7576 def int_hexagon_V6_vmpyubv_acc_128B :
7577 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">;
7578
7579 //
7580 // BUILTIN_INFO(HEXAGON.V6_vmpybusv,VD_ftype_VIVI,2)
7581 // tag : V6_vmpybusv
7582 def int_hexagon_V6_vmpybusv :
7583 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybusv">;
7584
7585 //
7586 // BUILTIN_INFO(HEXAGON.V6_vmpybusv_128B,VD_ftype_VIVI,2)
7587 // tag : V6_vmpybusv_128B
7588 def int_hexagon_V6_vmpybusv_128B :
7589 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybusv_128B">;
7590
7591 //
7592 // BUILTIN_INFO(HEXAGON.V6_vmpybusv_acc,VD_ftype_VDVIVI,3)
7593 // tag : V6_vmpybusv_acc
7594 def int_hexagon_V6_vmpybusv_acc :
7595 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybusv_acc">;
7596
7597 //
7598 // BUILTIN_INFO(HEXAGON.V6_vmpybusv_acc_128B,VD_ftype_VDVIVI,3)
7599 // tag : V6_vmpybusv_acc_128B
7600 def int_hexagon_V6_vmpybusv_acc_128B :
7601 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">;
7602
7603 //
7604 // BUILTIN_INFO(HEXAGON.V6_vmpabusv,VD_ftype_VDVD,2)
7605 // tag : V6_vmpabusv
7606 def int_hexagon_V6_vmpabusv :
7607 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpabusv">;
7608
7609 //
7610 // BUILTIN_INFO(HEXAGON.V6_vmpabusv_128B,VD_ftype_VDVD,2)
7611 // tag : V6_vmpabusv_128B
7612 def int_hexagon_V6_vmpabusv_128B :
7613 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vmpabusv_128B">;
7614
7615 //
7616 // BUILTIN_INFO(HEXAGON.V6_vmpabuuv,VD_ftype_VDVD,2)
7617 // tag : V6_vmpabuuv
7618 def int_hexagon_V6_vmpabuuv :
7619 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpabuuv">;
7620
7621 //
7622 // BUILTIN_INFO(HEXAGON.V6_vmpabuuv_128B,VD_ftype_VDVD,2)
7623 // tag : V6_vmpabuuv_128B
7624 def int_hexagon_V6_vmpabuuv_128B :
7625 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">;
7626
7627 //
7628 // BUILTIN_INFO(HEXAGON.V6_vmpyhv,VD_ftype_VIVI,2)
7629 // tag : V6_vmpyhv
7630 def int_hexagon_V6_vmpyhv :
7631 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhv">;
7632
7633 //
7634 // BUILTIN_INFO(HEXAGON.V6_vmpyhv_128B,VD_ftype_VIVI,2)
7635 // tag : V6_vmpyhv_128B
7636 def int_hexagon_V6_vmpyhv_128B :
7637 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhv_128B">;
7638
7639 //
7640 // BUILTIN_INFO(HEXAGON.V6_vmpyhv_acc,VD_ftype_VDVIVI,3)
7641 // tag : V6_vmpyhv_acc
7642 def int_hexagon_V6_vmpyhv_acc :
7643 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhv_acc">;
7644
7645 //
7646 // BUILTIN_INFO(HEXAGON.V6_vmpyhv_acc_128B,VD_ftype_VDVIVI,3)
7647 // tag : V6_vmpyhv_acc_128B
7648 def int_hexagon_V6_vmpyhv_acc_128B :
7649 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">;
7650
7651 //
7652 // BUILTIN_INFO(HEXAGON.V6_vmpyuhv,VD_ftype_VIVI,2)
7653 // tag : V6_vmpyuhv
7654 def int_hexagon_V6_vmpyuhv :
7655 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyuhv">;
7656
7657 //
7658 // BUILTIN_INFO(HEXAGON.V6_vmpyuhv_128B,VD_ftype_VIVI,2)
7659 // tag : V6_vmpyuhv_128B
7660 def int_hexagon_V6_vmpyuhv_128B :
7661 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">;
7662
7663 //
7664 // BUILTIN_INFO(HEXAGON.V6_vmpyuhv_acc,VD_ftype_VDVIVI,3)
7665 // tag : V6_vmpyuhv_acc
7666 def int_hexagon_V6_vmpyuhv_acc :
7667 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">;
7668
7669 //
7670 // BUILTIN_INFO(HEXAGON.V6_vmpyuhv_acc_128B,VD_ftype_VDVIVI,3)
7671 // tag : V6_vmpyuhv_acc_128B
7672 def int_hexagon_V6_vmpyuhv_acc_128B :
7673 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">;
7674
7675 //
7676 // BUILTIN_INFO(HEXAGON.V6_vmpyhvsrs,VI_ftype_VIVI,2)
7677 // tag : V6_vmpyhvsrs
7678 def int_hexagon_V6_vmpyhvsrs :
7679 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyhvsrs">;
7680
7681 //
7682 // BUILTIN_INFO(HEXAGON.V6_vmpyhvsrs_128B,VI_ftype_VIVI,2)
7683 // tag : V6_vmpyhvsrs_128B
7684 def int_hexagon_V6_vmpyhvsrs_128B :
7685 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">;
7686
7687 //
7688 // BUILTIN_INFO(HEXAGON.V6_vmpyhus,VD_ftype_VIVI,2)
7689 // tag : V6_vmpyhus
7690 def int_hexagon_V6_vmpyhus :
7691 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhus">;
7692
7693 //
7694 // BUILTIN_INFO(HEXAGON.V6_vmpyhus_128B,VD_ftype_VIVI,2)
7695 // tag : V6_vmpyhus_128B
7696 def int_hexagon_V6_vmpyhus_128B :
7697 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhus_128B">;
7698
7699 //
7700 // BUILTIN_INFO(HEXAGON.V6_vmpyhus_acc,VD_ftype_VDVIVI,3)
7701 // tag : V6_vmpyhus_acc
7702 def int_hexagon_V6_vmpyhus_acc :
7703 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhus_acc">;
7704
7705 //
7706 // BUILTIN_INFO(HEXAGON.V6_vmpyhus_acc_128B,VD_ftype_VDVIVI,3)
7707 // tag : V6_vmpyhus_acc_128B
7708 def int_hexagon_V6_vmpyhus_acc_128B :
7709 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">;
7710
7711 //
7712 // BUILTIN_INFO(HEXAGON.V6_vmpyih,VI_ftype_VIVI,2)
7713 // tag : V6_vmpyih
7714 def int_hexagon_V6_vmpyih :
7715 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyih">;
7716
7717 //
7718 // BUILTIN_INFO(HEXAGON.V6_vmpyih_128B,VI_ftype_VIVI,2)
7719 // tag : V6_vmpyih_128B
7720 def int_hexagon_V6_vmpyih_128B :
7721 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyih_128B">;
7722
7723 //
7724 // BUILTIN_INFO(HEXAGON.V6_vmpyih_acc,VI_ftype_VIVIVI,3)
7725 // tag : V6_vmpyih_acc
7726 def int_hexagon_V6_vmpyih_acc :
7727 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyih_acc">;
7728
7729 //
7730 // BUILTIN_INFO(HEXAGON.V6_vmpyih_acc_128B,VI_ftype_VIVIVI,3)
7731 // tag : V6_vmpyih_acc_128B
7732 def int_hexagon_V6_vmpyih_acc_128B :
7733 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">;
7734
7735 //
7736 // BUILTIN_INFO(HEXAGON.V6_vmpyewuh,VI_ftype_VIVI,2)
7737 // tag : V6_vmpyewuh
7738 def int_hexagon_V6_vmpyewuh :
7739 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyewuh">;
7740
7741 //
7742 // BUILTIN_INFO(HEXAGON.V6_vmpyewuh_128B,VI_ftype_VIVI,2)
7743 // tag : V6_vmpyewuh_128B
7744 def int_hexagon_V6_vmpyewuh_128B :
7745 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">;
7746
7747 //
7748 // BUILTIN_INFO(HEXAGON.V6_vmpyowh,VI_ftype_VIVI,2)
7749 // tag : V6_vmpyowh
7750 def int_hexagon_V6_vmpyowh :
7751 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh">;
7752
7753 //
7754 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_128B,VI_ftype_VIVI,2)
7755 // tag : V6_vmpyowh_128B
7756 def int_hexagon_V6_vmpyowh_128B :
7757 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_128B">;
7758
7759 //
7760 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd,VI_ftype_VIVI,2)
7761 // tag : V6_vmpyowh_rnd
7762 def int_hexagon_V6_vmpyowh_rnd :
7763 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">;
7764
7765 //
7766 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_128B,VI_ftype_VIVI,2)
7767 // tag : V6_vmpyowh_rnd_128B
7768 def int_hexagon_V6_vmpyowh_rnd_128B :
7769 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">;
7770
7771 //
7772 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_sacc,VI_ftype_VIVIVI,3)
7773 // tag : V6_vmpyowh_sacc
7774 def int_hexagon_V6_vmpyowh_sacc :
7775 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">;
7776
7777 //
7778 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_sacc_128B,VI_ftype_VIVIVI,3)
7779 // tag : V6_vmpyowh_sacc_128B
7780 def int_hexagon_V6_vmpyowh_sacc_128B :
7781 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">;
7782
7783 //
7784 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_sacc,VI_ftype_VIVIVI,3)
7785 // tag : V6_vmpyowh_rnd_sacc
7786 def int_hexagon_V6_vmpyowh_rnd_sacc :
7787 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">;
7788
7789 //
7790 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_sacc_128B,VI_ftype_VIVIVI,3)
7791 // tag : V6_vmpyowh_rnd_sacc_128B
7792 def int_hexagon_V6_vmpyowh_rnd_sacc_128B :
7793 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">;
7794
7795 //
7796 // BUILTIN_INFO(HEXAGON.V6_vmpyieoh,VI_ftype_VIVI,2)
7797 // tag : V6_vmpyieoh
7798 def int_hexagon_V6_vmpyieoh :
7799 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyieoh">;
7800
7801 //
7802 // BUILTIN_INFO(HEXAGON.V6_vmpyieoh_128B,VI_ftype_VIVI,2)
7803 // tag : V6_vmpyieoh_128B
7804 def int_hexagon_V6_vmpyieoh_128B :
7805 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">;
7806
7807 //
7808 // BUILTIN_INFO(HEXAGON.V6_vmpyiewuh,VI_ftype_VIVI,2)
7809 // tag : V6_vmpyiewuh
7810 def int_hexagon_V6_vmpyiewuh :
7811 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewuh">;
7812
7813 //
7814 // BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_128B,VI_ftype_VIVI,2)
7815 // tag : V6_vmpyiewuh_128B
7816 def int_hexagon_V6_vmpyiewuh_128B :
7817 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">;
7818
7819 //
7820 // BUILTIN_INFO(HEXAGON.V6_vmpyiowh,VI_ftype_VIVI,2)
7821 // tag : V6_vmpyiowh
7822 def int_hexagon_V6_vmpyiowh :
7823 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiowh">;
7824
7825 //
7826 // BUILTIN_INFO(HEXAGON.V6_vmpyiowh_128B,VI_ftype_VIVI,2)
7827 // tag : V6_vmpyiowh_128B
7828 def int_hexagon_V6_vmpyiowh_128B :
7829 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">;
7830
7831 //
7832 // BUILTIN_INFO(HEXAGON.V6_vmpyiewh_acc,VI_ftype_VIVIVI,3)
7833 // tag : V6_vmpyiewh_acc
7834 def int_hexagon_V6_vmpyiewh_acc :
7835 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">;
7836
7837 //
7838 // BUILTIN_INFO(HEXAGON.V6_vmpyiewh_acc_128B,VI_ftype_VIVIVI,3)
7839 // tag : V6_vmpyiewh_acc_128B
7840 def int_hexagon_V6_vmpyiewh_acc_128B :
7841 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">;
7842
7843 //
7844 // BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_acc,VI_ftype_VIVIVI,3)
7845 // tag : V6_vmpyiewuh_acc
7846 def int_hexagon_V6_vmpyiewuh_acc :
7847 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">;
7848
7849 //
7850 // BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_acc_128B,VI_ftype_VIVIVI,3)
7851 // tag : V6_vmpyiewuh_acc_128B
7852 def int_hexagon_V6_vmpyiewuh_acc_128B :
7853 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">;
7854
7855 //
7856 // BUILTIN_INFO(HEXAGON.V6_vmpyub,VD_ftype_VISI,2)
7857 // tag : V6_vmpyub
7858 def int_hexagon_V6_vmpyub :
7859 Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyub">;
7860
7861 //
7862 // BUILTIN_INFO(HEXAGON.V6_vmpyub_128B,VD_ftype_VISI,2)
7863 // tag : V6_vmpyub_128B
7864 def int_hexagon_V6_vmpyub_128B :
7865 Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyub_128B">;
7866
7867 //
7868 // BUILTIN_INFO(HEXAGON.V6_vmpyub_acc,VD_ftype_VDVISI,3)
7869 // tag : V6_vmpyub_acc
7870 def int_hexagon_V6_vmpyub_acc :
7871 Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyub_acc">;
7872
7873 //
7874 // BUILTIN_INFO(HEXAGON.V6_vmpyub_acc_128B,VD_ftype_VDVISI,3)
7875 // tag : V6_vmpyub_acc_128B
7876 def int_hexagon_V6_vmpyub_acc_128B :
7877 Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">;
7878
7879 //
7880 // BUILTIN_INFO(HEXAGON.V6_vmpybus,VD_ftype_VISI,2)
7881 // tag : V6_vmpybus
7882 def int_hexagon_V6_vmpybus :
7883 Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpybus">;
7884
7885 //
7886 // BUILTIN_INFO(HEXAGON.V6_vmpybus_128B,VD_ftype_VISI,2)
7887 // tag : V6_vmpybus_128B
7888 def int_hexagon_V6_vmpybus_128B :
7889 Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpybus_128B">;
7890
7891 //
7892 // BUILTIN_INFO(HEXAGON.V6_vmpybus_acc,VD_ftype_VDVISI,3)
7893 // tag : V6_vmpybus_acc
7894 def int_hexagon_V6_vmpybus_acc :
7895 Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpybus_acc">;
7896
7897 //
7898 // BUILTIN_INFO(HEXAGON.V6_vmpybus_acc_128B,VD_ftype_VDVISI,3)
7899 // tag : V6_vmpybus_acc_128B
7900 def int_hexagon_V6_vmpybus_acc_128B :
7901 Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">;
7902
7903 //
7904 // BUILTIN_INFO(HEXAGON.V6_vmpabus,VD_ftype_VDSI,2)
7905 // tag : V6_vmpabus
7906 def int_hexagon_V6_vmpabus :
7907 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabus">;
7908
7909 //
7910 // BUILTIN_INFO(HEXAGON.V6_vmpabus_128B,VD_ftype_VDSI,2)
7911 // tag : V6_vmpabus_128B
7912 def int_hexagon_V6_vmpabus_128B :
7913 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabus_128B">;
7914
7915 //
7916 // BUILTIN_INFO(HEXAGON.V6_vmpabus_acc,VD_ftype_VDVDSI,3)
7917 // tag : V6_vmpabus_acc
7918 def int_hexagon_V6_vmpabus_acc :
7919 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabus_acc">;
7920
7921 //
7922 // BUILTIN_INFO(HEXAGON.V6_vmpabus_acc_128B,VD_ftype_VDVDSI,3)
7923 // tag : V6_vmpabus_acc_128B
7924 def int_hexagon_V6_vmpabus_acc_128B :
7925 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">;
7926
7927 //
7928 // BUILTIN_INFO(HEXAGON.V6_vmpahb,VD_ftype_VDSI,2)
7929 // tag : V6_vmpahb
7930 def int_hexagon_V6_vmpahb :
7931 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpahb">;
7932
7933 //
7934 // BUILTIN_INFO(HEXAGON.V6_vmpahb_128B,VD_ftype_VDSI,2)
7935 // tag : V6_vmpahb_128B
7936 def int_hexagon_V6_vmpahb_128B :
7937 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpahb_128B">;
7938
7939 //
7940 // BUILTIN_INFO(HEXAGON.V6_vmpahb_acc,VD_ftype_VDVDSI,3)
7941 // tag : V6_vmpahb_acc
7942 def int_hexagon_V6_vmpahb_acc :
7943 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpahb_acc">;
7944
7945 //
7946 // BUILTIN_INFO(HEXAGON.V6_vmpahb_acc_128B,VD_ftype_VDVDSI,3)
7947 // tag : V6_vmpahb_acc_128B
7948 def int_hexagon_V6_vmpahb_acc_128B :
7949 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">;
7950
7951 //
7952 // BUILTIN_INFO(HEXAGON.V6_vmpyh,VD_ftype_VISI,2)
7953 // tag : V6_vmpyh
7954 def int_hexagon_V6_vmpyh :
7955 Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh">;
7956
7957 //
7958 // BUILTIN_INFO(HEXAGON.V6_vmpyh_128B,VD_ftype_VISI,2)
7959 // tag : V6_vmpyh_128B
7960 def int_hexagon_V6_vmpyh_128B :
7961 Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_128B">;
7962
7963 //
7964 // BUILTIN_INFO(HEXAGON.V6_vmpyhsat_acc,VD_ftype_VDVISI,3)
7965 // tag : V6_vmpyhsat_acc
7966 def int_hexagon_V6_vmpyhsat_acc :
7967 Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">;
7968
7969 //
7970 // BUILTIN_INFO(HEXAGON.V6_vmpyhsat_acc_128B,VD_ftype_VDVISI,3)
7971 // tag : V6_vmpyhsat_acc_128B
7972 def int_hexagon_V6_vmpyhsat_acc_128B :
7973 Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">;
7974
7975 //
7976 // BUILTIN_INFO(HEXAGON.V6_vmpyhss,VI_ftype_VISI,2)
7977 // tag : V6_vmpyhss
7978 def int_hexagon_V6_vmpyhss :
7979 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyhss">;
7980
7981 //
7982 // BUILTIN_INFO(HEXAGON.V6_vmpyhss_128B,VI_ftype_VISI,2)
7983 // tag : V6_vmpyhss_128B
7984 def int_hexagon_V6_vmpyhss_128B :
7985 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyhss_128B">;
7986
7987 //
7988 // BUILTIN_INFO(HEXAGON.V6_vmpyhsrs,VI_ftype_VISI,2)
7989 // tag : V6_vmpyhsrs
7990 def int_hexagon_V6_vmpyhsrs :
7991 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyhsrs">;
7992
7993 //
7994 // BUILTIN_INFO(HEXAGON.V6_vmpyhsrs_128B,VI_ftype_VISI,2)
7995 // tag : V6_vmpyhsrs_128B
7996 def int_hexagon_V6_vmpyhsrs_128B :
7997 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">;
7998
7999 //
8000 // BUILTIN_INFO(HEXAGON.V6_vmpyuh,VD_ftype_VISI,2)
8001 // tag : V6_vmpyuh
8002 def int_hexagon_V6_vmpyuh :
8003 Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyuh">;
8004
8005 //
8006 // BUILTIN_INFO(HEXAGON.V6_vmpyuh_128B,VD_ftype_VISI,2)
8007 // tag : V6_vmpyuh_128B
8008 def int_hexagon_V6_vmpyuh_128B :
8009 Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyuh_128B">;
8010
8011 //
8012 // BUILTIN_INFO(HEXAGON.V6_vmpyuh_acc,VD_ftype_VDVISI,3)
8013 // tag : V6_vmpyuh_acc
8014 def int_hexagon_V6_vmpyuh_acc :
8015 Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyuh_acc">;
8016
8017 //
8018 // BUILTIN_INFO(HEXAGON.V6_vmpyuh_acc_128B,VD_ftype_VDVISI,3)
8019 // tag : V6_vmpyuh_acc_128B
8020 def int_hexagon_V6_vmpyuh_acc_128B :
8021 Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">;
8022
8023 //
8024 // BUILTIN_INFO(HEXAGON.V6_vmpyihb,VI_ftype_VISI,2)
8025 // tag : V6_vmpyihb
8026 def int_hexagon_V6_vmpyihb :
8027 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyihb">;
8028
8029 //
8030 // BUILTIN_INFO(HEXAGON.V6_vmpyihb_128B,VI_ftype_VISI,2)
8031 // tag : V6_vmpyihb_128B
8032 def int_hexagon_V6_vmpyihb_128B :
8033 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyihb_128B">;
8034
8035 //
8036 // BUILTIN_INFO(HEXAGON.V6_vmpyihb_acc,VI_ftype_VIVISI,3)
8037 // tag : V6_vmpyihb_acc
8038 def int_hexagon_V6_vmpyihb_acc :
8039 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyihb_acc">;
8040
8041 //
8042 // BUILTIN_INFO(HEXAGON.V6_vmpyihb_acc_128B,VI_ftype_VIVISI,3)
8043 // tag : V6_vmpyihb_acc_128B
8044 def int_hexagon_V6_vmpyihb_acc_128B :
8045 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">;
8046
8047 //
8048 // BUILTIN_INFO(HEXAGON.V6_vmpyiwb,VI_ftype_VISI,2)
8049 // tag : V6_vmpyiwb
8050 def int_hexagon_V6_vmpyiwb :
8051 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwb">;
8052
8053 //
8054 // BUILTIN_INFO(HEXAGON.V6_vmpyiwb_128B,VI_ftype_VISI,2)
8055 // tag : V6_vmpyiwb_128B
8056 def int_hexagon_V6_vmpyiwb_128B :
8057 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">;
8058
8059 //
8060 // BUILTIN_INFO(HEXAGON.V6_vmpyiwb_acc,VI_ftype_VIVISI,3)
8061 // tag : V6_vmpyiwb_acc
8062 def int_hexagon_V6_vmpyiwb_acc :
8063 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">;
8064
8065 //
8066 // BUILTIN_INFO(HEXAGON.V6_vmpyiwb_acc_128B,VI_ftype_VIVISI,3)
8067 // tag : V6_vmpyiwb_acc_128B
8068 def int_hexagon_V6_vmpyiwb_acc_128B :
8069 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">;
8070
8071 //
8072 // BUILTIN_INFO(HEXAGON.V6_vmpyiwh,VI_ftype_VISI,2)
8073 // tag : V6_vmpyiwh
8074 def int_hexagon_V6_vmpyiwh :
8075 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwh">;
8076
8077 //
8078 // BUILTIN_INFO(HEXAGON.V6_vmpyiwh_128B,VI_ftype_VISI,2)
8079 // tag : V6_vmpyiwh_128B
8080 def int_hexagon_V6_vmpyiwh_128B :
8081 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">;
8082
8083 //
8084 // BUILTIN_INFO(HEXAGON.V6_vmpyiwh_acc,VI_ftype_VIVISI,3)
8085 // tag : V6_vmpyiwh_acc
8086 def int_hexagon_V6_vmpyiwh_acc :
8087 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">;
8088
8089 //
8090 // BUILTIN_INFO(HEXAGON.V6_vmpyiwh_acc_128B,VI_ftype_VIVISI,3)
8091 // tag : V6_vmpyiwh_acc_128B
8092 def int_hexagon_V6_vmpyiwh_acc_128B :
8093 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">;
8094
8095 //
8096 // BUILTIN_INFO(HEXAGON.V6_vand,VI_ftype_VIVI,2)
8097 // tag : V6_vand
8098 def int_hexagon_V6_vand :
8099 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vand">;
8100
8101 //
8102 // BUILTIN_INFO(HEXAGON.V6_vand_128B,VI_ftype_VIVI,2)
8103 // tag : V6_vand_128B
8104 def int_hexagon_V6_vand_128B :
8105 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vand_128B">;
8106
8107 //
8108 // BUILTIN_INFO(HEXAGON.V6_vor,VI_ftype_VIVI,2)
8109 // tag : V6_vor
8110 def int_hexagon_V6_vor :
8111 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vor">;
8112
8113 //
8114 // BUILTIN_INFO(HEXAGON.V6_vor_128B,VI_ftype_VIVI,2)
8115 // tag : V6_vor_128B
8116 def int_hexagon_V6_vor_128B :
8117 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vor_128B">;
8118
8119 //
8120 // BUILTIN_INFO(HEXAGON.V6_vxor,VI_ftype_VIVI,2)
8121 // tag : V6_vxor
8122 def int_hexagon_V6_vxor :
8123 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vxor">;
8124
8125 //
8126 // BUILTIN_INFO(HEXAGON.V6_vxor_128B,VI_ftype_VIVI,2)
8127 // tag : V6_vxor_128B
8128 def int_hexagon_V6_vxor_128B :
8129 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vxor_128B">;
8130
8131 //
8132 // BUILTIN_INFO(HEXAGON.V6_vnot,VI_ftype_VI,1)
8133 // tag : V6_vnot
8134 def int_hexagon_V6_vnot :
8135 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnot">;
8136
8137 //
8138 // BUILTIN_INFO(HEXAGON.V6_vnot_128B,VI_ftype_VI,1)
8139 // tag : V6_vnot_128B
8140 def int_hexagon_V6_vnot_128B :
8141 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnot_128B">;
8142
8143 //
8144 // BUILTIN_INFO(HEXAGON.V6_vandqrt,VI_ftype_QVSI,2)
8145 // tag : V6_vandqrt
8146 def int_hexagon_V6_vandqrt :
8147 Hexagon_v512v64ii_Intrinsic<"HEXAGON_V6_vandqrt">;
8148
8149 //
8150 // BUILTIN_INFO(HEXAGON.V6_vandqrt_128B,VI_ftype_QVSI,2)
8151 // tag : V6_vandqrt_128B
8152 def int_hexagon_V6_vandqrt_128B :
8153 Hexagon_v1024v128ii_Intrinsic<"HEXAGON_V6_vandqrt_128B">;
8154
8155 //
8156 // BUILTIN_INFO(HEXAGON.V6_vandqrt_acc,VI_ftype_VIQVSI,3)
8157 // tag : V6_vandqrt_acc
8158 def int_hexagon_V6_vandqrt_acc :
8159 Hexagon_v512v512v64ii_Intrinsic<"HEXAGON_V6_vandqrt_acc">;
8160
8161 //
8162 // BUILTIN_INFO(HEXAGON.V6_vandqrt_acc_128B,VI_ftype_VIQVSI,3)
8163 // tag : V6_vandqrt_acc_128B
8164 def int_hexagon_V6_vandqrt_acc_128B :
8165 Hexagon_v1024v1024v128ii_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">;
8166
8167 //
8168 // BUILTIN_INFO(HEXAGON.V6_vandvrt,QV_ftype_VISI,2)
8169 // tag : V6_vandvrt
8170 def int_hexagon_V6_vandvrt :
8171 Hexagon_v64iv512i_Intrinsic<"HEXAGON_V6_vandvrt">;
8172
8173 //
8174 // BUILTIN_INFO(HEXAGON.V6_vandvrt_128B,QV_ftype_VISI,2)
8175 // tag : V6_vandvrt_128B
8176 def int_hexagon_V6_vandvrt_128B :
8177 Hexagon_v128iv1024i_Intrinsic<"HEXAGON_V6_vandvrt_128B">;
8178
8179 //
8180 // BUILTIN_INFO(HEXAGON.V6_vandvrt_acc,QV_ftype_QVVISI,3)
8181 // tag : V6_vandvrt_acc
8182 def int_hexagon_V6_vandvrt_acc :
8183 Hexagon_v64iv64iv512i_Intrinsic<"HEXAGON_V6_vandvrt_acc">;
8184
8185 //
8186 // BUILTIN_INFO(HEXAGON.V6_vandvrt_acc_128B,QV_ftype_QVVISI,3)
8187 // tag : V6_vandvrt_acc_128B
8188 def int_hexagon_V6_vandvrt_acc_128B :
8189 Hexagon_v128iv128iv1024i_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">;
8190
8191 //
8192 // BUILTIN_INFO(HEXAGON.V6_vgtw,QV_ftype_VIVI,2)
8193 // tag : V6_vgtw
8194 def int_hexagon_V6_vgtw :
8195 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtw">;
8196
8197 //
8198 // BUILTIN_INFO(HEXAGON.V6_vgtw_128B,QV_ftype_VIVI,2)
8199 // tag : V6_vgtw_128B
8200 def int_hexagon_V6_vgtw_128B :
8201 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_128B">;
8202
8203 //
8204 // BUILTIN_INFO(HEXAGON.V6_vgtw_and,QV_ftype_QVVIVI,3)
8205 // tag : V6_vgtw_and
8206 def int_hexagon_V6_vgtw_and :
8207 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_and">;
8208
8209 //
8210 // BUILTIN_INFO(HEXAGON.V6_vgtw_and_128B,QV_ftype_QVVIVI,3)
8211 // tag : V6_vgtw_and_128B
8212 def int_hexagon_V6_vgtw_and_128B :
8213 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_and_128B">;
8214
8215 //
8216 // BUILTIN_INFO(HEXAGON.V6_vgtw_or,QV_ftype_QVVIVI,3)
8217 // tag : V6_vgtw_or
8218 def int_hexagon_V6_vgtw_or :
8219 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_or">;
8220
8221 //
8222 // BUILTIN_INFO(HEXAGON.V6_vgtw_or_128B,QV_ftype_QVVIVI,3)
8223 // tag : V6_vgtw_or_128B
8224 def int_hexagon_V6_vgtw_or_128B :
8225 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_or_128B">;
8226
8227 //
8228 // BUILTIN_INFO(HEXAGON.V6_vgtw_xor,QV_ftype_QVVIVI,3)
8229 // tag : V6_vgtw_xor
8230 def int_hexagon_V6_vgtw_xor :
8231 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_xor">;
8232
8233 //
8234 // BUILTIN_INFO(HEXAGON.V6_vgtw_xor_128B,QV_ftype_QVVIVI,3)
8235 // tag : V6_vgtw_xor_128B
8236 def int_hexagon_V6_vgtw_xor_128B :
8237 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">;
8238
8239 //
8240 // BUILTIN_INFO(HEXAGON.V6_veqw,QV_ftype_VIVI,2)
8241 // tag : V6_veqw
8242 def int_hexagon_V6_veqw :
8243 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqw">;
8244
8245 //
8246 // BUILTIN_INFO(HEXAGON.V6_veqw_128B,QV_ftype_VIVI,2)
8247 // tag : V6_veqw_128B
8248 def int_hexagon_V6_veqw_128B :
8249 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_128B">;
8250
8251 //
8252 // BUILTIN_INFO(HEXAGON.V6_veqw_and,QV_ftype_QVVIVI,3)
8253 // tag : V6_veqw_and
8254 def int_hexagon_V6_veqw_and :
8255 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_and">;
8256
8257 //
8258 // BUILTIN_INFO(HEXAGON.V6_veqw_and_128B,QV_ftype_QVVIVI,3)
8259 // tag : V6_veqw_and_128B
8260 def int_hexagon_V6_veqw_and_128B :
8261 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_and_128B">;
8262
8263 //
8264 // BUILTIN_INFO(HEXAGON.V6_veqw_or,QV_ftype_QVVIVI,3)
8265 // tag : V6_veqw_or
8266 def int_hexagon_V6_veqw_or :
8267 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_or">;
8268
8269 //
8270 // BUILTIN_INFO(HEXAGON.V6_veqw_or_128B,QV_ftype_QVVIVI,3)
8271 // tag : V6_veqw_or_128B
8272 def int_hexagon_V6_veqw_or_128B :
8273 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_or_128B">;
8274
8275 //
8276 // BUILTIN_INFO(HEXAGON.V6_veqw_xor,QV_ftype_QVVIVI,3)
8277 // tag : V6_veqw_xor
8278 def int_hexagon_V6_veqw_xor :
8279 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_xor">;
8280
8281 //
8282 // BUILTIN_INFO(HEXAGON.V6_veqw_xor_128B,QV_ftype_QVVIVI,3)
8283 // tag : V6_veqw_xor_128B
8284 def int_hexagon_V6_veqw_xor_128B :
8285 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_xor_128B">;
8286
8287 //
8288 // BUILTIN_INFO(HEXAGON.V6_vgth,QV_ftype_VIVI,2)
8289 // tag : V6_vgth
8290 def int_hexagon_V6_vgth :
8291 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgth">;
8292
8293 //
8294 // BUILTIN_INFO(HEXAGON.V6_vgth_128B,QV_ftype_VIVI,2)
8295 // tag : V6_vgth_128B
8296 def int_hexagon_V6_vgth_128B :
8297 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_128B">;
8298
8299 //
8300 // BUILTIN_INFO(HEXAGON.V6_vgth_and,QV_ftype_QVVIVI,3)
8301 // tag : V6_vgth_and
8302 def int_hexagon_V6_vgth_and :
8303 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_and">;
8304
8305 //
8306 // BUILTIN_INFO(HEXAGON.V6_vgth_and_128B,QV_ftype_QVVIVI,3)
8307 // tag : V6_vgth_and_128B
8308 def int_hexagon_V6_vgth_and_128B :
8309 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_and_128B">;
8310
8311 //
8312 // BUILTIN_INFO(HEXAGON.V6_vgth_or,QV_ftype_QVVIVI,3)
8313 // tag : V6_vgth_or
8314 def int_hexagon_V6_vgth_or :
8315 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_or">;
8316
8317 //
8318 // BUILTIN_INFO(HEXAGON.V6_vgth_or_128B,QV_ftype_QVVIVI,3)
8319 // tag : V6_vgth_or_128B
8320 def int_hexagon_V6_vgth_or_128B :
8321 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_or_128B">;
8322
8323 //
8324 // BUILTIN_INFO(HEXAGON.V6_vgth_xor,QV_ftype_QVVIVI,3)
8325 // tag : V6_vgth_xor
8326 def int_hexagon_V6_vgth_xor :
8327 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_xor">;
8328
8329 //
8330 // BUILTIN_INFO(HEXAGON.V6_vgth_xor_128B,QV_ftype_QVVIVI,3)
8331 // tag : V6_vgth_xor_128B
8332 def int_hexagon_V6_vgth_xor_128B :
8333 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_xor_128B">;
8334
8335 //
8336 // BUILTIN_INFO(HEXAGON.V6_veqh,QV_ftype_VIVI,2)
8337 // tag : V6_veqh
8338 def int_hexagon_V6_veqh :
8339 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqh">;
8340
8341 //
8342 // BUILTIN_INFO(HEXAGON.V6_veqh_128B,QV_ftype_VIVI,2)
8343 // tag : V6_veqh_128B
8344 def int_hexagon_V6_veqh_128B :
8345 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_128B">;
8346
8347 //
8348 // BUILTIN_INFO(HEXAGON.V6_veqh_and,QV_ftype_QVVIVI,3)
8349 // tag : V6_veqh_and
8350 def int_hexagon_V6_veqh_and :
8351 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_and">;
8352
8353 //
8354 // BUILTIN_INFO(HEXAGON.V6_veqh_and_128B,QV_ftype_QVVIVI,3)
8355 // tag : V6_veqh_and_128B
8356 def int_hexagon_V6_veqh_and_128B :
8357 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_and_128B">;
8358
8359 //
8360 // BUILTIN_INFO(HEXAGON.V6_veqh_or,QV_ftype_QVVIVI,3)
8361 // tag : V6_veqh_or
8362 def int_hexagon_V6_veqh_or :
8363 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_or">;
8364
8365 //
8366 // BUILTIN_INFO(HEXAGON.V6_veqh_or_128B,QV_ftype_QVVIVI,3)
8367 // tag : V6_veqh_or_128B
8368 def int_hexagon_V6_veqh_or_128B :
8369 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_or_128B">;
8370
8371 //
8372 // BUILTIN_INFO(HEXAGON.V6_veqh_xor,QV_ftype_QVVIVI,3)
8373 // tag : V6_veqh_xor
8374 def int_hexagon_V6_veqh_xor :
8375 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_xor">;
8376
8377 //
8378 // BUILTIN_INFO(HEXAGON.V6_veqh_xor_128B,QV_ftype_QVVIVI,3)
8379 // tag : V6_veqh_xor_128B
8380 def int_hexagon_V6_veqh_xor_128B :
8381 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_xor_128B">;
8382
8383 //
8384 // BUILTIN_INFO(HEXAGON.V6_vgtb,QV_ftype_VIVI,2)
8385 // tag : V6_vgtb
8386 def int_hexagon_V6_vgtb :
8387 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtb">;
8388
8389 //
8390 // BUILTIN_INFO(HEXAGON.V6_vgtb_128B,QV_ftype_VIVI,2)
8391 // tag : V6_vgtb_128B
8392 def int_hexagon_V6_vgtb_128B :
8393 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_128B">;
8394
8395 //
8396 // BUILTIN_INFO(HEXAGON.V6_vgtb_and,QV_ftype_QVVIVI,3)
8397 // tag : V6_vgtb_and
8398 def int_hexagon_V6_vgtb_and :
8399 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_and">;
8400
8401 //
8402 // BUILTIN_INFO(HEXAGON.V6_vgtb_and_128B,QV_ftype_QVVIVI,3)
8403 // tag : V6_vgtb_and_128B
8404 def int_hexagon_V6_vgtb_and_128B :
8405 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_and_128B">;
8406
8407 //
8408 // BUILTIN_INFO(HEXAGON.V6_vgtb_or,QV_ftype_QVVIVI,3)
8409 // tag : V6_vgtb_or
8410 def int_hexagon_V6_vgtb_or :
8411 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_or">;
8412
8413 //
8414 // BUILTIN_INFO(HEXAGON.V6_vgtb_or_128B,QV_ftype_QVVIVI,3)
8415 // tag : V6_vgtb_or_128B
8416 def int_hexagon_V6_vgtb_or_128B :
8417 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_or_128B">;
8418
8419 //
8420 // BUILTIN_INFO(HEXAGON.V6_vgtb_xor,QV_ftype_QVVIVI,3)
8421 // tag : V6_vgtb_xor
8422 def int_hexagon_V6_vgtb_xor :
8423 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_xor">;
8424
8425 //
8426 // BUILTIN_INFO(HEXAGON.V6_vgtb_xor_128B,QV_ftype_QVVIVI,3)
8427 // tag : V6_vgtb_xor_128B
8428 def int_hexagon_V6_vgtb_xor_128B :
8429 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">;
8430
8431 //
8432 // BUILTIN_INFO(HEXAGON.V6_veqb,QV_ftype_VIVI,2)
8433 // tag : V6_veqb
8434 def int_hexagon_V6_veqb :
8435 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqb">;
8436
8437 //
8438 // BUILTIN_INFO(HEXAGON.V6_veqb_128B,QV_ftype_VIVI,2)
8439 // tag : V6_veqb_128B
8440 def int_hexagon_V6_veqb_128B :
8441 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_128B">;
8442
8443 //
8444 // BUILTIN_INFO(HEXAGON.V6_veqb_and,QV_ftype_QVVIVI,3)
8445 // tag : V6_veqb_and
8446 def int_hexagon_V6_veqb_and :
8447 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_and">;
8448
8449 //
8450 // BUILTIN_INFO(HEXAGON.V6_veqb_and_128B,QV_ftype_QVVIVI,3)
8451 // tag : V6_veqb_and_128B
8452 def int_hexagon_V6_veqb_and_128B :
8453 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_and_128B">;
8454
8455 //
8456 // BUILTIN_INFO(HEXAGON.V6_veqb_or,QV_ftype_QVVIVI,3)
8457 // tag : V6_veqb_or
8458 def int_hexagon_V6_veqb_or :
8459 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_or">;
8460
8461 //
8462 // BUILTIN_INFO(HEXAGON.V6_veqb_or_128B,QV_ftype_QVVIVI,3)
8463 // tag : V6_veqb_or_128B
8464 def int_hexagon_V6_veqb_or_128B :
8465 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_or_128B">;
8466
8467 //
8468 // BUILTIN_INFO(HEXAGON.V6_veqb_xor,QV_ftype_QVVIVI,3)
8469 // tag : V6_veqb_xor
8470 def int_hexagon_V6_veqb_xor :
8471 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_xor">;
8472
8473 //
8474 // BUILTIN_INFO(HEXAGON.V6_veqb_xor_128B,QV_ftype_QVVIVI,3)
8475 // tag : V6_veqb_xor_128B
8476 def int_hexagon_V6_veqb_xor_128B :
8477 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_xor_128B">;
8478
8479 //
8480 // BUILTIN_INFO(HEXAGON.V6_vgtuw,QV_ftype_VIVI,2)
8481 // tag : V6_vgtuw
8482 def int_hexagon_V6_vgtuw :
8483 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw">;
8484
8485 //
8486 // BUILTIN_INFO(HEXAGON.V6_vgtuw_128B,QV_ftype_VIVI,2)
8487 // tag : V6_vgtuw_128B
8488 def int_hexagon_V6_vgtuw_128B :
8489 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_128B">;
8490
8491 //
8492 // BUILTIN_INFO(HEXAGON.V6_vgtuw_and,QV_ftype_QVVIVI,3)
8493 // tag : V6_vgtuw_and
8494 def int_hexagon_V6_vgtuw_and :
8495 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_and">;
8496
8497 //
8498 // BUILTIN_INFO(HEXAGON.V6_vgtuw_and_128B,QV_ftype_QVVIVI,3)
8499 // tag : V6_vgtuw_and_128B
8500 def int_hexagon_V6_vgtuw_and_128B :
8501 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">;
8502
8503 //
8504 // BUILTIN_INFO(HEXAGON.V6_vgtuw_or,QV_ftype_QVVIVI,3)
8505 // tag : V6_vgtuw_or
8506 def int_hexagon_V6_vgtuw_or :
8507 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_or">;
8508
8509 //
8510 // BUILTIN_INFO(HEXAGON.V6_vgtuw_or_128B,QV_ftype_QVVIVI,3)
8511 // tag : V6_vgtuw_or_128B
8512 def int_hexagon_V6_vgtuw_or_128B :
8513 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">;
8514
8515 //
8516 // BUILTIN_INFO(HEXAGON.V6_vgtuw_xor,QV_ftype_QVVIVI,3)
8517 // tag : V6_vgtuw_xor
8518 def int_hexagon_V6_vgtuw_xor :
8519 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_xor">;
8520
8521 //
8522 // BUILTIN_INFO(HEXAGON.V6_vgtuw_xor_128B,QV_ftype_QVVIVI,3)
8523 // tag : V6_vgtuw_xor_128B
8524 def int_hexagon_V6_vgtuw_xor_128B :
8525 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">;
8526
8527 //
8528 // BUILTIN_INFO(HEXAGON.V6_vgtuh,QV_ftype_VIVI,2)
8529 // tag : V6_vgtuh
8530 def int_hexagon_V6_vgtuh :
8531 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh">;
8532
8533 //
8534 // BUILTIN_INFO(HEXAGON.V6_vgtuh_128B,QV_ftype_VIVI,2)
8535 // tag : V6_vgtuh_128B
8536 def int_hexagon_V6_vgtuh_128B :
8537 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_128B">;
8538
8539 //
8540 // BUILTIN_INFO(HEXAGON.V6_vgtuh_and,QV_ftype_QVVIVI,3)
8541 // tag : V6_vgtuh_and
8542 def int_hexagon_V6_vgtuh_and :
8543 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_and">;
8544
8545 //
8546 // BUILTIN_INFO(HEXAGON.V6_vgtuh_and_128B,QV_ftype_QVVIVI,3)
8547 // tag : V6_vgtuh_and_128B
8548 def int_hexagon_V6_vgtuh_and_128B :
8549 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">;
8550
8551 //
8552 // BUILTIN_INFO(HEXAGON.V6_vgtuh_or,QV_ftype_QVVIVI,3)
8553 // tag : V6_vgtuh_or
8554 def int_hexagon_V6_vgtuh_or :
8555 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_or">;
8556
8557 //
8558 // BUILTIN_INFO(HEXAGON.V6_vgtuh_or_128B,QV_ftype_QVVIVI,3)
8559 // tag : V6_vgtuh_or_128B
8560 def int_hexagon_V6_vgtuh_or_128B :
8561 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">;
8562
8563 //
8564 // BUILTIN_INFO(HEXAGON.V6_vgtuh_xor,QV_ftype_QVVIVI,3)
8565 // tag : V6_vgtuh_xor
8566 def int_hexagon_V6_vgtuh_xor :
8567 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_xor">;
8568
8569 //
8570 // BUILTIN_INFO(HEXAGON.V6_vgtuh_xor_128B,QV_ftype_QVVIVI,3)
8571 // tag : V6_vgtuh_xor_128B
8572 def int_hexagon_V6_vgtuh_xor_128B :
8573 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">;
8574
8575 //
8576 // BUILTIN_INFO(HEXAGON.V6_vgtub,QV_ftype_VIVI,2)
8577 // tag : V6_vgtub
8578 def int_hexagon_V6_vgtub :
8579 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtub">;
8580
8581 //
8582 // BUILTIN_INFO(HEXAGON.V6_vgtub_128B,QV_ftype_VIVI,2)
8583 // tag : V6_vgtub_128B
8584 def int_hexagon_V6_vgtub_128B :
8585 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_128B">;
8586
8587 //
8588 // BUILTIN_INFO(HEXAGON.V6_vgtub_and,QV_ftype_QVVIVI,3)
8589 // tag : V6_vgtub_and
8590 def int_hexagon_V6_vgtub_and :
8591 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_and">;
8592
8593 //
8594 // BUILTIN_INFO(HEXAGON.V6_vgtub_and_128B,QV_ftype_QVVIVI,3)
8595 // tag : V6_vgtub_and_128B
8596 def int_hexagon_V6_vgtub_and_128B :
8597 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_and_128B">;
8598
8599 //
8600 // BUILTIN_INFO(HEXAGON.V6_vgtub_or,QV_ftype_QVVIVI,3)
8601 // tag : V6_vgtub_or
8602 def int_hexagon_V6_vgtub_or :
8603 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_or">;
8604
8605 //
8606 // BUILTIN_INFO(HEXAGON.V6_vgtub_or_128B,QV_ftype_QVVIVI,3)
8607 // tag : V6_vgtub_or_128B
8608 def int_hexagon_V6_vgtub_or_128B :
8609 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_or_128B">;
8610
8611 //
8612 // BUILTIN_INFO(HEXAGON.V6_vgtub_xor,QV_ftype_QVVIVI,3)
8613 // tag : V6_vgtub_xor
8614 def int_hexagon_V6_vgtub_xor :
8615 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_xor">;
8616
8617 //
8618 // BUILTIN_INFO(HEXAGON.V6_vgtub_xor_128B,QV_ftype_QVVIVI,3)
8619 // tag : V6_vgtub_xor_128B
8620 def int_hexagon_V6_vgtub_xor_128B :
8621 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">;
8622
8623 //
8624 // BUILTIN_INFO(HEXAGON.V6_pred_or,QV_ftype_QVQV,2)
8625 // tag : V6_pred_or
8626 def int_hexagon_V6_pred_or :
8627 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_or">;
8628
8629 //
8630 // BUILTIN_INFO(HEXAGON.V6_pred_or_128B,QV_ftype_QVQV,2)
8631 // tag : V6_pred_or_128B
8632 def int_hexagon_V6_pred_or_128B :
8633 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_or_128B">;
8634
8635 //
8636 // BUILTIN_INFO(HEXAGON.V6_pred_and,QV_ftype_QVQV,2)
8637 // tag : V6_pred_and
8638 def int_hexagon_V6_pred_and :
8639 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_and">;
8640
8641 //
8642 // BUILTIN_INFO(HEXAGON.V6_pred_and_128B,QV_ftype_QVQV,2)
8643 // tag : V6_pred_and_128B
8644 def int_hexagon_V6_pred_and_128B :
8645 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_and_128B">;
8646
8647 //
8648 // BUILTIN_INFO(HEXAGON.V6_pred_not,QV_ftype_QV,1)
8649 // tag : V6_pred_not
8650 def int_hexagon_V6_pred_not :
8651 Hexagon_v64iv64i_Intrinsic<"HEXAGON_V6_pred_not">;
8652
8653 //
8654 // BUILTIN_INFO(HEXAGON.V6_pred_not_128B,QV_ftype_QV,1)
8655 // tag : V6_pred_not_128B
8656 def int_hexagon_V6_pred_not_128B :
8657 Hexagon_v128iv128i_Intrinsic<"HEXAGON_V6_pred_not_128B">;
8658
8659 //
8660 // BUILTIN_INFO(HEXAGON.V6_pred_xor,QV_ftype_QVQV,2)
8661 // tag : V6_pred_xor
8662 def int_hexagon_V6_pred_xor :
8663 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_xor">;
8664
8665 //
8666 // BUILTIN_INFO(HEXAGON.V6_pred_xor_128B,QV_ftype_QVQV,2)
8667 // tag : V6_pred_xor_128B
8668 def int_hexagon_V6_pred_xor_128B :
8669 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_xor_128B">;
8670
8671 //
8672 // BUILTIN_INFO(HEXAGON.V6_pred_and_n,QV_ftype_QVQV,2)
8673 // tag : V6_pred_and_n
8674 def int_hexagon_V6_pred_and_n :
8675 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_and_n">;
8676
8677 //
8678 // BUILTIN_INFO(HEXAGON.V6_pred_and_n_128B,QV_ftype_QVQV,2)
8679 // tag : V6_pred_and_n_128B
8680 def int_hexagon_V6_pred_and_n_128B :
8681 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_and_n_128B">;
8682
8683 //
8684 // BUILTIN_INFO(HEXAGON.V6_pred_or_n,QV_ftype_QVQV,2)
8685 // tag : V6_pred_or_n
8686 def int_hexagon_V6_pred_or_n :
8687 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_or_n">;
8688
8689 //
8690 // BUILTIN_INFO(HEXAGON.V6_pred_or_n_128B,QV_ftype_QVQV,2)
8691 // tag : V6_pred_or_n_128B
8692 def int_hexagon_V6_pred_or_n_128B :
8693 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_or_n_128B">;
8694
8695 //
8696 // BUILTIN_INFO(HEXAGON.V6_pred_scalar2,QV_ftype_SI,1)
8697 // tag : V6_pred_scalar2
8698 def int_hexagon_V6_pred_scalar2 :
8699 Hexagon_v64ii_Intrinsic<"HEXAGON_V6_pred_scalar2">;
8700
8701 //
8702 // BUILTIN_INFO(HEXAGON.V6_pred_scalar2_128B,QV_ftype_SI,1)
8703 // tag : V6_pred_scalar2_128B
8704 def int_hexagon_V6_pred_scalar2_128B :
8705 Hexagon_v128ii_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">;
8706
8707 //
8708 // BUILTIN_INFO(HEXAGON.V6_vmux,VI_ftype_QVVIVI,3)
8709 // tag : V6_vmux
8710 def int_hexagon_V6_vmux :
8711 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vmux">;
8712
8713 //
8714 // BUILTIN_INFO(HEXAGON.V6_vmux_128B,VI_ftype_QVVIVI,3)
8715 // tag : V6_vmux_128B
8716 def int_hexagon_V6_vmux_128B :
8717 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vmux_128B">;
8718
8719 //
8720 // BUILTIN_INFO(HEXAGON.V6_vswap,VD_ftype_QVVIVI,3)
8721 // tag : V6_vswap
8722 def int_hexagon_V6_vswap :
8723 Hexagon_v1024v64iv512v512_Intrinsic<"HEXAGON_V6_vswap">;
8724
8725 //
8726 // BUILTIN_INFO(HEXAGON.V6_vswap_128B,VD_ftype_QVVIVI,3)
8727 // tag : V6_vswap_128B
8728 def int_hexagon_V6_vswap_128B :
8729 Hexagon_v2048v128iv1024v1024_Intrinsic<"HEXAGON_V6_vswap_128B">;
8730
8731 //
8732 // BUILTIN_INFO(HEXAGON.V6_vmaxub,VI_ftype_VIVI,2)
8733 // tag : V6_vmaxub
8734 def int_hexagon_V6_vmaxub :
8735 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxub">;
8736
8737 //
8738 // BUILTIN_INFO(HEXAGON.V6_vmaxub_128B,VI_ftype_VIVI,2)
8739 // tag : V6_vmaxub_128B
8740 def int_hexagon_V6_vmaxub_128B :
8741 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxub_128B">;
8742
8743 //
8744 // BUILTIN_INFO(HEXAGON.V6_vminub,VI_ftype_VIVI,2)
8745 // tag : V6_vminub
8746 def int_hexagon_V6_vminub :
8747 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminub">;
8748
8749 //
8750 // BUILTIN_INFO(HEXAGON.V6_vminub_128B,VI_ftype_VIVI,2)
8751 // tag : V6_vminub_128B
8752 def int_hexagon_V6_vminub_128B :
8753 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminub_128B">;
8754
8755 //
8756 // BUILTIN_INFO(HEXAGON.V6_vmaxuh,VI_ftype_VIVI,2)
8757 // tag : V6_vmaxuh
8758 def int_hexagon_V6_vmaxuh :
8759 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxuh">;
8760
8761 //
8762 // BUILTIN_INFO(HEXAGON.V6_vmaxuh_128B,VI_ftype_VIVI,2)
8763 // tag : V6_vmaxuh_128B
8764 def int_hexagon_V6_vmaxuh_128B :
8765 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxuh_128B">;
8766
8767 //
8768 // BUILTIN_INFO(HEXAGON.V6_vminuh,VI_ftype_VIVI,2)
8769 // tag : V6_vminuh
8770 def int_hexagon_V6_vminuh :
8771 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminuh">;
8772
8773 //
8774 // BUILTIN_INFO(HEXAGON.V6_vminuh_128B,VI_ftype_VIVI,2)
8775 // tag : V6_vminuh_128B
8776 def int_hexagon_V6_vminuh_128B :
8777 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminuh_128B">;
8778
8779 //
8780 // BUILTIN_INFO(HEXAGON.V6_vmaxh,VI_ftype_VIVI,2)
8781 // tag : V6_vmaxh
8782 def int_hexagon_V6_vmaxh :
8783 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxh">;
8784
8785 //
8786 // BUILTIN_INFO(HEXAGON.V6_vmaxh_128B,VI_ftype_VIVI,2)
8787 // tag : V6_vmaxh_128B
8788 def int_hexagon_V6_vmaxh_128B :
8789 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxh_128B">;
8790
8791 //
8792 // BUILTIN_INFO(HEXAGON.V6_vminh,VI_ftype_VIVI,2)
8793 // tag : V6_vminh
8794 def int_hexagon_V6_vminh :
8795 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminh">;
8796
8797 //
8798 // BUILTIN_INFO(HEXAGON.V6_vminh_128B,VI_ftype_VIVI,2)
8799 // tag : V6_vminh_128B
8800 def int_hexagon_V6_vminh_128B :
8801 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminh_128B">;
8802
8803 //
8804 // BUILTIN_INFO(HEXAGON.V6_vmaxw,VI_ftype_VIVI,2)
8805 // tag : V6_vmaxw
8806 def int_hexagon_V6_vmaxw :
8807 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxw">;
8808
8809 //
8810 // BUILTIN_INFO(HEXAGON.V6_vmaxw_128B,VI_ftype_VIVI,2)
8811 // tag : V6_vmaxw_128B
8812 def int_hexagon_V6_vmaxw_128B :
8813 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxw_128B">;
8814
8815 //
8816 // BUILTIN_INFO(HEXAGON.V6_vminw,VI_ftype_VIVI,2)
8817 // tag : V6_vminw
8818 def int_hexagon_V6_vminw :
8819 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminw">;
8820
8821 //
8822 // BUILTIN_INFO(HEXAGON.V6_vminw_128B,VI_ftype_VIVI,2)
8823 // tag : V6_vminw_128B
8824 def int_hexagon_V6_vminw_128B :
8825 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminw_128B">;
8826
8827 //
8828 // BUILTIN_INFO(HEXAGON.V6_vsathub,VI_ftype_VIVI,2)
8829 // tag : V6_vsathub
8830 def int_hexagon_V6_vsathub :
8831 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsathub">;
8832
8833 //
8834 // BUILTIN_INFO(HEXAGON.V6_vsathub_128B,VI_ftype_VIVI,2)
8835 // tag : V6_vsathub_128B
8836 def int_hexagon_V6_vsathub_128B :
8837 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsathub_128B">;
8838
8839 //
8840 // BUILTIN_INFO(HEXAGON.V6_vsatwh,VI_ftype_VIVI,2)
8841 // tag : V6_vsatwh
8842 def int_hexagon_V6_vsatwh :
8843 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsatwh">;
8844
8845 //
8846 // BUILTIN_INFO(HEXAGON.V6_vsatwh_128B,VI_ftype_VIVI,2)
8847 // tag : V6_vsatwh_128B
8848 def int_hexagon_V6_vsatwh_128B :
8849 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsatwh_128B">;
8850
8851 //
8852 // BUILTIN_INFO(HEXAGON.V6_vshuffeb,VI_ftype_VIVI,2)
8853 // tag : V6_vshuffeb
8854 def int_hexagon_V6_vshuffeb :
8855 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshuffeb">;
8856
8857 //
8858 // BUILTIN_INFO(HEXAGON.V6_vshuffeb_128B,VI_ftype_VIVI,2)
8859 // tag : V6_vshuffeb_128B
8860 def int_hexagon_V6_vshuffeb_128B :
8861 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshuffeb_128B">;
8862
8863 //
8864 // BUILTIN_INFO(HEXAGON.V6_vshuffob,VI_ftype_VIVI,2)
8865 // tag : V6_vshuffob
8866 def int_hexagon_V6_vshuffob :
8867 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshuffob">;
8868
8869 //
8870 // BUILTIN_INFO(HEXAGON.V6_vshuffob_128B,VI_ftype_VIVI,2)
8871 // tag : V6_vshuffob_128B
8872 def int_hexagon_V6_vshuffob_128B :
8873 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshuffob_128B">;
8874
8875 //
8876 // BUILTIN_INFO(HEXAGON.V6_vshufeh,VI_ftype_VIVI,2)
8877 // tag : V6_vshufeh
8878 def int_hexagon_V6_vshufeh :
8879 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshufeh">;
8880
8881 //
8882 // BUILTIN_INFO(HEXAGON.V6_vshufeh_128B,VI_ftype_VIVI,2)
8883 // tag : V6_vshufeh_128B
8884 def int_hexagon_V6_vshufeh_128B :
8885 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshufeh_128B">;
8886
8887 //
8888 // BUILTIN_INFO(HEXAGON.V6_vshufoh,VI_ftype_VIVI,2)
8889 // tag : V6_vshufoh
8890 def int_hexagon_V6_vshufoh :
8891 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshufoh">;
8892
8893 //
8894 // BUILTIN_INFO(HEXAGON.V6_vshufoh_128B,VI_ftype_VIVI,2)
8895 // tag : V6_vshufoh_128B
8896 def int_hexagon_V6_vshufoh_128B :
8897 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshufoh_128B">;
8898
8899 //
8900 // BUILTIN_INFO(HEXAGON.V6_vshuffvdd,VD_ftype_VIVISI,3)
8901 // tag : V6_vshuffvdd
8902 def int_hexagon_V6_vshuffvdd :
8903 Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vshuffvdd">;
8904
8905 //
8906 // BUILTIN_INFO(HEXAGON.V6_vshuffvdd_128B,VD_ftype_VIVISI,3)
8907 // tag : V6_vshuffvdd_128B
8908 def int_hexagon_V6_vshuffvdd_128B :
8909 Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">;
8910
8911 //
8912 // BUILTIN_INFO(HEXAGON.V6_vdealvdd,VD_ftype_VIVISI,3)
8913 // tag : V6_vdealvdd
8914 def int_hexagon_V6_vdealvdd :
8915 Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vdealvdd">;
8916
8917 //
8918 // BUILTIN_INFO(HEXAGON.V6_vdealvdd_128B,VD_ftype_VIVISI,3)
8919 // tag : V6_vdealvdd_128B
8920 def int_hexagon_V6_vdealvdd_128B :
8921 Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vdealvdd_128B">;
8922
8923 //
8924 // BUILTIN_INFO(HEXAGON.V6_vshufoeh,VD_ftype_VIVI,2)
8925 // tag : V6_vshufoeh
8926 def int_hexagon_V6_vshufoeh :
8927 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vshufoeh">;
8928
8929 //
8930 // BUILTIN_INFO(HEXAGON.V6_vshufoeh_128B,VD_ftype_VIVI,2)
8931 // tag : V6_vshufoeh_128B
8932 def int_hexagon_V6_vshufoeh_128B :
8933 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vshufoeh_128B">;
8934
8935 //
8936 // BUILTIN_INFO(HEXAGON.V6_vshufoeb,VD_ftype_VIVI,2)
8937 // tag : V6_vshufoeb
8938 def int_hexagon_V6_vshufoeb :
8939 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vshufoeb">;
8940
8941 //
8942 // BUILTIN_INFO(HEXAGON.V6_vshufoeb_128B,VD_ftype_VIVI,2)
8943 // tag : V6_vshufoeb_128B
8944 def int_hexagon_V6_vshufoeb_128B :
8945 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vshufoeb_128B">;
8946
8947 //
8948 // BUILTIN_INFO(HEXAGON.V6_vdealh,VI_ftype_VI,1)
8949 // tag : V6_vdealh
8950 def int_hexagon_V6_vdealh :
8951 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vdealh">;
8952
8953 //
8954 // BUILTIN_INFO(HEXAGON.V6_vdealh_128B,VI_ftype_VI,1)
8955 // tag : V6_vdealh_128B
8956 def int_hexagon_V6_vdealh_128B :
8957 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vdealh_128B">;
8958
8959 //
8960 // BUILTIN_INFO(HEXAGON.V6_vdealb,VI_ftype_VI,1)
8961 // tag : V6_vdealb
8962 def int_hexagon_V6_vdealb :
8963 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vdealb">;
8964
8965 //
8966 // BUILTIN_INFO(HEXAGON.V6_vdealb_128B,VI_ftype_VI,1)
8967 // tag : V6_vdealb_128B
8968 def int_hexagon_V6_vdealb_128B :
8969 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vdealb_128B">;
8970
8971 //
8972 // BUILTIN_INFO(HEXAGON.V6_vdealb4w,VI_ftype_VIVI,2)
8973 // tag : V6_vdealb4w
8974 def int_hexagon_V6_vdealb4w :
8975 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdealb4w">;
8976
8977 //
8978 // BUILTIN_INFO(HEXAGON.V6_vdealb4w_128B,VI_ftype_VIVI,2)
8979 // tag : V6_vdealb4w_128B
8980 def int_hexagon_V6_vdealb4w_128B :
8981 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdealb4w_128B">;
8982
8983 //
8984 // BUILTIN_INFO(HEXAGON.V6_vshuffh,VI_ftype_VI,1)
8985 // tag : V6_vshuffh
8986 def int_hexagon_V6_vshuffh :
8987 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vshuffh">;
8988
8989 //
8990 // BUILTIN_INFO(HEXAGON.V6_vshuffh_128B,VI_ftype_VI,1)
8991 // tag : V6_vshuffh_128B
8992 def int_hexagon_V6_vshuffh_128B :
8993 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vshuffh_128B">;
8994
8995 //
8996 // BUILTIN_INFO(HEXAGON.V6_vshuffb,VI_ftype_VI,1)
8997 // tag : V6_vshuffb
8998 def int_hexagon_V6_vshuffb :
8999 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vshuffb">;
9000
9001 //
9002 // BUILTIN_INFO(HEXAGON.V6_vshuffb_128B,VI_ftype_VI,1)
9003 // tag : V6_vshuffb_128B
9004 def int_hexagon_V6_vshuffb_128B :
9005 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vshuffb_128B">;
9006
9007 //
9008 // BUILTIN_INFO(HEXAGON.V6_extractw,SI_ftype_VISI,2)
9009 // tag : V6_extractw
9010 def int_hexagon_V6_extractw :
9011 Hexagon_iv512i_Intrinsic<"HEXAGON_V6_extractw">;
9012
9013 //
9014 // BUILTIN_INFO(HEXAGON.V6_extractw_128B,SI_ftype_VISI,2)
9015 // tag : V6_extractw_128B
9016 def int_hexagon_V6_extractw_128B :
9017 Hexagon_iv1024i_Intrinsic<"HEXAGON_V6_extractw_128B">;
9018
9019 //
9020 // BUILTIN_INFO(HEXAGON.V6_vinsertwr,VI_ftype_VISI,2)
9021 // tag : V6_vinsertwr
9022 def int_hexagon_V6_vinsertwr :
9023 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vinsertwr">;
9024
9025 //
9026 // BUILTIN_INFO(HEXAGON.V6_vinsertwr_128B,VI_ftype_VISI,2)
9027 // tag : V6_vinsertwr_128B
9028 def int_hexagon_V6_vinsertwr_128B :
9029 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vinsertwr_128B">;
9030
9031 //
9032 // BUILTIN_INFO(HEXAGON.V6_lvsplatw,VI_ftype_SI,1)
9033 // tag : V6_lvsplatw
9034 def int_hexagon_V6_lvsplatw :
9035 Hexagon_v512i_Intrinsic<"HEXAGON_V6_lvsplatw">;
9036
9037 //
9038 // BUILTIN_INFO(HEXAGON.V6_lvsplatw_128B,VI_ftype_SI,1)
9039 // tag : V6_lvsplatw_128B
9040 def int_hexagon_V6_lvsplatw_128B :
9041 Hexagon_v1024i_Intrinsic<"HEXAGON_V6_lvsplatw_128B">;
9042
9043 //
9044 // BUILTIN_INFO(HEXAGON.V6_vassign,VI_ftype_VI,1)
9045 // tag : V6_vassign
9046 def int_hexagon_V6_vassign :
9047 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vassign">;
9048
9049 //
9050 // BUILTIN_INFO(HEXAGON.V6_vassign_128B,VI_ftype_VI,1)
9051 // tag : V6_vassign_128B
9052 def int_hexagon_V6_vassign_128B :
9053 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vassign_128B">;
9054
9055 //
9056 // BUILTIN_INFO(HEXAGON.V6_vcombine,VD_ftype_VIVI,2)
9057 // tag : V6_vcombine
9058 def int_hexagon_V6_vcombine :
9059 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vcombine">;
9060
9061 //
9062 // BUILTIN_INFO(HEXAGON.V6_vcombine_128B,VD_ftype_VIVI,2)
9063 // tag : V6_vcombine_128B
9064 def int_hexagon_V6_vcombine_128B :
9065 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vcombine_128B">;
9066
9067 //
9068 // BUILTIN_INFO(HEXAGON.V6_vdelta,VI_ftype_VIVI,2)
9069 // tag : V6_vdelta
9070 def int_hexagon_V6_vdelta :
9071 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdelta">;
9072
9073 //
9074 // BUILTIN_INFO(HEXAGON.V6_vdelta_128B,VI_ftype_VIVI,2)
9075 // tag : V6_vdelta_128B
9076 def int_hexagon_V6_vdelta_128B :
9077 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdelta_128B">;
9078
9079 //
9080 // BUILTIN_INFO(HEXAGON.V6_vrdelta,VI_ftype_VIVI,2)
9081 // tag : V6_vrdelta
9082 def int_hexagon_V6_vrdelta :
9083 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrdelta">;
9084
9085 //
9086 // BUILTIN_INFO(HEXAGON.V6_vrdelta_128B,VI_ftype_VIVI,2)
9087 // tag : V6_vrdelta_128B
9088 def int_hexagon_V6_vrdelta_128B :
9089 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrdelta_128B">;
9090
9091 //
9092 // BUILTIN_INFO(HEXAGON.V6_vcl0w,VI_ftype_VI,1)
9093 // tag : V6_vcl0w
9094 def int_hexagon_V6_vcl0w :
9095 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vcl0w">;
9096
9097 //
9098 // BUILTIN_INFO(HEXAGON.V6_vcl0w_128B,VI_ftype_VI,1)
9099 // tag : V6_vcl0w_128B
9100 def int_hexagon_V6_vcl0w_128B :
9101 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vcl0w_128B">;
9102
9103 //
9104 // BUILTIN_INFO(HEXAGON.V6_vcl0h,VI_ftype_VI,1)
9105 // tag : V6_vcl0h
9106 def int_hexagon_V6_vcl0h :
9107 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vcl0h">;
9108
9109 //
9110 // BUILTIN_INFO(HEXAGON.V6_vcl0h_128B,VI_ftype_VI,1)
9111 // tag : V6_vcl0h_128B
9112 def int_hexagon_V6_vcl0h_128B :
9113 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vcl0h_128B">;
9114
9115 //
9116 // BUILTIN_INFO(HEXAGON.V6_vnormamtw,VI_ftype_VI,1)
9117 // tag : V6_vnormamtw
9118 def int_hexagon_V6_vnormamtw :
9119 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnormamtw">;
9120
9121 //
9122 // BUILTIN_INFO(HEXAGON.V6_vnormamtw_128B,VI_ftype_VI,1)
9123 // tag : V6_vnormamtw_128B
9124 def int_hexagon_V6_vnormamtw_128B :
9125 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnormamtw_128B">;
9126
9127 //
9128 // BUILTIN_INFO(HEXAGON.V6_vnormamth,VI_ftype_VI,1)
9129 // tag : V6_vnormamth
9130 def int_hexagon_V6_vnormamth :
9131 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnormamth">;
9132
9133 //
9134 // BUILTIN_INFO(HEXAGON.V6_vnormamth_128B,VI_ftype_VI,1)
9135 // tag : V6_vnormamth_128B
9136 def int_hexagon_V6_vnormamth_128B :
9137 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnormamth_128B">;
9138
9139 //
9140 // BUILTIN_INFO(HEXAGON.V6_vpopcounth,VI_ftype_VI,1)
9141 // tag : V6_vpopcounth
9142 def int_hexagon_V6_vpopcounth :
9143 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vpopcounth">;
9144
9145 //
9146 // BUILTIN_INFO(HEXAGON.V6_vpopcounth_128B,VI_ftype_VI,1)
9147 // tag : V6_vpopcounth_128B
9148 def int_hexagon_V6_vpopcounth_128B :
9149 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vpopcounth_128B">;
9150
9151 //
9152 // BUILTIN_INFO(HEXAGON.V6_vlutvvb,VI_ftype_VIVISI,3)
9153 // tag : V6_vlutvvb
9154 def int_hexagon_V6_vlutvvb :
9155 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb">;
9156
9157 //
9158 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_128B,VI_ftype_VIVISI,3)
9159 // tag : V6_vlutvvb_128B
9160 def int_hexagon_V6_vlutvvb_128B :
9161 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_128B">;
9162
9163 //
9164 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracc,VI_ftype_VIVIVISI,4)
9165 // tag : V6_vlutvvb_oracc
9166 def int_hexagon_V6_vlutvvb_oracc :
9167 Hexagon_v512v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">;
9168
9169 //
9170 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracc_128B,VI_ftype_VIVIVISI,4)
9171 // tag : V6_vlutvvb_oracc_128B
9172 def int_hexagon_V6_vlutvvb_oracc_128B :
9173 Hexagon_v1024v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">;
9174
9175 //
9176 // BUILTIN_INFO(HEXAGON.V6_vlutvwh,VD_ftype_VIVISI,3)
9177 // tag : V6_vlutvwh
9178 def int_hexagon_V6_vlutvwh :
9179 Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh">;
9180
9181 //
9182 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_128B,VD_ftype_VIVISI,3)
9183 // tag : V6_vlutvwh_128B
9184 def int_hexagon_V6_vlutvwh_128B :
9185 Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_128B">;
9186
9187 //
9188 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracc,VD_ftype_VDVIVISI,4)
9189 // tag : V6_vlutvwh_oracc
9190 def int_hexagon_V6_vlutvwh_oracc :
9191 Hexagon_v1024v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">;
9192
9193 //
9194 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracc_128B,VD_ftype_VDVIVISI,4)
9195 // tag : V6_vlutvwh_oracc_128B
9196 def int_hexagon_V6_vlutvwh_oracc_128B :
9197 Hexagon_v2048v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">;
9198
9199 //
9200 // Masked vector stores
9201 //
9202 def int_hexagon_V6_vS32b_qpred_ai :
9203 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;
9204
9205 def int_hexagon_V6_vS32b_nqpred_ai :
9206 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;
9207
9208 def int_hexagon_V6_vS32b_nt_qpred_ai :
9209 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;
9210
9211 def int_hexagon_V6_vS32b_nt_nqpred_ai :
9212 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;
9213
9214 def int_hexagon_V6_vS32b_qpred_ai_128B :
9215 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;
9216
9217 def int_hexagon_V6_vS32b_nqpred_ai_128B :
9218 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;
9219
9220 def int_hexagon_V6_vS32b_nt_qpred_ai_128B :
9221 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;
9222
9223 def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :
9224 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;
9225
9226 def int_hexagon_V6_vmaskedstoreq :
9227 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;
9228
9229 def int_hexagon_V6_vmaskedstorenq :
9230 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">;
9231
9232 def int_hexagon_V6_vmaskedstorentq :
9233 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">;
9234
9235 def int_hexagon_V6_vmaskedstorentnq :
9236 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">;
9237
9238 def int_hexagon_V6_vmaskedstoreq_128B :
9239 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">;
9240
9241 def int_hexagon_V6_vmaskedstorenq_128B :
9242 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">;
9243
9244 def int_hexagon_V6_vmaskedstorentq_128B :
9245 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">;
9246
9247 def int_hexagon_V6_vmaskedstorentnq_128B :
9248 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">;
9249
9250 multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> {
9251   def NAME#_pci : Hexagon_NonGCC_Intrinsic<
9252     [ElTy, llvm_ptr_ty],
9253     [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty],
9254     [IntrArgMemOnly, NoCapture<3>]>;
9255   def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
9256     [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty],
9257     [IntrArgMemOnly, NoCapture<2>]>;
9258 }
9259
9260 defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
9261 defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
9262 defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
9263 defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
9264 defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
9265 defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>;
9266
9267 multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> {
9268   def NAME#_pci : Hexagon_NonGCC_Intrinsic<
9269     [llvm_ptr_ty],
9270     [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
9271     [IntrArgMemOnly, NoCapture<4>]>;
9272   def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
9273     [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
9274     [IntrArgMemOnly, NoCapture<3>]>;
9275 }
9276
9277 defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
9278 defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
9279 defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
9280 defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
9281 defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>;
9282
9283 // The front-end emits the intrinsic call with only two arguments. The third
9284 // argument from the builtin is already used by front-end to write to memory
9285 // by generating a store.
9286 class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy>
9287  : Hexagon_NonGCC_Intrinsic<
9288     [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty],
9289     [IntrReadMem]>;
9290
9291 def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
9292 def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
9293 def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
9294 def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
9295 def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
9296 def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>;
9297
9298 def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
9299 def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
9300 def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
9301 def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
9302 def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">;
9303
9304
9305 ///
9306 /// HexagonV62 intrinsics
9307 ///
9308
9309 //
9310 // Hexagon_LLiLLiLLi_Intrinsic<string GCCIntSuffix>
9311 // tag : M6_vabsdiffb
9312 class Hexagon_LLiLLiLLi_Intrinsic<string GCCIntSuffix>
9313  : Hexagon_Intrinsic<GCCIntSuffix,
9314                           [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],
9315                           [IntrNoMem]>;
9316
9317 //
9318 // Hexagon_LLii_Intrinsic<string GCCIntSuffix>
9319 // tag : S6_vsplatrbp
9320 class Hexagon_LLii_Intrinsic<string GCCIntSuffix>
9321  : Hexagon_Intrinsic<GCCIntSuffix,
9322                           [llvm_i64_ty], [llvm_i32_ty],
9323                           [IntrNoMem]>;
9324
9325 //
9326 // Hexagon_V62_v512v512i_Intrinsic<string GCCIntSuffix>
9327 // tag : V6_vlsrb
9328 class Hexagon_V62_v512v512i_Intrinsic<string GCCIntSuffix>
9329  : Hexagon_Intrinsic<GCCIntSuffix,
9330                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
9331                           [IntrNoMem]>;
9332
9333 //
9334 // Hexagon_V62_v1024v1024i_Intrinsic<string GCCIntSuffix>
9335 // tag : V6_vlsrb_128B
9336 class Hexagon_V62_v1024v1024i_Intrinsic<string GCCIntSuffix>
9337  : Hexagon_Intrinsic<GCCIntSuffix,
9338                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
9339                           [IntrNoMem]>;
9340
9341 //
9342 // Hexagon_V62_v512v512v512i_Intrinsic<string GCCIntSuffix>
9343 // tag : V6_vasrwuhrndsat
9344 class Hexagon_V62_v512v512v512i_Intrinsic<string GCCIntSuffix>
9345  : Hexagon_Intrinsic<GCCIntSuffix,
9346                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
9347                           [IntrNoMem]>;
9348
9349 //
9350 // Hexagon_V62_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
9351 // tag : V6_vasrwuhrndsat_128B
9352 class Hexagon_V62_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
9353  : Hexagon_Intrinsic<GCCIntSuffix,
9354                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
9355                           [IntrNoMem]>;
9356
9357 //
9358 // Hexagon_V62_v512v512v512_Intrinsic<string GCCIntSuffix>
9359 // tag : V6_vrounduwuh
9360 class Hexagon_V62_v512v512v512_Intrinsic<string GCCIntSuffix>
9361  : Hexagon_Intrinsic<GCCIntSuffix,
9362                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
9363                           [IntrNoMem]>;
9364
9365 //
9366 // Hexagon_V62_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
9367 // tag : V6_vrounduwuh_128B
9368 class Hexagon_V62_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
9369  : Hexagon_Intrinsic<GCCIntSuffix,
9370                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
9371                           [IntrNoMem]>;
9372
9373 //
9374 // Hexagon_V62_v2048v2048v2048_Intrinsic<string GCCIntSuffix>
9375 // tag : V6_vadduwsat_dv_128B
9376 class Hexagon_V62_v2048v2048v2048_Intrinsic<string GCCIntSuffix>
9377  : Hexagon_Intrinsic<GCCIntSuffix,
9378                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
9379                           [IntrNoMem]>;
9380
9381 //
9382 // Hexagon_V62_v1024v1024v512v512_Intrinsic<string GCCIntSuffix>
9383 // tag : V6_vaddhw_acc
9384 class Hexagon_V62_v1024v1024v512v512_Intrinsic<string GCCIntSuffix>
9385  : Hexagon_Intrinsic<GCCIntSuffix,
9386                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
9387                           [IntrNoMem]>;
9388
9389 //
9390 // Hexagon_V62_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix>
9391 // tag : V6_vaddhw_acc_128B
9392 class Hexagon_V62_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix>
9393  : Hexagon_Intrinsic<GCCIntSuffix,
9394                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
9395                           [IntrNoMem]>;
9396
9397 //
9398 // Hexagon_V62_v1024v512v512_Intrinsic<string GCCIntSuffix>
9399 // tag : V6_vmpyewuh_64
9400 class Hexagon_V62_v1024v512v512_Intrinsic<string GCCIntSuffix>
9401  : Hexagon_Intrinsic<GCCIntSuffix,
9402                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
9403                           [IntrNoMem]>;
9404
9405 //
9406 // Hexagon_V62_v2048v1024v1024_Intrinsic<string GCCIntSuffix>
9407 // tag : V6_vmpyewuh_64_128B
9408 class Hexagon_V62_v2048v1024v1024_Intrinsic<string GCCIntSuffix>
9409  : Hexagon_Intrinsic<GCCIntSuffix,
9410                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
9411                           [IntrNoMem]>;
9412
9413 //
9414 // Hexagon_V62_v2048v2048i_Intrinsic<string GCCIntSuffix>
9415 // tag : V6_vmpauhb_128B
9416 class Hexagon_V62_v2048v2048i_Intrinsic<string GCCIntSuffix>
9417  : Hexagon_Intrinsic<GCCIntSuffix,
9418                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
9419                           [IntrNoMem]>;
9420
9421 //
9422 // Hexagon_V62_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
9423 // tag : V6_vmpauhb_acc_128B
9424 class Hexagon_V62_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
9425  : Hexagon_Intrinsic<GCCIntSuffix,
9426                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
9427                           [IntrNoMem]>;
9428
9429 //
9430 // Hexagon_V62_v512v64ii_Intrinsic<string GCCIntSuffix>
9431 // tag : V6_vandnqrt
9432 class Hexagon_V62_v512v64ii_Intrinsic<string GCCIntSuffix>
9433  : Hexagon_Intrinsic<GCCIntSuffix,
9434                           [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],
9435                           [IntrNoMem]>;
9436
9437 //
9438 // Hexagon_V62_v1024v128ii_Intrinsic<string GCCIntSuffix>
9439 // tag : V6_vandnqrt_128B
9440 class Hexagon_V62_v1024v128ii_Intrinsic<string GCCIntSuffix>
9441  : Hexagon_Intrinsic<GCCIntSuffix,
9442                           [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],
9443                           [IntrNoMem]>;
9444
9445 //
9446 // Hexagon_V62_v512v512v64ii_Intrinsic<string GCCIntSuffix>
9447 // tag : V6_vandnqrt_acc
9448 class Hexagon_V62_v512v512v64ii_Intrinsic<string GCCIntSuffix>
9449  : Hexagon_Intrinsic<GCCIntSuffix,
9450                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],
9451                           [IntrNoMem]>;
9452
9453 //
9454 // Hexagon_V62_v1024v1024v128ii_Intrinsic<string GCCIntSuffix>
9455 // tag : V6_vandnqrt_acc_128B
9456 class Hexagon_V62_v1024v1024v128ii_Intrinsic<string GCCIntSuffix>
9457  : Hexagon_Intrinsic<GCCIntSuffix,
9458                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],
9459                           [IntrNoMem]>;
9460
9461 //
9462 // Hexagon_V62_v512v64iv512_Intrinsic<string GCCIntSuffix>
9463 // tag : V6_vandvqv
9464 class Hexagon_V62_v512v64iv512_Intrinsic<string GCCIntSuffix>
9465  : Hexagon_Intrinsic<GCCIntSuffix,
9466                           [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty],
9467                           [IntrNoMem]>;
9468
9469 //
9470 // Hexagon_V62_v1024v128iv1024_Intrinsic<string GCCIntSuffix>
9471 // tag : V6_vandvqv_128B
9472 class Hexagon_V62_v1024v128iv1024_Intrinsic<string GCCIntSuffix>
9473  : Hexagon_Intrinsic<GCCIntSuffix,
9474                           [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty],
9475                           [IntrNoMem]>;
9476
9477 //
9478 // Hexagon_V62_v64ii_Intrinsic<string GCCIntSuffix>
9479 // tag : V6_pred_scalar2v2
9480 class Hexagon_V62_v64ii_Intrinsic<string GCCIntSuffix>
9481  : Hexagon_Intrinsic<GCCIntSuffix,
9482                           [llvm_v512i1_ty], [llvm_i32_ty],
9483                           [IntrNoMem]>;
9484
9485 //
9486 // Hexagon_V62_v128ii_Intrinsic<string GCCIntSuffix>
9487 // tag : V6_pred_scalar2v2_128B
9488 class Hexagon_V62_v128ii_Intrinsic<string GCCIntSuffix>
9489  : Hexagon_Intrinsic<GCCIntSuffix,
9490                           [llvm_v1024i1_ty], [llvm_i32_ty],
9491                           [IntrNoMem]>;
9492
9493 //
9494 // Hexagon_V62_v64iv64iv64i_Intrinsic<string GCCIntSuffix>
9495 // tag : V6_shuffeqw
9496 class Hexagon_V62_v64iv64iv64i_Intrinsic<string GCCIntSuffix>
9497  : Hexagon_Intrinsic<GCCIntSuffix,
9498                           [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],
9499                           [IntrNoMem]>;
9500
9501 //
9502 // Hexagon_V62_v128iv128iv128i_Intrinsic<string GCCIntSuffix>
9503 // tag : V6_shuffeqw_128B
9504 class Hexagon_V62_v128iv128iv128i_Intrinsic<string GCCIntSuffix>
9505  : Hexagon_Intrinsic<GCCIntSuffix,
9506                           [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],
9507                           [IntrNoMem]>;
9508
9509 //
9510 // Hexagon_V62_v512i_Intrinsic<string GCCIntSuffix>
9511 // tag : V6_lvsplath
9512 class Hexagon_V62_v512i_Intrinsic<string GCCIntSuffix>
9513  : Hexagon_Intrinsic<GCCIntSuffix,
9514                           [llvm_v16i32_ty], [llvm_i32_ty],
9515                           [IntrNoMem]>;
9516
9517 //
9518 // Hexagon_V62_v1024i_Intrinsic<string GCCIntSuffix>
9519 // tag : V6_lvsplath_128B
9520 class Hexagon_V62_v1024i_Intrinsic<string GCCIntSuffix>
9521  : Hexagon_Intrinsic<GCCIntSuffix,
9522                           [llvm_v32i32_ty], [llvm_i32_ty],
9523                           [IntrNoMem]>;
9524
9525 //
9526 // Hexagon_V62_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
9527 // tag : V6_vlutvvb_oracci
9528 class Hexagon_V62_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
9529  : Hexagon_Intrinsic<GCCIntSuffix,
9530                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
9531                           [IntrNoMem]>;
9532
9533 //
9534 // Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
9535 // tag : V6_vlutvvb_oracci_128B
9536 class Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
9537  : Hexagon_Intrinsic<GCCIntSuffix,
9538                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
9539                           [IntrNoMem]>;
9540
9541 //
9542 // Hexagon_V62_v1024v512v512i_Intrinsic<string GCCIntSuffix>
9543 // tag : V6_vlutvwhi
9544 class Hexagon_V62_v1024v512v512i_Intrinsic<string GCCIntSuffix>
9545  : Hexagon_Intrinsic<GCCIntSuffix,
9546                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
9547                           [IntrNoMem]>;
9548
9549 //
9550 // Hexagon_V62_v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
9551 // tag : V6_vlutvwhi_128B
9552 class Hexagon_V62_v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
9553  : Hexagon_Intrinsic<GCCIntSuffix,
9554                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
9555                           [IntrNoMem]>;
9556
9557 //
9558 // Hexagon_V62_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix>
9559 // tag : V6_vlutvwh_oracci
9560 class Hexagon_V62_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix>
9561  : Hexagon_Intrinsic<GCCIntSuffix,
9562                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
9563                           [IntrNoMem]>;
9564
9565 //
9566 // Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
9567 // tag : V6_vlutvwh_oracci_128B
9568 class Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
9569  : Hexagon_Intrinsic<GCCIntSuffix,
9570                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
9571                           [IntrNoMem]>;
9572
9573 // Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix>
9574 // tag: V6_vaddcarry
9575 class Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix>
9576   : Hexagon_Intrinsic<GCCIntSuffix,
9577                           [llvm_v16i32_ty, llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
9578                           [IntrNoMem]>;
9579
9580 // Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix>
9581 // tag: V6_vaddcarry_128B
9582 class Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix>
9583   : Hexagon_Intrinsic<GCCIntSuffix,
9584                           [llvm_v32i32_ty, llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
9585                           [IntrNoMem]>;
9586
9587
9588 //
9589 // BUILTIN_INFO(HEXAGON.M6_vabsdiffb,DI_ftype_DIDI,2)
9590 // tag : M6_vabsdiffb
9591 def int_hexagon_M6_vabsdiffb :
9592 Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_M6_vabsdiffb">;
9593
9594 //
9595 // BUILTIN_INFO(HEXAGON.M6_vabsdiffub,DI_ftype_DIDI,2)
9596 // tag : M6_vabsdiffub
9597 def int_hexagon_M6_vabsdiffub :
9598 Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_M6_vabsdiffub">;
9599
9600 //
9601 // BUILTIN_INFO(HEXAGON.S6_vtrunehb_ppp,DI_ftype_DIDI,2)
9602 // tag : S6_vtrunehb_ppp
9603 def int_hexagon_S6_vtrunehb_ppp :
9604 Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">;
9605
9606 //
9607 // BUILTIN_INFO(HEXAGON.S6_vtrunohb_ppp,DI_ftype_DIDI,2)
9608 // tag : S6_vtrunohb_ppp
9609 def int_hexagon_S6_vtrunohb_ppp :
9610 Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">;
9611
9612 //
9613 // BUILTIN_INFO(HEXAGON.S6_vsplatrbp,DI_ftype_SI,1)
9614 // tag : S6_vsplatrbp
9615 def int_hexagon_S6_vsplatrbp :
9616 Hexagon_LLii_Intrinsic<"HEXAGON_S6_vsplatrbp">;
9617
9618 //
9619 // BUILTIN_INFO(HEXAGON.V6_vlsrb,VI_ftype_VISI,2)
9620 // tag : V6_vlsrb
9621 def int_hexagon_V6_vlsrb :
9622 Hexagon_V62_v512v512i_Intrinsic<"HEXAGON_V6_vlsrb">;
9623
9624 //
9625 // BUILTIN_INFO(HEXAGON.V6_vlsrb_128B,VI_ftype_VISI,2)
9626 // tag : V6_vlsrb_128B
9627 def int_hexagon_V6_vlsrb_128B :
9628 Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrb_128B">;
9629
9630 //
9631 // BUILTIN_INFO(HEXAGON.V6_vasrwuhrndsat,VI_ftype_VIVISI,3)
9632 // tag : V6_vasrwuhrndsat
9633 def int_hexagon_V6_vasrwuhrndsat :
9634 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">;
9635
9636 //
9637 // BUILTIN_INFO(HEXAGON.V6_vasrwuhrndsat_128B,VI_ftype_VIVISI,3)
9638 // tag : V6_vasrwuhrndsat_128B
9639 def int_hexagon_V6_vasrwuhrndsat_128B :
9640 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">;
9641
9642 //
9643 // BUILTIN_INFO(HEXAGON.V6_vasruwuhrndsat,VI_ftype_VIVISI,3)
9644 // tag : V6_vasruwuhrndsat
9645 def int_hexagon_V6_vasruwuhrndsat :
9646 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">;
9647
9648 //
9649 // BUILTIN_INFO(HEXAGON.V6_vasruwuhrndsat_128B,VI_ftype_VIVISI,3)
9650 // tag : V6_vasruwuhrndsat_128B
9651 def int_hexagon_V6_vasruwuhrndsat_128B :
9652 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">;
9653
9654 //
9655 // BUILTIN_INFO(HEXAGON.V6_vasrhbsat,VI_ftype_VIVISI,3)
9656 // tag : V6_vasrhbsat
9657 def int_hexagon_V6_vasrhbsat :
9658 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhbsat">;
9659
9660 //
9661 // BUILTIN_INFO(HEXAGON.V6_vasrhbsat_128B,VI_ftype_VIVISI,3)
9662 // tag : V6_vasrhbsat_128B
9663 def int_hexagon_V6_vasrhbsat_128B :
9664 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">;
9665
9666 //
9667 // BUILTIN_INFO(HEXAGON.V6_vrounduwuh,VI_ftype_VIVI,2)
9668 // tag : V6_vrounduwuh
9669 def int_hexagon_V6_vrounduwuh :
9670 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vrounduwuh">;
9671
9672 //
9673 // BUILTIN_INFO(HEXAGON.V6_vrounduwuh_128B,VI_ftype_VIVI,2)
9674 // tag : V6_vrounduwuh_128B
9675 def int_hexagon_V6_vrounduwuh_128B :
9676 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">;
9677
9678 //
9679 // BUILTIN_INFO(HEXAGON.V6_vrounduhub,VI_ftype_VIVI,2)
9680 // tag : V6_vrounduhub
9681 def int_hexagon_V6_vrounduhub :
9682 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vrounduhub">;
9683
9684 //
9685 // BUILTIN_INFO(HEXAGON.V6_vrounduhub_128B,VI_ftype_VIVI,2)
9686 // tag : V6_vrounduhub_128B
9687 def int_hexagon_V6_vrounduhub_128B :
9688 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrounduhub_128B">;
9689
9690 //
9691 // BUILTIN_INFO(HEXAGON.V6_vadduwsat,VI_ftype_VIVI,2)
9692 // tag : V6_vadduwsat
9693 def int_hexagon_V6_vadduwsat :
9694 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vadduwsat">;
9695
9696 //
9697 // BUILTIN_INFO(HEXAGON.V6_vadduwsat_128B,VI_ftype_VIVI,2)
9698 // tag : V6_vadduwsat_128B
9699 def int_hexagon_V6_vadduwsat_128B :
9700 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduwsat_128B">;
9701
9702 //
9703 // BUILTIN_INFO(HEXAGON.V6_vadduwsat_dv,VD_ftype_VDVD,2)
9704 // tag : V6_vadduwsat_dv
9705 def int_hexagon_V6_vadduwsat_dv :
9706 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduwsat_dv">;
9707
9708 //
9709 // BUILTIN_INFO(HEXAGON.V6_vadduwsat_dv_128B,VD_ftype_VDVD,2)
9710 // tag : V6_vadduwsat_dv_128B
9711 def int_hexagon_V6_vadduwsat_dv_128B :
9712 Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">;
9713
9714 //
9715 // BUILTIN_INFO(HEXAGON.V6_vsubuwsat,VI_ftype_VIVI,2)
9716 // tag : V6_vsubuwsat
9717 def int_hexagon_V6_vsubuwsat :
9718 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubuwsat">;
9719
9720 //
9721 // BUILTIN_INFO(HEXAGON.V6_vsubuwsat_128B,VI_ftype_VIVI,2)
9722 // tag : V6_vsubuwsat_128B
9723 def int_hexagon_V6_vsubuwsat_128B :
9724 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">;
9725
9726 //
9727 // BUILTIN_INFO(HEXAGON.V6_vsubuwsat_dv,VD_ftype_VDVD,2)
9728 // tag : V6_vsubuwsat_dv
9729 def int_hexagon_V6_vsubuwsat_dv :
9730 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">;
9731
9732 //
9733 // BUILTIN_INFO(HEXAGON.V6_vsubuwsat_dv_128B,VD_ftype_VDVD,2)
9734 // tag : V6_vsubuwsat_dv_128B
9735 def int_hexagon_V6_vsubuwsat_dv_128B :
9736 Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">;
9737
9738 //
9739 // BUILTIN_INFO(HEXAGON.V6_vaddbsat,VI_ftype_VIVI,2)
9740 // tag : V6_vaddbsat
9741 def int_hexagon_V6_vaddbsat :
9742 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddbsat">;
9743
9744 //
9745 // BUILTIN_INFO(HEXAGON.V6_vaddbsat_128B,VI_ftype_VIVI,2)
9746 // tag : V6_vaddbsat_128B
9747 def int_hexagon_V6_vaddbsat_128B :
9748 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddbsat_128B">;
9749
9750 //
9751 // BUILTIN_INFO(HEXAGON.V6_vaddbsat_dv,VD_ftype_VDVD,2)
9752 // tag : V6_vaddbsat_dv
9753 def int_hexagon_V6_vaddbsat_dv :
9754 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddbsat_dv">;
9755
9756 //
9757 // BUILTIN_INFO(HEXAGON.V6_vaddbsat_dv_128B,VD_ftype_VDVD,2)
9758 // tag : V6_vaddbsat_dv_128B
9759 def int_hexagon_V6_vaddbsat_dv_128B :
9760 Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">;
9761
9762 //
9763 // BUILTIN_INFO(HEXAGON.V6_vsubbsat,VI_ftype_VIVI,2)
9764 // tag : V6_vsubbsat
9765 def int_hexagon_V6_vsubbsat :
9766 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubbsat">;
9767
9768 //
9769 // BUILTIN_INFO(HEXAGON.V6_vsubbsat_128B,VI_ftype_VIVI,2)
9770 // tag : V6_vsubbsat_128B
9771 def int_hexagon_V6_vsubbsat_128B :
9772 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubbsat_128B">;
9773
9774 //
9775 // BUILTIN_INFO(HEXAGON.V6_vsubbsat_dv,VD_ftype_VDVD,2)
9776 // tag : V6_vsubbsat_dv
9777 def int_hexagon_V6_vsubbsat_dv :
9778 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubbsat_dv">;
9779
9780 //
9781 // BUILTIN_INFO(HEXAGON.V6_vsubbsat_dv_128B,VD_ftype_VDVD,2)
9782 // tag : V6_vsubbsat_dv_128B
9783 def int_hexagon_V6_vsubbsat_dv_128B :
9784 Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">;
9785
9786 //
9787 // BUILTIN_INFO(HEXAGON.V6_vaddububb_sat,VI_ftype_VIVI,2)
9788 // tag : V6_vaddububb_sat
9789 def int_hexagon_V6_vaddububb_sat :
9790 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddububb_sat">;
9791
9792 //
9793 // BUILTIN_INFO(HEXAGON.V6_vaddububb_sat_128B,VI_ftype_VIVI,2)
9794 // tag : V6_vaddububb_sat_128B
9795 def int_hexagon_V6_vaddububb_sat_128B :
9796 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">;
9797
9798 //
9799 // BUILTIN_INFO(HEXAGON.V6_vsubububb_sat,VI_ftype_VIVI,2)
9800 // tag : V6_vsubububb_sat
9801 def int_hexagon_V6_vsubububb_sat :
9802 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubububb_sat">;
9803
9804 //
9805 // BUILTIN_INFO(HEXAGON.V6_vsubububb_sat_128B,VI_ftype_VIVI,2)
9806 // tag : V6_vsubububb_sat_128B
9807 def int_hexagon_V6_vsubububb_sat_128B :
9808 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">;
9809
9810 //
9811 // BUILTIN_INFO(HEXAGON.V6_vaddhw_acc,VD_ftype_VDVIVI,3)
9812 // tag : V6_vaddhw_acc
9813 def int_hexagon_V6_vaddhw_acc :
9814 Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vaddhw_acc">;
9815
9816 //
9817 // BUILTIN_INFO(HEXAGON.V6_vaddhw_acc_128B,VD_ftype_VDVIVI,3)
9818 // tag : V6_vaddhw_acc_128B
9819 def int_hexagon_V6_vaddhw_acc_128B :
9820 Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">;
9821
9822 //
9823 // BUILTIN_INFO(HEXAGON.V6_vadduhw_acc,VD_ftype_VDVIVI,3)
9824 // tag : V6_vadduhw_acc
9825 def int_hexagon_V6_vadduhw_acc :
9826 Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vadduhw_acc">;
9827
9828 //
9829 // BUILTIN_INFO(HEXAGON.V6_vadduhw_acc_128B,VD_ftype_VDVIVI,3)
9830 // tag : V6_vadduhw_acc_128B
9831 def int_hexagon_V6_vadduhw_acc_128B :
9832 Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">;
9833
9834 //
9835 // BUILTIN_INFO(HEXAGON.V6_vaddubh_acc,VD_ftype_VDVIVI,3)
9836 // tag : V6_vaddubh_acc
9837 def int_hexagon_V6_vaddubh_acc :
9838 Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vaddubh_acc">;
9839
9840 //
9841 // BUILTIN_INFO(HEXAGON.V6_vaddubh_acc_128B,VD_ftype_VDVIVI,3)
9842 // tag : V6_vaddubh_acc_128B
9843 def int_hexagon_V6_vaddubh_acc_128B :
9844 Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">;
9845
9846 //
9847 // BUILTIN_INFO(HEXAGON.V6_vmpyewuh_64,VD_ftype_VIVI,2)
9848 // tag : V6_vmpyewuh_64
9849 def int_hexagon_V6_vmpyewuh_64 :
9850 Hexagon_V62_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyewuh_64">;
9851
9852 //
9853 // BUILTIN_INFO(HEXAGON.V6_vmpyewuh_64_128B,VD_ftype_VIVI,2)
9854 // tag : V6_vmpyewuh_64_128B
9855 def int_hexagon_V6_vmpyewuh_64_128B :
9856 Hexagon_V62_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">;
9857
9858 //
9859 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_64_acc,VD_ftype_VDVIVI,3)
9860 // tag : V6_vmpyowh_64_acc
9861 def int_hexagon_V6_vmpyowh_64_acc :
9862 Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">;
9863
9864 //
9865 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_64_acc_128B,VD_ftype_VDVIVI,3)
9866 // tag : V6_vmpyowh_64_acc_128B
9867 def int_hexagon_V6_vmpyowh_64_acc_128B :
9868 Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">;
9869
9870 //
9871 // BUILTIN_INFO(HEXAGON.V6_vmpauhb,VD_ftype_VDSI,2)
9872 // tag : V6_vmpauhb
9873 def int_hexagon_V6_vmpauhb :
9874 Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpauhb">;
9875
9876 //
9877 // BUILTIN_INFO(HEXAGON.V6_vmpauhb_128B,VD_ftype_VDSI,2)
9878 // tag : V6_vmpauhb_128B
9879 def int_hexagon_V6_vmpauhb_128B :
9880 Hexagon_V62_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpauhb_128B">;
9881
9882 //
9883 // BUILTIN_INFO(HEXAGON.V6_vmpauhb_acc,VD_ftype_VDVDSI,3)
9884 // tag : V6_vmpauhb_acc
9885 def int_hexagon_V6_vmpauhb_acc :
9886 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpauhb_acc">;
9887
9888 //
9889 // BUILTIN_INFO(HEXAGON.V6_vmpauhb_acc_128B,VD_ftype_VDVDSI,3)
9890 // tag : V6_vmpauhb_acc_128B
9891 def int_hexagon_V6_vmpauhb_acc_128B :
9892 Hexagon_V62_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">;
9893
9894 //
9895 // BUILTIN_INFO(HEXAGON.V6_vmpyiwub,VI_ftype_VISI,2)
9896 // tag : V6_vmpyiwub
9897 def int_hexagon_V6_vmpyiwub :
9898 Hexagon_V62_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwub">;
9899
9900 //
9901 // BUILTIN_INFO(HEXAGON.V6_vmpyiwub_128B,VI_ftype_VISI,2)
9902 // tag : V6_vmpyiwub_128B
9903 def int_hexagon_V6_vmpyiwub_128B :
9904 Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">;
9905
9906 //
9907 // BUILTIN_INFO(HEXAGON.V6_vmpyiwub_acc,VI_ftype_VIVISI,3)
9908 // tag : V6_vmpyiwub_acc
9909 def int_hexagon_V6_vmpyiwub_acc :
9910 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">;
9911
9912 //
9913 // BUILTIN_INFO(HEXAGON.V6_vmpyiwub_acc_128B,VI_ftype_VIVISI,3)
9914 // tag : V6_vmpyiwub_acc_128B
9915 def int_hexagon_V6_vmpyiwub_acc_128B :
9916 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">;
9917
9918 //
9919 // BUILTIN_INFO(HEXAGON.V6_vandnqrt,VI_ftype_QVSI,2)
9920 // tag : V6_vandnqrt
9921 def int_hexagon_V6_vandnqrt :
9922 Hexagon_V62_v512v64ii_Intrinsic<"HEXAGON_V6_vandnqrt">;
9923
9924 //
9925 // BUILTIN_INFO(HEXAGON.V6_vandnqrt_128B,VI_ftype_QVSI,2)
9926 // tag : V6_vandnqrt_128B
9927 def int_hexagon_V6_vandnqrt_128B :
9928 Hexagon_V62_v1024v128ii_Intrinsic<"HEXAGON_V6_vandnqrt_128B">;
9929
9930 //
9931 // BUILTIN_INFO(HEXAGON.V6_vandnqrt_acc,VI_ftype_VIQVSI,3)
9932 // tag : V6_vandnqrt_acc
9933 def int_hexagon_V6_vandnqrt_acc :
9934 Hexagon_V62_v512v512v64ii_Intrinsic<"HEXAGON_V6_vandnqrt_acc">;
9935
9936 //
9937 // BUILTIN_INFO(HEXAGON.V6_vandnqrt_acc_128B,VI_ftype_VIQVSI,3)
9938 // tag : V6_vandnqrt_acc_128B
9939 def int_hexagon_V6_vandnqrt_acc_128B :
9940 Hexagon_V62_v1024v1024v128ii_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">;
9941
9942 //
9943 // BUILTIN_INFO(HEXAGON.V6_vandvqv,VI_ftype_QVVI,2)
9944 // tag : V6_vandvqv
9945 def int_hexagon_V6_vandvqv :
9946 Hexagon_V62_v512v64iv512_Intrinsic<"HEXAGON_V6_vandvqv">;
9947
9948 //
9949 // BUILTIN_INFO(HEXAGON.V6_vandvqv_128B,VI_ftype_QVVI,2)
9950 // tag : V6_vandvqv_128B
9951 def int_hexagon_V6_vandvqv_128B :
9952 Hexagon_V62_v1024v128iv1024_Intrinsic<"HEXAGON_V6_vandvqv_128B">;
9953
9954 //
9955 // BUILTIN_INFO(HEXAGON.V6_vandvnqv,VI_ftype_QVVI,2)
9956 // tag : V6_vandvnqv
9957 def int_hexagon_V6_vandvnqv :
9958 Hexagon_V62_v512v64iv512_Intrinsic<"HEXAGON_V6_vandvnqv">;
9959
9960 //
9961 // BUILTIN_INFO(HEXAGON.V6_vandvnqv_128B,VI_ftype_QVVI,2)
9962 // tag : V6_vandvnqv_128B
9963 def int_hexagon_V6_vandvnqv_128B :
9964 Hexagon_V62_v1024v128iv1024_Intrinsic<"HEXAGON_V6_vandvnqv_128B">;
9965
9966 //
9967 // BUILTIN_INFO(HEXAGON.V6_pred_scalar2v2,QV_ftype_SI,1)
9968 // tag : V6_pred_scalar2v2
9969 def int_hexagon_V6_pred_scalar2v2 :
9970 Hexagon_V62_v64ii_Intrinsic<"HEXAGON_V6_pred_scalar2v2">;
9971
9972 //
9973 // BUILTIN_INFO(HEXAGON.V6_pred_scalar2v2_128B,QV_ftype_SI,1)
9974 // tag : V6_pred_scalar2v2_128B
9975 def int_hexagon_V6_pred_scalar2v2_128B :
9976 Hexagon_V62_v128ii_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">;
9977
9978 //
9979 // BUILTIN_INFO(HEXAGON.V6_shuffeqw,QV_ftype_QVQV,2)
9980 // tag : V6_shuffeqw
9981 def int_hexagon_V6_shuffeqw :
9982 Hexagon_V62_v64iv64iv64i_Intrinsic<"HEXAGON_V6_shuffeqw">;
9983
9984 //
9985 // BUILTIN_INFO(HEXAGON.V6_shuffeqw_128B,QV_ftype_QVQV,2)
9986 // tag : V6_shuffeqw_128B
9987 def int_hexagon_V6_shuffeqw_128B :
9988 Hexagon_V62_v128iv128iv128i_Intrinsic<"HEXAGON_V6_shuffeqw_128B">;
9989
9990 //
9991 // BUILTIN_INFO(HEXAGON.V6_shuffeqh,QV_ftype_QVQV,2)
9992 // tag : V6_shuffeqh
9993 def int_hexagon_V6_shuffeqh :
9994 Hexagon_V62_v64iv64iv64i_Intrinsic<"HEXAGON_V6_shuffeqh">;
9995
9996 //
9997 // BUILTIN_INFO(HEXAGON.V6_shuffeqh_128B,QV_ftype_QVQV,2)
9998 // tag : V6_shuffeqh_128B
9999 def int_hexagon_V6_shuffeqh_128B :
10000 Hexagon_V62_v128iv128iv128i_Intrinsic<"HEXAGON_V6_shuffeqh_128B">;
10001
10002 //
10003 // BUILTIN_INFO(HEXAGON.V6_vmaxb,VI_ftype_VIVI,2)
10004 // tag : V6_vmaxb
10005 def int_hexagon_V6_vmaxb :
10006 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxb">;
10007
10008 //
10009 // BUILTIN_INFO(HEXAGON.V6_vmaxb_128B,VI_ftype_VIVI,2)
10010 // tag : V6_vmaxb_128B
10011 def int_hexagon_V6_vmaxb_128B :
10012 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxb_128B">;
10013
10014 //
10015 // BUILTIN_INFO(HEXAGON.V6_vminb,VI_ftype_VIVI,2)
10016 // tag : V6_vminb
10017 def int_hexagon_V6_vminb :
10018 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vminb">;
10019
10020 //
10021 // BUILTIN_INFO(HEXAGON.V6_vminb_128B,VI_ftype_VIVI,2)
10022 // tag : V6_vminb_128B
10023 def int_hexagon_V6_vminb_128B :
10024 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminb_128B">;
10025
10026 //
10027 // BUILTIN_INFO(HEXAGON.V6_vsatuwuh,VI_ftype_VIVI,2)
10028 // tag : V6_vsatuwuh
10029 def int_hexagon_V6_vsatuwuh :
10030 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsatuwuh">;
10031
10032 //
10033 // BUILTIN_INFO(HEXAGON.V6_vsatuwuh_128B,VI_ftype_VIVI,2)
10034 // tag : V6_vsatuwuh_128B
10035 def int_hexagon_V6_vsatuwuh_128B :
10036 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">;
10037
10038 //
10039 // BUILTIN_INFO(HEXAGON.V6_lvsplath,VI_ftype_SI,1)
10040 // tag : V6_lvsplath
10041 def int_hexagon_V6_lvsplath :
10042 Hexagon_V62_v512i_Intrinsic<"HEXAGON_V6_lvsplath">;
10043
10044 //
10045 // BUILTIN_INFO(HEXAGON.V6_lvsplath_128B,VI_ftype_SI,1)
10046 // tag : V6_lvsplath_128B
10047 def int_hexagon_V6_lvsplath_128B :
10048 Hexagon_V62_v1024i_Intrinsic<"HEXAGON_V6_lvsplath_128B">;
10049
10050 //
10051 // BUILTIN_INFO(HEXAGON.V6_lvsplatb,VI_ftype_SI,1)
10052 // tag : V6_lvsplatb
10053 def int_hexagon_V6_lvsplatb :
10054 Hexagon_V62_v512i_Intrinsic<"HEXAGON_V6_lvsplatb">;
10055
10056 //
10057 // BUILTIN_INFO(HEXAGON.V6_lvsplatb_128B,VI_ftype_SI,1)
10058 // tag : V6_lvsplatb_128B
10059 def int_hexagon_V6_lvsplatb_128B :
10060 Hexagon_V62_v1024i_Intrinsic<"HEXAGON_V6_lvsplatb_128B">;
10061
10062 //
10063 // BUILTIN_INFO(HEXAGON.V6_vaddclbw,VI_ftype_VIVI,2)
10064 // tag : V6_vaddclbw
10065 def int_hexagon_V6_vaddclbw :
10066 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddclbw">;
10067
10068 //
10069 // BUILTIN_INFO(HEXAGON.V6_vaddclbw_128B,VI_ftype_VIVI,2)
10070 // tag : V6_vaddclbw_128B
10071 def int_hexagon_V6_vaddclbw_128B :
10072 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddclbw_128B">;
10073
10074 //
10075 // BUILTIN_INFO(HEXAGON.V6_vaddclbh,VI_ftype_VIVI,2)
10076 // tag : V6_vaddclbh
10077 def int_hexagon_V6_vaddclbh :
10078 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddclbh">;
10079
10080 //
10081 // BUILTIN_INFO(HEXAGON.V6_vaddclbh_128B,VI_ftype_VIVI,2)
10082 // tag : V6_vaddclbh_128B
10083 def int_hexagon_V6_vaddclbh_128B :
10084 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddclbh_128B">;
10085
10086 //
10087 // BUILTIN_INFO(HEXAGON.V6_vlutvvbi,VI_ftype_VIVISI,3)
10088 // tag : V6_vlutvvbi
10089 def int_hexagon_V6_vlutvvbi :
10090 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvbi">;
10091
10092 //
10093 // BUILTIN_INFO(HEXAGON.V6_vlutvvbi_128B,VI_ftype_VIVISI,3)
10094 // tag : V6_vlutvvbi_128B
10095 def int_hexagon_V6_vlutvvbi_128B :
10096 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvbi_128B">;
10097
10098 //
10099 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracci,VI_ftype_VIVIVISI,4)
10100 // tag : V6_vlutvvb_oracci
10101 def int_hexagon_V6_vlutvvb_oracci :
10102 Hexagon_V62_v512v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_oracci">;
10103
10104 //
10105 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracci_128B,VI_ftype_VIVIVISI,4)
10106 // tag : V6_vlutvvb_oracci_128B
10107 def int_hexagon_V6_vlutvvb_oracci_128B :
10108 Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B">;
10109
10110 //
10111 // BUILTIN_INFO(HEXAGON.V6_vlutvwhi,VD_ftype_VIVISI,3)
10112 // tag : V6_vlutvwhi
10113 def int_hexagon_V6_vlutvwhi :
10114 Hexagon_V62_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwhi">;
10115
10116 //
10117 // BUILTIN_INFO(HEXAGON.V6_vlutvwhi_128B,VD_ftype_VIVISI,3)
10118 // tag : V6_vlutvwhi_128B
10119 def int_hexagon_V6_vlutvwhi_128B :
10120 Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwhi_128B">;
10121
10122 //
10123 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracci,VD_ftype_VDVIVISI,4)
10124 // tag : V6_vlutvwh_oracci
10125 def int_hexagon_V6_vlutvwh_oracci :
10126 Hexagon_V62_v1024v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_oracci">;
10127
10128 //
10129 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracci_128B,VD_ftype_VDVIVISI,4)
10130 // tag : V6_vlutvwh_oracci_128B
10131 def int_hexagon_V6_vlutvwh_oracci_128B :
10132 Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B">;
10133
10134 //
10135 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_nm,VI_ftype_VIVISI,3)
10136 // tag : V6_vlutvvb_nm
10137 def int_hexagon_V6_vlutvvb_nm :
10138 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_nm">;
10139
10140 //
10141 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_nm_128B,VI_ftype_VIVISI,3)
10142 // tag : V6_vlutvvb_nm_128B
10143 def int_hexagon_V6_vlutvvb_nm_128B :
10144 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">;
10145
10146 //
10147 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_nm,VD_ftype_VIVISI,3)
10148 // tag : V6_vlutvwh_nm
10149 def int_hexagon_V6_vlutvwh_nm :
10150 Hexagon_V62_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_nm">;
10151
10152 //
10153 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_nm_128B,VD_ftype_VIVISI,3)
10154 // tag : V6_vlutvwh_nm_128B
10155 def int_hexagon_V6_vlutvwh_nm_128B :
10156 Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;
10157
10158 //
10159 // BUILTIN_INFO(HEXAGON.V6_vaddcarry,VI_ftype_VIVIQV,3)
10160 // tag: V6_vaddcarry
10161 def int_hexagon_V6_vaddcarry :
10162 Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vaddcarry">;
10163
10164 //
10165 // BUILTIN_INFO(HEXAGON.V6_vaddcarry_128B,VI_ftype_VIVIQV,3)
10166 // tag: V6_vaddcarry_128B
10167 def int_hexagon_V6_vaddcarry_128B :
10168 Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vaddcarry_128B">;
10169
10170 //
10171 // BUILTIN_INFO(HEXAGON.V6_vsubcarry,VI_ftype_VIVIQV,3)
10172 // tag: V6_vsubcarry
10173 def int_hexagon_V6_vsubcarry :
10174 Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vsubcarry">;
10175
10176 //
10177 // BUILTIN_INFO(HEXAGON.V6_vsubcarry_128B,VI_ftype_VIVIQV,3)
10178 // tag: V6_vsubcarry_128B
10179 def int_hexagon_V6_vsubcarry_128B :
10180 Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vsubcarry_128B">;
10181
10182
10183 ///
10184 /// HexagonV65 intrinsics
10185 ///
10186
10187 //
10188 // Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix>
10189 // tag : A6_vcmpbeq_notany
10190 class Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix>
10191  : Hexagon_Intrinsic<GCCIntSuffix,
10192                           [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
10193                           [IntrNoMem]>;
10194
10195 //
10196 // Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix>
10197 // tag : V6_vrmpyub_rtt
10198 class Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix>
10199  : Hexagon_Intrinsic<GCCIntSuffix,
10200                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
10201                           [IntrNoMem]>;
10202
10203 //
10204 // Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix>
10205 // tag : V6_vrmpyub_rtt_128B
10206 class Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix>
10207  : Hexagon_Intrinsic<GCCIntSuffix,
10208                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
10209                           [IntrNoMem]>;
10210
10211 //
10212 // Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix>
10213 // tag : V6_vrmpyub_rtt_acc
10214 class Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix>
10215  : Hexagon_Intrinsic<GCCIntSuffix,
10216                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
10217                           [IntrNoMem]>;
10218
10219 //
10220 // Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix>
10221 // tag : V6_vrmpyub_rtt_acc_128B
10222 class Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix>
10223  : Hexagon_Intrinsic<GCCIntSuffix,
10224                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
10225                           [IntrNoMem]>;
10226
10227 //
10228 // Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix>
10229 // tag : V6_vasruwuhsat
10230 class Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix>
10231  : Hexagon_Intrinsic<GCCIntSuffix,
10232                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
10233                           [IntrNoMem]>;
10234
10235 //
10236 // Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
10237 // tag : V6_vasruwuhsat_128B
10238 class Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
10239  : Hexagon_Intrinsic<GCCIntSuffix,
10240                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
10241                           [IntrNoMem]>;
10242
10243 //
10244 // Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix>
10245 // tag : V6_vavguw
10246 class Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix>
10247  : Hexagon_Intrinsic<GCCIntSuffix,
10248                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
10249                           [IntrNoMem]>;
10250
10251 //
10252 // Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
10253 // tag : V6_vavguw_128B
10254 class Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
10255  : Hexagon_Intrinsic<GCCIntSuffix,
10256                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
10257                           [IntrNoMem]>;
10258
10259 //
10260 // Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix>
10261 // tag : V6_vabsb
10262 class Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix>
10263  : Hexagon_Intrinsic<GCCIntSuffix,
10264                           [llvm_v16i32_ty], [llvm_v16i32_ty],
10265                           [IntrNoMem]>;
10266
10267 //
10268 // Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix>
10269 // tag : V6_vabsb_128B
10270 class Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix>
10271  : Hexagon_Intrinsic<GCCIntSuffix,
10272                           [llvm_v32i32_ty], [llvm_v32i32_ty],
10273                           [IntrNoMem]>;
10274
10275 //
10276 // Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix>
10277 // tag : V6_vmpabuu
10278 class Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix>
10279  : Hexagon_Intrinsic<GCCIntSuffix,
10280                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
10281                           [IntrNoMem]>;
10282
10283 //
10284 // Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix>
10285 // tag : V6_vmpabuu_128B
10286 class Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix>
10287  : Hexagon_Intrinsic<GCCIntSuffix,
10288                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
10289                           [IntrNoMem]>;
10290
10291 //
10292 // Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
10293 // tag : V6_vmpabuu_acc_128B
10294 class Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
10295  : Hexagon_Intrinsic<GCCIntSuffix,
10296                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
10297                           [IntrNoMem]>;
10298
10299 //
10300 // Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
10301 // tag : V6_vmpyh_acc
10302 class Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
10303  : Hexagon_Intrinsic<GCCIntSuffix,
10304                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
10305                           [IntrNoMem]>;
10306
10307 //
10308 // Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
10309 // tag : V6_vmpyh_acc_128B
10310 class Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
10311  : Hexagon_Intrinsic<GCCIntSuffix,
10312                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
10313                           [IntrNoMem]>;
10314
10315 //
10316 // Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix>
10317 // tag : V6_vmpahhsat
10318 class Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix>
10319  : Hexagon_Intrinsic<GCCIntSuffix,
10320                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],
10321                           [IntrNoMem]>;
10322
10323 //
10324 // Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix>
10325 // tag : V6_vmpahhsat_128B
10326 class Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix>
10327  : Hexagon_Intrinsic<GCCIntSuffix,
10328                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],
10329                           [IntrNoMem]>;
10330
10331 //
10332 // Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix>
10333 // tag : V6_vlut4
10334 class Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix>
10335  : Hexagon_Intrinsic<GCCIntSuffix,
10336                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
10337                           [IntrNoMem]>;
10338
10339 //
10340 // Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix>
10341 // tag : V6_vlut4_128B
10342 class Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix>
10343  : Hexagon_Intrinsic<GCCIntSuffix,
10344                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
10345                           [IntrNoMem]>;
10346
10347 //
10348 // Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix>
10349 // tag : V6_vmpyuhe
10350 class Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix>
10351  : Hexagon_Intrinsic<GCCIntSuffix,
10352                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
10353                           [IntrNoMem]>;
10354
10355 //
10356 // Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix>
10357 // tag : V6_vprefixqb
10358 class Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix>
10359  : Hexagon_Intrinsic<GCCIntSuffix,
10360                           [llvm_v16i32_ty], [llvm_v512i1_ty],
10361                           [IntrNoMem]>;
10362
10363 //
10364 // Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix>
10365 // tag : V6_vprefixqb_128B
10366 class Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix>
10367  : Hexagon_Intrinsic<GCCIntSuffix,
10368                           [llvm_v32i32_ty], [llvm_v1024i1_ty],
10369                           [IntrNoMem]>;
10370
10371 //
10372 // BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany,QI_ftype_DIDI,2)
10373 // tag : A6_vcmpbeq_notany
10374 def int_hexagon_A6_vcmpbeq_notany :
10375 Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;
10376
10377 //
10378 // BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany_128B,QI_ftype_DIDI,2)
10379 // tag : A6_vcmpbeq_notany_128B
10380 def int_hexagon_A6_vcmpbeq_notany_128B :
10381 Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany_128B">;
10382
10383 //
10384 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt,VD_ftype_VIDI,2)
10385 // tag : V6_vrmpyub_rtt
10386 def int_hexagon_V6_vrmpyub_rtt :
10387 Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;
10388
10389 //
10390 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_128B,VD_ftype_VIDI,2)
10391 // tag : V6_vrmpyub_rtt_128B
10392 def int_hexagon_V6_vrmpyub_rtt_128B :
10393 Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;
10394
10395 //
10396 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc,VD_ftype_VDVIDI,3)
10397 // tag : V6_vrmpyub_rtt_acc
10398 def int_hexagon_V6_vrmpyub_rtt_acc :
10399 Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;
10400
10401 //
10402 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc_128B,VD_ftype_VDVIDI,3)
10403 // tag : V6_vrmpyub_rtt_acc_128B
10404 def int_hexagon_V6_vrmpyub_rtt_acc_128B :
10405 Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;
10406
10407 //
10408 // BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt,VD_ftype_VIDI,2)
10409 // tag : V6_vrmpybub_rtt
10410 def int_hexagon_V6_vrmpybub_rtt :
10411 Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;
10412
10413 //
10414 // BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_128B,VD_ftype_VIDI,2)
10415 // tag : V6_vrmpybub_rtt_128B
10416 def int_hexagon_V6_vrmpybub_rtt_128B :
10417 Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;
10418
10419 //
10420 // BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc,VD_ftype_VDVIDI,3)
10421 // tag : V6_vrmpybub_rtt_acc
10422 def int_hexagon_V6_vrmpybub_rtt_acc :
10423 Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;
10424
10425 //
10426 // BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc_128B,VD_ftype_VDVIDI,3)
10427 // tag : V6_vrmpybub_rtt_acc_128B
10428 def int_hexagon_V6_vrmpybub_rtt_acc_128B :
10429 Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;
10430
10431 //
10432 // BUILTIN_INFO(HEXAGON.V6_vasruwuhsat,VI_ftype_VIVISI,3)
10433 // tag : V6_vasruwuhsat
10434 def int_hexagon_V6_vasruwuhsat :
10435 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhsat">;
10436
10437 //
10438 // BUILTIN_INFO(HEXAGON.V6_vasruwuhsat_128B,VI_ftype_VIVISI,3)
10439 // tag : V6_vasruwuhsat_128B
10440 def int_hexagon_V6_vasruwuhsat_128B :
10441 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;
10442
10443 //
10444 // BUILTIN_INFO(HEXAGON.V6_vasruhubsat,VI_ftype_VIVISI,3)
10445 // tag : V6_vasruhubsat
10446 def int_hexagon_V6_vasruhubsat :
10447 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubsat">;
10448
10449 //
10450 // BUILTIN_INFO(HEXAGON.V6_vasruhubsat_128B,VI_ftype_VIVISI,3)
10451 // tag : V6_vasruhubsat_128B
10452 def int_hexagon_V6_vasruhubsat_128B :
10453 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;
10454
10455 //
10456 // BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat,VI_ftype_VIVISI,3)
10457 // tag : V6_vasruhubrndsat
10458 def int_hexagon_V6_vasruhubrndsat :
10459 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;
10460
10461 //
10462 // BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat_128B,VI_ftype_VIVISI,3)
10463 // tag : V6_vasruhubrndsat_128B
10464 def int_hexagon_V6_vasruhubrndsat_128B :
10465 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;
10466
10467 //
10468 // BUILTIN_INFO(HEXAGON.V6_vaslh_acc,VI_ftype_VIVISI,3)
10469 // tag : V6_vaslh_acc
10470 def int_hexagon_V6_vaslh_acc :
10471 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslh_acc">;
10472
10473 //
10474 // BUILTIN_INFO(HEXAGON.V6_vaslh_acc_128B,VI_ftype_VIVISI,3)
10475 // tag : V6_vaslh_acc_128B
10476 def int_hexagon_V6_vaslh_acc_128B :
10477 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;
10478
10479 //
10480 // BUILTIN_INFO(HEXAGON.V6_vasrh_acc,VI_ftype_VIVISI,3)
10481 // tag : V6_vasrh_acc
10482 def int_hexagon_V6_vasrh_acc :
10483 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrh_acc">;
10484
10485 //
10486 // BUILTIN_INFO(HEXAGON.V6_vasrh_acc_128B,VI_ftype_VIVISI,3)
10487 // tag : V6_vasrh_acc_128B
10488 def int_hexagon_V6_vasrh_acc_128B :
10489 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;
10490
10491 //
10492 // BUILTIN_INFO(HEXAGON.V6_vavguw,VI_ftype_VIVI,2)
10493 // tag : V6_vavguw
10494 def int_hexagon_V6_vavguw :
10495 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguw">;
10496
10497 //
10498 // BUILTIN_INFO(HEXAGON.V6_vavguw_128B,VI_ftype_VIVI,2)
10499 // tag : V6_vavguw_128B
10500 def int_hexagon_V6_vavguw_128B :
10501 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguw_128B">;
10502
10503 //
10504 // BUILTIN_INFO(HEXAGON.V6_vavguwrnd,VI_ftype_VIVI,2)
10505 // tag : V6_vavguwrnd
10506 def int_hexagon_V6_vavguwrnd :
10507 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguwrnd">;
10508
10509 //
10510 // BUILTIN_INFO(HEXAGON.V6_vavguwrnd_128B,VI_ftype_VIVI,2)
10511 // tag : V6_vavguwrnd_128B
10512 def int_hexagon_V6_vavguwrnd_128B :
10513 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;
10514
10515 //
10516 // BUILTIN_INFO(HEXAGON.V6_vavgb,VI_ftype_VIVI,2)
10517 // tag : V6_vavgb
10518 def int_hexagon_V6_vavgb :
10519 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgb">;
10520
10521 //
10522 // BUILTIN_INFO(HEXAGON.V6_vavgb_128B,VI_ftype_VIVI,2)
10523 // tag : V6_vavgb_128B
10524 def int_hexagon_V6_vavgb_128B :
10525 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgb_128B">;
10526
10527 //
10528 // BUILTIN_INFO(HEXAGON.V6_vavgbrnd,VI_ftype_VIVI,2)
10529 // tag : V6_vavgbrnd
10530 def int_hexagon_V6_vavgbrnd :
10531 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgbrnd">;
10532
10533 //
10534 // BUILTIN_INFO(HEXAGON.V6_vavgbrnd_128B,VI_ftype_VIVI,2)
10535 // tag : V6_vavgbrnd_128B
10536 def int_hexagon_V6_vavgbrnd_128B :
10537 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;
10538
10539 //
10540 // BUILTIN_INFO(HEXAGON.V6_vnavgb,VI_ftype_VIVI,2)
10541 // tag : V6_vnavgb
10542 def int_hexagon_V6_vnavgb :
10543 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgb">;
10544
10545 //
10546 // BUILTIN_INFO(HEXAGON.V6_vnavgb_128B,VI_ftype_VIVI,2)
10547 // tag : V6_vnavgb_128B
10548 def int_hexagon_V6_vnavgb_128B :
10549 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgb_128B">;
10550
10551 //
10552 // BUILTIN_INFO(HEXAGON.V6_vabsb,VI_ftype_VI,1)
10553 // tag : V6_vabsb
10554 def int_hexagon_V6_vabsb :
10555 Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb">;
10556
10557 //
10558 // BUILTIN_INFO(HEXAGON.V6_vabsb_128B,VI_ftype_VI,1)
10559 // tag : V6_vabsb_128B
10560 def int_hexagon_V6_vabsb_128B :
10561 Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_128B">;
10562
10563 //
10564 // BUILTIN_INFO(HEXAGON.V6_vabsb_sat,VI_ftype_VI,1)
10565 // tag : V6_vabsb_sat
10566 def int_hexagon_V6_vabsb_sat :
10567 Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb_sat">;
10568
10569 //
10570 // BUILTIN_INFO(HEXAGON.V6_vabsb_sat_128B,VI_ftype_VI,1)
10571 // tag : V6_vabsb_sat_128B
10572 def int_hexagon_V6_vabsb_sat_128B :
10573 Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;
10574
10575 //
10576 // BUILTIN_INFO(HEXAGON.V6_vmpabuu,VD_ftype_VDSI,2)
10577 // tag : V6_vmpabuu
10578 def int_hexagon_V6_vmpabuu :
10579 Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu">;
10580
10581 //
10582 // BUILTIN_INFO(HEXAGON.V6_vmpabuu_128B,VD_ftype_VDSI,2)
10583 // tag : V6_vmpabuu_128B
10584 def int_hexagon_V6_vmpabuu_128B :
10585 Hexagon_V65_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;
10586
10587 //
10588 // BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc,VD_ftype_VDVDSI,3)
10589 // tag : V6_vmpabuu_acc
10590 def int_hexagon_V6_vmpabuu_acc :
10591 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;
10592
10593 //
10594 // BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc_128B,VD_ftype_VDVDSI,3)
10595 // tag : V6_vmpabuu_acc_128B
10596 def int_hexagon_V6_vmpabuu_acc_128B :
10597 Hexagon_V65_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;
10598
10599 //
10600 // BUILTIN_INFO(HEXAGON.V6_vmpyh_acc,VD_ftype_VDVISI,3)
10601 // tag : V6_vmpyh_acc
10602 def int_hexagon_V6_vmpyh_acc :
10603 Hexagon_V65_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh_acc">;
10604
10605 //
10606 // BUILTIN_INFO(HEXAGON.V6_vmpyh_acc_128B,VD_ftype_VDVISI,3)
10607 // tag : V6_vmpyh_acc_128B
10608 def int_hexagon_V6_vmpyh_acc_128B :
10609 Hexagon_V65_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;
10610
10611 //
10612 // BUILTIN_INFO(HEXAGON.V6_vmpahhsat,VI_ftype_VIVIDI,3)
10613 // tag : V6_vmpahhsat
10614 def int_hexagon_V6_vmpahhsat :
10615 Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpahhsat">;
10616
10617 //
10618 // BUILTIN_INFO(HEXAGON.V6_vmpahhsat_128B,VI_ftype_VIVIDI,3)
10619 // tag : V6_vmpahhsat_128B
10620 def int_hexagon_V6_vmpahhsat_128B :
10621 Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;
10622
10623 //
10624 // BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat,VI_ftype_VIVIDI,3)
10625 // tag : V6_vmpauhuhsat
10626 def int_hexagon_V6_vmpauhuhsat :
10627 Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;
10628
10629 //
10630 // BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat_128B,VI_ftype_VIVIDI,3)
10631 // tag : V6_vmpauhuhsat_128B
10632 def int_hexagon_V6_vmpauhuhsat_128B :
10633 Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;
10634
10635 //
10636 // BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat,VI_ftype_VIVIDI,3)
10637 // tag : V6_vmpsuhuhsat
10638 def int_hexagon_V6_vmpsuhuhsat :
10639 Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;
10640
10641 //
10642 // BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat_128B,VI_ftype_VIVIDI,3)
10643 // tag : V6_vmpsuhuhsat_128B
10644 def int_hexagon_V6_vmpsuhuhsat_128B :
10645 Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;
10646
10647 //
10648 // BUILTIN_INFO(HEXAGON.V6_vlut4,VI_ftype_VIDI,2)
10649 // tag : V6_vlut4
10650 def int_hexagon_V6_vlut4 :
10651 Hexagon_V65_v512v512LLi_Intrinsic<"HEXAGON_V6_vlut4">;
10652
10653 //
10654 // BUILTIN_INFO(HEXAGON.V6_vlut4_128B,VI_ftype_VIDI,2)
10655 // tag : V6_vlut4_128B
10656 def int_hexagon_V6_vlut4_128B :
10657 Hexagon_V65_v1024v1024LLi_Intrinsic<"HEXAGON_V6_vlut4_128B">;
10658
10659 //
10660 // BUILTIN_INFO(HEXAGON.V6_vmpyuhe,VI_ftype_VISI,2)
10661 // tag : V6_vmpyuhe
10662 def int_hexagon_V6_vmpyuhe :
10663 Hexagon_V65_v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe">;
10664
10665 //
10666 // BUILTIN_INFO(HEXAGON.V6_vmpyuhe_128B,VI_ftype_VISI,2)
10667 // tag : V6_vmpyuhe_128B
10668 def int_hexagon_V6_vmpyuhe_128B :
10669 Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;
10670
10671 //
10672 // BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc,VI_ftype_VIVISI,3)
10673 // tag : V6_vmpyuhe_acc
10674 def int_hexagon_V6_vmpyuhe_acc :
10675 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;
10676
10677 //
10678 // BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc_128B,VI_ftype_VIVISI,3)
10679 // tag : V6_vmpyuhe_acc_128B
10680 def int_hexagon_V6_vmpyuhe_acc_128B :
10681 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;
10682
10683 //
10684 // BUILTIN_INFO(HEXAGON.V6_vprefixqb,VI_ftype_QV,1)
10685 // tag : V6_vprefixqb
10686 def int_hexagon_V6_vprefixqb :
10687 Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqb">;
10688
10689 //
10690 // BUILTIN_INFO(HEXAGON.V6_vprefixqb_128B,VI_ftype_QV,1)
10691 // tag : V6_vprefixqb_128B
10692 def int_hexagon_V6_vprefixqb_128B :
10693 Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;
10694
10695 //
10696 // BUILTIN_INFO(HEXAGON.V6_vprefixqh,VI_ftype_QV,1)
10697 // tag : V6_vprefixqh
10698 def int_hexagon_V6_vprefixqh :
10699 Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqh">;
10700
10701 //
10702 // BUILTIN_INFO(HEXAGON.V6_vprefixqh_128B,VI_ftype_QV,1)
10703 // tag : V6_vprefixqh_128B
10704 def int_hexagon_V6_vprefixqh_128B :
10705 Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;
10706
10707 //
10708 // BUILTIN_INFO(HEXAGON.V6_vprefixqw,VI_ftype_QV,1)
10709 // tag : V6_vprefixqw
10710 def int_hexagon_V6_vprefixqw :
10711 Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqw">;
10712
10713 //
10714 // BUILTIN_INFO(HEXAGON.V6_vprefixqw_128B,VI_ftype_QV,1)
10715 // tag : V6_vprefixqw_128B
10716 def int_hexagon_V6_vprefixqw_128B :
10717 Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;
10718
10719
10720 // The scatter/gather ones below will not be generated from iset.py. Make sure
10721 // you don't overwrite these.
10722 class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix>
10723  : Hexagon_Intrinsic<GCCIntSuffix,
10724                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
10725                                llvm_v16i32_ty],
10726                           [IntrArgMemOnly]>;
10727
10728 class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix>
10729  : Hexagon_Intrinsic<GCCIntSuffix,
10730                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
10731                                llvm_v32i32_ty],
10732                           [IntrArgMemOnly]>;
10733
10734 class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix>
10735  : Hexagon_Intrinsic<GCCIntSuffix,
10736                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
10737                                llvm_v64i32_ty],
10738                           [IntrArgMemOnly]>;
10739
10740 class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix>
10741  : Hexagon_Intrinsic<GCCIntSuffix,
10742                           [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
10743                                llvm_i32_ty,llvm_v16i32_ty],
10744                           [IntrArgMemOnly]>;
10745
10746 class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix>
10747  : Hexagon_Intrinsic<GCCIntSuffix,
10748                           [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
10749                                llvm_i32_ty,llvm_v32i32_ty],
10750                           [IntrArgMemOnly]>;
10751
10752 class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix>
10753  : Hexagon_Intrinsic<GCCIntSuffix,
10754                           [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
10755                                llvm_i32_ty,llvm_v32i32_ty],
10756                           [IntrArgMemOnly]>;
10757
10758 class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix>
10759  : Hexagon_Intrinsic<GCCIntSuffix,
10760                           [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
10761                                llvm_i32_ty,llvm_v64i32_ty],
10762                           [IntrArgMemOnly]>;
10763
10764 def int_hexagon_V6_vgathermw :
10765 Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;
10766
10767 def int_hexagon_V6_vgathermw_128B :
10768 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;
10769
10770 def int_hexagon_V6_vgathermh :
10771 Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;
10772
10773 def int_hexagon_V6_vgathermh_128B :
10774 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;
10775
10776 def int_hexagon_V6_vgathermhw :
10777 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;
10778
10779 def int_hexagon_V6_vgathermhw_128B :
10780 Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;
10781
10782 def int_hexagon_V6_vgathermwq :
10783 Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;
10784
10785 def int_hexagon_V6_vgathermwq_128B :
10786 Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;
10787
10788 def int_hexagon_V6_vgathermhq :
10789 Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;
10790
10791 def int_hexagon_V6_vgathermhq_128B :
10792 Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;
10793
10794 def int_hexagon_V6_vgathermhwq :
10795 Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;
10796
10797 def int_hexagon_V6_vgathermhwq_128B :
10798 Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;
10799
10800 class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix>
10801  : Hexagon_Intrinsic<GCCIntSuffix,
10802                           [], [llvm_i32_ty,llvm_i32_ty,
10803                                            llvm_v16i32_ty,llvm_v16i32_ty],
10804                           [IntrWriteMem]>;
10805
10806 class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix>
10807  : Hexagon_Intrinsic<GCCIntSuffix,
10808                           [], [llvm_i32_ty,llvm_i32_ty,
10809                                            llvm_v32i32_ty,llvm_v32i32_ty],
10810                           [IntrWriteMem]>;
10811
10812 class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix>
10813  : Hexagon_Intrinsic<GCCIntSuffix,
10814                           [], [llvm_v512i1_ty,llvm_i32_ty,
10815                                            llvm_i32_ty,llvm_v16i32_ty,
10816                                            llvm_v16i32_ty],
10817                           [IntrWriteMem]>;
10818
10819 class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix>
10820  : Hexagon_Intrinsic<GCCIntSuffix,
10821                           [], [llvm_v1024i1_ty,llvm_i32_ty,
10822                                            llvm_i32_ty,llvm_v32i32_ty,
10823                                            llvm_v32i32_ty],
10824                           [IntrWriteMem]>;
10825
10826 class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix>
10827  : Hexagon_Intrinsic<GCCIntSuffix,
10828                           [], [llvm_i32_ty,llvm_i32_ty,
10829                                            llvm_v32i32_ty,llvm_v16i32_ty],
10830                           [IntrWriteMem]>;
10831
10832 class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix>
10833  : Hexagon_Intrinsic<GCCIntSuffix,
10834                           [], [llvm_i32_ty,llvm_i32_ty,
10835                                            llvm_v64i32_ty,llvm_v32i32_ty],
10836                           [IntrWriteMem]>;
10837
10838 class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix>
10839  : Hexagon_Intrinsic<GCCIntSuffix,
10840                           [], [llvm_v512i1_ty,llvm_i32_ty,
10841                                            llvm_i32_ty,llvm_v32i32_ty,
10842                                            llvm_v16i32_ty],
10843                           [IntrWriteMem]>;
10844
10845 class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix>
10846  : Hexagon_Intrinsic<GCCIntSuffix,
10847                           [], [llvm_v1024i1_ty,llvm_i32_ty,
10848                                            llvm_i32_ty,llvm_v64i32_ty,
10849                                            llvm_v32i32_ty],
10850                           [IntrWriteMem]>;
10851
10852 class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix>
10853  : Hexagon_Intrinsic<GCCIntSuffix,
10854                           [llvm_v64i32_ty], [],
10855                           [IntrNoMem]>;
10856
10857 //
10858 // BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)
10859 // tag : V6_vscattermw
10860 def int_hexagon_V6_vscattermw :
10861 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;
10862
10863 //
10864 // BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)
10865 // tag : V6_vscattermw_128B
10866 def int_hexagon_V6_vscattermw_128B :
10867 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;
10868
10869 //
10870 // BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)
10871 // tag : V6_vscattermh
10872 def int_hexagon_V6_vscattermh :
10873 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;
10874
10875 //
10876 // BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)
10877 // tag : V6_vscattermh_128B
10878 def int_hexagon_V6_vscattermh_128B :
10879 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;
10880
10881 //
10882 // BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)
10883 // tag : V6_vscattermw_add
10884 def int_hexagon_V6_vscattermw_add :
10885 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;
10886
10887 //
10888 // BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)
10889 // tag : V6_vscattermw_add_128B
10890 def int_hexagon_V6_vscattermw_add_128B :
10891 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;
10892
10893 //
10894 // BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)
10895 // tag : V6_vscattermh_add
10896 def int_hexagon_V6_vscattermh_add :
10897 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;
10898
10899 //
10900 // BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)
10901 // tag : V6_vscattermh_add_128B
10902 def int_hexagon_V6_vscattermh_add_128B :
10903 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;
10904
10905 //
10906 // BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)
10907 // tag : V6_vscattermwq
10908 def int_hexagon_V6_vscattermwq :
10909 Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;
10910
10911 //
10912 // BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)
10913 // tag : V6_vscattermwq_128B
10914 def int_hexagon_V6_vscattermwq_128B :
10915 Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;
10916
10917 //
10918 // BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)
10919 // tag : V6_vscattermhq
10920 def int_hexagon_V6_vscattermhq :
10921 Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;
10922
10923 //
10924 // BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)
10925 // tag : V6_vscattermhq_128B
10926 def int_hexagon_V6_vscattermhq_128B :
10927 Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;
10928
10929 //
10930 // BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)
10931 // tag : V6_vscattermhw
10932 def int_hexagon_V6_vscattermhw :
10933 Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;
10934
10935 //
10936 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)
10937 // tag : V6_vscattermhw_128B
10938 def int_hexagon_V6_vscattermhw_128B :
10939 Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;
10940
10941 //
10942 // BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)
10943 // tag : V6_vscattermhwq
10944 def int_hexagon_V6_vscattermhwq :
10945 Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;
10946
10947 //
10948 // BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)
10949 // tag : V6_vscattermhwq_128B
10950 def int_hexagon_V6_vscattermhwq_128B :
10951 Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;
10952
10953 //
10954 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)
10955 // tag : V6_vscattermhw_add
10956 def int_hexagon_V6_vscattermhw_add :
10957 Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;
10958
10959 //
10960 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)
10961 // tag : V6_vscattermhw_add_128B
10962 def int_hexagon_V6_vscattermhw_add_128B :
10963 Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;
10964
10965 //
10966 // BUILTIN_INFO(HEXAGON.V6_vdd0,VD_ftype_,0)
10967 // tag : V6_vdd0
10968 def int_hexagon_V6_vdd0 :
10969 Hexagon_v1024_Intrinsic<"HEXAGON_V6_vdd0">;
10970
10971 //
10972 // BUILTIN_INFO(HEXAGON.V6_vdd0_128B,VD_ftype_,0)
10973 // tag : V6_vdd0_128B
10974 def int_hexagon_V6_vdd0_128B :
10975 Hexagon_V65_v2048_Intrinsic<"HEXAGON_V6_vdd0_128B">;