contrib/llvm/include/llvm/IR/IntrinsicsHexagon.td

   1 //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===//
   2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   3 // See https://llvm.org/LICENSE.txt for license information.
   4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   5 //
   6 //===----------------------------------------------------------------------===//
   7 //
   8 // This file defines all of the Hexagon-specific intrinsics.
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Definitions for all Hexagon intrinsics.
  14 //
  15 // All Hexagon intrinsics start with "llvm.hexagon.".
  16 let TargetPrefix = "hexagon" in {
  17   /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics.
  18   class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
  19                               list<LLVMType> param_types,
  20                               list<IntrinsicProperty> properties>
  21     : GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
  22       Intrinsic<ret_types, param_types, properties>;
  23
  24   /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon
  25   /// intrinsics.
  26   class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types,
  27                                  list<LLVMType> param_types,
  28                                  list<IntrinsicProperty> properties>
  29     : Intrinsic<ret_types, param_types, properties>;
  30 }
  31
  32 class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
  33   : Hexagon_Intrinsic<GCCIntSuffix,
  34                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
  35                            llvm_i32_ty],
  36                           [IntrArgMemOnly]>;
  37
  38 class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix>
  39   : Hexagon_Intrinsic<GCCIntSuffix,
  40                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
  41                            llvm_i32_ty],
  42                           [IntrWriteMem]>;
  43
  44 class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix>
  45   : Hexagon_Intrinsic<GCCIntSuffix,
  46                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
  47                            llvm_i32_ty],
  48                           [IntrWriteMem]>;
  49
  50 class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
  51   : Hexagon_Intrinsic<GCCIntSuffix,
  52                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
  53                            llvm_i32_ty, llvm_i32_ty],
  54                           [IntrArgMemOnly, ImmArg<3>]>;
  55
  56 class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix>
  57   : Hexagon_Intrinsic<GCCIntSuffix,
  58                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
  59                            llvm_i32_ty, llvm_i32_ty],
  60                           [IntrWriteMem, ImmArg<3>]>;
  61
  62 class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix>
  63   : Hexagon_Intrinsic<GCCIntSuffix,
  64                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
  65                            llvm_i32_ty, llvm_i32_ty],
  66                           [IntrWriteMem, ImmArg<3>]>;
  67
  68 //
  69 // BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
  70 //
  71 def int_hexagon_circ_ldd :
  72 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
  73 //
  74 // BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4)
  75 //
  76 def int_hexagon_circ_ldw :
  77 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">;
  78 //
  79 // BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4)
  80 //
  81 def int_hexagon_circ_ldh :
  82 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">;
  83 //
  84 // BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4)
  85 //
  86 def int_hexagon_circ_lduh :
  87 Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">;
  88 //
  89 // BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4)
  90 //
  91 def int_hexagon_circ_ldb :
  92 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">;
  93 //
  94 // BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4)
  95 //
  96 def int_hexagon_circ_ldub :
  97 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">;
  98
  99 //
 100 // BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4)
 101 //
 102 def int_hexagon_circ_std :
 103 Hexagon_mem_memdisisi_Intrinsic<"circ_std">;
 104 //
 105 // BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4)
 106 //
 107 def int_hexagon_circ_stw :
 108 Hexagon_mem_memsisisi_Intrinsic<"circ_stw">;
 109 //
 110 // BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4)
 111 //
 112 def int_hexagon_circ_sth :
 113 Hexagon_mem_memsisisi_Intrinsic<"circ_sth">;
 114 //
 115 // BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4)
 116 //
 117 def int_hexagon_circ_sthhi :
 118 Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">;
 119 //
 120 // BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4)
 121 //
 122 def int_hexagon_circ_stb :
 123 Hexagon_mem_memsisisi_Intrinsic<"circ_stb">;
 124
 125 //
 126 // BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1)
 127 //
 128 def int_hexagon_prefetch :
 129 Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>;
 130 def int_hexagon_Y2_dccleana :
 131 Hexagon_Intrinsic<"HEXAGON_Y2_dccleana", [], [llvm_ptr_ty], []>;
 132 def int_hexagon_Y2_dccleaninva :
 133 Hexagon_Intrinsic<"HEXAGON_Y2_dccleaninva", [], [llvm_ptr_ty], []>;
 134 def int_hexagon_Y2_dcinva :
 135 Hexagon_Intrinsic<"HEXAGON_Y2_dcinva", [], [llvm_ptr_ty], []>;
 136 def int_hexagon_Y2_dczeroa :
 137 Hexagon_Intrinsic<"HEXAGON_Y2_dczeroa", [], [llvm_ptr_ty],
 138       [IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects]>;
 139 def int_hexagon_Y4_l2fetch :
 140 Hexagon_Intrinsic<"HEXAGON_Y4_l2fetch", [], [llvm_ptr_ty, llvm_i32_ty], []>;
 141 def int_hexagon_Y5_l2fetch :
 142 Hexagon_Intrinsic<"HEXAGON_Y5_l2fetch", [], [llvm_ptr_ty, llvm_i64_ty], []>;
 143
 144 def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;
 145 def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
 146
 147 // Mark locked loads as read/write to prevent any accidental reordering.
 148 def int_hexagon_L2_loadw_locked :
 149 Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
 150       [IntrArgMemOnly, NoCapture<0>]>;
 151 def int_hexagon_L4_loadd_locked :
 152 Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
 153       [IntrArgMemOnly, NoCapture<0>]>;
 154
 155 def int_hexagon_S2_storew_locked :
 156 Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
 157       [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<0>]>;
 158 def int_hexagon_S4_stored_locked :
 159 Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
 160       [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<0>]>;
 161
 162 def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy",
 163     [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
 164     [IntrArgMemOnly, NoCapture<0>, NoCapture<1>, WriteOnly<0>, ReadOnly<1>]>;
 165
 166 def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset",
 167     [], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
 168     [IntrArgMemOnly, NoCapture<0>, WriteOnly<0>]>;
 169
 170 multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> {
 171   def NAME#_pci : Hexagon_NonGCC_Intrinsic<
 172     [ElTy, llvm_ptr_ty],
 173     [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty],
 174     [IntrArgMemOnly, NoCapture<3>]>;
 175   def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
 176     [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty],
 177     [IntrArgMemOnly, NoCapture<2>]>;
 178 }
 179
 180 defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 181 defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 182 defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 183 defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 184 defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 185 defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>;
 186
 187 multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> {
 188   def NAME#_pci : Hexagon_NonGCC_Intrinsic<
 189     [llvm_ptr_ty],
 190     [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
 191     [IntrArgMemOnly, NoCapture<4>]>;
 192   def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
 193     [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
 194     [IntrArgMemOnly, NoCapture<3>]>;
 195 }
 196
 197 defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
 198 defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
 199 defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
 200 defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
 201 defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>;
 202
 203 // The front-end emits the intrinsic call with only two arguments. The third
 204 // argument from the builtin is already used by front-end to write to memory
 205 // by generating a store.
 206 class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy>
 207  : Hexagon_NonGCC_Intrinsic<
 208     [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty],
 209     [IntrReadMem]>;
 210
 211 def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 212 def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 213 def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 214 def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 215 def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 216 def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>;
 217
 218 def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
 219 def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
 220 def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
 221 def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
 222 def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">;
 223
 224 //
 225 // Masked vector stores
 226 //
 227
 228 //
 229 // Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
 230 // tag: V6_vS32b_qpred_ai
 231 class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
 232  : Hexagon_Intrinsic<GCCIntSuffix,
 233                           [], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty],
 234                           [IntrArgMemOnly]>;
 235
 236 //
 237 // Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
 238 // tag: V6_vS32b_qpred_ai_128B
 239 class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
 240  : Hexagon_Intrinsic<GCCIntSuffix,
 241                           [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty],
 242                           [IntrArgMemOnly]>;
 243
 244 def int_hexagon_V6_vS32b_qpred_ai :
 245 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;
 246
 247 def int_hexagon_V6_vS32b_nqpred_ai :
 248 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;
 249
 250 def int_hexagon_V6_vS32b_nt_qpred_ai :
 251 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;
 252
 253 def int_hexagon_V6_vS32b_nt_nqpred_ai :
 254 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;
 255
 256 def int_hexagon_V6_vS32b_qpred_ai_128B :
 257 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;
 258
 259 def int_hexagon_V6_vS32b_nqpred_ai_128B :
 260 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;
 261
 262 def int_hexagon_V6_vS32b_nt_qpred_ai_128B :
 263 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;
 264
 265 def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :
 266 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;
 267
 268 def int_hexagon_V6_vmaskedstoreq :
 269 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;
 270
 271 def int_hexagon_V6_vmaskedstorenq :
 272 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">;
 273
 274 def int_hexagon_V6_vmaskedstorentq :
 275 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">;
 276
 277 def int_hexagon_V6_vmaskedstorentnq :
 278 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">;
 279
 280 def int_hexagon_V6_vmaskedstoreq_128B :
 281 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">;
 282
 283 def int_hexagon_V6_vmaskedstorenq_128B :
 284 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">;
 285
 286 def int_hexagon_V6_vmaskedstorentq_128B :
 287 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">;
 288
 289 def int_hexagon_V6_vmaskedstorentnq_128B :
 290 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">;
 291
 292 class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix>
 293  : Hexagon_Intrinsic<GCCIntSuffix,
 294                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
 295                                llvm_v16i32_ty],
 296                           [IntrArgMemOnly]>;
 297
 298 class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix>
 299  : Hexagon_Intrinsic<GCCIntSuffix,
 300                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
 301                                llvm_v32i32_ty],
 302                           [IntrArgMemOnly]>;
 303
 304 class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix>
 305  : Hexagon_Intrinsic<GCCIntSuffix,
 306                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
 307                                llvm_v64i32_ty],
 308                           [IntrArgMemOnly]>;
 309
 310 class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix>
 311  : Hexagon_Intrinsic<GCCIntSuffix,
 312                           [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
 313                                llvm_i32_ty,llvm_v16i32_ty],
 314                           [IntrArgMemOnly]>;
 315
 316 class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix>
 317  : Hexagon_Intrinsic<GCCIntSuffix,
 318                           [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
 319                                llvm_i32_ty,llvm_v32i32_ty],
 320                           [IntrArgMemOnly]>;
 321
 322 class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix>
 323  : Hexagon_Intrinsic<GCCIntSuffix,
 324                           [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
 325                                llvm_i32_ty,llvm_v32i32_ty],
 326                           [IntrArgMemOnly]>;
 327
 328 class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix>
 329  : Hexagon_Intrinsic<GCCIntSuffix,
 330                           [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
 331                                llvm_i32_ty,llvm_v64i32_ty],
 332                           [IntrArgMemOnly]>;
 333
 334 def int_hexagon_V6_vgathermw :
 335 Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;
 336
 337 def int_hexagon_V6_vgathermw_128B :
 338 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;
 339
 340 def int_hexagon_V6_vgathermh :
 341 Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;
 342
 343 def int_hexagon_V6_vgathermh_128B :
 344 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;
 345
 346 def int_hexagon_V6_vgathermhw :
 347 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;
 348
 349 def int_hexagon_V6_vgathermhw_128B :
 350 Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;
 351
 352 def int_hexagon_V6_vgathermwq :
 353 Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;
 354
 355 def int_hexagon_V6_vgathermwq_128B :
 356 Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;
 357
 358 def int_hexagon_V6_vgathermhq :
 359 Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;
 360
 361 def int_hexagon_V6_vgathermhq_128B :
 362 Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;
 363
 364 def int_hexagon_V6_vgathermhwq :
 365 Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;
 366
 367 def int_hexagon_V6_vgathermhwq_128B :
 368 Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;
 369
 370 class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix>
 371  : Hexagon_Intrinsic<GCCIntSuffix,
 372                           [], [llvm_i32_ty,llvm_i32_ty,
 373                                            llvm_v16i32_ty,llvm_v16i32_ty],
 374                           [IntrWriteMem]>;
 375
 376 class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix>
 377  : Hexagon_Intrinsic<GCCIntSuffix,
 378                           [], [llvm_i32_ty,llvm_i32_ty,
 379                                            llvm_v32i32_ty,llvm_v32i32_ty],
 380                           [IntrWriteMem]>;
 381
 382 class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix>
 383  : Hexagon_Intrinsic<GCCIntSuffix,
 384                           [], [llvm_v512i1_ty,llvm_i32_ty,
 385                                            llvm_i32_ty,llvm_v16i32_ty,
 386                                            llvm_v16i32_ty],
 387                           [IntrWriteMem]>;
 388
 389 class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix>
 390  : Hexagon_Intrinsic<GCCIntSuffix,
 391                           [], [llvm_v1024i1_ty,llvm_i32_ty,
 392                                            llvm_i32_ty,llvm_v32i32_ty,
 393                                            llvm_v32i32_ty],
 394                           [IntrWriteMem]>;
 395
 396 class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix>
 397  : Hexagon_Intrinsic<GCCIntSuffix,
 398                           [], [llvm_i32_ty,llvm_i32_ty,
 399                                            llvm_v32i32_ty,llvm_v16i32_ty],
 400                           [IntrWriteMem]>;
 401
 402 class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix>
 403  : Hexagon_Intrinsic<GCCIntSuffix,
 404                           [], [llvm_i32_ty,llvm_i32_ty,
 405                                            llvm_v64i32_ty,llvm_v32i32_ty],
 406                           [IntrWriteMem]>;
 407
 408 class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix>
 409  : Hexagon_Intrinsic<GCCIntSuffix,
 410                           [], [llvm_v512i1_ty,llvm_i32_ty,
 411                                            llvm_i32_ty,llvm_v32i32_ty,
 412                                            llvm_v16i32_ty],
 413                           [IntrWriteMem]>;
 414
 415 class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix>
 416  : Hexagon_Intrinsic<GCCIntSuffix,
 417                           [], [llvm_v1024i1_ty,llvm_i32_ty,
 418                                            llvm_i32_ty,llvm_v64i32_ty,
 419                                            llvm_v32i32_ty],
 420                           [IntrWriteMem]>;
 421
 422 class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix>
 423  : Hexagon_Intrinsic<GCCIntSuffix,
 424                           [llvm_v64i32_ty], [],
 425                           [IntrNoMem]>;
 426
 427 //
 428 // BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)
 429 // tag : V6_vscattermw
 430 def int_hexagon_V6_vscattermw :
 431 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;
 432
 433 //
 434 // BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)
 435 // tag : V6_vscattermw_128B
 436 def int_hexagon_V6_vscattermw_128B :
 437 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;
 438
 439 //
 440 // BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)
 441 // tag : V6_vscattermh
 442 def int_hexagon_V6_vscattermh :
 443 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;
 444
 445 //
 446 // BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)
 447 // tag : V6_vscattermh_128B
 448 def int_hexagon_V6_vscattermh_128B :
 449 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;
 450
 451 //
 452 // BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)
 453 // tag : V6_vscattermw_add
 454 def int_hexagon_V6_vscattermw_add :
 455 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;
 456
 457 //
 458 // BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)
 459 // tag : V6_vscattermw_add_128B
 460 def int_hexagon_V6_vscattermw_add_128B :
 461 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;
 462
 463 //
 464 // BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)
 465 // tag : V6_vscattermh_add
 466 def int_hexagon_V6_vscattermh_add :
 467 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;
 468
 469 //
 470 // BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)
 471 // tag : V6_vscattermh_add_128B
 472 def int_hexagon_V6_vscattermh_add_128B :
 473 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;
 474
 475 //
 476 // BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)
 477 // tag : V6_vscattermwq
 478 def int_hexagon_V6_vscattermwq :
 479 Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;
 480
 481 //
 482 // BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)
 483 // tag : V6_vscattermwq_128B
 484 def int_hexagon_V6_vscattermwq_128B :
 485 Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;
 486
 487 //
 488 // BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)
 489 // tag : V6_vscattermhq
 490 def int_hexagon_V6_vscattermhq :
 491 Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;
 492
 493 //
 494 // BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)
 495 // tag : V6_vscattermhq_128B
 496 def int_hexagon_V6_vscattermhq_128B :
 497 Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;
 498
 499 //
 500 // BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)
 501 // tag : V6_vscattermhw
 502 def int_hexagon_V6_vscattermhw :
 503 Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;
 504
 505 //
 506 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)
 507 // tag : V6_vscattermhw_128B
 508 def int_hexagon_V6_vscattermhw_128B :
 509 Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;
 510
 511 //
 512 // BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)
 513 // tag : V6_vscattermhwq
 514 def int_hexagon_V6_vscattermhwq :
 515 Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;
 516
 517 //
 518 // BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)
 519 // tag : V6_vscattermhwq_128B
 520 def int_hexagon_V6_vscattermhwq_128B :
 521 Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;
 522
 523 //
 524 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)
 525 // tag : V6_vscattermhw_add
 526 def int_hexagon_V6_vscattermhw_add :
 527 Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;
 528
 529 //
 530 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)
 531 // tag : V6_vscattermhw_add_128B
 532 def int_hexagon_V6_vscattermhw_add_128B :
 533 Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;
 534
 535 // Auto-generated intrinsics
 536
 537 // tag : S2_vsatwh
 538 class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix>
 539   : Hexagon_Intrinsic<GCCIntSuffix,
 540        [llvm_i32_ty], [llvm_i64_ty],
 541        [IntrNoMem]>;
 542
 543 // tag : V6_vrmpybusv
 544 class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix>
 545   : Hexagon_Intrinsic<GCCIntSuffix,
 546        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
 547        [IntrNoMem]>;
 548
 549 // tag : V6_vrmpybusv
 550 class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix>
 551   : Hexagon_Intrinsic<GCCIntSuffix,
 552        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
 553        [IntrNoMem]>;
 554
 555 // tag : V6_vaslw_acc
 556 class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
 557                                                list<IntrinsicProperty> intr_properties = []>
 558   : Hexagon_Intrinsic<GCCIntSuffix,
 559        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
 560        !listconcat([IntrNoMem], intr_properties)>;
 561
 562 // tag : V6_vaslw_acc
 563 class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
 564                                                list<IntrinsicProperty> intr_properties = []>
 565   : Hexagon_Intrinsic<GCCIntSuffix,
 566        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
 567        !listconcat([IntrNoMem], intr_properties)>;
 568
 569 // tag : V6_vmux
 570 class Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
 571   : Hexagon_Intrinsic<GCCIntSuffix,
 572        [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
 573        [IntrNoMem]>;
 574
 575 // tag : V6_vmux
 576 class Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
 577   : Hexagon_Intrinsic<GCCIntSuffix,
 578        [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
 579        [IntrNoMem]>;
 580
 581 // tag : S2_tableidxd_goodsyntax
 582 class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix>
 583   : Hexagon_Intrinsic<GCCIntSuffix,
 584        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
 585        [IntrNoMem, ImmArg<2>, ImmArg<3>]>;
 586
 587 // tag : V6_vandnqrt_acc
 588 class Hexagon_v16i32_v16i32v512i1i32_Intrinsic<string GCCIntSuffix>
 589   : Hexagon_Intrinsic<GCCIntSuffix,
 590        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],
 591        [IntrNoMem]>;
 592
 593 // tag : V6_vandnqrt_acc
 594 class Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<string GCCIntSuffix>
 595   : Hexagon_Intrinsic<GCCIntSuffix,
 596        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],
 597        [IntrNoMem]>;
 598
 599 // tag : V6_vrmpybusi
 600 class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix,
 601       list<IntrinsicProperty> intr_properties = []>
 602   : Hexagon_Intrinsic<GCCIntSuffix,
 603        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
 604        !listconcat([IntrNoMem], intr_properties)>;
 605
 606 // tag : V6_vrmpybusi
 607 class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix,
 608                                             list<IntrinsicProperty> intr_properties = []>
 609   : Hexagon_Intrinsic<GCCIntSuffix,
 610        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
 611        !listconcat([IntrNoMem], intr_properties)>;
 612
 613 // tag : V6_vsubb_dv
 614 class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
 615   : Hexagon_Intrinsic<GCCIntSuffix,
 616        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
 617        !listconcat([IntrNoMem], intr_properties)>;
 618
 619 // tag : M2_mpysu_up
 620 class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix,
 621                                    list<IntrinsicProperty> intr_properties = []>
 622   : Hexagon_Intrinsic<GCCIntSuffix,
 623        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],
 624        !listconcat([IntrNoMem], intr_properties)>;
 625
 626 // tag : M2_mpyud_acc_ll_s0
 627 class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
 628   : Hexagon_Intrinsic<GCCIntSuffix,
 629        [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
 630        !listconcat([IntrNoMem], intr_properties)>;
 631
 632 // tag : S2_lsr_i_r_nac
 633 class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix,
 634                                              list<IntrinsicProperty> intr_properties = []>
 635   : Hexagon_Intrinsic<GCCIntSuffix,
 636        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
 637        !listconcat([IntrNoMem], intr_properties)>;
 638
 639 // tag : M2_cmpysc_s0
 640 class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
 641   : Hexagon_Intrinsic<GCCIntSuffix,
 642        [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty],
 643        !listconcat([IntrNoMem], intr_properties)>;
 644
 645 // tag : V6_lo
 646 class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
 647   : Hexagon_Intrinsic<GCCIntSuffix,
 648        [llvm_v16i32_ty], [llvm_v32i32_ty],
 649        !listconcat([IntrNoMem], intr_properties)>;
 650
 651 // tag : V6_lo
 652 class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
 653   : Hexagon_Intrinsic<GCCIntSuffix,
 654        [llvm_v32i32_ty], [llvm_v64i32_ty],
 655        !listconcat([IntrNoMem], intr_properties)>;
 656
 657 // tag : S2_shuffoh
 658 class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix>
 659   : Hexagon_Intrinsic<GCCIntSuffix,
 660        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],
 661        [IntrNoMem]>;
 662
 663 // tag : F2_sfmax
 664 class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix>
 665   : Hexagon_Intrinsic<GCCIntSuffix,
 666        [llvm_float_ty], [llvm_float_ty,llvm_float_ty],
 667        [IntrNoMem, Throws]>;
 668
 669 // tag : A2_vabswsat
 670 class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix>
 671   : Hexagon_Intrinsic<GCCIntSuffix,
 672        [llvm_i64_ty], [llvm_i64_ty],
 673        [IntrNoMem]>;
 674
 675 // tag :
 676 class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix>
 677   : Hexagon_Intrinsic<GCCIntSuffix,
 678        [llvm_v32i32_ty], [llvm_v32i32_ty],
 679        [IntrNoMem]>;
 680
 681 // tag : V6_ldnp0
 682 class Hexagon_v16i32_i32i32_Intrinsic<string GCCIntSuffix>
 683   : Hexagon_Intrinsic<GCCIntSuffix,
 684        [llvm_v16i32_ty], [llvm_i32_ty,llvm_i32_ty],
 685        [IntrNoMem]>;
 686
 687 // tag : V6_ldnp0
 688 class Hexagon_v32i32_i32i32_Intrinsic<string GCCIntSuffix>
 689   : Hexagon_Intrinsic<GCCIntSuffix,
 690        [llvm_v32i32_ty], [llvm_i32_ty,llvm_i32_ty],
 691        [IntrNoMem]>;
 692
 693 // tag : V6_vdmpyhb
 694 class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix>
 695   : Hexagon_Intrinsic<GCCIntSuffix,
 696        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
 697        [IntrNoMem]>;
 698
 699 // tag : V6_vdmpyhb
 700 class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix>
 701   : Hexagon_Intrinsic<GCCIntSuffix,
 702        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
 703        [IntrNoMem]>;
 704
 705 // tag : A4_vcmphgti
 706 class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
 707   : Hexagon_Intrinsic<GCCIntSuffix,
 708        [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty],
 709        !listconcat([IntrNoMem], intr_properties)>;
 710
 711 // tag :
 712 class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix>
 713   : Hexagon_Intrinsic<GCCIntSuffix,
 714        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
 715        [IntrNoMem]>;
 716
 717 // tag : S6_rol_i_p_or
 718 class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix,
 719                                       list<IntrinsicProperty> intr_properties = []>
 720   : Hexagon_Intrinsic<GCCIntSuffix,
 721        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
 722        !listconcat([IntrNoMem], intr_properties)>;
 723
 724 // tag : V6_vgtuh_and
 725 class Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
 726   : Hexagon_Intrinsic<GCCIntSuffix,
 727        [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
 728        [IntrNoMem]>;
 729
 730 // tag : V6_vgtuh_and
 731 class Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
 732   : Hexagon_Intrinsic<GCCIntSuffix,
 733        [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
 734        [IntrNoMem]>;
 735
 736 // tag : A2_abssat
 737 class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix,
 738                                 list<IntrinsicProperty> intr_properties = []>
 739   : Hexagon_Intrinsic<GCCIntSuffix,
 740        [llvm_i32_ty], [llvm_i32_ty],
 741        !listconcat([IntrNoMem], intr_properties)>;
 742
 743 // tag : A2_vcmpwgtu
 744 class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix,
 745                                   list<IntrinsicProperty> intr_properties = []>
 746   : Hexagon_Intrinsic<GCCIntSuffix,
 747        [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
 748        !listconcat([IntrNoMem], intr_properties)>;
 749
 750 // tag : V6_vtmpybus_acc
 751 class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix>
 752   : Hexagon_Intrinsic<GCCIntSuffix,
 753        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
 754        [IntrNoMem]>;
 755
 756 // tag : F2_conv_df2uw_chop
 757 class Hexagon_i32_double_Intrinsic<string GCCIntSuffix>
 758   : Hexagon_Intrinsic<GCCIntSuffix,
 759        [llvm_i32_ty], [llvm_double_ty],
 760        [IntrNoMem]>;
 761
 762 // tag : V6_pred_or
 763 class Hexagon_v512i1_v512i1v512i1_Intrinsic<string GCCIntSuffix>
 764   : Hexagon_Intrinsic<GCCIntSuffix,
 765        [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],
 766        [IntrNoMem]>;
 767
 768 // tag : V6_pred_or
 769 class Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<string GCCIntSuffix>
 770   : Hexagon_Intrinsic<GCCIntSuffix,
 771        [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],
 772        [IntrNoMem]>;
 773
 774 // tag : S2_asr_i_p_rnd_goodsyntax
 775 class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix,
 776       list<IntrinsicProperty> intr_properties = []>
 777   : Hexagon_Intrinsic<GCCIntSuffix,
 778        [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],
 779        !listconcat([IntrNoMem], intr_properties)>;
 780
 781 // tag : F2_conv_w2df
 782 class Hexagon_double_i32_Intrinsic<string GCCIntSuffix,
 783       list<IntrinsicProperty> intr_properties = []>
 784   : Hexagon_Intrinsic<GCCIntSuffix,
 785        [llvm_double_ty], [llvm_i32_ty],
 786        !listconcat([IntrNoMem], intr_properties)>;
 787
 788 // tag : V6_vunpackuh
 789 class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix>
 790   : Hexagon_Intrinsic<GCCIntSuffix,
 791        [llvm_v32i32_ty], [llvm_v16i32_ty],
 792        [IntrNoMem]>;
 793
 794 // tag : V6_vunpackuh
 795 class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix>
 796   : Hexagon_Intrinsic<GCCIntSuffix,
 797        [llvm_v64i32_ty], [llvm_v32i32_ty],
 798        [IntrNoMem]>;
 799
 800 // tag : V6_vadduhw_acc
 801 class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix>
 802   : Hexagon_Intrinsic<GCCIntSuffix,
 803        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
 804        [IntrNoMem]>;
 805
 806 // tag : V6_vadduhw_acc
 807 class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix>
 808   : Hexagon_Intrinsic<GCCIntSuffix,
 809        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
 810        [IntrNoMem]>;
 811
 812 // tag : M2_vdmacs_s0
 813 class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix>
 814   : Hexagon_Intrinsic<GCCIntSuffix,
 815        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],
 816        [IntrNoMem]>;
 817
 818 // tag : V6_vrmpybub_rtt_acc
 819 class Hexagon_v32i32_v32i32v16i32i64_Intrinsic<string GCCIntSuffix>
 820   : Hexagon_Intrinsic<GCCIntSuffix,
 821        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
 822        [IntrNoMem]>;
 823
 824 // tag : V6_vrmpybub_rtt_acc
 825 class Hexagon_v64i32_v64i32v32i32i64_Intrinsic<string GCCIntSuffix>
 826   : Hexagon_Intrinsic<GCCIntSuffix,
 827        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
 828        [IntrNoMem]>;
 829
 830 // tag : V6_ldu0
 831 class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix>
 832   : Hexagon_Intrinsic<GCCIntSuffix,
 833        [llvm_v16i32_ty], [llvm_i32_ty],
 834        [IntrNoMem]>;
 835
 836 // tag : V6_ldu0
 837 class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix>
 838   : Hexagon_Intrinsic<GCCIntSuffix,
 839        [llvm_v32i32_ty], [llvm_i32_ty],
 840        [IntrNoMem]>;
 841
 842 // tag : S4_extract_rp
 843 class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix>
 844   : Hexagon_Intrinsic<GCCIntSuffix,
 845        [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty],
 846        [IntrNoMem]>;
 847
 848 // tag : V6_vdmpyhsuisat
 849 class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix>
 850   : Hexagon_Intrinsic<GCCIntSuffix,
 851        [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
 852        [IntrNoMem]>;
 853
 854 // tag : V6_vdmpyhsuisat
 855 class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix>
 856   : Hexagon_Intrinsic<GCCIntSuffix,
 857        [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
 858        [IntrNoMem]>;
 859
 860 // tag : A2_addsp
 861 class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix>
 862   : Hexagon_Intrinsic<GCCIntSuffix,
 863        [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty],
 864        [IntrNoMem]>;
 865
 866 // tag : V6_extractw
 867 class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix>
 868   : Hexagon_Intrinsic<GCCIntSuffix,
 869        [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
 870        [IntrNoMem]>;
 871
 872 // tag : V6_extractw
 873 class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix>
 874   : Hexagon_Intrinsic<GCCIntSuffix,
 875        [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
 876        [IntrNoMem]>;
 877
 878 // tag : V6_vlutvwhi
 879 class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
 880       list<IntrinsicProperty> intr_properties = []>
 881   : Hexagon_Intrinsic<GCCIntSuffix,
 882        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
 883        !listconcat([IntrNoMem], intr_properties)>;
 884
 885 // tag : V6_vlutvwhi
 886 class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
 887       list<IntrinsicProperty> intr_properties = []>
 888   : Hexagon_Intrinsic<GCCIntSuffix,
 889        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
 890        !listconcat([IntrNoMem], intr_properties)>;
 891
 892 // tag : V6_vgtuh
 893 class Hexagon_v512i1_v16i32v16i32_Intrinsic<string GCCIntSuffix>
 894   : Hexagon_Intrinsic<GCCIntSuffix,
 895        [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
 896        [IntrNoMem]>;
 897
 898 // tag : V6_vgtuh
 899 class Hexagon_v1024i1_v32i32v32i32_Intrinsic<string GCCIntSuffix>
 900   : Hexagon_Intrinsic<GCCIntSuffix,
 901        [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
 902        [IntrNoMem]>;
 903
 904 // tag : F2_sffma_lib
 905 class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix>
 906   : Hexagon_Intrinsic<GCCIntSuffix,
 907        [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty],
 908        [IntrNoMem, Throws]>;
 909
 910 // tag : F2_conv_ud2df
 911 class Hexagon_double_i64_Intrinsic<string GCCIntSuffix>
 912   : Hexagon_Intrinsic<GCCIntSuffix,
 913        [llvm_double_ty], [llvm_i64_ty],
 914        [IntrNoMem]>;
 915
 916 // tag : S2_vzxthw
 917 class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix,
 918       list<IntrinsicProperty> intr_properties = []>
 919   : Hexagon_Intrinsic<GCCIntSuffix,
 920        [llvm_i64_ty], [llvm_i32_ty],
 921        !listconcat([IntrNoMem], intr_properties)>;
 922
 923 // tag : V6_vtmpyhb
 924 class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix>
 925   : Hexagon_Intrinsic<GCCIntSuffix,
 926        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
 927        [IntrNoMem]>;
 928
 929 // tag : V6_vshufoeh
 930 class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix>
 931   : Hexagon_Intrinsic<GCCIntSuffix,
 932        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
 933        [IntrNoMem]>;
 934
 935 // tag : V6_vshufoeh
 936 class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix>
 937   : Hexagon_Intrinsic<GCCIntSuffix,
 938        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
 939        [IntrNoMem]>;
 940
 941 // tag : V6_vlut4
 942 class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix>
 943   : Hexagon_Intrinsic<GCCIntSuffix,
 944        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
 945        [IntrNoMem]>;
 946
 947 // tag : V6_vlut4
 948 class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix>
 949   : Hexagon_Intrinsic<GCCIntSuffix,
 950        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
 951        [IntrNoMem]>;
 952
 953 // tag :
 954 class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix>
 955   : Hexagon_Intrinsic<GCCIntSuffix,
 956        [llvm_v16i32_ty], [llvm_v16i32_ty],
 957        [IntrNoMem]>;
 958
 959 // tag : F2_conv_uw2sf
 960 class Hexagon_float_i32_Intrinsic<string GCCIntSuffix,
 961       list<IntrinsicProperty> intr_properties = []>
 962   : Hexagon_Intrinsic<GCCIntSuffix,
 963        [llvm_float_ty], [llvm_i32_ty],
 964        !listconcat([IntrNoMem], intr_properties)>;
 965
 966 // tag : V6_vswap
 967 class Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
 968   : Hexagon_Intrinsic<GCCIntSuffix,
 969        [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
 970        [IntrNoMem]>;
 971
 972 // tag : V6_vswap
 973 class Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
 974   : Hexagon_Intrinsic<GCCIntSuffix,
 975        [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
 976        [IntrNoMem]>;
 977
 978 // tag : V6_vandnqrt
 979 class Hexagon_v16i32_v512i1i32_Intrinsic<string GCCIntSuffix>
 980   : Hexagon_Intrinsic<GCCIntSuffix,
 981        [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],
 982        [IntrNoMem]>;
 983
 984 // tag : V6_vandnqrt
 985 class Hexagon_v32i32_v1024i1i32_Intrinsic<string GCCIntSuffix>
 986   : Hexagon_Intrinsic<GCCIntSuffix,
 987        [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],
 988        [IntrNoMem]>;
 989
 990 // tag : V6_vmpyub
 991 class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix>
 992   : Hexagon_Intrinsic<GCCIntSuffix,
 993        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
 994        [IntrNoMem]>;
 995
 996 // tag : A5_ACS
 997 class Hexagon_i64i32_i64i64i64_Intrinsic<string GCCIntSuffix>
 998   : Hexagon_Intrinsic<GCCIntSuffix,
 999        [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],
1000        [IntrNoMem]>;
1001
1002 // tag : V6_vunpackob
1003 class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix>
1004   : Hexagon_Intrinsic<GCCIntSuffix,
1005        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],
1006        [IntrNoMem]>;
1007
1008 // tag : V6_vunpackob
1009 class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix>
1010   : Hexagon_Intrinsic<GCCIntSuffix,
1011        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],
1012        [IntrNoMem]>;
1013
1014 // tag : V6_vmpyhsat_acc
1015 class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix>
1016   : Hexagon_Intrinsic<GCCIntSuffix,
1017        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
1018        [IntrNoMem]>;
1019
1020 // tag : V6_vmpyhsat_acc
1021 class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix>
1022   : Hexagon_Intrinsic<GCCIntSuffix,
1023        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1024        [IntrNoMem]>;
1025
1026 // tag : V6_vaddcarrysat
1027 class Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<string GCCIntSuffix>
1028   : Hexagon_Intrinsic<GCCIntSuffix,
1029        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
1030        [IntrNoMem]>;
1031
1032 // tag : V6_vaddcarrysat
1033 class Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<string GCCIntSuffix>
1034   : Hexagon_Intrinsic<GCCIntSuffix,
1035        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
1036        [IntrNoMem]>;
1037
1038 // tag : V6_vlutvvb_oracc
1039 class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
1040                                                      list<IntrinsicProperty> intr_properties = []>
1041   : Hexagon_Intrinsic<GCCIntSuffix,
1042        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
1043        !listconcat([IntrNoMem], intr_properties)>;
1044
1045 // tag : V6_vlutvvb_oracc
1046 class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
1047   : Hexagon_Intrinsic<GCCIntSuffix,
1048        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1049        !listconcat([IntrNoMem], intr_properties)>;
1050
1051 // tag : V6_vrmpybub_rtt
1052 class Hexagon_v32i32_v16i32i64_Intrinsic<string GCCIntSuffix>
1053   : Hexagon_Intrinsic<GCCIntSuffix,
1054        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
1055        [IntrNoMem]>;
1056
1057 // tag : V6_vrmpybub_rtt
1058 class Hexagon_v64i32_v32i32i64_Intrinsic<string GCCIntSuffix>
1059   : Hexagon_Intrinsic<GCCIntSuffix,
1060        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
1061        [IntrNoMem]>;
1062
1063 // tag : A4_addp_c
1064 class Hexagon_i64i32_i64i64i32_Intrinsic<string GCCIntSuffix>
1065   : Hexagon_Intrinsic<GCCIntSuffix,
1066        [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
1067        [IntrNoMem]>;
1068
1069 // tag : V6_vrsadubi_acc
1070 class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix,
1071                                                   list<IntrinsicProperty> intr_properties = []>
1072   : Hexagon_Intrinsic<GCCIntSuffix,
1073        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
1074        !listconcat([IntrNoMem], intr_properties)>;
1075
1076 // tag : V6_vrsadubi_acc
1077 class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix,
1078       list<IntrinsicProperty> intr_properties = []>
1079   : Hexagon_Intrinsic<GCCIntSuffix,
1080        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
1081        !listconcat([IntrNoMem], intr_properties)>;
1082
1083 // tag : F2_conv_df2sf
1084 class Hexagon_float_double_Intrinsic<string GCCIntSuffix>
1085   : Hexagon_Intrinsic<GCCIntSuffix,
1086        [llvm_float_ty], [llvm_double_ty],
1087        [IntrNoMem]>;
1088
1089 // tag : V6_vandvqv
1090 class Hexagon_v16i32_v512i1v16i32_Intrinsic<string GCCIntSuffix>
1091   : Hexagon_Intrinsic<GCCIntSuffix,
1092        [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty],
1093        [IntrNoMem]>;
1094
1095 // tag : V6_vandvqv
1096 class Hexagon_v32i32_v1024i1v32i32_Intrinsic<string GCCIntSuffix>
1097   : Hexagon_Intrinsic<GCCIntSuffix,
1098        [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty],
1099        [IntrNoMem]>;
1100
1101 // tag : C2_vmux
1102 class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix>
1103   : Hexagon_Intrinsic<GCCIntSuffix,
1104        [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty],
1105        [IntrNoMem]>;
1106
1107 // tag : F2_sfcmpeq
1108 class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix>
1109   : Hexagon_Intrinsic<GCCIntSuffix,
1110        [llvm_i32_ty], [llvm_float_ty,llvm_float_ty],
1111        [IntrNoMem, Throws]>;
1112
1113 // tag : V6_vmpahhsat
1114 class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix>
1115   : Hexagon_Intrinsic<GCCIntSuffix,
1116        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],
1117        [IntrNoMem]>;
1118
1119 // tag : V6_vmpahhsat
1120 class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix>
1121   : Hexagon_Intrinsic<GCCIntSuffix,
1122        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],
1123        [IntrNoMem]>;
1124
1125 // tag : V6_vandvrt
1126 class Hexagon_v512i1_v16i32i32_Intrinsic<string GCCIntSuffix>
1127   : Hexagon_Intrinsic<GCCIntSuffix,
1128        [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty],
1129        [IntrNoMem]>;
1130
1131 // tag : V6_vandvrt
1132 class Hexagon_v1024i1_v32i32i32_Intrinsic<string GCCIntSuffix>
1133   : Hexagon_Intrinsic<GCCIntSuffix,
1134        [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty],
1135        [IntrNoMem]>;
1136
1137 // tag : V6_vsubcarry
1138 class Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic
1139   : Hexagon_NonGCC_Intrinsic<
1140        [llvm_v16i32_ty,llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
1141        [IntrNoMem]>;
1142
1143 // tag : V6_vsubcarry
1144 class Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B
1145   : Hexagon_NonGCC_Intrinsic<
1146        [llvm_v32i32_ty,llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
1147        [IntrNoMem]>;
1148
1149 // tag : F2_sffixupr
1150 class Hexagon_float_float_Intrinsic<string GCCIntSuffix>
1151   : Hexagon_Intrinsic<GCCIntSuffix,
1152        [llvm_float_ty], [llvm_float_ty],
1153        [IntrNoMem, Throws]>;
1154
1155 // tag : V6_vandvrt_acc
1156 class Hexagon_v512i1_v512i1v16i32i32_Intrinsic<string GCCIntSuffix>
1157   : Hexagon_Intrinsic<GCCIntSuffix,
1158        [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty],
1159        [IntrNoMem]>;
1160
1161 // tag : V6_vandvrt_acc
1162 class Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<string GCCIntSuffix>
1163   : Hexagon_Intrinsic<GCCIntSuffix,
1164        [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty],
1165        [IntrNoMem]>;
1166
1167 // tag : F2_dfsub
1168 class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix>
1169   : Hexagon_Intrinsic<GCCIntSuffix,
1170        [llvm_double_ty], [llvm_double_ty,llvm_double_ty],
1171        [IntrNoMem, Throws]>;
1172
1173 // tag : V6_vmpyowh_sacc
1174 class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix>
1175   : Hexagon_Intrinsic<GCCIntSuffix,
1176        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
1177        [IntrNoMem]>;
1178
1179 // tag : V6_vmpyowh_sacc
1180 class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix>
1181   : Hexagon_Intrinsic<GCCIntSuffix,
1182        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
1183        [IntrNoMem]>;
1184
1185 // tag : S2_insertp
1186 class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix,
1187                                          list<IntrinsicProperty> intr_properties = []>
1188   : Hexagon_Intrinsic<GCCIntSuffix,
1189        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
1190        !listconcat([IntrNoMem], intr_properties)>;
1191
1192 // tag : F2_sfinvsqrta
1193 class Hexagon_floati32_float_Intrinsic<string GCCIntSuffix>
1194   : Hexagon_Intrinsic<GCCIntSuffix,
1195        [llvm_float_ty,llvm_i32_ty], [llvm_float_ty],
1196        [IntrNoMem, Throws]>;
1197
1198 // tag : V6_vtran2x2_map
1199 class Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
1200   : Hexagon_Intrinsic<GCCIntSuffix,
1201        [llvm_v16i32_ty,llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
1202        [IntrNoMem]>;
1203
1204 // tag : V6_vtran2x2_map
1205 class Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
1206   : Hexagon_Intrinsic<GCCIntSuffix,
1207        [llvm_v32i32_ty,llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1208        [IntrNoMem]>;
1209
1210 // tag : V6_vlutvwh_oracc
1211 class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
1212       list<IntrinsicProperty> intr_properties = []>
1213   : Hexagon_Intrinsic<GCCIntSuffix,
1214        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
1215        !listconcat([IntrNoMem], intr_properties)>;
1216
1217 // tag : V6_vlutvwh_oracc
1218 class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
1219       list<IntrinsicProperty> intr_properties = []>
1220   : Hexagon_Intrinsic<GCCIntSuffix,
1221        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1222        !listconcat([IntrNoMem], intr_properties)>;
1223
1224 // tag : F2_dfcmpge
1225 class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix>
1226   : Hexagon_Intrinsic<GCCIntSuffix,
1227        [llvm_i32_ty], [llvm_double_ty,llvm_double_ty],
1228        [IntrNoMem, Throws]>;
1229
1230 // tag : F2_conv_df2d_chop
1231 class Hexagon_i64_double_Intrinsic<string GCCIntSuffix>
1232   : Hexagon_Intrinsic<GCCIntSuffix,
1233        [llvm_i64_ty], [llvm_double_ty],
1234        [IntrNoMem]>;
1235
1236 // tag : F2_conv_sf2w
1237 class Hexagon_i32_float_Intrinsic<string GCCIntSuffix>
1238   : Hexagon_Intrinsic<GCCIntSuffix,
1239        [llvm_i32_ty], [llvm_float_ty],
1240        [IntrNoMem]>;
1241
1242 // tag : F2_sfclass
1243 class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix>
1244   : Hexagon_Intrinsic<GCCIntSuffix,
1245        [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty],
1246        [IntrNoMem, Throws, ImmArg<1>]>;
1247
1248 // tag : F2_conv_sf2ud_chop
1249 class Hexagon_i64_float_Intrinsic<string GCCIntSuffix>
1250   : Hexagon_Intrinsic<GCCIntSuffix,
1251        [llvm_i64_ty], [llvm_float_ty],
1252        [IntrNoMem]>;
1253
1254 // tag : V6_pred_scalar2v2
1255 class Hexagon_v512i1_i32_Intrinsic<string GCCIntSuffix>
1256   : Hexagon_Intrinsic<GCCIntSuffix,
1257        [llvm_v512i1_ty], [llvm_i32_ty],
1258        [IntrNoMem]>;
1259
1260 // tag : V6_pred_scalar2v2
1261 class Hexagon_v1024i1_i32_Intrinsic<string GCCIntSuffix>
1262   : Hexagon_Intrinsic<GCCIntSuffix,
1263        [llvm_v1024i1_ty], [llvm_i32_ty],
1264        [IntrNoMem]>;
1265
1266 // tag : F2_sfrecipa
1267 class Hexagon_floati32_floatfloat_Intrinsic<string GCCIntSuffix>
1268   : Hexagon_Intrinsic<GCCIntSuffix,
1269        [llvm_float_ty,llvm_i32_ty], [llvm_float_ty,llvm_float_ty],
1270        [IntrNoMem, Throws]>;
1271
1272 // tag : V6_vprefixqh
1273 class Hexagon_v16i32_v512i1_Intrinsic<string GCCIntSuffix>
1274   : Hexagon_Intrinsic<GCCIntSuffix,
1275        [llvm_v16i32_ty], [llvm_v512i1_ty],
1276        [IntrNoMem]>;
1277
1278 // tag : V6_vprefixqh
1279 class Hexagon_v32i32_v1024i1_Intrinsic<string GCCIntSuffix>
1280   : Hexagon_Intrinsic<GCCIntSuffix,
1281        [llvm_v32i32_ty], [llvm_v1024i1_ty],
1282        [IntrNoMem]>;
1283
1284 // tag : V6_vdmpyhisat_acc
1285 class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix>
1286   : Hexagon_Intrinsic<GCCIntSuffix,
1287        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1288        [IntrNoMem]>;
1289
1290 // tag : V6_vdmpyhisat_acc
1291 class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix>
1292   : Hexagon_Intrinsic<GCCIntSuffix,
1293        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty],
1294        [IntrNoMem]>;
1295
1296 // tag : F2_conv_ud2sf
1297 class Hexagon_float_i64_Intrinsic<string GCCIntSuffix>
1298   : Hexagon_Intrinsic<GCCIntSuffix,
1299        [llvm_float_ty], [llvm_i64_ty],
1300        [IntrNoMem]>;
1301
1302 // tag : F2_conv_sf2df
1303 class Hexagon_double_float_Intrinsic<string GCCIntSuffix>
1304   : Hexagon_Intrinsic<GCCIntSuffix,
1305        [llvm_double_ty], [llvm_float_ty],
1306        [IntrNoMem]>;
1307
1308 // tag : F2_sffma_sc
1309 class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix>
1310   : Hexagon_Intrinsic<GCCIntSuffix,
1311        [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty],
1312        [IntrNoMem, Throws]>;
1313
1314 // tag : F2_dfclass
1315 class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix,
1316                                       list<IntrinsicProperty> intr_properties = []>
1317   : Hexagon_Intrinsic<GCCIntSuffix,
1318        [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty],
1319        !listconcat([IntrNoMem, Throws], intr_properties)>;
1320
1321 // tag : V6_vd0
1322 class Hexagon_v16i32__Intrinsic<string GCCIntSuffix>
1323   : Hexagon_Intrinsic<GCCIntSuffix,
1324        [llvm_v16i32_ty], [],
1325        [IntrNoMem]>;
1326
1327 // tag : V6_vd0
1328 class Hexagon_v32i32__Intrinsic<string GCCIntSuffix>
1329   : Hexagon_Intrinsic<GCCIntSuffix,
1330        [llvm_v32i32_ty], [],
1331        [IntrNoMem]>;
1332
1333 // tag : V6_vdd0
1334 class Hexagon_v64i32__Intrinsic<string GCCIntSuffix>
1335   : Hexagon_Intrinsic<GCCIntSuffix,
1336        [llvm_v64i32_ty], [],
1337        [IntrNoMem]>;
1338
1339 // tag : S2_insert_rp
1340 class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix>
1341   : Hexagon_Intrinsic<GCCIntSuffix,
1342        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty],
1343        [IntrNoMem]>;
1344
1345 // tag : V6_vassignp
1346 class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix>
1347   : Hexagon_Intrinsic<GCCIntSuffix,
1348        [llvm_v64i32_ty], [llvm_v64i32_ty],
1349        [IntrNoMem]>;
1350
1351 // tag : A6_vminub_RdP
1352 class Hexagon_i64i32_i64i64_Intrinsic<string GCCIntSuffix>
1353   : Hexagon_Intrinsic<GCCIntSuffix,
1354        [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
1355        [IntrNoMem]>;
1356
1357 // tag : V6_pred_not
1358 class Hexagon_v512i1_v512i1_Intrinsic<string GCCIntSuffix>
1359   : Hexagon_Intrinsic<GCCIntSuffix,
1360        [llvm_v512i1_ty], [llvm_v512i1_ty],
1361        [IntrNoMem]>;
1362
1363 // tag : V6_pred_not
1364 class Hexagon_v1024i1_v1024i1_Intrinsic<string GCCIntSuffix>
1365   : Hexagon_Intrinsic<GCCIntSuffix,
1366        [llvm_v1024i1_ty], [llvm_v1024i1_ty],
1367        [IntrNoMem]>;
1368
1369 // V5 Scalar Instructions.
1370
1371 def int_hexagon_S2_asr_r_p_or :
1372 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">;
1373
1374 def int_hexagon_S2_vsatwh :
1375 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">;
1376
1377 def int_hexagon_S2_tableidxd_goodsyntax :
1378 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">;
1379
1380 def int_hexagon_M2_mpysu_up :
1381 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">;
1382
1383 def int_hexagon_M2_mpyud_acc_ll_s0 :
1384 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;
1385
1386 def int_hexagon_M2_mpyud_acc_ll_s1 :
1387 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;
1388
1389 def int_hexagon_M2_cmpysc_s1 :
1390 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">;
1391
1392 def int_hexagon_M2_cmpysc_s0 :
1393 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">;
1394
1395 def int_hexagon_M4_cmpyi_whc :
1396 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">;
1397
1398 def int_hexagon_M2_mpy_sat_rnd_lh_s1 :
1399 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;
1400
1401 def int_hexagon_M2_mpy_sat_rnd_lh_s0 :
1402 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;
1403
1404 def int_hexagon_S2_tableidxb_goodsyntax :
1405 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">;
1406
1407 def int_hexagon_S2_shuffoh :
1408 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">;
1409
1410 def int_hexagon_F2_sfmax :
1411 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax">;
1412
1413 def int_hexagon_A2_vabswsat :
1414 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">;
1415
1416 def int_hexagon_S2_asr_i_r :
1417 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [ImmArg<1>]>;
1418
1419 def int_hexagon_S2_asr_i_p :
1420 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [ImmArg<1>]>;
1421
1422 def int_hexagon_A4_combineri :
1423 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [ImmArg<1>]>;
1424
1425 def int_hexagon_M2_mpy_nac_sat_hl_s1 :
1426 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;
1427
1428 def int_hexagon_M4_vpmpyh_acc :
1429 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;
1430
1431 def int_hexagon_M2_vcmpy_s0_sat_i :
1432 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;
1433
1434 def int_hexagon_A2_notp :
1435 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">;
1436
1437 def int_hexagon_M2_mpy_hl_s1 :
1438 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;
1439
1440 def int_hexagon_M2_mpy_hl_s0 :
1441 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;
1442
1443 def int_hexagon_C4_or_and :
1444 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">;
1445
1446 def int_hexagon_M2_vmac2s_s0 :
1447 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">;
1448
1449 def int_hexagon_M2_vmac2s_s1 :
1450 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">;
1451
1452 def int_hexagon_S2_brevp :
1453 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">;
1454
1455 def int_hexagon_M4_pmpyw_acc :
1456 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">;
1457
1458 def int_hexagon_S2_cl1 :
1459 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">;
1460
1461 def int_hexagon_C4_cmplte :
1462 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">;
1463
1464 def int_hexagon_M2_mmpyul_s0 :
1465 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">;
1466
1467 def int_hexagon_A2_vaddws :
1468 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">;
1469
1470 def int_hexagon_A2_maxup :
1471 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">;
1472
1473 def int_hexagon_A4_vcmphgti :
1474 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [ImmArg<1>]>;
1475
1476 def int_hexagon_S2_interleave :
1477 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">;
1478
1479 def int_hexagon_M2_vrcmpyi_s0 :
1480 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;
1481
1482 def int_hexagon_A2_abssat :
1483 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">;
1484
1485 def int_hexagon_A2_vcmpwgtu :
1486 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">;
1487
1488 def int_hexagon_C2_cmpgtu :
1489 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">;
1490
1491 def int_hexagon_C2_cmpgtp :
1492 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">;
1493
1494 def int_hexagon_A4_cmphgtui :
1495 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [ImmArg<1>]>;
1496
1497 def int_hexagon_C2_cmpgti :
1498 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [ImmArg<1>]>;
1499
1500 def int_hexagon_M2_mpyi :
1501 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">;
1502
1503 def int_hexagon_F2_conv_df2uw_chop :
1504 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;
1505
1506 def int_hexagon_A4_cmpheq :
1507 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">;
1508
1509 def int_hexagon_M2_mpy_lh_s1 :
1510 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;
1511
1512 def int_hexagon_M2_mpy_lh_s0 :
1513 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;
1514
1515 def int_hexagon_S2_lsr_i_r_xacc :
1516 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [ImmArg<2>]>;
1517
1518 def int_hexagon_S2_vrcnegh :
1519 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">;
1520
1521 def int_hexagon_S2_extractup :
1522 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [ImmArg<1>, ImmArg<2>]>;
1523
1524 def int_hexagon_S2_asr_i_p_rnd_goodsyntax :
1525 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [ImmArg<1>]>;
1526
1527 def int_hexagon_S4_ntstbit_r :
1528 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">;
1529
1530 def int_hexagon_F2_conv_w2sf :
1531 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">;
1532
1533 def int_hexagon_C2_not :
1534 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">;
1535
1536 def int_hexagon_C2_tfrpr :
1537 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">;
1538
1539 def int_hexagon_M2_mpy_ll_s1 :
1540 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;
1541
1542 def int_hexagon_M2_mpy_ll_s0 :
1543 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;
1544
1545 def int_hexagon_A4_cmpbgt :
1546 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">;
1547
1548 def int_hexagon_S2_asr_r_r_and :
1549 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">;
1550
1551 def int_hexagon_A4_rcmpneqi :
1552 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [ImmArg<1>]>;
1553
1554 def int_hexagon_S2_asl_i_r_nac :
1555 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [ImmArg<2>]>;
1556
1557 def int_hexagon_M2_subacc :
1558 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">;
1559
1560 def int_hexagon_A2_orp :
1561 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">;
1562
1563 def int_hexagon_M2_mpyu_up :
1564 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">;
1565
1566 def int_hexagon_M2_mpy_acc_sat_lh_s1 :
1567 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;
1568
1569 def int_hexagon_S2_asr_i_vh :
1570 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [ImmArg<1>]>;
1571
1572 def int_hexagon_S2_asr_i_vw :
1573 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [ImmArg<1>]>;
1574
1575 def int_hexagon_A4_cmpbgtu :
1576 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">;
1577
1578 def int_hexagon_A4_vcmpbeq_any :
1579 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;
1580
1581 def int_hexagon_A4_cmpbgti :
1582 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [ImmArg<1>]>;
1583
1584 def int_hexagon_M2_mpyd_lh_s1 :
1585 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;
1586
1587 def int_hexagon_S2_asl_r_p_nac :
1588 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;
1589
1590 def int_hexagon_S2_lsr_i_r_nac :
1591 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [ImmArg<2>]>;
1592
1593 def int_hexagon_A2_addsp :
1594 Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">;
1595
1596 def int_hexagon_S4_vxsubaddw :
1597 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">;
1598
1599 def int_hexagon_A4_vcmpheqi :
1600 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [ImmArg<1>]>;
1601
1602 def int_hexagon_S4_vxsubaddh :
1603 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">;
1604
1605 def int_hexagon_M4_pmpyw :
1606 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">;
1607
1608 def int_hexagon_S2_vsathb :
1609 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">;
1610
1611 def int_hexagon_S2_asr_r_p_and :
1612 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">;
1613
1614 def int_hexagon_M2_mpyu_acc_lh_s1 :
1615 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;
1616
1617 def int_hexagon_M2_mpyu_acc_lh_s0 :
1618 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;
1619
1620 def int_hexagon_S2_lsl_r_p_acc :
1621 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;
1622
1623 def int_hexagon_A2_pxorf :
1624 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_A2_pxorf">;
1625
1626 def int_hexagon_C2_cmpgei :
1627 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [ImmArg<1>]>;
1628
1629 def int_hexagon_A2_vsubub :
1630 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">;
1631
1632 def int_hexagon_S2_asl_i_p :
1633 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [ImmArg<1>]>;
1634
1635 def int_hexagon_S2_asl_i_r :
1636 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [ImmArg<1>]>;
1637
1638 def int_hexagon_A4_vrminuw :
1639 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">;
1640
1641 def int_hexagon_F2_sffma :
1642 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma">;
1643
1644 def int_hexagon_A2_absp :
1645 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">;
1646
1647 def int_hexagon_C2_all8 :
1648 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">;
1649
1650 def int_hexagon_A4_vrminuh :
1651 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">;
1652
1653 def int_hexagon_F2_sffma_lib :
1654 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib">;
1655
1656 def int_hexagon_M4_vrmpyoh_s0 :
1657 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;
1658
1659 def int_hexagon_M4_vrmpyoh_s1 :
1660 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;
1661
1662 def int_hexagon_C2_bitsset :
1663 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">;
1664
1665 def int_hexagon_M2_mpysip :
1666 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysip", [ImmArg<1>]>;
1667
1668 def int_hexagon_M2_mpysin :
1669 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysin", [ImmArg<1>]>;
1670
1671 def int_hexagon_A4_boundscheck :
1672 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">;
1673
1674 def int_hexagon_M5_vrmpybuu :
1675 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">;
1676
1677 def int_hexagon_C4_fastcorner9 :
1678 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">;
1679
1680 def int_hexagon_M2_vrcmpys_s1rp :
1681 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;
1682
1683 def int_hexagon_A2_neg :
1684 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">;
1685
1686 def int_hexagon_A2_subsat :
1687 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">;
1688
1689 def int_hexagon_S2_asl_r_r :
1690 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">;
1691
1692 def int_hexagon_S2_asl_r_p :
1693 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">;
1694
1695 def int_hexagon_A2_vnavgh :
1696 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">;
1697
1698 def int_hexagon_M2_mpy_nac_sat_hl_s0 :
1699 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;
1700
1701 def int_hexagon_F2_conv_ud2df :
1702 Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">;
1703
1704 def int_hexagon_A2_vnavgw :
1705 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">;
1706
1707 def int_hexagon_S2_asl_i_r_acc :
1708 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [ImmArg<2>]>;
1709
1710 def int_hexagon_S4_subi_lsr_ri :
1711 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
1712
1713 def int_hexagon_S2_vzxthw :
1714 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">;
1715
1716 def int_hexagon_F2_sfadd :
1717 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd">;
1718
1719 def int_hexagon_A2_sub :
1720 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">;
1721
1722 def int_hexagon_M2_vmac2su_s0 :
1723 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">;
1724
1725 def int_hexagon_M2_vmac2su_s1 :
1726 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">;
1727
1728 def int_hexagon_M2_dpmpyss_s0 :
1729 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;
1730
1731 def int_hexagon_S2_insert :
1732 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert">;
1733
1734 def int_hexagon_S2_packhl :
1735 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">;
1736
1737 def int_hexagon_A4_vcmpwgti :
1738 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [ImmArg<1>]>;
1739
1740 def int_hexagon_A2_vavguwr :
1741 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">;
1742
1743 def int_hexagon_S2_asl_r_r_and :
1744 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">;
1745
1746 def int_hexagon_A2_svsubhs :
1747 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">;
1748
1749 def int_hexagon_A2_addh_l16_hl :
1750 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">;
1751
1752 def int_hexagon_M4_and_and :
1753 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">;
1754
1755 def int_hexagon_F2_conv_d2df :
1756 Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">;
1757
1758 def int_hexagon_C2_cmpgtui :
1759 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [ImmArg<1>]>;
1760
1761 def int_hexagon_A2_vconj :
1762 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">;
1763
1764 def int_hexagon_S2_lsr_r_vw :
1765 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">;
1766
1767 def int_hexagon_S2_lsr_r_vh :
1768 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">;
1769
1770 def int_hexagon_A2_subh_l16_hl :
1771 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">;
1772
1773 def int_hexagon_S4_vxsubaddhr :
1774 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">;
1775
1776 def int_hexagon_S2_clbp :
1777 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">;
1778
1779 def int_hexagon_S2_deinterleave :
1780 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">;
1781
1782 def int_hexagon_C2_any8 :
1783 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">;
1784
1785 def int_hexagon_S2_togglebit_r :
1786 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">;
1787
1788 def int_hexagon_S2_togglebit_i :
1789 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [ImmArg<1>]>;
1790
1791 def int_hexagon_F2_conv_uw2sf :
1792 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">;
1793
1794 def int_hexagon_S2_vsathb_nopack :
1795 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">;
1796
1797 def int_hexagon_M2_cmacs_s0 :
1798 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">;
1799
1800 def int_hexagon_M2_cmacs_s1 :
1801 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">;
1802
1803 def int_hexagon_M2_mpy_sat_hh_s0 :
1804 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;
1805
1806 def int_hexagon_M2_mpy_sat_hh_s1 :
1807 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;
1808
1809 def int_hexagon_M2_mmacuhs_s1 :
1810 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;
1811
1812 def int_hexagon_M2_mmacuhs_s0 :
1813 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;
1814
1815 def int_hexagon_S2_clrbit_r :
1816 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">;
1817
1818 def int_hexagon_C4_or_andn :
1819 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">;
1820
1821 def int_hexagon_S2_asl_r_r_nac :
1822 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;
1823
1824 def int_hexagon_S2_asl_i_p_acc :
1825 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [ImmArg<2>]>;
1826
1827 def int_hexagon_A4_vcmpwgtui :
1828 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [ImmArg<1>]>;
1829
1830 def int_hexagon_M4_vrmpyoh_acc_s0 :
1831 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;
1832
1833 def int_hexagon_M4_vrmpyoh_acc_s1 :
1834 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;
1835
1836 def int_hexagon_A4_vrmaxh :
1837 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">;
1838
1839 def int_hexagon_A2_vcmpbeq :
1840 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">;
1841
1842 def int_hexagon_A2_vcmphgt :
1843 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">;
1844
1845 def int_hexagon_A2_vnavgwcr :
1846 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">;
1847
1848 def int_hexagon_M2_vrcmacr_s0c :
1849 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;
1850
1851 def int_hexagon_A2_vavgwcr :
1852 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">;
1853
1854 def int_hexagon_S2_asl_i_p_xacc :
1855 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [ImmArg<2>]>;
1856
1857 def int_hexagon_A4_vrmaxw :
1858 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">;
1859
1860 def int_hexagon_A2_vnavghr :
1861 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">;
1862
1863 def int_hexagon_M4_cmpyi_wh :
1864 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">;
1865
1866 def int_hexagon_A2_tfrsi :
1867 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [ImmArg<0>]>;
1868
1869 def int_hexagon_S2_asr_i_r_acc :
1870 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [ImmArg<2>]>;
1871
1872 def int_hexagon_A2_svnavgh :
1873 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">;
1874
1875 def int_hexagon_S2_lsr_i_r :
1876 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [ImmArg<1>]>;
1877
1878 def int_hexagon_M2_vmac2 :
1879 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">;
1880
1881 def int_hexagon_A4_vcmphgtui :
1882 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [ImmArg<1>]>;
1883
1884 def int_hexagon_A2_svavgh :
1885 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">;
1886
1887 def int_hexagon_M4_vrmpyeh_acc_s0 :
1888 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;
1889
1890 def int_hexagon_M4_vrmpyeh_acc_s1 :
1891 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;
1892
1893 def int_hexagon_S2_lsr_i_p :
1894 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [ImmArg<1>]>;
1895
1896 def int_hexagon_A2_combine_hl :
1897 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">;
1898
1899 def int_hexagon_M2_mpy_up :
1900 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">;
1901
1902 def int_hexagon_A2_combine_hh :
1903 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">;
1904
1905 def int_hexagon_A2_negsat :
1906 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">;
1907
1908 def int_hexagon_M2_mpyd_hl_s0 :
1909 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;
1910
1911 def int_hexagon_M2_mpyd_hl_s1 :
1912 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;
1913
1914 def int_hexagon_A4_bitsplit :
1915 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">;
1916
1917 def int_hexagon_A2_vabshsat :
1918 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">;
1919
1920 def int_hexagon_M2_mpyui :
1921 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">;
1922
1923 def int_hexagon_A2_addh_l16_sat_ll :
1924 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;
1925
1926 def int_hexagon_S2_lsl_r_r_and :
1927 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;
1928
1929 def int_hexagon_M2_mmpyul_rs0 :
1930 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;
1931
1932 def int_hexagon_S2_asr_i_r_rnd_goodsyntax :
1933 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [ImmArg<1>]>;
1934
1935 def int_hexagon_S2_lsr_r_p_nac :
1936 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;
1937
1938 def int_hexagon_C2_cmplt :
1939 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">;
1940
1941 def int_hexagon_M2_cmacr_s0 :
1942 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">;
1943
1944 def int_hexagon_M4_or_and :
1945 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">;
1946
1947 def int_hexagon_M4_mpyrr_addi :
1948 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [ImmArg<0>]>;
1949
1950 def int_hexagon_S4_or_andi :
1951 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [ImmArg<2>]>;
1952
1953 def int_hexagon_M2_mpy_sat_hl_s0 :
1954 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;
1955
1956 def int_hexagon_M2_mpy_sat_hl_s1 :
1957 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;
1958
1959 def int_hexagon_M4_mpyrr_addr :
1960 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">;
1961
1962 def int_hexagon_M2_mmachs_rs0 :
1963 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">;
1964
1965 def int_hexagon_M2_mmachs_rs1 :
1966 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">;
1967
1968 def int_hexagon_M2_vrcmpyr_s0c :
1969 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;
1970
1971 def int_hexagon_M2_mpy_acc_sat_hl_s0 :
1972 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;
1973
1974 def int_hexagon_M2_mpyd_acc_ll_s1 :
1975 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;
1976
1977 def int_hexagon_F2_sffixupn :
1978 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn">;
1979
1980 def int_hexagon_M2_mpyd_acc_lh_s0 :
1981 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;
1982
1983 def int_hexagon_M2_mpyd_acc_lh_s1 :
1984 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;
1985
1986 def int_hexagon_M2_mpy_rnd_hh_s0 :
1987 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;
1988
1989 def int_hexagon_M2_mpy_rnd_hh_s1 :
1990 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;
1991
1992 def int_hexagon_A2_vadduhs :
1993 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">;
1994
1995 def int_hexagon_A2_vsubuhs :
1996 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">;
1997
1998 def int_hexagon_A2_subh_h16_hl :
1999 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">;
2000
2001 def int_hexagon_A2_subh_h16_hh :
2002 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">;
2003
2004 def int_hexagon_A2_xorp :
2005 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">;
2006
2007 def int_hexagon_A4_tfrpcp :
2008 Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrpcp">;
2009
2010 def int_hexagon_A2_addh_h16_lh :
2011 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">;
2012
2013 def int_hexagon_A2_addh_h16_sat_hl :
2014 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;
2015
2016 def int_hexagon_A2_addh_h16_ll :
2017 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">;
2018
2019 def int_hexagon_A2_addh_h16_sat_hh :
2020 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;
2021
2022 def int_hexagon_A2_zxtb :
2023 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">;
2024
2025 def int_hexagon_A2_zxth :
2026 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">;
2027
2028 def int_hexagon_A2_vnavgwr :
2029 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">;
2030
2031 def int_hexagon_M4_or_xor :
2032 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">;
2033
2034 def int_hexagon_M2_mpyud_acc_hh_s0 :
2035 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;
2036
2037 def int_hexagon_M2_mpyud_acc_hh_s1 :
2038 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;
2039
2040 def int_hexagon_M5_vmacbsu :
2041 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">;
2042
2043 def int_hexagon_M2_dpmpyuu_acc_s0 :
2044 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;
2045
2046 def int_hexagon_M2_mpy_rnd_hl_s0 :
2047 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;
2048
2049 def int_hexagon_M2_mpy_rnd_hl_s1 :
2050 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;
2051
2052 def int_hexagon_F2_sffms_lib :
2053 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib">;
2054
2055 def int_hexagon_C4_cmpneqi :
2056 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [ImmArg<1>]>;
2057
2058 def int_hexagon_M4_and_xor :
2059 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">;
2060
2061 def int_hexagon_A2_sat :
2062 Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">;
2063
2064 def int_hexagon_M2_mpyd_nac_lh_s1 :
2065 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;
2066
2067 def int_hexagon_M2_mpyd_nac_lh_s0 :
2068 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;
2069
2070 def int_hexagon_A2_addsat :
2071 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">;
2072
2073 def int_hexagon_A2_svavghs :
2074 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">;
2075
2076 def int_hexagon_A2_vrsadub_acc :
2077 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">;
2078
2079 def int_hexagon_C2_bitsclri :
2080 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [ImmArg<1>]>;
2081
2082 def int_hexagon_A2_subh_h16_sat_hh :
2083 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;
2084
2085 def int_hexagon_A2_subh_h16_sat_hl :
2086 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;
2087
2088 def int_hexagon_M2_mmaculs_rs0 :
2089 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;
2090
2091 def int_hexagon_M2_mmaculs_rs1 :
2092 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;
2093
2094 def int_hexagon_M2_vradduh :
2095 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">;
2096
2097 def int_hexagon_A4_addp_c :
2098 Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_addp_c">;
2099
2100 def int_hexagon_C2_xor :
2101 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">;
2102
2103 def int_hexagon_S2_lsl_r_r_acc :
2104 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;
2105
2106 def int_hexagon_M2_mmpyh_rs1 :
2107 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;
2108
2109 def int_hexagon_M2_mmpyh_rs0 :
2110 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;
2111
2112 def int_hexagon_F2_conv_df2ud_chop :
2113 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;
2114
2115 def int_hexagon_C4_or_or :
2116 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">;
2117
2118 def int_hexagon_S4_vxaddsubhr :
2119 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">;
2120
2121 def int_hexagon_S2_vsathub :
2122 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">;
2123
2124 def int_hexagon_F2_conv_df2sf :
2125 Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">;
2126
2127 def int_hexagon_M2_hmmpyh_rs1 :
2128 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;
2129
2130 def int_hexagon_M2_hmmpyh_s1 :
2131 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;
2132
2133 def int_hexagon_A2_vavgwr :
2134 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">;
2135
2136 def int_hexagon_S2_tableidxh_goodsyntax :
2137 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">;
2138
2139 def int_hexagon_A2_sxth :
2140 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">;
2141
2142 def int_hexagon_A2_sxtb :
2143 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">;
2144
2145 def int_hexagon_C4_or_orn :
2146 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">;
2147
2148 def int_hexagon_M2_vrcmaci_s0c :
2149 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;
2150
2151 def int_hexagon_A2_sxtw :
2152 Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">;
2153
2154 def int_hexagon_M2_vabsdiffh :
2155 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">;
2156
2157 def int_hexagon_M2_mpy_acc_lh_s1 :
2158 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;
2159
2160 def int_hexagon_M2_mpy_acc_lh_s0 :
2161 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;
2162
2163 def int_hexagon_M2_hmmpyl_s1 :
2164 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;
2165
2166 def int_hexagon_S2_cl1p :
2167 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">;
2168
2169 def int_hexagon_M2_vabsdiffw :
2170 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">;
2171
2172 def int_hexagon_A4_andnp :
2173 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">;
2174
2175 def int_hexagon_C2_vmux :
2176 Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">;
2177
2178 def int_hexagon_S2_parityp :
2179 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">;
2180
2181 def int_hexagon_S2_lsr_i_p_and :
2182 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [ImmArg<2>]>;
2183
2184 def int_hexagon_S2_asr_i_r_or :
2185 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [ImmArg<2>]>;
2186
2187 def int_hexagon_M2_mpyu_nac_ll_s0 :
2188 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;
2189
2190 def int_hexagon_M2_mpyu_nac_ll_s1 :
2191 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;
2192
2193 def int_hexagon_F2_sfcmpeq :
2194 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq">;
2195
2196 def int_hexagon_A2_vaddb_map :
2197 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">;
2198
2199 def int_hexagon_S2_lsr_r_r_nac :
2200 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;
2201
2202 def int_hexagon_A2_vcmpheq :
2203 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">;
2204
2205 def int_hexagon_S2_clbnorm :
2206 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">;
2207
2208 def int_hexagon_M2_cnacsc_s1 :
2209 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">;
2210
2211 def int_hexagon_M2_cnacsc_s0 :
2212 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">;
2213
2214 def int_hexagon_S4_subaddi :
2215 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [ImmArg<1>]>;
2216
2217 def int_hexagon_M2_mpyud_nac_hl_s1 :
2218 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;
2219
2220 def int_hexagon_M2_mpyud_nac_hl_s0 :
2221 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;
2222
2223 def int_hexagon_S5_vasrhrnd_goodsyntax :
2224 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [ImmArg<1>]>;
2225
2226 def int_hexagon_S2_tstbit_r :
2227 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">;
2228
2229 def int_hexagon_S4_vrcrotate :
2230 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [ImmArg<2>]>;
2231
2232 def int_hexagon_M2_mmachs_s1 :
2233 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">;
2234
2235 def int_hexagon_M2_mmachs_s0 :
2236 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">;
2237
2238 def int_hexagon_S2_tstbit_i :
2239 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [ImmArg<1>]>;
2240
2241 def int_hexagon_M2_mpy_up_s1 :
2242 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">;
2243
2244 def int_hexagon_S2_extractu_rp :
2245 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">;
2246
2247 def int_hexagon_M2_mmpyuh_rs0 :
2248 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;
2249
2250 def int_hexagon_S2_lsr_i_vw :
2251 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [ImmArg<1>]>;
2252
2253 def int_hexagon_M2_mpy_rnd_ll_s0 :
2254 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;
2255
2256 def int_hexagon_M2_mpy_rnd_ll_s1 :
2257 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;
2258
2259 def int_hexagon_M4_or_or :
2260 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">;
2261
2262 def int_hexagon_M2_mpyu_hh_s1 :
2263 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;
2264
2265 def int_hexagon_M2_mpyu_hh_s0 :
2266 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;
2267
2268 def int_hexagon_S2_asl_r_p_acc :
2269 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;
2270
2271 def int_hexagon_M2_mpyu_nac_lh_s0 :
2272 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;
2273
2274 def int_hexagon_M2_mpyu_nac_lh_s1 :
2275 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;
2276
2277 def int_hexagon_M2_mpy_sat_ll_s0 :
2278 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;
2279
2280 def int_hexagon_M2_mpy_sat_ll_s1 :
2281 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;
2282
2283 def int_hexagon_F2_conv_w2df :
2284 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">;
2285
2286 def int_hexagon_A2_subh_l16_sat_hl :
2287 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;
2288
2289 def int_hexagon_C2_cmpeqi :
2290 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [ImmArg<1>]>;
2291
2292 def int_hexagon_S2_asl_i_r_and :
2293 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [ImmArg<2>]>;
2294
2295 def int_hexagon_S2_vcnegh :
2296 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">;
2297
2298 def int_hexagon_A4_vcmpweqi :
2299 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [ImmArg<1>]>;
2300
2301 def int_hexagon_M2_vdmpyrs_s0 :
2302 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;
2303
2304 def int_hexagon_M2_vdmpyrs_s1 :
2305 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;
2306
2307 def int_hexagon_M4_xor_xacc :
2308 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">;
2309
2310 def int_hexagon_M2_vdmpys_s1 :
2311 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">;
2312
2313 def int_hexagon_M2_vdmpys_s0 :
2314 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">;
2315
2316 def int_hexagon_A2_vavgubr :
2317 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">;
2318
2319 def int_hexagon_M2_mpyu_hl_s1 :
2320 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;
2321
2322 def int_hexagon_M2_mpyu_hl_s0 :
2323 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;
2324
2325 def int_hexagon_S2_asl_r_r_acc :
2326 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;
2327
2328 def int_hexagon_S2_cl0p :
2329 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">;
2330
2331 def int_hexagon_S2_valignib :
2332 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [ImmArg<2>]>;
2333
2334 def int_hexagon_F2_sffixupd :
2335 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd">;
2336
2337 def int_hexagon_M2_mpy_sat_rnd_hl_s1 :
2338 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;
2339
2340 def int_hexagon_M2_mpy_sat_rnd_hl_s0 :
2341 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;
2342
2343 def int_hexagon_M2_cmacsc_s0 :
2344 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">;
2345
2346 def int_hexagon_M2_cmacsc_s1 :
2347 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">;
2348
2349 def int_hexagon_S2_ct1 :
2350 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">;
2351
2352 def int_hexagon_S2_ct0 :
2353 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">;
2354
2355 def int_hexagon_M2_dpmpyuu_nac_s0 :
2356 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;
2357
2358 def int_hexagon_M2_mmpyul_rs1 :
2359 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;
2360
2361 def int_hexagon_S4_ntstbit_i :
2362 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [ImmArg<1>]>   ;
2363
2364 def int_hexagon_F2_sffixupr :
2365 Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr">;
2366
2367 def int_hexagon_S2_asr_r_p_xor :
2368 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;
2369
2370 def int_hexagon_M2_mpyud_acc_hl_s0 :
2371 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;
2372
2373 def int_hexagon_M2_mpyud_acc_hl_s1 :
2374 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;
2375
2376 def int_hexagon_A2_vcmphgtu :
2377 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">;
2378
2379 def int_hexagon_C2_andn :
2380 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">;
2381
2382 def int_hexagon_M2_vmpy2s_s0pack :
2383 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;
2384
2385 def int_hexagon_S4_addaddi :
2386 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [ImmArg<2>]>;
2387
2388 def int_hexagon_M2_mpyd_acc_ll_s0 :
2389 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;
2390
2391 def int_hexagon_M2_mpy_acc_sat_hl_s1 :
2392 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;
2393
2394 def int_hexagon_A4_rcmpeqi :
2395 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [ImmArg<1>]>;
2396
2397 def int_hexagon_M4_xor_and :
2398 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">;
2399
2400 def int_hexagon_S2_asl_i_p_and :
2401 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [ImmArg<2>]>;
2402
2403 def int_hexagon_M2_mmpyuh_rs1 :
2404 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;
2405
2406 def int_hexagon_S2_asr_r_r_or :
2407 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">;
2408
2409 def int_hexagon_A4_round_ri :
2410 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [ImmArg<1>]>;
2411
2412 def int_hexagon_A2_max :
2413 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">;
2414
2415 def int_hexagon_A4_round_rr :
2416 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">;
2417
2418 def int_hexagon_A4_combineii :
2419 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineii", [ImmArg<0>, ImmArg<1>]>;
2420
2421 def int_hexagon_A4_combineir :
2422 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [ImmArg<0>]>;
2423
2424 def int_hexagon_C4_and_orn :
2425 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">;
2426
2427 def int_hexagon_M5_vmacbuu :
2428 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">;
2429
2430 def int_hexagon_A4_rcmpeq :
2431 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">;
2432
2433 def int_hexagon_M4_cmpyr_whc :
2434 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">;
2435
2436 def int_hexagon_S2_lsr_i_r_acc :
2437 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [ImmArg<2>]>;
2438
2439 def int_hexagon_S2_vzxtbh :
2440 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">;
2441
2442 def int_hexagon_M2_mmacuhs_rs1 :
2443 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;
2444
2445 def int_hexagon_S2_asr_r_r_sat :
2446 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;
2447
2448 def int_hexagon_A2_combinew :
2449 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">;
2450
2451 def int_hexagon_M2_mpy_acc_ll_s1 :
2452 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;
2453
2454 def int_hexagon_M2_mpy_acc_ll_s0 :
2455 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;
2456
2457 def int_hexagon_M2_cmpyi_s0 :
2458 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">;
2459
2460 def int_hexagon_S2_asl_r_p_or :
2461 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">;
2462
2463 def int_hexagon_S4_ori_asl_ri :
2464 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [ImmArg<0>, ImmArg<2>]>;
2465
2466 def int_hexagon_C4_nbitsset :
2467 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">;
2468
2469 def int_hexagon_M2_mpyu_acc_hh_s1 :
2470 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;
2471
2472 def int_hexagon_M2_mpyu_acc_hh_s0 :
2473 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;
2474
2475 def int_hexagon_M2_mpyu_ll_s1 :
2476 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;
2477
2478 def int_hexagon_M2_mpyu_ll_s0 :
2479 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;
2480
2481 def int_hexagon_A2_addh_l16_ll :
2482 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">;
2483
2484 def int_hexagon_S2_lsr_r_r_and :
2485 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;
2486
2487 def int_hexagon_A4_modwrapu :
2488 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">;
2489
2490 def int_hexagon_A4_rcmpneq :
2491 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">;
2492
2493 def int_hexagon_M2_mpyd_acc_hh_s0 :
2494 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;
2495
2496 def int_hexagon_M2_mpyd_acc_hh_s1 :
2497 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;
2498
2499 def int_hexagon_F2_sfimm_p :
2500 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [ImmArg<0>]>;
2501
2502 def int_hexagon_F2_sfimm_n :
2503 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [ImmArg<0>]>;
2504
2505 def int_hexagon_M4_cmpyr_wh :
2506 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">;
2507
2508 def int_hexagon_S2_lsl_r_p_and :
2509 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;
2510
2511 def int_hexagon_A2_vavgub :
2512 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">;
2513
2514 def int_hexagon_F2_conv_d2sf :
2515 Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">;
2516
2517 def int_hexagon_A2_vavguh :
2518 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">;
2519
2520 def int_hexagon_A4_cmpbeqi :
2521 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [ImmArg<1>]>;
2522
2523 def int_hexagon_F2_sfcmpuo :
2524 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo">;
2525
2526 def int_hexagon_A2_vavguw :
2527 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">;
2528
2529 def int_hexagon_S2_asr_i_p_nac :
2530 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [ImmArg<2>]>;
2531
2532 def int_hexagon_S2_vsatwh_nopack :
2533 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;
2534
2535 def int_hexagon_M2_mpyd_hh_s0 :
2536 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;
2537
2538 def int_hexagon_M2_mpyd_hh_s1 :
2539 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;
2540
2541 def int_hexagon_S2_lsl_r_p_or :
2542 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;
2543
2544 def int_hexagon_A2_minu :
2545 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">;
2546
2547 def int_hexagon_M2_mpy_sat_lh_s1 :
2548 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;
2549
2550 def int_hexagon_M4_or_andn :
2551 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">;
2552
2553 def int_hexagon_A2_minp :
2554 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">;
2555
2556 def int_hexagon_S4_or_andix :
2557 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [ImmArg<2>]>;
2558
2559 def int_hexagon_M2_mpy_rnd_lh_s0 :
2560 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;
2561
2562 def int_hexagon_M2_mpy_rnd_lh_s1 :
2563 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;
2564
2565 def int_hexagon_M2_mmpyuh_s0 :
2566 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;
2567
2568 def int_hexagon_M2_mmpyuh_s1 :
2569 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;
2570
2571 def int_hexagon_M2_mpy_acc_sat_lh_s0 :
2572 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;
2573
2574 def int_hexagon_F2_sfcmpge :
2575 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge">;
2576
2577 def int_hexagon_F2_sfmin :
2578 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin">;
2579
2580 def int_hexagon_F2_sfcmpgt :
2581 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt">;
2582
2583 def int_hexagon_M4_vpmpyh :
2584 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">;
2585
2586 def int_hexagon_M2_mmacuhs_rs0 :
2587 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;
2588
2589 def int_hexagon_M2_mpyd_rnd_lh_s1 :
2590 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;
2591
2592 def int_hexagon_M2_mpyd_rnd_lh_s0 :
2593 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;
2594
2595 def int_hexagon_A2_roundsat :
2596 Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">;
2597
2598 def int_hexagon_S2_ct1p :
2599 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">;
2600
2601 def int_hexagon_S4_extract_rp :
2602 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">;
2603
2604 def int_hexagon_S2_lsl_r_r_or :
2605 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;
2606
2607 def int_hexagon_C4_cmplteui :
2608 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [ImmArg<1>]>;
2609
2610 def int_hexagon_S4_addi_lsr_ri :
2611 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
2612
2613 def int_hexagon_A4_tfrcpp :
2614 Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrcpp">;
2615
2616 def int_hexagon_S2_asr_i_svw_trun :
2617 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [ImmArg<1>]>;
2618
2619 def int_hexagon_A4_cmphgti :
2620 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [ImmArg<1>]>;
2621
2622 def int_hexagon_A4_vrminh :
2623 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">;
2624
2625 def int_hexagon_A4_vrminw :
2626 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">;
2627
2628 def int_hexagon_A4_cmphgtu :
2629 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">;
2630
2631 def int_hexagon_S2_insertp_rp :
2632 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">;
2633
2634 def int_hexagon_A2_vnavghcr :
2635 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">;
2636
2637 def int_hexagon_S4_subi_asl_ri :
2638 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [ImmArg<0>, ImmArg<2>]>;
2639
2640 def int_hexagon_S2_lsl_r_vh :
2641 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">;
2642
2643 def int_hexagon_M2_mpy_hh_s0 :
2644 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;
2645
2646 def int_hexagon_A2_vsubws :
2647 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">;
2648
2649 def int_hexagon_A2_sath :
2650 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">;
2651
2652 def int_hexagon_S2_asl_r_p_xor :
2653 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;
2654
2655 def int_hexagon_A2_satb :
2656 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">;
2657
2658 def int_hexagon_C2_cmpltu :
2659 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">;
2660
2661 def int_hexagon_S2_insertp :
2662 Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [ImmArg<2>, ImmArg<3>]>;
2663
2664 def int_hexagon_M2_mpyd_rnd_ll_s1 :
2665 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;
2666
2667 def int_hexagon_M2_mpyd_rnd_ll_s0 :
2668 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;
2669
2670 def int_hexagon_S2_lsr_i_p_nac :
2671 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [ImmArg<2>]>;
2672
2673 def int_hexagon_S2_extractup_rp :
2674 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">;
2675
2676 def int_hexagon_S4_vxaddsubw :
2677 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">;
2678
2679 def int_hexagon_S4_vxaddsubh :
2680 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">;
2681
2682 def int_hexagon_A2_asrh :
2683 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">;
2684
2685 def int_hexagon_S4_extractp_rp :
2686 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">;
2687
2688 def int_hexagon_S2_lsr_r_r_acc :
2689 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;
2690
2691 def int_hexagon_M2_mpyd_nac_ll_s1 :
2692 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;
2693
2694 def int_hexagon_M2_mpyd_nac_ll_s0 :
2695 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;
2696
2697 def int_hexagon_C2_or :
2698 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">;
2699
2700 def int_hexagon_M2_mmpyul_s1 :
2701 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">;
2702
2703 def int_hexagon_M2_vrcmacr_s0 :
2704 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;
2705
2706 def int_hexagon_A2_xor :
2707 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">;
2708
2709 def int_hexagon_A2_add :
2710 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">;
2711
2712 def int_hexagon_A2_vsububs :
2713 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">;
2714
2715 def int_hexagon_M2_vmpy2s_s1 :
2716 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;
2717
2718 def int_hexagon_M2_vmpy2s_s0 :
2719 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;
2720
2721 def int_hexagon_A2_vraddub_acc :
2722 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">;
2723
2724 def int_hexagon_F2_sfinvsqrta :
2725 Hexagon_floati32_float_Intrinsic<"HEXAGON_F2_sfinvsqrta">;
2726
2727 def int_hexagon_S2_ct0p :
2728 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">;
2729
2730 def int_hexagon_A2_svaddh :
2731 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">;
2732
2733 def int_hexagon_S2_vcrotate :
2734 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">;
2735
2736 def int_hexagon_A2_aslh :
2737 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">;
2738
2739 def int_hexagon_A2_subh_h16_lh :
2740 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">;
2741
2742 def int_hexagon_A2_subh_h16_ll :
2743 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">;
2744
2745 def int_hexagon_M2_hmmpyl_rs1 :
2746 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;
2747
2748 def int_hexagon_S2_asr_r_p :
2749 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">;
2750
2751 def int_hexagon_S2_vsplatrh :
2752 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">;
2753
2754 def int_hexagon_S2_asr_r_r :
2755 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">;
2756
2757 def int_hexagon_A2_addh_h16_hl :
2758 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">;
2759
2760 def int_hexagon_S2_vsplatrb :
2761 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">;
2762
2763 def int_hexagon_A2_addh_h16_hh :
2764 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">;
2765
2766 def int_hexagon_M2_cmpyr_s0 :
2767 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">;
2768
2769 def int_hexagon_M2_dpmpyss_rnd_s0 :
2770 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;
2771
2772 def int_hexagon_C2_muxri :
2773 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [ImmArg<1>]>;
2774
2775 def int_hexagon_M2_vmac2es_s0 :
2776 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">;
2777
2778 def int_hexagon_M2_vmac2es_s1 :
2779 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">;
2780
2781 def int_hexagon_C2_pxfer_map :
2782 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">;
2783
2784 def int_hexagon_M2_mpyu_lh_s1 :
2785 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;
2786
2787 def int_hexagon_M2_mpyu_lh_s0 :
2788 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;
2789
2790 def int_hexagon_S2_asl_i_r_or :
2791 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [ImmArg<2>]>;
2792
2793 def int_hexagon_M2_mpyd_acc_hl_s0 :
2794 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;
2795
2796 def int_hexagon_M2_mpyd_acc_hl_s1 :
2797 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;
2798
2799 def int_hexagon_S2_asr_r_p_nac :
2800 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;
2801
2802 def int_hexagon_A2_vaddw :
2803 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">;
2804
2805 def int_hexagon_S2_asr_i_r_and :
2806 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [ImmArg<2>]>;
2807
2808 def int_hexagon_A2_vaddh :
2809 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">;
2810
2811 def int_hexagon_M2_mpy_nac_sat_lh_s1 :
2812 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;
2813
2814 def int_hexagon_M2_mpy_nac_sat_lh_s0 :
2815 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;
2816
2817 def int_hexagon_C2_cmpeqp :
2818 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">;
2819
2820 def int_hexagon_M4_mpyri_addi :
2821 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [ImmArg<0>, ImmArg<2>]>;
2822
2823 def int_hexagon_A2_not :
2824 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">;
2825
2826 def int_hexagon_S4_andi_lsr_ri :
2827 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
2828
2829 def int_hexagon_M2_macsip :
2830 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [ImmArg<2>]>;
2831
2832 def int_hexagon_A2_tfrcrr :
2833 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrcrr">;
2834
2835 def int_hexagon_M2_macsin :
2836 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [ImmArg<2>]>;
2837
2838 def int_hexagon_C2_orn :
2839 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">;
2840
2841 def int_hexagon_M4_and_andn :
2842 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">;
2843
2844 def int_hexagon_F2_sfmpy :
2845 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy">;
2846
2847 def int_hexagon_M2_mpyud_nac_hh_s1 :
2848 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;
2849
2850 def int_hexagon_M2_mpyud_nac_hh_s0 :
2851 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;
2852
2853 def int_hexagon_S2_lsr_r_p_acc :
2854 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;
2855
2856 def int_hexagon_S2_asr_r_vw :
2857 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">;
2858
2859 def int_hexagon_M4_and_or :
2860 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">;
2861
2862 def int_hexagon_S2_asr_r_vh :
2863 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">;
2864
2865 def int_hexagon_C2_mask :
2866 Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">;
2867
2868 def int_hexagon_M2_mpy_nac_hh_s0 :
2869 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;
2870
2871 def int_hexagon_M2_mpy_nac_hh_s1 :
2872 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;
2873
2874 def int_hexagon_M2_mpy_up_s1_sat :
2875 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;
2876
2877 def int_hexagon_A4_vcmpbgt :
2878 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">;
2879
2880 def int_hexagon_M5_vrmacbsu :
2881 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">;
2882
2883 def int_hexagon_S2_tableidxw_goodsyntax :
2884 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">;
2885
2886 def int_hexagon_A2_vrsadub :
2887 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">;
2888
2889 def int_hexagon_A2_tfrrcr :
2890 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrrcr">;
2891
2892 def int_hexagon_M2_vrcmpys_acc_s1 :
2893 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;
2894
2895 def int_hexagon_F2_dfcmpge :
2896 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge">;
2897
2898 def int_hexagon_M2_accii :
2899 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [ImmArg<2>]>;
2900
2901 def int_hexagon_A5_vaddhubs :
2902 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">;
2903
2904 def int_hexagon_A2_vmaxw :
2905 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">;
2906
2907 def int_hexagon_A2_vmaxb :
2908 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">;
2909
2910 def int_hexagon_A2_vmaxh :
2911 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">;
2912
2913 def int_hexagon_S2_vsxthw :
2914 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">;
2915
2916 def int_hexagon_S4_andi_asl_ri :
2917 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [ImmArg<0>, ImmArg<2>]>;
2918
2919 def int_hexagon_S2_asl_i_p_nac :
2920 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [ImmArg<2>]>;
2921
2922 def int_hexagon_S2_lsl_r_p_xor :
2923 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;
2924
2925 def int_hexagon_C2_cmpgt :
2926 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">;
2927
2928 def int_hexagon_F2_conv_df2d_chop :
2929 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;
2930
2931 def int_hexagon_M2_mpyu_nac_hl_s0 :
2932 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;
2933
2934 def int_hexagon_M2_mpyu_nac_hl_s1 :
2935 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;
2936
2937 def int_hexagon_F2_conv_sf2w :
2938 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">;
2939
2940 def int_hexagon_S2_lsr_r_p_or :
2941 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;
2942
2943 def int_hexagon_F2_sfclass :
2944 Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass">;
2945
2946 def int_hexagon_M2_mpyud_acc_lh_s0 :
2947 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;
2948
2949 def int_hexagon_M4_xor_andn :
2950 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">;
2951
2952 def int_hexagon_S2_addasl_rrri :
2953 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [ImmArg<2>]>;
2954
2955 def int_hexagon_M5_vdmpybsu :
2956 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">;
2957
2958 def int_hexagon_M2_mpyu_nac_hh_s0 :
2959 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;
2960
2961 def int_hexagon_M2_mpyu_nac_hh_s1 :
2962 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;
2963
2964 def int_hexagon_A2_addi :
2965 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [ImmArg<1>]>;
2966
2967 def int_hexagon_A2_addp :
2968 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">;
2969
2970 def int_hexagon_M2_vmpy2s_s1pack :
2971 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;
2972
2973 def int_hexagon_S4_clbpnorm :
2974 Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">;
2975
2976 def int_hexagon_A4_round_rr_sat :
2977 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">;
2978
2979 def int_hexagon_M2_nacci :
2980 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">;
2981
2982 def int_hexagon_S2_shuffeh :
2983 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">;
2984
2985 def int_hexagon_S2_lsr_i_r_and :
2986 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [ImmArg<2>]>;
2987
2988 def int_hexagon_M2_mpy_sat_rnd_hh_s1 :
2989 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;
2990
2991 def int_hexagon_M2_mpy_sat_rnd_hh_s0 :
2992 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;
2993
2994 def int_hexagon_F2_conv_sf2uw :
2995 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">;
2996
2997 def int_hexagon_A2_vsubh :
2998 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">;
2999
3000 def int_hexagon_F2_conv_sf2ud :
3001 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">;
3002
3003 def int_hexagon_A2_vsubw :
3004 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">;
3005
3006 def int_hexagon_A2_vcmpwgt :
3007 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">;
3008
3009 def int_hexagon_M4_xor_or :
3010 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">;
3011
3012 def int_hexagon_F2_conv_sf2uw_chop :
3013 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">;
3014
3015 def int_hexagon_S2_asl_r_vw :
3016 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">;
3017
3018 def int_hexagon_S2_vsatwuh_nopack :
3019 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">;
3020
3021 def int_hexagon_S2_asl_r_vh :
3022 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">;
3023
3024 def int_hexagon_A2_svsubuhs :
3025 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">;
3026
3027 def int_hexagon_M5_vmpybsu :
3028 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">;
3029
3030 def int_hexagon_A2_subh_l16_sat_ll :
3031 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">;
3032
3033 def int_hexagon_C4_and_and :
3034 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">;
3035
3036 def int_hexagon_M2_mpyu_acc_hl_s1 :
3037 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">;
3038
3039 def int_hexagon_M2_mpyu_acc_hl_s0 :
3040 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">;
3041
3042 def int_hexagon_S2_lsr_r_p :
3043 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">;
3044
3045 def int_hexagon_S2_lsr_r_r :
3046 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">;
3047
3048 def int_hexagon_A4_subp_c :
3049 Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_subp_c">;
3050
3051 def int_hexagon_A2_vsubhs :
3052 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">;
3053
3054 def int_hexagon_C2_vitpack :
3055 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">;
3056
3057 def int_hexagon_A2_vavguhr :
3058 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">;
3059
3060 def int_hexagon_S2_vsplicerb :
3061 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">;
3062
3063 def int_hexagon_C4_nbitsclr :
3064 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">;
3065
3066 def int_hexagon_A2_vcmpbgtu :
3067 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">;
3068
3069 def int_hexagon_M2_cmpys_s1 :
3070 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">;
3071
3072 def int_hexagon_M2_cmpys_s0 :
3073 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">;
3074
3075 def int_hexagon_F2_dfcmpuo :
3076 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo">;
3077
3078 def int_hexagon_S2_shuffob :
3079 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">;
3080
3081 def int_hexagon_C2_and :
3082 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">;
3083
3084 def int_hexagon_S5_popcountp :
3085 Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">;
3086
3087 def int_hexagon_S4_extractp :
3088 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [ImmArg<1>, ImmArg<2>]>;
3089
3090 def int_hexagon_S2_cl0 :
3091 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">;
3092
3093 def int_hexagon_A4_vcmpbgti :
3094 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [ImmArg<1>]>;
3095
3096 def int_hexagon_M2_mmacls_s1 :
3097 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">;
3098
3099 def int_hexagon_M2_mmacls_s0 :
3100 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">;
3101
3102 def int_hexagon_C4_cmpneq :
3103 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">;
3104
3105 def int_hexagon_M2_vmac2es :
3106 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">;
3107
3108 def int_hexagon_M2_vdmacs_s0 :
3109 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">;
3110
3111 def int_hexagon_M2_vdmacs_s1 :
3112 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">;
3113
3114 def int_hexagon_M2_mpyud_ll_s0 :
3115 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">;
3116
3117 def int_hexagon_M2_mpyud_ll_s1 :
3118 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">;
3119
3120 def int_hexagon_S2_clb :
3121 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">;
3122
3123 def int_hexagon_M2_mpy_nac_ll_s0 :
3124 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">;
3125
3126 def int_hexagon_M2_mpy_nac_ll_s1 :
3127 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">;
3128
3129 def int_hexagon_M2_mpyd_nac_hl_s1 :
3130 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">;
3131
3132 def int_hexagon_M2_mpyd_nac_hl_s0 :
3133 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">;
3134
3135 def int_hexagon_M2_maci :
3136 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">;
3137
3138 def int_hexagon_A2_vmaxuh :
3139 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">;
3140
3141 def int_hexagon_A4_bitspliti :
3142 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [ImmArg<1>]>;
3143
3144 def int_hexagon_A2_vmaxub :
3145 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">;
3146
3147 def int_hexagon_M2_mpyud_hh_s0 :
3148 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;
3149
3150 def int_hexagon_M2_mpyud_hh_s1 :
3151 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">;
3152
3153 def int_hexagon_M2_vrmac_s0 :
3154 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">;
3155
3156 def int_hexagon_M2_mpy_sat_lh_s0 :
3157 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">;
3158
3159 def int_hexagon_S2_asl_r_r_sat :
3160 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">;
3161
3162 def int_hexagon_F2_conv_sf2d :
3163 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">;
3164
3165 def int_hexagon_S2_asr_r_r_nac :
3166 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;
3167
3168 def int_hexagon_F2_dfimm_n :
3169 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [ImmArg<0>]>;
3170
3171 def int_hexagon_A4_cmphgt :
3172 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">;
3173
3174 def int_hexagon_F2_dfimm_p :
3175 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [ImmArg<0>]>;
3176
3177 def int_hexagon_M2_mpyud_acc_lh_s1 :
3178 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;
3179
3180 def int_hexagon_M2_vcmpy_s1_sat_r :
3181 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;
3182
3183 def int_hexagon_M4_mpyri_addr_u2 :
3184 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [ImmArg<1>]>;
3185
3186 def int_hexagon_M2_vcmpy_s1_sat_i :
3187 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;
3188
3189 def int_hexagon_S2_lsl_r_p_nac :
3190 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;
3191
3192 def int_hexagon_M5_vrmacbuu :
3193 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">;
3194
3195 def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :
3196 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [ImmArg<1>]>;
3197
3198 def int_hexagon_S2_vspliceib :
3199 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [ImmArg<2>]>;
3200
3201 def int_hexagon_M2_dpmpyss_acc_s0 :
3202 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;
3203
3204 def int_hexagon_M2_cnacs_s1 :
3205 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">;
3206
3207 def int_hexagon_M2_cnacs_s0 :
3208 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">;
3209
3210 def int_hexagon_A2_maxu :
3211 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">;
3212
3213 def int_hexagon_A2_maxp :
3214 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">;
3215
3216 def int_hexagon_A2_andir :
3217 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [ImmArg<1>]>;
3218
3219 def int_hexagon_F2_sfrecipa :
3220 Hexagon_floati32_floatfloat_Intrinsic<"HEXAGON_F2_sfrecipa">;
3221
3222 def int_hexagon_A2_combineii :
3223 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [ImmArg<0>, ImmArg<1>]>;
3224
3225 def int_hexagon_A4_orn :
3226 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">;
3227
3228 def int_hexagon_A4_cmpbgtui :
3229 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [ImmArg<1>]>;
3230
3231 def int_hexagon_S2_lsr_r_r_or :
3232 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;
3233
3234 def int_hexagon_A4_vcmpbeqi :
3235 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [ImmArg<1>]>;
3236
3237 def int_hexagon_S2_lsl_r_r :
3238 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">;
3239
3240 def int_hexagon_S2_lsl_r_p :
3241 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">;
3242
3243 def int_hexagon_A2_or :
3244 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">;
3245
3246 def int_hexagon_F2_dfcmpeq :
3247 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq">;
3248
3249 def int_hexagon_C2_cmpeq :
3250 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">;
3251
3252 def int_hexagon_A2_tfrp :
3253 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">;
3254
3255 def int_hexagon_C4_and_andn :
3256 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">;
3257
3258 def int_hexagon_S2_vsathub_nopack :
3259 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">;
3260
3261 def int_hexagon_A2_satuh :
3262 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">;
3263
3264 def int_hexagon_A2_satub :
3265 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">;
3266
3267 def int_hexagon_M2_vrcmpys_s1 :
3268 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;
3269
3270 def int_hexagon_S4_or_ori :
3271 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [ImmArg<2>]>;
3272
3273 def int_hexagon_C4_fastcorner9_not :
3274 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">;
3275
3276 def int_hexagon_A2_tfrih :
3277 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [ImmArg<1>]>;
3278
3279 def int_hexagon_A2_tfril :
3280 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [ImmArg<1>]>;
3281
3282 def int_hexagon_M4_mpyri_addr :
3283 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [ImmArg<2>]>;
3284
3285 def int_hexagon_S2_vtrunehb :
3286 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">;
3287
3288 def int_hexagon_A2_vabsw :
3289 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">;
3290
3291 def int_hexagon_A2_vabsh :
3292 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">;
3293
3294 def int_hexagon_F2_sfsub :
3295 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub">;
3296
3297 def int_hexagon_C2_muxii :
3298 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [ImmArg<1>, ImmArg<2>]>;
3299
3300 def int_hexagon_C2_muxir :
3301 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [ImmArg<2>]>;
3302
3303 def int_hexagon_A2_swiz :
3304 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">;
3305
3306 def int_hexagon_S2_asr_i_p_and :
3307 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [ImmArg<2>]>;
3308
3309 def int_hexagon_M2_cmpyrsc_s0 :
3310 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;
3311
3312 def int_hexagon_M2_cmpyrsc_s1 :
3313 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;
3314
3315 def int_hexagon_A2_vraddub :
3316 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">;
3317
3318 def int_hexagon_A4_tlbmatch :
3319 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">;
3320
3321 def int_hexagon_F2_conv_df2w_chop :
3322 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">;
3323
3324 def int_hexagon_A2_and :
3325 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">;
3326
3327 def int_hexagon_S2_lsr_r_p_and :
3328 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">;
3329
3330 def int_hexagon_M2_mpy_nac_sat_ll_s1 :
3331 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;
3332
3333 def int_hexagon_M2_mpy_nac_sat_ll_s0 :
3334 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;
3335
3336 def int_hexagon_S4_extract :
3337 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [ImmArg<1>, ImmArg<2>]>;
3338
3339 def int_hexagon_A2_vcmpweq :
3340 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">;
3341
3342 def int_hexagon_M2_acci :
3343 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">;
3344
3345 def int_hexagon_S2_lsr_i_p_acc :
3346 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [ImmArg<2>]>;
3347
3348 def int_hexagon_S2_lsr_i_p_or :
3349 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [ImmArg<2>]>;
3350
3351 def int_hexagon_F2_conv_ud2sf :
3352 Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">;
3353
3354 def int_hexagon_A2_tfr :
3355 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">;
3356
3357 def int_hexagon_S2_asr_i_p_or :
3358 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [ImmArg<2>]>;
3359
3360 def int_hexagon_A2_subri :
3361 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [ImmArg<0>]>;
3362
3363 def int_hexagon_A4_vrmaxuw :
3364 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">;
3365
3366 def int_hexagon_M5_vmpybuu :
3367 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">;
3368
3369 def int_hexagon_A4_vrmaxuh :
3370 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">;
3371
3372 def int_hexagon_S2_asl_i_vw :
3373 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [ImmArg<1>]>;
3374
3375 def int_hexagon_A2_vavgw :
3376 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">;
3377
3378 def int_hexagon_S2_brev :
3379 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">;
3380
3381 def int_hexagon_A2_vavgh :
3382 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">;
3383
3384 def int_hexagon_S2_clrbit_i :
3385 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [ImmArg<1>]>;
3386
3387 def int_hexagon_S2_asl_i_vh :
3388 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [ImmArg<1>]>;
3389
3390 def int_hexagon_S2_lsr_i_r_or :
3391 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [ImmArg<2>]>;
3392
3393 def int_hexagon_S2_lsl_r_r_nac :
3394 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;
3395
3396 def int_hexagon_M2_mmpyl_rs1 :
3397 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;
3398
3399 def int_hexagon_M2_mpyud_hl_s1 :
3400 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;
3401
3402 def int_hexagon_M2_mmpyl_s0 :
3403 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">;
3404
3405 def int_hexagon_M2_mmpyl_s1 :
3406 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">;
3407
3408 def int_hexagon_M2_naccii :
3409 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [ImmArg<2>]>;
3410
3411 def int_hexagon_S2_vrndpackwhs :
3412 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">;
3413
3414 def int_hexagon_S2_vtrunewh :
3415 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">;
3416
3417 def int_hexagon_M2_dpmpyss_nac_s0 :
3418 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;
3419
3420 def int_hexagon_M2_mpyd_ll_s0 :
3421 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;
3422
3423 def int_hexagon_M2_mpyd_ll_s1 :
3424 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;
3425
3426 def int_hexagon_M4_mac_up_s1_sat :
3427 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;
3428
3429 def int_hexagon_S4_vrcrotate_acc :
3430 Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [ImmArg<3>]>;
3431
3432 def int_hexagon_F2_conv_uw2df :
3433 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">;
3434
3435 def int_hexagon_A2_vaddubs :
3436 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">;
3437
3438 def int_hexagon_S2_asr_r_r_acc :
3439 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;
3440
3441 def int_hexagon_A2_orir :
3442 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [ImmArg<1>]>;
3443
3444 def int_hexagon_A2_andp :
3445 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">;
3446
3447 def int_hexagon_S2_lfsp :
3448 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">;
3449
3450 def int_hexagon_A2_min :
3451 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">;
3452
3453 def int_hexagon_M2_mpysmi :
3454 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [ImmArg<1>]>;
3455
3456 def int_hexagon_M2_vcmpy_s0_sat_r :
3457 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;
3458
3459 def int_hexagon_M2_mpyu_acc_ll_s1 :
3460 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;
3461
3462 def int_hexagon_M2_mpyu_acc_ll_s0 :
3463 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">;
3464
3465 def int_hexagon_S2_asr_r_svw_trun :
3466 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">;
3467
3468 def int_hexagon_M2_mmpyh_s0 :
3469 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">;
3470
3471 def int_hexagon_M2_mmpyh_s1 :
3472 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">;
3473
3474 def int_hexagon_F2_conv_sf2df :
3475 Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">;
3476
3477 def int_hexagon_S2_vtrunohb :
3478 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">;
3479
3480 def int_hexagon_F2_conv_sf2d_chop :
3481 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">;
3482
3483 def int_hexagon_M2_mpyd_lh_s0 :
3484 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;
3485
3486 def int_hexagon_F2_conv_df2w :
3487 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">;
3488
3489 def int_hexagon_S5_asrhub_sat :
3490 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [ImmArg<1>]>;
3491
3492 def int_hexagon_S2_asl_i_r_xacc :
3493 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [ImmArg<2>]>;
3494
3495 def int_hexagon_F2_conv_df2d :
3496 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">;
3497
3498 def int_hexagon_M2_mmaculs_s1 :
3499 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">;
3500
3501 def int_hexagon_M2_mmaculs_s0 :
3502 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">;
3503
3504 def int_hexagon_A2_svadduhs :
3505 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">;
3506
3507 def int_hexagon_F2_conv_sf2w_chop :
3508 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">;
3509
3510 def int_hexagon_S2_svsathub :
3511 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">;
3512
3513 def int_hexagon_M2_mpyd_rnd_hl_s1 :
3514 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">;
3515
3516 def int_hexagon_M2_mpyd_rnd_hl_s0 :
3517 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">;
3518
3519 def int_hexagon_S2_setbit_r :
3520 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">;
3521
3522 def int_hexagon_A2_vavghr :
3523 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">;
3524
3525 def int_hexagon_F2_sffma_sc :
3526 Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc">;
3527
3528 def int_hexagon_F2_dfclass :
3529 Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [ImmArg<1>]>;
3530
3531 def int_hexagon_F2_conv_df2ud :
3532 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">;
3533
3534 def int_hexagon_F2_conv_df2uw :
3535 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">;
3536
3537 def int_hexagon_M2_cmpyrs_s0 :
3538 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;
3539
3540 def int_hexagon_M2_cmpyrs_s1 :
3541 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;
3542
3543 def int_hexagon_C4_cmpltei :
3544 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [ImmArg<1>]>;
3545
3546 def int_hexagon_C4_cmplteu :
3547 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">;
3548
3549 def int_hexagon_A2_vsubb_map :
3550 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">;
3551
3552 def int_hexagon_A2_subh_l16_ll :
3553 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">;
3554
3555 def int_hexagon_S2_asr_i_r_rnd :
3556 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [ImmArg<1>]>;
3557
3558 def int_hexagon_M2_vrmpy_s0 :
3559 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">;
3560
3561 def int_hexagon_M2_mpyd_rnd_hh_s1 :
3562 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;
3563
3564 def int_hexagon_M2_mpyd_rnd_hh_s0 :
3565 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">;
3566
3567 def int_hexagon_A2_minup :
3568 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">;
3569
3570 def int_hexagon_S2_valignrb :
3571 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">;
3572
3573 def int_hexagon_S2_asr_r_p_acc :
3574 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">;
3575
3576 def int_hexagon_M2_mmpyl_rs0 :
3577 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">;
3578
3579 def int_hexagon_M2_vrcmaci_s0 :
3580 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">;
3581
3582 def int_hexagon_A2_vaddub :
3583 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">;
3584
3585 def int_hexagon_A2_combine_lh :
3586 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">;
3587
3588 def int_hexagon_M5_vdmacbsu :
3589 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">;
3590
3591 def int_hexagon_A2_combine_ll :
3592 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">;
3593
3594 def int_hexagon_M2_mpyud_hl_s0 :
3595 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;
3596
3597 def int_hexagon_M2_vrcmpyi_s0c :
3598 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;
3599
3600 def int_hexagon_S2_asr_i_p_rnd :
3601 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [ImmArg<1>]>;
3602
3603 def int_hexagon_A2_addpsat :
3604 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">;
3605
3606 def int_hexagon_A2_svaddhs :
3607 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">;
3608
3609 def int_hexagon_S4_ori_lsr_ri :
3610 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
3611
3612 def int_hexagon_M2_mpy_sat_rnd_ll_s1 :
3613 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;
3614
3615 def int_hexagon_M2_mpy_sat_rnd_ll_s0 :
3616 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;
3617
3618 def int_hexagon_A2_vminw :
3619 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">;
3620
3621 def int_hexagon_A2_vminh :
3622 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">;
3623
3624 def int_hexagon_M2_vrcmpyr_s0 :
3625 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">;
3626
3627 def int_hexagon_A2_vminb :
3628 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">;
3629
3630 def int_hexagon_M2_vcmac_s0_sat_i :
3631 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">;
3632
3633 def int_hexagon_M2_mpyud_lh_s0 :
3634 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">;
3635
3636 def int_hexagon_M2_mpyud_lh_s1 :
3637 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;
3638
3639 def int_hexagon_S2_asl_r_r_or :
3640 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">;
3641
3642 def int_hexagon_S4_lsli :
3643 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [ImmArg<0>]>;
3644
3645 def int_hexagon_S2_lsl_r_vw :
3646 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">;
3647
3648 def int_hexagon_M2_mpy_hh_s1 :
3649 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;
3650
3651 def int_hexagon_M4_vrmpyeh_s0 :
3652 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">;
3653
3654 def int_hexagon_M4_vrmpyeh_s1 :
3655 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">;
3656
3657 def int_hexagon_M2_mpy_nac_lh_s0 :
3658 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">;
3659
3660 def int_hexagon_M2_mpy_nac_lh_s1 :
3661 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">;
3662
3663 def int_hexagon_M2_vraddh :
3664 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">;
3665
3666 def int_hexagon_C2_tfrrp :
3667 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">;
3668
3669 def int_hexagon_M2_mpy_acc_sat_ll_s0 :
3670 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">;
3671
3672 def int_hexagon_M2_mpy_acc_sat_ll_s1 :
3673 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">;
3674
3675 def int_hexagon_S2_vtrunowh :
3676 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">;
3677
3678 def int_hexagon_A2_abs :
3679 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">;
3680
3681 def int_hexagon_A4_cmpbeq :
3682 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">;
3683
3684 def int_hexagon_A2_negp :
3685 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">;
3686
3687 def int_hexagon_S2_asl_i_r_sat :
3688 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [ImmArg<1>]>;
3689
3690 def int_hexagon_A2_addh_l16_sat_hl :
3691 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;
3692
3693 def int_hexagon_S2_vsatwuh :
3694 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">;
3695
3696 def int_hexagon_F2_dfcmpgt :
3697 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt">;
3698
3699 def int_hexagon_S2_svsathb :
3700 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">;
3701
3702 def int_hexagon_C2_cmpgtup :
3703 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">;
3704
3705 def int_hexagon_A4_cround_ri :
3706 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [ImmArg<1>]>;
3707
3708 def int_hexagon_S4_clbpaddi :
3709 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [ImmArg<1>]>;
3710
3711 def int_hexagon_A4_cround_rr :
3712 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">;
3713
3714 def int_hexagon_C2_mux :
3715 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">;
3716
3717 def int_hexagon_M2_dpmpyuu_s0 :
3718 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">;
3719
3720 def int_hexagon_S2_shuffeb :
3721 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">;
3722
3723 def int_hexagon_A2_vminuw :
3724 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">;
3725
3726 def int_hexagon_A2_vaddhs :
3727 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">;
3728
3729 def int_hexagon_S2_insert_rp :
3730 Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">;
3731
3732 def int_hexagon_A2_vminuh :
3733 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">;
3734
3735 def int_hexagon_A2_vminub :
3736 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">;
3737
3738 def int_hexagon_S2_extractu :
3739 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [ImmArg<1>, ImmArg<2>]>;
3740
3741 def int_hexagon_A2_svsubh :
3742 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">;
3743
3744 def int_hexagon_S4_clbaddi :
3745 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [ImmArg<1>]>;
3746
3747 def int_hexagon_F2_sffms :
3748 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms">;
3749
3750 def int_hexagon_S2_vsxtbh :
3751 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">;
3752
3753 def int_hexagon_M2_mpyud_nac_ll_s1 :
3754 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">;
3755
3756 def int_hexagon_M2_mpyud_nac_ll_s0 :
3757 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">;
3758
3759 def int_hexagon_A2_subp :
3760 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">;
3761
3762 def int_hexagon_M2_vmpy2es_s1 :
3763 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">;
3764
3765 def int_hexagon_M2_vmpy2es_s0 :
3766 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">;
3767
3768 def int_hexagon_S4_parity :
3769 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">;
3770
3771 def int_hexagon_M2_mpy_acc_hh_s1 :
3772 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;
3773
3774 def int_hexagon_M2_mpy_acc_hh_s0 :
3775 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;
3776
3777 def int_hexagon_S4_addi_asl_ri :
3778 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [ImmArg<0>, ImmArg<2>]>;
3779
3780 def int_hexagon_M2_mpyd_nac_hh_s1 :
3781 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;
3782
3783 def int_hexagon_M2_mpyd_nac_hh_s0 :
3784 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;
3785
3786 def int_hexagon_S2_asr_i_r_nac :
3787 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [ImmArg<2>]>;
3788
3789 def int_hexagon_A4_cmpheqi :
3790 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [ImmArg<1>]>;
3791
3792 def int_hexagon_S2_lsr_r_p_xor :
3793 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;
3794
3795 def int_hexagon_M2_mpy_acc_hl_s1 :
3796 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;
3797
3798 def int_hexagon_M2_mpy_acc_hl_s0 :
3799 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;
3800
3801 def int_hexagon_F2_conv_sf2ud_chop :
3802 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;
3803
3804 def int_hexagon_C2_cmpgeui :
3805 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [ImmArg<1>]>;
3806
3807 def int_hexagon_M2_mpy_acc_sat_hh_s0 :
3808 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;
3809
3810 def int_hexagon_M2_mpy_acc_sat_hh_s1 :
3811 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;
3812
3813 def int_hexagon_S2_asl_r_p_and :
3814 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">;
3815
3816 def int_hexagon_A2_addh_h16_sat_lh :
3817 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">;
3818
3819 def int_hexagon_A2_addh_h16_sat_ll :
3820 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">;
3821
3822 def int_hexagon_M4_nac_up_s1_sat :
3823 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">;
3824
3825 def int_hexagon_M2_mpyud_nac_lh_s1 :
3826 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;
3827
3828 def int_hexagon_M2_mpyud_nac_lh_s0 :
3829 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;
3830
3831 def int_hexagon_A4_round_ri_sat :
3832 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [ImmArg<1>]>;
3833
3834 def int_hexagon_M2_mpy_nac_hl_s0 :
3835 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;
3836
3837 def int_hexagon_M2_mpy_nac_hl_s1 :
3838 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;
3839
3840 def int_hexagon_A2_vavghcr :
3841 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">;
3842
3843 def int_hexagon_M2_mmacls_rs0 :
3844 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">;
3845
3846 def int_hexagon_M2_mmacls_rs1 :
3847 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">;
3848
3849 def int_hexagon_M2_cmaci_s0 :
3850 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">;
3851
3852 def int_hexagon_S2_setbit_i :
3853 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [ImmArg<1>]>;
3854
3855 def int_hexagon_S2_asl_i_p_or :
3856 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [ImmArg<2>]>;
3857
3858 def int_hexagon_A4_andn :
3859 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">;
3860
3861 def int_hexagon_M5_vrmpybsu :
3862 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">;
3863
3864 def int_hexagon_S2_vrndpackwh :
3865 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">;
3866
3867 def int_hexagon_M2_vcmac_s0_sat_r :
3868 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;
3869
3870 def int_hexagon_A2_vmaxuw :
3871 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">;
3872
3873 def int_hexagon_C2_bitsclr :
3874 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">;
3875
3876 def int_hexagon_M2_xor_xacc :
3877 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">;
3878
3879 def int_hexagon_A4_vcmpbgtui :
3880 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [ImmArg<1>]>;
3881
3882 def int_hexagon_A4_ornp :
3883 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">;
3884
3885 def int_hexagon_A2_tfrpi :
3886 Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [ImmArg<0>]>;
3887
3888 def int_hexagon_C4_and_or :
3889 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">;
3890
3891 def int_hexagon_M2_mpy_nac_sat_hh_s1 :
3892 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;
3893
3894 def int_hexagon_M2_mpy_nac_sat_hh_s0 :
3895 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;
3896
3897 def int_hexagon_A2_subh_h16_sat_ll :
3898 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;
3899
3900 def int_hexagon_A2_subh_h16_sat_lh :
3901 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;
3902
3903 def int_hexagon_M2_vmpy2su_s1 :
3904 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;
3905
3906 def int_hexagon_M2_vmpy2su_s0 :
3907 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;
3908
3909 def int_hexagon_S2_asr_i_p_acc :
3910 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [ImmArg<2>]>;
3911
3912 def int_hexagon_C4_nbitsclri :
3913 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [ImmArg<1>]>;
3914
3915 def int_hexagon_S2_lsr_i_vh :
3916 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [ImmArg<1>]>;
3917
3918 def int_hexagon_S2_lsr_i_p_xacc :
3919 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [ImmArg<2>]>;
3920
3921 // V55 Scalar Instructions.
3922
3923 def int_hexagon_A5_ACS :
3924 Hexagon_i64i32_i64i64i64_Intrinsic<"HEXAGON_A5_ACS">;
3925
3926 // V60 Scalar Instructions.
3927
3928 def int_hexagon_S6_rol_i_p_and :
3929 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [ImmArg<2>]>;
3930
3931 def int_hexagon_S6_rol_i_r_xacc :
3932 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [ImmArg<2>]>;
3933
3934 def int_hexagon_S6_rol_i_r_and :
3935 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [ImmArg<2>]>;
3936
3937 def int_hexagon_S6_rol_i_r_acc :
3938 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [ImmArg<2>]>;
3939
3940 def int_hexagon_S6_rol_i_p_xacc :
3941 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [ImmArg<2>]>;
3942
3943 def int_hexagon_S6_rol_i_p :
3944 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [ImmArg<1>]>;
3945
3946 def int_hexagon_S6_rol_i_p_nac :
3947 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [ImmArg<2>]>;
3948
3949 def int_hexagon_S6_rol_i_p_acc :
3950 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [ImmArg<2>]>;
3951
3952 def int_hexagon_S6_rol_i_r_or :
3953 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [ImmArg<2>]>;
3954
3955 def int_hexagon_S6_rol_i_r :
3956 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [ImmArg<1>]>;
3957
3958 def int_hexagon_S6_rol_i_r_nac :
3959 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [ImmArg<2>]>;
3960
3961 def int_hexagon_S6_rol_i_p_or :
3962 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [ImmArg<2>]>;
3963
3964 // V62 Scalar Instructions.
3965
3966 def int_hexagon_S6_vtrunehb_ppp :
3967 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">;
3968
3969 def int_hexagon_V6_ldntnt0 :
3970 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldntnt0">;
3971
3972 def int_hexagon_M6_vabsdiffub :
3973 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">;
3974
3975 def int_hexagon_S6_vtrunohb_ppp :
3976 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">;
3977
3978 def int_hexagon_M6_vabsdiffb :
3979 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">;
3980
3981 def int_hexagon_A6_vminub_RdP :
3982 Hexagon_i64i32_i64i64_Intrinsic<"HEXAGON_A6_vminub_RdP">;
3983
3984 def int_hexagon_S6_vsplatrbp :
3985 Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">;
3986
3987 // V65 Scalar Instructions.
3988
3989 def int_hexagon_A6_vcmpbeq_notany :
3990 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;
3991
3992 // V66 Scalar Instructions.
3993
3994 def int_hexagon_F2_dfsub :
3995 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub">;
3996
3997 def int_hexagon_F2_dfadd :
3998 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd">;
3999
4000 def int_hexagon_M2_mnaci :
4001 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">;
4002
4003 def int_hexagon_S2_mask :
4004 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [ImmArg<0>, ImmArg<1>]>;
4005
4006 // V60 HVX Instructions.
4007
4008 def int_hexagon_V6_veqb_or :
4009 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">;
4010
4011 def int_hexagon_V6_veqb_or_128B :
4012 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">;
4013
4014 def int_hexagon_V6_vminub :
4015 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">;
4016
4017 def int_hexagon_V6_vminub_128B :
4018 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">;
4019
4020 def int_hexagon_V6_vaslw_acc :
4021 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">;
4022
4023 def int_hexagon_V6_vaslw_acc_128B :
4024 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">;
4025
4026 def int_hexagon_V6_vmpyhvsrs :
4027 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">;
4028
4029 def int_hexagon_V6_vmpyhvsrs_128B :
4030 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">;
4031
4032 def int_hexagon_V6_vsathub :
4033 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">;
4034
4035 def int_hexagon_V6_vsathub_128B :
4036 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">;
4037
4038 def int_hexagon_V6_vaddh_dv :
4039 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">;
4040
4041 def int_hexagon_V6_vaddh_dv_128B :
4042 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">;
4043
4044 def int_hexagon_V6_vrmpybusi :
4045 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [ImmArg<2>]>;
4046
4047 def int_hexagon_V6_vrmpybusi_128B :
4048 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [ImmArg<2>]>;
4049
4050 def int_hexagon_V6_vshufoh :
4051 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">;
4052
4053 def int_hexagon_V6_vshufoh_128B :
4054 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">;
4055
4056 def int_hexagon_V6_vasrwv :
4057 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">;
4058
4059 def int_hexagon_V6_vasrwv_128B :
4060 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">;
4061
4062 def int_hexagon_V6_vdmpyhsuisat :
4063 Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">;
4064
4065 def int_hexagon_V6_vdmpyhsuisat_128B :
4066 Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">;
4067
4068 def int_hexagon_V6_vrsadubi_acc :
4069 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [ImmArg<3>]>;
4070
4071 def int_hexagon_V6_vrsadubi_acc_128B :
4072 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [ImmArg<3>]>;
4073
4074 def int_hexagon_V6_vnavgw :
4075 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">;
4076
4077 def int_hexagon_V6_vnavgw_128B :
4078 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">;
4079
4080 def int_hexagon_V6_vnavgh :
4081 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">;
4082
4083 def int_hexagon_V6_vnavgh_128B :
4084 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">;
4085
4086 def int_hexagon_V6_vavgub :
4087 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">;
4088
4089 def int_hexagon_V6_vavgub_128B :
4090 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">;
4091
4092 def int_hexagon_V6_vsubb :
4093 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">;
4094
4095 def int_hexagon_V6_vsubb_128B :
4096 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">;
4097
4098 def int_hexagon_V6_vgtw_and :
4099 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">;
4100
4101 def int_hexagon_V6_vgtw_and_128B :
4102 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">;
4103
4104 def int_hexagon_V6_vavgubrnd :
4105 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">;
4106
4107 def int_hexagon_V6_vavgubrnd_128B :
4108 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">;
4109
4110 def int_hexagon_V6_vrmpybusv :
4111 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">;
4112
4113 def int_hexagon_V6_vrmpybusv_128B :
4114 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">;
4115
4116 def int_hexagon_V6_vsubbnq :
4117 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">;
4118
4119 def int_hexagon_V6_vsubbnq_128B :
4120 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">;
4121
4122 def int_hexagon_V6_vroundhb :
4123 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">;
4124
4125 def int_hexagon_V6_vroundhb_128B :
4126 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">;
4127
4128 def int_hexagon_V6_vadduhsat_dv :
4129 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">;
4130
4131 def int_hexagon_V6_vadduhsat_dv_128B :
4132 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">;
4133
4134 def int_hexagon_V6_vsububsat :
4135 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">;
4136
4137 def int_hexagon_V6_vsububsat_128B :
4138 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">;
4139
4140 def int_hexagon_V6_vmpabus_acc :
4141 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">;
4142
4143 def int_hexagon_V6_vmpabus_acc_128B :
4144 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">;
4145
4146 def int_hexagon_V6_vmux :
4147 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">;
4148
4149 def int_hexagon_V6_vmux_128B :
4150 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">;
4151
4152 def int_hexagon_V6_vmpyhus :
4153 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">;
4154
4155 def int_hexagon_V6_vmpyhus_128B :
4156 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">;
4157
4158 def int_hexagon_V6_vpackeb :
4159 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">;
4160
4161 def int_hexagon_V6_vpackeb_128B :
4162 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">;
4163
4164 def int_hexagon_V6_vsubhnq :
4165 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">;
4166
4167 def int_hexagon_V6_vsubhnq_128B :
4168 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">;
4169
4170 def int_hexagon_V6_vavghrnd :
4171 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">;
4172
4173 def int_hexagon_V6_vavghrnd_128B :
4174 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">;
4175
4176 def int_hexagon_V6_vtran2x2_map :
4177 Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map">;
4178
4179 def int_hexagon_V6_vtran2x2_map_128B :
4180 Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map_128B">;
4181
4182 def int_hexagon_V6_vdelta :
4183 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">;
4184
4185 def int_hexagon_V6_vdelta_128B :
4186 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">;
4187
4188 def int_hexagon_V6_vgtuh_and :
4189 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">;
4190
4191 def int_hexagon_V6_vgtuh_and_128B :
4192 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">;
4193
4194 def int_hexagon_V6_vtmpyhb :
4195 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">;
4196
4197 def int_hexagon_V6_vtmpyhb_128B :
4198 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">;
4199
4200 def int_hexagon_V6_vpackob :
4201 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">;
4202
4203 def int_hexagon_V6_vpackob_128B :
4204 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">;
4205
4206 def int_hexagon_V6_vmaxh :
4207 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">;
4208
4209 def int_hexagon_V6_vmaxh_128B :
4210 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">;
4211
4212 def int_hexagon_V6_vtmpybus_acc :
4213 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">;
4214
4215 def int_hexagon_V6_vtmpybus_acc_128B :
4216 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">;
4217
4218 def int_hexagon_V6_vsubuhsat :
4219 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">;
4220
4221 def int_hexagon_V6_vsubuhsat_128B :
4222 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">;
4223
4224 def int_hexagon_V6_vasrw_acc :
4225 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">;
4226
4227 def int_hexagon_V6_vasrw_acc_128B :
4228 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">;
4229
4230 def int_hexagon_V6_pred_or :
4231 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or">;
4232
4233 def int_hexagon_V6_pred_or_128B :
4234 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_128B">;
4235
4236 def int_hexagon_V6_vrmpyub_acc :
4237 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">;
4238
4239 def int_hexagon_V6_vrmpyub_acc_128B :
4240 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">;
4241
4242 def int_hexagon_V6_lo :
4243 Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">;
4244
4245 def int_hexagon_V6_lo_128B :
4246 Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">;
4247
4248 def int_hexagon_V6_vsubb_dv :
4249 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">;
4250
4251 def int_hexagon_V6_vsubb_dv_128B :
4252 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">;
4253
4254 def int_hexagon_V6_vsubhsat_dv :
4255 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">;
4256
4257 def int_hexagon_V6_vsubhsat_dv_128B :
4258 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">;
4259
4260 def int_hexagon_V6_vmpyiwh :
4261 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">;
4262
4263 def int_hexagon_V6_vmpyiwh_128B :
4264 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">;
4265
4266 def int_hexagon_V6_vmpyiwb :
4267 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">;
4268
4269 def int_hexagon_V6_vmpyiwb_128B :
4270 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">;
4271
4272 def int_hexagon_V6_ldu0 :
4273 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldu0">;
4274
4275 def int_hexagon_V6_ldu0_128B :
4276 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldu0_128B">;
4277
4278 def int_hexagon_V6_vgtuh_xor :
4279 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">;
4280
4281 def int_hexagon_V6_vgtuh_xor_128B :
4282 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">;
4283
4284 def int_hexagon_V6_vgth_or :
4285 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">;
4286
4287 def int_hexagon_V6_vgth_or_128B :
4288 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">;
4289
4290 def int_hexagon_V6_vavgh :
4291 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">;
4292
4293 def int_hexagon_V6_vavgh_128B :
4294 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">;
4295
4296 def int_hexagon_V6_vlalignb :
4297 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">;
4298
4299 def int_hexagon_V6_vlalignb_128B :
4300 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">;
4301
4302 def int_hexagon_V6_vsh :
4303 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">;
4304
4305 def int_hexagon_V6_vsh_128B :
4306 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">;
4307
4308 def int_hexagon_V6_pred_and_n :
4309 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and_n">;
4310
4311 def int_hexagon_V6_pred_and_n_128B :
4312 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">;
4313
4314 def int_hexagon_V6_vsb :
4315 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">;
4316
4317 def int_hexagon_V6_vsb_128B :
4318 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">;
4319
4320 def int_hexagon_V6_vroundwuh :
4321 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">;
4322
4323 def int_hexagon_V6_vroundwuh_128B :
4324 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">;
4325
4326 def int_hexagon_V6_vasrhv :
4327 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">;
4328
4329 def int_hexagon_V6_vasrhv_128B :
4330 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">;
4331
4332 def int_hexagon_V6_vshuffh :
4333 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">;
4334
4335 def int_hexagon_V6_vshuffh_128B :
4336 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">;
4337
4338 def int_hexagon_V6_vaddhsat_dv :
4339 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">;
4340
4341 def int_hexagon_V6_vaddhsat_dv_128B :
4342 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">;
4343
4344 def int_hexagon_V6_vnavgub :
4345 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">;
4346
4347 def int_hexagon_V6_vnavgub_128B :
4348 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">;
4349
4350 def int_hexagon_V6_vrmpybv :
4351 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">;
4352
4353 def int_hexagon_V6_vrmpybv_128B :
4354 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">;
4355
4356 def int_hexagon_V6_vnormamth :
4357 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">;
4358
4359 def int_hexagon_V6_vnormamth_128B :
4360 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">;
4361
4362 def int_hexagon_V6_vdmpyhb :
4363 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">;
4364
4365 def int_hexagon_V6_vdmpyhb_128B :
4366 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">;
4367
4368 def int_hexagon_V6_vavguh :
4369 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">;
4370
4371 def int_hexagon_V6_vavguh_128B :
4372 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">;
4373
4374 def int_hexagon_V6_vlsrwv :
4375 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">;
4376
4377 def int_hexagon_V6_vlsrwv_128B :
4378 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">;
4379
4380 def int_hexagon_V6_vlsrhv :
4381 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">;
4382
4383 def int_hexagon_V6_vlsrhv_128B :
4384 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">;
4385
4386 def int_hexagon_V6_vdmpyhisat :
4387 Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">;
4388
4389 def int_hexagon_V6_vdmpyhisat_128B :
4390 Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">;
4391
4392 def int_hexagon_V6_vdmpyhvsat :
4393 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">;
4394
4395 def int_hexagon_V6_vdmpyhvsat_128B :
4396 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">;
4397
4398 def int_hexagon_V6_vaddw :
4399 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">;
4400
4401 def int_hexagon_V6_vaddw_128B :
4402 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">;
4403
4404 def int_hexagon_V6_vzh :
4405 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">;
4406
4407 def int_hexagon_V6_vzh_128B :
4408 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">;
4409
4410 def int_hexagon_V6_vaddh :
4411 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">;
4412
4413 def int_hexagon_V6_vaddh_128B :
4414 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">;
4415
4416 def int_hexagon_V6_vmaxub :
4417 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">;
4418
4419 def int_hexagon_V6_vmaxub_128B :
4420 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">;
4421
4422 def int_hexagon_V6_vmpyhv_acc :
4423 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">;
4424
4425 def int_hexagon_V6_vmpyhv_acc_128B :
4426 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">;
4427
4428 def int_hexagon_V6_vadduhsat :
4429 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">;
4430
4431 def int_hexagon_V6_vadduhsat_128B :
4432 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">;
4433
4434 def int_hexagon_V6_vshufoeh :
4435 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">;
4436
4437 def int_hexagon_V6_vshufoeh_128B :
4438 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">;
4439
4440 def int_hexagon_V6_vmpyuhv_acc :
4441 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">;
4442
4443 def int_hexagon_V6_vmpyuhv_acc_128B :
4444 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">;
4445
4446 def int_hexagon_V6_veqh :
4447 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">;
4448
4449 def int_hexagon_V6_veqh_128B :
4450 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">;
4451
4452 def int_hexagon_V6_vmpabuuv :
4453 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">;
4454
4455 def int_hexagon_V6_vmpabuuv_128B :
4456 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">;
4457
4458 def int_hexagon_V6_vasrwhsat :
4459 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">;
4460
4461 def int_hexagon_V6_vasrwhsat_128B :
4462 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">;
4463
4464 def int_hexagon_V6_vminuh :
4465 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">;
4466
4467 def int_hexagon_V6_vminuh_128B :
4468 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">;
4469
4470 def int_hexagon_V6_vror :
4471 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">;
4472
4473 def int_hexagon_V6_vror_128B :
4474 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">;
4475
4476 def int_hexagon_V6_vmpyowh_rnd_sacc :
4477 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">;
4478
4479 def int_hexagon_V6_vmpyowh_rnd_sacc_128B :
4480 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">;
4481
4482 def int_hexagon_V6_vmaxuh :
4483 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">;
4484
4485 def int_hexagon_V6_vmaxuh_128B :
4486 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">;
4487
4488 def int_hexagon_V6_vabsh_sat :
4489 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">;
4490
4491 def int_hexagon_V6_vabsh_sat_128B :
4492 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">;
4493
4494 def int_hexagon_V6_pred_or_n :
4495 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or_n">;
4496
4497 def int_hexagon_V6_pred_or_n_128B :
4498 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">;
4499
4500 def int_hexagon_V6_vdealb :
4501 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">;
4502
4503 def int_hexagon_V6_vdealb_128B :
4504 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">;
4505
4506 def int_hexagon_V6_vmpybusv :
4507 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">;
4508
4509 def int_hexagon_V6_vmpybusv_128B :
4510 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">;
4511
4512 def int_hexagon_V6_vzb :
4513 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">;
4514
4515 def int_hexagon_V6_vzb_128B :
4516 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">;
4517
4518 def int_hexagon_V6_vdmpybus_dv :
4519 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">;
4520
4521 def int_hexagon_V6_vdmpybus_dv_128B :
4522 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">;
4523
4524 def int_hexagon_V6_vaddbq :
4525 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">;
4526
4527 def int_hexagon_V6_vaddbq_128B :
4528 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">;
4529
4530 def int_hexagon_V6_vaddb :
4531 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">;
4532
4533 def int_hexagon_V6_vaddb_128B :
4534 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">;
4535
4536 def int_hexagon_V6_vaddwq :
4537 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">;
4538
4539 def int_hexagon_V6_vaddwq_128B :
4540 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">;
4541
4542 def int_hexagon_V6_vasrhubrndsat :
4543 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">;
4544
4545 def int_hexagon_V6_vasrhubrndsat_128B :
4546 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">;
4547
4548 def int_hexagon_V6_vasrhubsat :
4549 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">;
4550
4551 def int_hexagon_V6_vasrhubsat_128B :
4552 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">;
4553
4554 def int_hexagon_V6_vshufoeb :
4555 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">;
4556
4557 def int_hexagon_V6_vshufoeb_128B :
4558 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">;
4559
4560 def int_hexagon_V6_vpackhub_sat :
4561 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">;
4562
4563 def int_hexagon_V6_vpackhub_sat_128B :
4564 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">;
4565
4566 def int_hexagon_V6_vmpyiwh_acc :
4567 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">;
4568
4569 def int_hexagon_V6_vmpyiwh_acc_128B :
4570 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">;
4571
4572 def int_hexagon_V6_vtmpyb :
4573 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">;
4574
4575 def int_hexagon_V6_vtmpyb_128B :
4576 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">;
4577
4578 def int_hexagon_V6_vmpabusv :
4579 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">;
4580
4581 def int_hexagon_V6_vmpabusv_128B :
4582 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">;
4583
4584 def int_hexagon_V6_pred_and :
4585 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and">;
4586
4587 def int_hexagon_V6_pred_and_128B :
4588 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_128B">;
4589
4590 def int_hexagon_V6_vsubwnq :
4591 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">;
4592
4593 def int_hexagon_V6_vsubwnq_128B :
4594 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">;
4595
4596 def int_hexagon_V6_vpackwuh_sat :
4597 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">;
4598
4599 def int_hexagon_V6_vpackwuh_sat_128B :
4600 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">;
4601
4602 def int_hexagon_V6_vswap :
4603 Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">;
4604
4605 def int_hexagon_V6_vswap_128B :
4606 Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">;
4607
4608 def int_hexagon_V6_vrmpyubv_acc :
4609 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">;
4610
4611 def int_hexagon_V6_vrmpyubv_acc_128B :
4612 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">;
4613
4614 def int_hexagon_V6_vgtb_and :
4615 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">;
4616
4617 def int_hexagon_V6_vgtb_and_128B :
4618 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">;
4619
4620 def int_hexagon_V6_vaslw :
4621 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">;
4622
4623 def int_hexagon_V6_vaslw_128B :
4624 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">;
4625
4626 def int_hexagon_V6_vpackhb_sat :
4627 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">;
4628
4629 def int_hexagon_V6_vpackhb_sat_128B :
4630 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">;
4631
4632 def int_hexagon_V6_vmpyih_acc :
4633 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">;
4634
4635 def int_hexagon_V6_vmpyih_acc_128B :
4636 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">;
4637
4638 def int_hexagon_V6_vshuffvdd :
4639 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">;
4640
4641 def int_hexagon_V6_vshuffvdd_128B :
4642 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">;
4643
4644 def int_hexagon_V6_vaddb_dv :
4645 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">;
4646
4647 def int_hexagon_V6_vaddb_dv_128B :
4648 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">;
4649
4650 def int_hexagon_V6_vunpackub :
4651 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">;
4652
4653 def int_hexagon_V6_vunpackub_128B :
4654 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">;
4655
4656 def int_hexagon_V6_vgtuw :
4657 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">;
4658
4659 def int_hexagon_V6_vgtuw_128B :
4660 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">;
4661
4662 def int_hexagon_V6_vlutvwh :
4663 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">;
4664
4665 def int_hexagon_V6_vlutvwh_128B :
4666 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">;
4667
4668 def int_hexagon_V6_vgtub :
4669 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">;
4670
4671 def int_hexagon_V6_vgtub_128B :
4672 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">;
4673
4674 def int_hexagon_V6_vmpyowh :
4675 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">;
4676
4677 def int_hexagon_V6_vmpyowh_128B :
4678 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">;
4679
4680 def int_hexagon_V6_vmpyieoh :
4681 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">;
4682
4683 def int_hexagon_V6_vmpyieoh_128B :
4684 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">;
4685
4686 def int_hexagon_V6_extractw :
4687 Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">;
4688
4689 def int_hexagon_V6_extractw_128B :
4690 Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">;
4691
4692 def int_hexagon_V6_vavgwrnd :
4693 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">;
4694
4695 def int_hexagon_V6_vavgwrnd_128B :
4696 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">;
4697
4698 def int_hexagon_V6_vdmpyhsat_acc :
4699 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">;
4700
4701 def int_hexagon_V6_vdmpyhsat_acc_128B :
4702 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">;
4703
4704 def int_hexagon_V6_vgtub_xor :
4705 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">;
4706
4707 def int_hexagon_V6_vgtub_xor_128B :
4708 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">;
4709
4710 def int_hexagon_V6_vmpyub :
4711 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">;
4712
4713 def int_hexagon_V6_vmpyub_128B :
4714 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">;
4715
4716 def int_hexagon_V6_vmpyuh :
4717 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">;
4718
4719 def int_hexagon_V6_vmpyuh_128B :
4720 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">;
4721
4722 def int_hexagon_V6_vunpackob :
4723 Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">;
4724
4725 def int_hexagon_V6_vunpackob_128B :
4726 Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">;
4727
4728 def int_hexagon_V6_vmpahb :
4729 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">;
4730
4731 def int_hexagon_V6_vmpahb_128B :
4732 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">;
4733
4734 def int_hexagon_V6_veqw_or :
4735 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">;
4736
4737 def int_hexagon_V6_veqw_or_128B :
4738 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">;
4739
4740 def int_hexagon_V6_vandqrt :
4741 Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt">;
4742
4743 def int_hexagon_V6_vandqrt_128B :
4744 Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">;
4745
4746 def int_hexagon_V6_vxor :
4747 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">;
4748
4749 def int_hexagon_V6_vxor_128B :
4750 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">;
4751
4752 def int_hexagon_V6_vasrwhrndsat :
4753 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">;
4754
4755 def int_hexagon_V6_vasrwhrndsat_128B :
4756 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">;
4757
4758 def int_hexagon_V6_vmpyhsat_acc :
4759 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">;
4760
4761 def int_hexagon_V6_vmpyhsat_acc_128B :
4762 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">;
4763
4764 def int_hexagon_V6_vrmpybus_acc :
4765 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">;
4766
4767 def int_hexagon_V6_vrmpybus_acc_128B :
4768 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">;
4769
4770 def int_hexagon_V6_vsubhw :
4771 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">;
4772
4773 def int_hexagon_V6_vsubhw_128B :
4774 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">;
4775
4776 def int_hexagon_V6_vdealb4w :
4777 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">;
4778
4779 def int_hexagon_V6_vdealb4w_128B :
4780 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">;
4781
4782 def int_hexagon_V6_vmpyowh_sacc :
4783 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">;
4784
4785 def int_hexagon_V6_vmpyowh_sacc_128B :
4786 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">;
4787
4788 def int_hexagon_V6_vmpybv :
4789 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">;
4790
4791 def int_hexagon_V6_vmpybv_128B :
4792 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">;
4793
4794 def int_hexagon_V6_vabsdiffh :
4795 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">;
4796
4797 def int_hexagon_V6_vabsdiffh_128B :
4798 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">;
4799
4800 def int_hexagon_V6_vshuffob :
4801 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">;
4802
4803 def int_hexagon_V6_vshuffob_128B :
4804 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">;
4805
4806 def int_hexagon_V6_vmpyub_acc :
4807 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">;
4808
4809 def int_hexagon_V6_vmpyub_acc_128B :
4810 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">;
4811
4812 def int_hexagon_V6_vnormamtw :
4813 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">;
4814
4815 def int_hexagon_V6_vnormamtw_128B :
4816 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">;
4817
4818 def int_hexagon_V6_vunpackuh :
4819 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">;
4820
4821 def int_hexagon_V6_vunpackuh_128B :
4822 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">;
4823
4824 def int_hexagon_V6_vgtuh_or :
4825 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">;
4826
4827 def int_hexagon_V6_vgtuh_or_128B :
4828 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">;
4829
4830 def int_hexagon_V6_vmpyiewuh_acc :
4831 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">;
4832
4833 def int_hexagon_V6_vmpyiewuh_acc_128B :
4834 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">;
4835
4836 def int_hexagon_V6_vunpackoh :
4837 Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">;
4838
4839 def int_hexagon_V6_vunpackoh_128B :
4840 Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">;
4841
4842 def int_hexagon_V6_vdmpyhsat :
4843 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">;
4844
4845 def int_hexagon_V6_vdmpyhsat_128B :
4846 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">;
4847
4848 def int_hexagon_V6_vmpyubv :
4849 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">;
4850
4851 def int_hexagon_V6_vmpyubv_128B :
4852 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">;
4853
4854 def int_hexagon_V6_vmpyhss :
4855 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">;
4856
4857 def int_hexagon_V6_vmpyhss_128B :
4858 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">;
4859
4860 def int_hexagon_V6_hi :
4861 Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">;
4862
4863 def int_hexagon_V6_hi_128B :
4864 Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">;
4865
4866 def int_hexagon_V6_vasrwuhsat :
4867 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">;
4868
4869 def int_hexagon_V6_vasrwuhsat_128B :
4870 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">;
4871
4872 def int_hexagon_V6_veqw :
4873 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">;
4874
4875 def int_hexagon_V6_veqw_128B :
4876 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">;
4877
4878 def int_hexagon_V6_vdsaduh :
4879 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">;
4880
4881 def int_hexagon_V6_vdsaduh_128B :
4882 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">;
4883
4884 def int_hexagon_V6_vsubw :
4885 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">;
4886
4887 def int_hexagon_V6_vsubw_128B :
4888 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">;
4889
4890 def int_hexagon_V6_vsubw_dv :
4891 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">;
4892
4893 def int_hexagon_V6_vsubw_dv_128B :
4894 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">;
4895
4896 def int_hexagon_V6_veqb_and :
4897 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">;
4898
4899 def int_hexagon_V6_veqb_and_128B :
4900 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">;
4901
4902 def int_hexagon_V6_vmpyih :
4903 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">;
4904
4905 def int_hexagon_V6_vmpyih_128B :
4906 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">;
4907
4908 def int_hexagon_V6_vtmpyb_acc :
4909 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">;
4910
4911 def int_hexagon_V6_vtmpyb_acc_128B :
4912 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">;
4913
4914 def int_hexagon_V6_vrmpybus :
4915 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">;
4916
4917 def int_hexagon_V6_vrmpybus_128B :
4918 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">;
4919
4920 def int_hexagon_V6_vmpybus_acc :
4921 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">;
4922
4923 def int_hexagon_V6_vmpybus_acc_128B :
4924 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">;
4925
4926 def int_hexagon_V6_vgth_xor :
4927 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">;
4928
4929 def int_hexagon_V6_vgth_xor_128B :
4930 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">;
4931
4932 def int_hexagon_V6_vsubhsat :
4933 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">;
4934
4935 def int_hexagon_V6_vsubhsat_128B :
4936 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">;
4937
4938 def int_hexagon_V6_vrmpyubi_acc :
4939 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [ImmArg<3>]>;
4940
4941 def int_hexagon_V6_vrmpyubi_acc_128B :
4942 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [ImmArg<3>]>;
4943
4944 def int_hexagon_V6_vabsw :
4945 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">;
4946
4947 def int_hexagon_V6_vabsw_128B :
4948 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">;
4949
4950 def int_hexagon_V6_vaddwsat_dv :
4951 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">;
4952
4953 def int_hexagon_V6_vaddwsat_dv_128B :
4954 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">;
4955
4956 def int_hexagon_V6_vlsrw :
4957 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">;
4958
4959 def int_hexagon_V6_vlsrw_128B :
4960 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">;
4961
4962 def int_hexagon_V6_vabsh :
4963 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">;
4964
4965 def int_hexagon_V6_vabsh_128B :
4966 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">;
4967
4968 def int_hexagon_V6_vlsrh :
4969 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">;
4970
4971 def int_hexagon_V6_vlsrh_128B :
4972 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">;
4973
4974 def int_hexagon_V6_valignb :
4975 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">;
4976
4977 def int_hexagon_V6_valignb_128B :
4978 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">;
4979
4980 def int_hexagon_V6_vsubhq :
4981 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">;
4982
4983 def int_hexagon_V6_vsubhq_128B :
4984 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">;
4985
4986 def int_hexagon_V6_vpackoh :
4987 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">;
4988
4989 def int_hexagon_V6_vpackoh_128B :
4990 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">;
4991
4992 def int_hexagon_V6_vdmpybus_acc :
4993 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">;
4994
4995 def int_hexagon_V6_vdmpybus_acc_128B :
4996 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">;
4997
4998 def int_hexagon_V6_vdmpyhvsat_acc :
4999 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">;
5000
5001 def int_hexagon_V6_vdmpyhvsat_acc_128B :
5002 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">;
5003
5004 def int_hexagon_V6_vrmpybv_acc :
5005 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">;
5006
5007 def int_hexagon_V6_vrmpybv_acc_128B :
5008 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">;
5009
5010 def int_hexagon_V6_vaddhsat :
5011 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">;
5012
5013 def int_hexagon_V6_vaddhsat_128B :
5014 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">;
5015
5016 def int_hexagon_V6_vcombine :
5017 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">;
5018
5019 def int_hexagon_V6_vcombine_128B :
5020 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">;
5021
5022 def int_hexagon_V6_vandqrt_acc :
5023 Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">;
5024
5025 def int_hexagon_V6_vandqrt_acc_128B :
5026 Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">;
5027
5028 def int_hexagon_V6_vaslhv :
5029 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">;
5030
5031 def int_hexagon_V6_vaslhv_128B :
5032 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">;
5033
5034 def int_hexagon_V6_vinsertwr :
5035 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">;
5036
5037 def int_hexagon_V6_vinsertwr_128B :
5038 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">;
5039
5040 def int_hexagon_V6_vsubh_dv :
5041 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">;
5042
5043 def int_hexagon_V6_vsubh_dv_128B :
5044 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">;
5045
5046 def int_hexagon_V6_vshuffb :
5047 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">;
5048
5049 def int_hexagon_V6_vshuffb_128B :
5050 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">;
5051
5052 def int_hexagon_V6_vand :
5053 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">;
5054
5055 def int_hexagon_V6_vand_128B :
5056 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">;
5057
5058 def int_hexagon_V6_vmpyhv :
5059 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">;
5060
5061 def int_hexagon_V6_vmpyhv_128B :
5062 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">;
5063
5064 def int_hexagon_V6_vdmpyhsuisat_acc :
5065 Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">;
5066
5067 def int_hexagon_V6_vdmpyhsuisat_acc_128B :
5068 Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">;
5069
5070 def int_hexagon_V6_vsububsat_dv :
5071 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">;
5072
5073 def int_hexagon_V6_vsububsat_dv_128B :
5074 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">;
5075
5076 def int_hexagon_V6_vgtb_xor :
5077 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">;
5078
5079 def int_hexagon_V6_vgtb_xor_128B :
5080 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">;
5081
5082 def int_hexagon_V6_vdsaduh_acc :
5083 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">;
5084
5085 def int_hexagon_V6_vdsaduh_acc_128B :
5086 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">;
5087
5088 def int_hexagon_V6_vrmpyub :
5089 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">;
5090
5091 def int_hexagon_V6_vrmpyub_128B :
5092 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">;
5093
5094 def int_hexagon_V6_vmpyuh_acc :
5095 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">;
5096
5097 def int_hexagon_V6_vmpyuh_acc_128B :
5098 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">;
5099
5100 def int_hexagon_V6_vcl0h :
5101 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">;
5102
5103 def int_hexagon_V6_vcl0h_128B :
5104 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">;
5105
5106 def int_hexagon_V6_vmpyhus_acc :
5107 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">;
5108
5109 def int_hexagon_V6_vmpyhus_acc_128B :
5110 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">;
5111
5112 def int_hexagon_V6_vmpybv_acc :
5113 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">;
5114
5115 def int_hexagon_V6_vmpybv_acc_128B :
5116 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">;
5117
5118 def int_hexagon_V6_vrsadubi :
5119 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [ImmArg<2>]>;
5120
5121 def int_hexagon_V6_vrsadubi_128B :
5122 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [ImmArg<2>]>;
5123
5124 def int_hexagon_V6_vdmpyhb_dv_acc :
5125 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">;
5126
5127 def int_hexagon_V6_vdmpyhb_dv_acc_128B :
5128 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">;
5129
5130 def int_hexagon_V6_vshufeh :
5131 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">;
5132
5133 def int_hexagon_V6_vshufeh_128B :
5134 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">;
5135
5136 def int_hexagon_V6_vmpyewuh :
5137 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">;
5138
5139 def int_hexagon_V6_vmpyewuh_128B :
5140 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">;
5141
5142 def int_hexagon_V6_vmpyhsrs :
5143 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">;
5144
5145 def int_hexagon_V6_vmpyhsrs_128B :
5146 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">;
5147
5148 def int_hexagon_V6_vdmpybus_dv_acc :
5149 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">;
5150
5151 def int_hexagon_V6_vdmpybus_dv_acc_128B :
5152 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">;
5153
5154 def int_hexagon_V6_vaddubh :
5155 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">;
5156
5157 def int_hexagon_V6_vaddubh_128B :
5158 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">;
5159
5160 def int_hexagon_V6_vasrwh :
5161 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">;
5162
5163 def int_hexagon_V6_vasrwh_128B :
5164 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">;
5165
5166 def int_hexagon_V6_ld0 :
5167 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ld0">;
5168
5169 def int_hexagon_V6_ld0_128B :
5170 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ld0_128B">;
5171
5172 def int_hexagon_V6_vpopcounth :
5173 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">;
5174
5175 def int_hexagon_V6_vpopcounth_128B :
5176 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">;
5177
5178 def int_hexagon_V6_ldnt0 :
5179 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldnt0">;
5180
5181 def int_hexagon_V6_ldnt0_128B :
5182 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldnt0_128B">;
5183
5184 def int_hexagon_V6_vgth_and :
5185 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">;
5186
5187 def int_hexagon_V6_vgth_and_128B :
5188 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">;
5189
5190 def int_hexagon_V6_vaddubsat_dv :
5191 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">;
5192
5193 def int_hexagon_V6_vaddubsat_dv_128B :
5194 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">;
5195
5196 def int_hexagon_V6_vpackeh :
5197 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">;
5198
5199 def int_hexagon_V6_vpackeh_128B :
5200 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">;
5201
5202 def int_hexagon_V6_vmpyh :
5203 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">;
5204
5205 def int_hexagon_V6_vmpyh_128B :
5206 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">;
5207
5208 def int_hexagon_V6_vminh :
5209 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">;
5210
5211 def int_hexagon_V6_vminh_128B :
5212 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">;
5213
5214 def int_hexagon_V6_pred_scalar2 :
5215 Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">;
5216
5217 def int_hexagon_V6_pred_scalar2_128B :
5218 Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">;
5219
5220 def int_hexagon_V6_vdealh :
5221 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">;
5222
5223 def int_hexagon_V6_vdealh_128B :
5224 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">;
5225
5226 def int_hexagon_V6_vpackwh_sat :
5227 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">;
5228
5229 def int_hexagon_V6_vpackwh_sat_128B :
5230 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">;
5231
5232 def int_hexagon_V6_vaslh :
5233 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">;
5234
5235 def int_hexagon_V6_vaslh_128B :
5236 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">;
5237
5238 def int_hexagon_V6_vgtuw_and :
5239 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">;
5240
5241 def int_hexagon_V6_vgtuw_and_128B :
5242 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">;
5243
5244 def int_hexagon_V6_vor :
5245 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">;
5246
5247 def int_hexagon_V6_vor_128B :
5248 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">;
5249
5250 def int_hexagon_V6_vlutvvb :
5251 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">;
5252
5253 def int_hexagon_V6_vlutvvb_128B :
5254 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">;
5255
5256 def int_hexagon_V6_vmpyiowh :
5257 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">;
5258
5259 def int_hexagon_V6_vmpyiowh_128B :
5260 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">;
5261
5262 def int_hexagon_V6_vlutvvb_oracc :
5263 Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">;
5264
5265 def int_hexagon_V6_vlutvvb_oracc_128B :
5266 Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">;
5267
5268 def int_hexagon_V6_vandvrt :
5269 Hexagon_v512i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">;
5270
5271 def int_hexagon_V6_vandvrt_128B :
5272 Hexagon_v1024i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">;
5273
5274 def int_hexagon_V6_veqh_xor :
5275 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">;
5276
5277 def int_hexagon_V6_veqh_xor_128B :
5278 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">;
5279
5280 def int_hexagon_V6_vadduhw :
5281 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">;
5282
5283 def int_hexagon_V6_vadduhw_128B :
5284 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">;
5285
5286 def int_hexagon_V6_vcl0w :
5287 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">;
5288
5289 def int_hexagon_V6_vcl0w_128B :
5290 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">;
5291
5292 def int_hexagon_V6_vmpyihb :
5293 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">;
5294
5295 def int_hexagon_V6_vmpyihb_128B :
5296 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">;
5297
5298 def int_hexagon_V6_vtmpybus :
5299 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">;
5300
5301 def int_hexagon_V6_vtmpybus_128B :
5302 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">;
5303
5304 def int_hexagon_V6_vd0 :
5305 Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">;
5306
5307 def int_hexagon_V6_vd0_128B :
5308 Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">;
5309
5310 def int_hexagon_V6_veqh_or :
5311 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">;
5312
5313 def int_hexagon_V6_veqh_or_128B :
5314 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">;
5315
5316 def int_hexagon_V6_vgtw_or :
5317 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">;
5318
5319 def int_hexagon_V6_vgtw_or_128B :
5320 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">;
5321
5322 def int_hexagon_V6_vdmpybus :
5323 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">;
5324
5325 def int_hexagon_V6_vdmpybus_128B :
5326 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">;
5327
5328 def int_hexagon_V6_vgtub_or :
5329 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">;
5330
5331 def int_hexagon_V6_vgtub_or_128B :
5332 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">;
5333
5334 def int_hexagon_V6_vmpybus :
5335 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">;
5336
5337 def int_hexagon_V6_vmpybus_128B :
5338 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">;
5339
5340 def int_hexagon_V6_vdmpyhb_acc :
5341 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">;
5342
5343 def int_hexagon_V6_vdmpyhb_acc_128B :
5344 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">;
5345
5346 def int_hexagon_V6_vandvrt_acc :
5347 Hexagon_v512i1_v512i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">;
5348
5349 def int_hexagon_V6_vandvrt_acc_128B :
5350 Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">;
5351
5352 def int_hexagon_V6_vassign :
5353 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">;
5354
5355 def int_hexagon_V6_vassign_128B :
5356 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">;
5357
5358 def int_hexagon_V6_vaddwnq :
5359 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">;
5360
5361 def int_hexagon_V6_vaddwnq_128B :
5362 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">;
5363
5364 def int_hexagon_V6_vgtub_and :
5365 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">;
5366
5367 def int_hexagon_V6_vgtub_and_128B :
5368 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">;
5369
5370 def int_hexagon_V6_vdmpyhb_dv :
5371 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">;
5372
5373 def int_hexagon_V6_vdmpyhb_dv_128B :
5374 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">;
5375
5376 def int_hexagon_V6_vunpackb :
5377 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">;
5378
5379 def int_hexagon_V6_vunpackb_128B :
5380 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">;
5381
5382 def int_hexagon_V6_vunpackh :
5383 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">;
5384
5385 def int_hexagon_V6_vunpackh_128B :
5386 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">;
5387
5388 def int_hexagon_V6_vmpahb_acc :
5389 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">;
5390
5391 def int_hexagon_V6_vmpahb_acc_128B :
5392 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">;
5393
5394 def int_hexagon_V6_vaddbnq :
5395 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">;
5396
5397 def int_hexagon_V6_vaddbnq_128B :
5398 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">;
5399
5400 def int_hexagon_V6_vlalignbi :
5401 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [ImmArg<2>]>;
5402
5403 def int_hexagon_V6_vlalignbi_128B :
5404 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [ImmArg<2>]>;
5405
5406 def int_hexagon_V6_vsatwh :
5407 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">;
5408
5409 def int_hexagon_V6_vsatwh_128B :
5410 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">;
5411
5412 def int_hexagon_V6_vgtuh :
5413 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">;
5414
5415 def int_hexagon_V6_vgtuh_128B :
5416 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">;
5417
5418 def int_hexagon_V6_vmpyihb_acc :
5419 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">;
5420
5421 def int_hexagon_V6_vmpyihb_acc_128B :
5422 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">;
5423
5424 def int_hexagon_V6_vrmpybusv_acc :
5425 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">;
5426
5427 def int_hexagon_V6_vrmpybusv_acc_128B :
5428 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">;
5429
5430 def int_hexagon_V6_vrdelta :
5431 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">;
5432
5433 def int_hexagon_V6_vrdelta_128B :
5434 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">;
5435
5436 def int_hexagon_V6_vroundwh :
5437 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">;
5438
5439 def int_hexagon_V6_vroundwh_128B :
5440 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">;
5441
5442 def int_hexagon_V6_vaddw_dv :
5443 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">;
5444
5445 def int_hexagon_V6_vaddw_dv_128B :
5446 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">;
5447
5448 def int_hexagon_V6_vmpyiwb_acc :
5449 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">;
5450
5451 def int_hexagon_V6_vmpyiwb_acc_128B :
5452 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">;
5453
5454 def int_hexagon_V6_vsubbq :
5455 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">;
5456
5457 def int_hexagon_V6_vsubbq_128B :
5458 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">;
5459
5460 def int_hexagon_V6_veqh_and :
5461 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">;
5462
5463 def int_hexagon_V6_veqh_and_128B :
5464 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">;
5465
5466 def int_hexagon_V6_valignbi :
5467 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [ImmArg<2>]>;
5468
5469 def int_hexagon_V6_valignbi_128B :
5470 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [ImmArg<2>]>;
5471
5472 def int_hexagon_V6_vaddwsat :
5473 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">;
5474
5475 def int_hexagon_V6_vaddwsat_128B :
5476 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">;
5477
5478 def int_hexagon_V6_veqw_and :
5479 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">;
5480
5481 def int_hexagon_V6_veqw_and_128B :
5482 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">;
5483
5484 def int_hexagon_V6_vabsdiffub :
5485 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">;
5486
5487 def int_hexagon_V6_vabsdiffub_128B :
5488 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">;
5489
5490 def int_hexagon_V6_vshuffeb :
5491 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">;
5492
5493 def int_hexagon_V6_vshuffeb_128B :
5494 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">;
5495
5496 def int_hexagon_V6_vabsdiffuh :
5497 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">;
5498
5499 def int_hexagon_V6_vabsdiffuh_128B :
5500 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">;
5501
5502 def int_hexagon_V6_veqw_xor :
5503 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">;
5504
5505 def int_hexagon_V6_veqw_xor_128B :
5506 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">;
5507
5508 def int_hexagon_V6_vgth :
5509 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">;
5510
5511 def int_hexagon_V6_vgth_128B :
5512 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">;
5513
5514 def int_hexagon_V6_vgtuw_xor :
5515 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">;
5516
5517 def int_hexagon_V6_vgtuw_xor_128B :
5518 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">;
5519
5520 def int_hexagon_V6_vgtb :
5521 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">;
5522
5523 def int_hexagon_V6_vgtb_128B :
5524 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">;
5525
5526 def int_hexagon_V6_vgtw :
5527 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">;
5528
5529 def int_hexagon_V6_vgtw_128B :
5530 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">;
5531
5532 def int_hexagon_V6_vsubwq :
5533 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">;
5534
5535 def int_hexagon_V6_vsubwq_128B :
5536 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">;
5537
5538 def int_hexagon_V6_vnot :
5539 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">;
5540
5541 def int_hexagon_V6_vnot_128B :
5542 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">;
5543
5544 def int_hexagon_V6_vgtb_or :
5545 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">;
5546
5547 def int_hexagon_V6_vgtb_or_128B :
5548 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">;
5549
5550 def int_hexagon_V6_vgtuw_or :
5551 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">;
5552
5553 def int_hexagon_V6_vgtuw_or_128B :
5554 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">;
5555
5556 def int_hexagon_V6_vaddubsat :
5557 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">;
5558
5559 def int_hexagon_V6_vaddubsat_128B :
5560 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">;
5561
5562 def int_hexagon_V6_vmaxw :
5563 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">;
5564
5565 def int_hexagon_V6_vmaxw_128B :
5566 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">;
5567
5568 def int_hexagon_V6_vaslwv :
5569 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">;
5570
5571 def int_hexagon_V6_vaslwv_128B :
5572 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">;
5573
5574 def int_hexagon_V6_vabsw_sat :
5575 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">;
5576
5577 def int_hexagon_V6_vabsw_sat_128B :
5578 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">;
5579
5580 def int_hexagon_V6_vsubwsat_dv :
5581 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">;
5582
5583 def int_hexagon_V6_vsubwsat_dv_128B :
5584 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">;
5585
5586 def int_hexagon_V6_vroundhub :
5587 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">;
5588
5589 def int_hexagon_V6_vroundhub_128B :
5590 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">;
5591
5592 def int_hexagon_V6_vdmpyhisat_acc :
5593 Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">;
5594
5595 def int_hexagon_V6_vdmpyhisat_acc_128B :
5596 Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">;
5597
5598 def int_hexagon_V6_vmpabus :
5599 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">;
5600
5601 def int_hexagon_V6_vmpabus_128B :
5602 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">;
5603
5604 def int_hexagon_V6_vassignp :
5605 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">;
5606
5607 def int_hexagon_V6_vassignp_128B :
5608 Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">;
5609
5610 def int_hexagon_V6_veqb :
5611 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">;
5612
5613 def int_hexagon_V6_veqb_128B :
5614 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">;
5615
5616 def int_hexagon_V6_vsububh :
5617 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">;
5618
5619 def int_hexagon_V6_vsububh_128B :
5620 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">;
5621
5622 def int_hexagon_V6_lvsplatw :
5623 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">;
5624
5625 def int_hexagon_V6_lvsplatw_128B :
5626 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">;
5627
5628 def int_hexagon_V6_vaddhnq :
5629 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">;
5630
5631 def int_hexagon_V6_vaddhnq_128B :
5632 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">;
5633
5634 def int_hexagon_V6_vdmpyhsusat :
5635 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">;
5636
5637 def int_hexagon_V6_vdmpyhsusat_128B :
5638 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">;
5639
5640 def int_hexagon_V6_pred_not :
5641 Hexagon_v512i1_v512i1_Intrinsic<"HEXAGON_V6_pred_not">;
5642
5643 def int_hexagon_V6_pred_not_128B :
5644 Hexagon_v1024i1_v1024i1_Intrinsic<"HEXAGON_V6_pred_not_128B">;
5645
5646 def int_hexagon_V6_vlutvwh_oracc :
5647 Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">;
5648
5649 def int_hexagon_V6_vlutvwh_oracc_128B :
5650 Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">;
5651
5652 def int_hexagon_V6_vmpyiewh_acc :
5653 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">;
5654
5655 def int_hexagon_V6_vmpyiewh_acc_128B :
5656 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">;
5657
5658 def int_hexagon_V6_vdealvdd :
5659 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">;
5660
5661 def int_hexagon_V6_vdealvdd_128B :
5662 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">;
5663
5664 def int_hexagon_V6_vavgw :
5665 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">;
5666
5667 def int_hexagon_V6_vavgw_128B :
5668 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">;
5669
5670 def int_hexagon_V6_vdmpyhsusat_acc :
5671 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">;
5672
5673 def int_hexagon_V6_vdmpyhsusat_acc_128B :
5674 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">;
5675
5676 def int_hexagon_V6_vgtw_xor :
5677 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">;
5678
5679 def int_hexagon_V6_vgtw_xor_128B :
5680 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">;
5681
5682 def int_hexagon_V6_vtmpyhb_acc :
5683 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">;
5684
5685 def int_hexagon_V6_vtmpyhb_acc_128B :
5686 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">;
5687
5688 def int_hexagon_V6_vaddhw :
5689 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">;
5690
5691 def int_hexagon_V6_vaddhw_128B :
5692 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">;
5693
5694 def int_hexagon_V6_vaddhq :
5695 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">;
5696
5697 def int_hexagon_V6_vaddhq_128B :
5698 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">;
5699
5700 def int_hexagon_V6_vrmpyubv :
5701 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">;
5702
5703 def int_hexagon_V6_vrmpyubv_128B :
5704 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">;
5705
5706 def int_hexagon_V6_vsubh :
5707 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">;
5708
5709 def int_hexagon_V6_vsubh_128B :
5710 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">;
5711
5712 def int_hexagon_V6_vrmpyubi :
5713 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [ImmArg<2>]>;
5714
5715 def int_hexagon_V6_vrmpyubi_128B :
5716 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [ImmArg<2>]>;
5717
5718 def int_hexagon_V6_vminw :
5719 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">;
5720
5721 def int_hexagon_V6_vminw_128B :
5722 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">;
5723
5724 def int_hexagon_V6_vmpyubv_acc :
5725 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">;
5726
5727 def int_hexagon_V6_vmpyubv_acc_128B :
5728 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">;
5729
5730 def int_hexagon_V6_pred_xor :
5731 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_xor">;
5732
5733 def int_hexagon_V6_pred_xor_128B :
5734 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">;
5735
5736 def int_hexagon_V6_veqb_xor :
5737 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">;
5738
5739 def int_hexagon_V6_veqb_xor_128B :
5740 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">;
5741
5742 def int_hexagon_V6_vmpyiewuh :
5743 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">;
5744
5745 def int_hexagon_V6_vmpyiewuh_128B :
5746 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">;
5747
5748 def int_hexagon_V6_vmpybusv_acc :
5749 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">;
5750
5751 def int_hexagon_V6_vmpybusv_acc_128B :
5752 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">;
5753
5754 def int_hexagon_V6_vavguhrnd :
5755 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">;
5756
5757 def int_hexagon_V6_vavguhrnd_128B :
5758 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">;
5759
5760 def int_hexagon_V6_vmpyowh_rnd :
5761 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">;
5762
5763 def int_hexagon_V6_vmpyowh_rnd_128B :
5764 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">;
5765
5766 def int_hexagon_V6_vsubwsat :
5767 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">;
5768
5769 def int_hexagon_V6_vsubwsat_128B :
5770 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">;
5771
5772 def int_hexagon_V6_vsubuhw :
5773 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">;
5774
5775 def int_hexagon_V6_vsubuhw_128B :
5776 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">;
5777
5778 def int_hexagon_V6_vrmpybusi_acc :
5779 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [ImmArg<3>]>;
5780
5781 def int_hexagon_V6_vrmpybusi_acc_128B :
5782 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [ImmArg<3>]>;
5783
5784 def int_hexagon_V6_vasrw :
5785 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">;
5786
5787 def int_hexagon_V6_vasrw_128B :
5788 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">;
5789
5790 def int_hexagon_V6_vasrh :
5791 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">;
5792
5793 def int_hexagon_V6_vasrh_128B :
5794 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">;
5795
5796 def int_hexagon_V6_vmpyuhv :
5797 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">;
5798
5799 def int_hexagon_V6_vmpyuhv_128B :
5800 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">;
5801
5802 def int_hexagon_V6_vasrhbrndsat :
5803 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">;
5804
5805 def int_hexagon_V6_vasrhbrndsat_128B :
5806 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">;
5807
5808 def int_hexagon_V6_vsubuhsat_dv :
5809 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">;
5810
5811 def int_hexagon_V6_vsubuhsat_dv_128B :
5812 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">;
5813
5814 def int_hexagon_V6_vabsdiffw :
5815 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">;
5816
5817 def int_hexagon_V6_vabsdiffw_128B :
5818 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">;
5819
5820 // V62 HVX Instructions.
5821
5822 def int_hexagon_V6_vandnqrt_acc :
5823 Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">;
5824
5825 def int_hexagon_V6_vandnqrt_acc_128B :
5826 Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">;
5827
5828 def int_hexagon_V6_vaddclbh :
5829 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">;
5830
5831 def int_hexagon_V6_vaddclbh_128B :
5832 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">;
5833
5834 def int_hexagon_V6_vmpyowh_64_acc :
5835 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">;
5836
5837 def int_hexagon_V6_vmpyowh_64_acc_128B :
5838 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">;
5839
5840 def int_hexagon_V6_vmpyewuh_64 :
5841 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">;
5842
5843 def int_hexagon_V6_vmpyewuh_64_128B :
5844 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">;
5845
5846 def int_hexagon_V6_vsatuwuh :
5847 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">;
5848
5849 def int_hexagon_V6_vsatuwuh_128B :
5850 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">;
5851
5852 def int_hexagon_V6_shuffeqh :
5853 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqh">;
5854
5855 def int_hexagon_V6_shuffeqh_128B :
5856 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">;
5857
5858 def int_hexagon_V6_shuffeqw :
5859 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqw">;
5860
5861 def int_hexagon_V6_shuffeqw_128B :
5862 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">;
5863
5864 def int_hexagon_V6_ldcnpnt0 :
5865 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0">;
5866
5867 def int_hexagon_V6_ldcnpnt0_128B :
5868 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0_128B">;
5869
5870 def int_hexagon_V6_vsubcarry :
5871 Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic;
5872
5873 def int_hexagon_V6_vsubcarry_128B :
5874 Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B;
5875
5876 def int_hexagon_V6_vasrhbsat :
5877 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">;
5878
5879 def int_hexagon_V6_vasrhbsat_128B :
5880 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">;
5881
5882 def int_hexagon_V6_vminb :
5883 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">;
5884
5885 def int_hexagon_V6_vminb_128B :
5886 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">;
5887
5888 def int_hexagon_V6_vmpauhb_acc :
5889 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">;
5890
5891 def int_hexagon_V6_vmpauhb_acc_128B :
5892 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">;
5893
5894 def int_hexagon_V6_vaddhw_acc :
5895 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">;
5896
5897 def int_hexagon_V6_vaddhw_acc_128B :
5898 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">;
5899
5900 def int_hexagon_V6_vlsrb :
5901 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">;
5902
5903 def int_hexagon_V6_vlsrb_128B :
5904 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">;
5905
5906 def int_hexagon_V6_vlutvwhi :
5907 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [ImmArg<2>]>;
5908
5909 def int_hexagon_V6_vlutvwhi_128B :
5910 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [ImmArg<2>]>;
5911
5912 def int_hexagon_V6_vaddububb_sat :
5913 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">;
5914
5915 def int_hexagon_V6_vaddububb_sat_128B :
5916 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">;
5917
5918 def int_hexagon_V6_vsubbsat_dv :
5919 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">;
5920
5921 def int_hexagon_V6_vsubbsat_dv_128B :
5922 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">;
5923
5924 def int_hexagon_V6_ldtp0 :
5925 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0">;
5926
5927 def int_hexagon_V6_ldtp0_128B :
5928 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0_128B">;
5929
5930 def int_hexagon_V6_vlutvvb_oracci :
5931 Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [ImmArg<3>]>;
5932
5933 def int_hexagon_V6_vlutvvb_oracci_128B :
5934 Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [ImmArg<3>]>;
5935
5936 def int_hexagon_V6_vsubuwsat_dv :
5937 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">;
5938
5939 def int_hexagon_V6_vsubuwsat_dv_128B :
5940 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">;
5941
5942 def int_hexagon_V6_ldpnt0 :
5943 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0">;
5944
5945 def int_hexagon_V6_ldpnt0_128B :
5946 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0_128B">;
5947
5948 def int_hexagon_V6_vandvnqv :
5949 Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">;
5950
5951 def int_hexagon_V6_vandvnqv_128B :
5952 Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">;
5953
5954 def int_hexagon_V6_lvsplatb :
5955 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">;
5956
5957 def int_hexagon_V6_lvsplatb_128B :
5958 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">;
5959
5960 def int_hexagon_V6_lvsplath :
5961 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">;
5962
5963 def int_hexagon_V6_lvsplath_128B :
5964 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">;
5965
5966 def int_hexagon_V6_ldtpnt0 :
5967 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0">;
5968
5969 def int_hexagon_V6_ldtpnt0_128B :
5970 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0_128B">;
5971
5972 def int_hexagon_V6_vlutvwh_nm :
5973 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">;
5974
5975 def int_hexagon_V6_vlutvwh_nm_128B :
5976 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;
5977
5978 def int_hexagon_V6_ldnpnt0 :
5979 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0">;
5980
5981 def int_hexagon_V6_ldnpnt0_128B :
5982 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0_128B">;
5983
5984 def int_hexagon_V6_vmpauhb :
5985 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">;
5986
5987 def int_hexagon_V6_vmpauhb_128B :
5988 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">;
5989
5990 def int_hexagon_V6_ldtnp0 :
5991 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0">;
5992
5993 def int_hexagon_V6_ldtnp0_128B :
5994 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0_128B">;
5995
5996 def int_hexagon_V6_vrounduhub :
5997 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">;
5998
5999 def int_hexagon_V6_vrounduhub_128B :
6000 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">;
6001
6002 def int_hexagon_V6_vadduhw_acc :
6003 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">;
6004
6005 def int_hexagon_V6_vadduhw_acc_128B :
6006 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">;
6007
6008 def int_hexagon_V6_ldcp0 :
6009 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0">;
6010
6011 def int_hexagon_V6_ldcp0_128B :
6012 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0_128B">;
6013
6014 def int_hexagon_V6_vadduwsat :
6015 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">;
6016
6017 def int_hexagon_V6_vadduwsat_128B :
6018 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">;
6019
6020 def int_hexagon_V6_ldtnpnt0 :
6021 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0">;
6022
6023 def int_hexagon_V6_ldtnpnt0_128B :
6024 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0_128B">;
6025
6026 def int_hexagon_V6_vaddbsat :
6027 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">;
6028
6029 def int_hexagon_V6_vaddbsat_128B :
6030 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">;
6031
6032 def int_hexagon_V6_vandnqrt :
6033 Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">;
6034
6035 def int_hexagon_V6_vandnqrt_128B :
6036 Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">;
6037
6038 def int_hexagon_V6_vmpyiwub_acc :
6039 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">;
6040
6041 def int_hexagon_V6_vmpyiwub_acc_128B :
6042 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">;
6043
6044 def int_hexagon_V6_vmaxb :
6045 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">;
6046
6047 def int_hexagon_V6_vmaxb_128B :
6048 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">;
6049
6050 def int_hexagon_V6_vandvqv :
6051 Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">;
6052
6053 def int_hexagon_V6_vandvqv_128B :
6054 Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">;
6055
6056 def int_hexagon_V6_vaddcarry :
6057 Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic;
6058
6059 def int_hexagon_V6_vaddcarry_128B :
6060 Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B;
6061
6062 def int_hexagon_V6_vasrwuhrndsat :
6063 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">;
6064
6065 def int_hexagon_V6_vasrwuhrndsat_128B :
6066 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">;
6067
6068 def int_hexagon_V6_vlutvvbi :
6069 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [ImmArg<2>]>;
6070
6071 def int_hexagon_V6_vlutvvbi_128B :
6072 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [ImmArg<2>]>;
6073
6074 def int_hexagon_V6_vsubuwsat :
6075 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">;
6076
6077 def int_hexagon_V6_vsubuwsat_128B :
6078 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">;
6079
6080 def int_hexagon_V6_vaddbsat_dv :
6081 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">;
6082
6083 def int_hexagon_V6_vaddbsat_dv_128B :
6084 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">;
6085
6086 def int_hexagon_V6_ldnp0 :
6087 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0">;
6088
6089 def int_hexagon_V6_ldnp0_128B :
6090 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0_128B">;
6091
6092 def int_hexagon_V6_vasruwuhrndsat :
6093 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">;
6094
6095 def int_hexagon_V6_vasruwuhrndsat_128B :
6096 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">;
6097
6098 def int_hexagon_V6_vrounduwuh :
6099 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">;
6100
6101 def int_hexagon_V6_vrounduwuh_128B :
6102 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">;
6103
6104 def int_hexagon_V6_vlutvvb_nm :
6105 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">;
6106
6107 def int_hexagon_V6_vlutvvb_nm_128B :
6108 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">;
6109
6110 def int_hexagon_V6_pred_scalar2v2 :
6111 Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">;
6112
6113 def int_hexagon_V6_pred_scalar2v2_128B :
6114 Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">;
6115
6116 def int_hexagon_V6_ldp0 :
6117 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0">;
6118
6119 def int_hexagon_V6_ldp0_128B :
6120 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0_128B">;
6121
6122 def int_hexagon_V6_vaddubh_acc :
6123 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">;
6124
6125 def int_hexagon_V6_vaddubh_acc_128B :
6126 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">;
6127
6128 def int_hexagon_V6_vaddclbw :
6129 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">;
6130
6131 def int_hexagon_V6_vaddclbw_128B :
6132 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">;
6133
6134 def int_hexagon_V6_ldcpnt0 :
6135 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0">;
6136
6137 def int_hexagon_V6_ldcpnt0_128B :
6138 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0_128B">;
6139
6140 def int_hexagon_V6_vadduwsat_dv :
6141 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">;
6142
6143 def int_hexagon_V6_vadduwsat_dv_128B :
6144 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">;
6145
6146 def int_hexagon_V6_vmpyiwub :
6147 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">;
6148
6149 def int_hexagon_V6_vmpyiwub_128B :
6150 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">;
6151
6152 def int_hexagon_V6_vsubububb_sat :
6153 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">;
6154
6155 def int_hexagon_V6_vsubububb_sat_128B :
6156 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">;
6157
6158 def int_hexagon_V6_ldcnp0 :
6159 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0">;
6160
6161 def int_hexagon_V6_ldcnp0_128B :
6162 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0_128B">;
6163
6164 def int_hexagon_V6_vlutvwh_oracci :
6165 Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [ImmArg<3>]>;
6166
6167 def int_hexagon_V6_vlutvwh_oracci_128B :
6168 Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [ImmArg<3>]>;
6169
6170 def int_hexagon_V6_vsubbsat :
6171 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">;
6172
6173 def int_hexagon_V6_vsubbsat_128B :
6174 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">;
6175
6176 // V65 HVX Instructions.
6177
6178 def int_hexagon_V6_vasruhubrndsat :
6179 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;
6180
6181 def int_hexagon_V6_vasruhubrndsat_128B :
6182 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;
6183
6184 def int_hexagon_V6_vrmpybub_rtt :
6185 Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;
6186
6187 def int_hexagon_V6_vrmpybub_rtt_128B :
6188 Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;
6189
6190 def int_hexagon_V6_vmpahhsat :
6191 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">;
6192
6193 def int_hexagon_V6_vmpahhsat_128B :
6194 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;
6195
6196 def int_hexagon_V6_vavguwrnd :
6197 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">;
6198
6199 def int_hexagon_V6_vavguwrnd_128B :
6200 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;
6201
6202 def int_hexagon_V6_vnavgb :
6203 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">;
6204
6205 def int_hexagon_V6_vnavgb_128B :
6206 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">;
6207
6208 def int_hexagon_V6_vasrh_acc :
6209 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">;
6210
6211 def int_hexagon_V6_vasrh_acc_128B :
6212 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;
6213
6214 def int_hexagon_V6_vmpauhuhsat :
6215 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;
6216
6217 def int_hexagon_V6_vmpauhuhsat_128B :
6218 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;
6219
6220 def int_hexagon_V6_vmpyh_acc :
6221 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">;
6222
6223 def int_hexagon_V6_vmpyh_acc_128B :
6224 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;
6225
6226 def int_hexagon_V6_vrmpybub_rtt_acc :
6227 Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;
6228
6229 def int_hexagon_V6_vrmpybub_rtt_acc_128B :
6230 Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;
6231
6232 def int_hexagon_V6_vavgb :
6233 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">;
6234
6235 def int_hexagon_V6_vavgb_128B :
6236 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">;
6237
6238 def int_hexagon_V6_vaslh_acc :
6239 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">;
6240
6241 def int_hexagon_V6_vaslh_acc_128B :
6242 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;
6243
6244 def int_hexagon_V6_vavguw :
6245 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">;
6246
6247 def int_hexagon_V6_vavguw_128B :
6248 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">;
6249
6250 def int_hexagon_V6_vlut4 :
6251 Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">;
6252
6253 def int_hexagon_V6_vlut4_128B :
6254 Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">;
6255
6256 def int_hexagon_V6_vmpyuhe_acc :
6257 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;
6258
6259 def int_hexagon_V6_vmpyuhe_acc_128B :
6260 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;
6261
6262 def int_hexagon_V6_vrmpyub_rtt :
6263 Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;
6264
6265 def int_hexagon_V6_vrmpyub_rtt_128B :
6266 Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;
6267
6268 def int_hexagon_V6_vmpsuhuhsat :
6269 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;
6270
6271 def int_hexagon_V6_vmpsuhuhsat_128B :
6272 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;
6273
6274 def int_hexagon_V6_vasruhubsat :
6275 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">;
6276
6277 def int_hexagon_V6_vasruhubsat_128B :
6278 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;
6279
6280 def int_hexagon_V6_vmpyuhe :
6281 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">;
6282
6283 def int_hexagon_V6_vmpyuhe_128B :
6284 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;
6285
6286 def int_hexagon_V6_vrmpyub_rtt_acc :
6287 Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;
6288
6289 def int_hexagon_V6_vrmpyub_rtt_acc_128B :
6290 Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;
6291
6292 def int_hexagon_V6_vasruwuhsat :
6293 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">;
6294
6295 def int_hexagon_V6_vasruwuhsat_128B :
6296 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;
6297
6298 def int_hexagon_V6_vmpabuu_acc :
6299 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;
6300
6301 def int_hexagon_V6_vmpabuu_acc_128B :
6302 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;
6303
6304 def int_hexagon_V6_vprefixqw :
6305 Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqw">;
6306
6307 def int_hexagon_V6_vprefixqw_128B :
6308 Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;
6309
6310 def int_hexagon_V6_vprefixqh :
6311 Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqh">;
6312
6313 def int_hexagon_V6_vprefixqh_128B :
6314 Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;
6315
6316 def int_hexagon_V6_vprefixqb :
6317 Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqb">;
6318
6319 def int_hexagon_V6_vprefixqb_128B :
6320 Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;
6321
6322 def int_hexagon_V6_vabsb :
6323 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">;
6324
6325 def int_hexagon_V6_vabsb_128B :
6326 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">;
6327
6328 def int_hexagon_V6_vavgbrnd :
6329 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">;
6330
6331 def int_hexagon_V6_vavgbrnd_128B :
6332 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;
6333
6334 def int_hexagon_V6_vdd0 :
6335 Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">;
6336
6337 def int_hexagon_V6_vdd0_128B :
6338 Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">;
6339
6340 def int_hexagon_V6_vmpabuu :
6341 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">;
6342
6343 def int_hexagon_V6_vmpabuu_128B :
6344 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;
6345
6346 def int_hexagon_V6_vabsb_sat :
6347 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">;
6348
6349 def int_hexagon_V6_vabsb_sat_128B :
6350 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;
6351
6352 // V66 HVX Instructions.
6353
6354 def int_hexagon_V6_vaddcarrysat :
6355 Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">;
6356
6357 def int_hexagon_V6_vaddcarrysat_128B :
6358 Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">;
6359
6360 def int_hexagon_V6_vasr_into :
6361 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">;
6362
6363 def int_hexagon_V6_vasr_into_128B :
6364 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">;
6365
6366 def int_hexagon_V6_vsatdw :
6367 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">;
6368
6369 def int_hexagon_V6_vsatdw_128B :
6370 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">;
6371
6372 def int_hexagon_V6_vrotr :
6373 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">;
6374
6375 def int_hexagon_V6_vrotr_128B :
6376 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">;
6377