contrib/llvm/include/llvm/IR/IntrinsicsHexagon.td

   1 //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===//
   2 //                     The LLVM Compiler Infrastructure
   3 //
   4 // This file is distributed under the University of Illinois Open Source
   5 // License. See LICENSE.TXT for details.
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines all of the Hexagon-specific intrinsics.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Definitions for all Hexagon intrinsics.
  15 //
  16 // All Hexagon intrinsics start with "llvm.hexagon.".
  17 let TargetPrefix = "hexagon" in {
  18   /// Hexagon_Intrinsic - Base class for all Hexagon intrinsics.
  19   class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
  20                               list<LLVMType> param_types,
  21                               list<IntrinsicProperty> properties>
  22     : GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
  23       Intrinsic<ret_types, param_types, properties>;
  24 }
  25
  26 //===----------------------------------------------------------------------===//
  27 //
  28 // DEF_FUNCTION_TYPE_1(QI_ftype_MEM,BT_BOOL,BT_PTR) ->
  29 // Hexagon_qi_mem_Intrinsic<string GCCIntSuffix>
  30 //
  31 class Hexagon_qi_mem_Intrinsic<string GCCIntSuffix>
  32   : Hexagon_Intrinsic<GCCIntSuffix,
  33                           [llvm_i1_ty], [llvm_ptr_ty],
  34                           [IntrNoMem]>;
  35 //
  36 // DEF_FUNCTION_TYPE_1(HI_ftype_SI,BT_I16,BT_INT) ->
  37 // Hexagon_hi_si_Intrinsic<string GCCIntSuffix>
  38 //
  39 class Hexagon_hi_si_Intrinsic<string GCCIntSuffix>
  40   : Hexagon_Intrinsic<GCCIntSuffix,
  41                           [llvm_i16_ty], [llvm_i32_ty],
  42                           [IntrNoMem]>;
  43 //
  44 // DEF_FUNCTION_TYPE_1(SI_ftype_SI,BT_INT,BT_INT) ->
  45 // Hexagon_si_si_Intrinsic<string GCCIntSuffix>
  46 //
  47 class Hexagon_si_si_Intrinsic<string GCCIntSuffix>
  48   : Hexagon_Intrinsic<GCCIntSuffix,
  49                           [llvm_i32_ty], [llvm_i32_ty],
  50                           [IntrNoMem]>;
  51 //
  52 // DEF_FUNCTION_TYPE_1(DI_ftype_SI,BT_LONGLONG,BT_INT) ->
  53 // Hexagon_di_si_Intrinsic<string GCCIntSuffix>
  54 //
  55 class Hexagon_di_si_Intrinsic<string GCCIntSuffix>
  56   : Hexagon_Intrinsic<GCCIntSuffix,
  57                           [llvm_i64_ty], [llvm_i32_ty],
  58                           [IntrNoMem]>;
  59 //
  60 // DEF_FUNCTION_TYPE_1(SI_ftype_DI,BT_INT,BT_LONGLONG) ->
  61 // Hexagon_si_di_Intrinsic<string GCCIntSuffix>
  62 //
  63 class Hexagon_si_di_Intrinsic<string GCCIntSuffix>
  64   : Hexagon_Intrinsic<GCCIntSuffix,
  65                           [llvm_i32_ty], [llvm_i64_ty],
  66                           [IntrNoMem]>;
  67 //
  68 // DEF_FUNCTION_TYPE_1(DI_ftype_DI,BT_LONGLONG,BT_LONGLONG) ->
  69 // Hexagon_di_di_Intrinsic<string GCCIntSuffix>
  70 //
  71 class Hexagon_di_di_Intrinsic<string GCCIntSuffix>
  72   : Hexagon_Intrinsic<GCCIntSuffix,
  73                           [llvm_i64_ty], [llvm_i64_ty],
  74                           [IntrNoMem]>;
  75 //
  76 // DEF_FUNCTION_TYPE_1(QI_ftype_QI,BT_BOOL,BT_BOOL) ->
  77 // Hexagon_qi_qi_Intrinsic<string GCCIntSuffix>
  78 //
  79 class Hexagon_qi_qi_Intrinsic<string GCCIntSuffix>
  80   : Hexagon_Intrinsic<GCCIntSuffix,
  81                           [llvm_i1_ty], [llvm_i32_ty],
  82                           [IntrNoMem]>;
  83 //
  84 // DEF_FUNCTION_TYPE_1(QI_ftype_SI,BT_BOOL,BT_INT) ->
  85 // Hexagon_qi_si_Intrinsic<string GCCIntSuffix>
  86 //
  87 class Hexagon_qi_si_Intrinsic<string GCCIntSuffix>
  88   : Hexagon_Intrinsic<GCCIntSuffix,
  89                           [llvm_i1_ty], [llvm_i32_ty],
  90                           [IntrNoMem]>;
  91 //
  92 // DEF_FUNCTION_TYPE_1(DI_ftype_QI,BT_LONGLONG,BT_BOOL) ->
  93 // Hexagon_di_qi_Intrinsic<string GCCIntSuffix>
  94 //
  95 class Hexagon_di_qi_Intrinsic<string GCCIntSuffix>
  96   : Hexagon_Intrinsic<GCCIntSuffix,
  97                           [llvm_i64_ty], [llvm_i32_ty],
  98                           [IntrNoMem]>;
  99 //
 100 // DEF_FUNCTION_TYPE_1(SI_ftype_QI,BT_INT,BT_BOOL) ->
 101 // Hexagon_si_qi_Intrinsic<string GCCIntSuffix>
 102 //
 103 class Hexagon_si_qi_Intrinsic<string GCCIntSuffix>
 104   : Hexagon_Intrinsic<GCCIntSuffix,
 105                           [llvm_i32_ty], [llvm_i32_ty],
 106                           [IntrNoMem]>;
 107 //
 108 // DEF_FUNCTION_TYPE_2(QI_ftype_SISI,BT_BOOL,BT_INT,BT_INT) ->
 109 // Hexagon_qi_sisi_Intrinsic<string GCCIntSuffix>
 110 //
 111 class Hexagon_qi_sisi_Intrinsic<string GCCIntSuffix>
 112   : Hexagon_Intrinsic<GCCIntSuffix,
 113                           [llvm_i1_ty], [llvm_i32_ty, llvm_i32_ty],
 114                           [IntrNoMem]>;
 115 //
 116 // DEF_FUNCTION_TYPE_2(void_ftype_SISI,BT_VOID,BT_INT,BT_INT) ->
 117 // Hexagon_void_sisi_Intrinsic<string GCCIntSuffix>
 118 //
 119 class Hexagon_void_sisi_Intrinsic<string GCCIntSuffix>
 120   : Hexagon_Intrinsic<GCCIntSuffix,
 121                           [llvm_void_ty], [llvm_i32_ty, llvm_i32_ty],
 122                           [IntrNoMem]>;
 123 //
 124 // DEF_FUNCTION_TYPE_2(SI_ftype_SISI,BT_INT,BT_INT,BT_INT) ->
 125 // Hexagon_si_sisi_Intrinsic<string GCCIntSuffix>
 126 //
 127 class Hexagon_si_sisi_Intrinsic<string GCCIntSuffix>
 128   : Hexagon_Intrinsic<GCCIntSuffix,
 129                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 130                           [IntrNoMem]>;
 131 //
 132 // DEF_FUNCTION_TYPE_2(USI_ftype_SISI,BT_UINT,BT_INT,BT_INT) ->
 133 // Hexagon_usi_sisi_Intrinsic<string GCCIntSuffix>
 134 //
 135 class Hexagon_usi_sisi_Intrinsic<string GCCIntSuffix>
 136   : Hexagon_Intrinsic<GCCIntSuffix,
 137                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 138                           [IntrNoMem]>;
 139 //
 140 // DEF_FUNCTION_TYPE_2(DI_ftype_SISI,BT_LONGLONG,BT_INT,BT_INT) ->
 141 // Hexagon_di_sisi_Intrinsic<string GCCIntSuffix>
 142 //
 143 class Hexagon_di_sisi_Intrinsic<string GCCIntSuffix>
 144   : Hexagon_Intrinsic<GCCIntSuffix,
 145                           [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty],
 146                           [IntrNoMem]>;
 147 //
 148 // DEF_FUNCTION_TYPE_2(UDI_ftype_SISI,BT_ULONGLONG,BT_INT,BT_INT) ->
 149 // Hexagon_udi_sisi_Intrinsic<string GCCIntSuffix>
 150 //
 151 class Hexagon_udi_sisi_Intrinsic<string GCCIntSuffix>
 152   : Hexagon_Intrinsic<GCCIntSuffix,
 153                           [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty],
 154                           [IntrNoMem]>;
 155 //
 156 // DEF_FUNCTION_TYPE_2(DI_ftype_SIDI,BT_LONGLONG,BT_INT,BT_LONGLONG) ->
 157 // Hexagon_di_sidi_Intrinsic<string GCCIntSuffix>
 158 //
 159 class Hexagon_di_sidi_Intrinsic<string GCCIntSuffix>
 160   : Hexagon_Intrinsic<GCCIntSuffix,
 161                           [llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty],
 162                           [IntrNoMem]>;
 163 //
 164 // DEF_FUNCTION_TYPE_2(DI_ftype_DISI,BT_LONGLONG,BT_LONGLONG,BT_INT) ->
 165 // Hexagon_di_disi_Intrinsic<string GCCIntSuffix>
 166 //
 167 class Hexagon_di_disi_Intrinsic<string GCCIntSuffix>
 168   : Hexagon_Intrinsic<GCCIntSuffix,
 169                           [llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty],
 170                           [IntrNoMem]>;
 171 //
 172 // DEF_FUNCTION_TYPE_2(SI_ftype_SIDI,BT_INT,BT_INT,BT_LONGLONG) ->
 173 // Hexagon_si_sidi_Intrinsic<string GCCIntSuffix>
 174 //
 175 class Hexagon_si_sidi_Intrinsic<string GCCIntSuffix>
 176   : Hexagon_Intrinsic<GCCIntSuffix,
 177                           [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 178                           [IntrNoMem]>;
 179 //
 180 // DEF_FUNCTION_TYPE_2(SI_ftype_DIDI,BT_INT,BT_LONGLONG,BT_LONGLONG) ->
 181 // Hexagon_si_didi_Intrinsic<string GCCIntSuffix>
 182 //
 183 class Hexagon_si_didi_Intrinsic<string GCCIntSuffix>
 184   : Hexagon_Intrinsic<GCCIntSuffix,
 185                           [llvm_i32_ty], [llvm_i64_ty, llvm_i64_ty],
 186                           [IntrNoMem]>;
 187 //
 188 // DEF_FUNCTION_TYPE_2(DI_ftype_DIDI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG) ->
 189 // Hexagon_di_didi_Intrinsic<string GCCIntSuffix>
 190 //
 191 class Hexagon_di_didi_Intrinsic<string GCCIntSuffix>
 192   : Hexagon_Intrinsic<GCCIntSuffix,
 193                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
 194                           [IntrNoMem]>;
 195 //
 196 // DEF_FUNCTION_TYPE_2(UDI_ftype_DIDI,BT_ULONGLONG,BT_LONGLONG,BT_LONGLONG) ->
 197 // Hexagon_udi_didi_Intrinsic<string GCCIntSuffix>
 198 //
 199 class Hexagon_udi_didi_Intrinsic<string GCCIntSuffix>
 200   : Hexagon_Intrinsic<GCCIntSuffix,
 201                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
 202                           [IntrNoMem]>;
 203 //
 204 // DEF_FUNCTION_TYPE_2(SI_ftype_DISI,BT_INT,BT_LONGLONG,BT_INT) ->
 205 // Hexagon_si_disi_Intrinsic<string GCCIntSuffix>
 206 //
 207 class Hexagon_si_disi_Intrinsic<string GCCIntSuffix>
 208   : Hexagon_Intrinsic<GCCIntSuffix,
 209                           [llvm_i32_ty], [llvm_i64_ty, llvm_i32_ty],
 210                           [IntrNoMem]>;
 211 //
 212 // DEF_FUNCTION_TYPE_2(QI_ftype_DIDI,BT_BOOL,BT_LONGLONG,BT_LONGLONG) ->
 213 // Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
 214 //
 215 class Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
 216   : Hexagon_Intrinsic<GCCIntSuffix,
 217                           [llvm_i1_ty], [llvm_i64_ty, llvm_i64_ty],
 218                           [IntrNoMem]>;
 219 //
 220 // DEF_FUNCTION_TYPE_2(QI_ftype_SIDI,BT_BOOL,BT_INT,BT_LONGLONG) ->
 221 // Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
 222 //
 223 class Hexagon_qi_sidi_Intrinsic<string GCCIntSuffix>
 224   : Hexagon_Intrinsic<GCCIntSuffix,
 225                           [llvm_i1_ty], [llvm_i32_ty, llvm_i64_ty],
 226                           [IntrNoMem]>;
 227 //
 228 // DEF_FUNCTION_TYPE_2(QI_ftype_DISI,BT_BOOL,BT_LONGLONG,BT_INT) ->
 229 // Hexagon_qi_disi_Intrinsic<string GCCIntSuffix>
 230 //
 231 class Hexagon_qi_disi_Intrinsic<string GCCIntSuffix>
 232   : Hexagon_Intrinsic<GCCIntSuffix,
 233                           [llvm_i1_ty], [llvm_i64_ty, llvm_i32_ty],
 234                           [IntrNoMem]>;
 235 //
 236 // DEF_FUNCTION_TYPE_2(QI_ftype_QIQI,BT_BOOL,BT_BOOL,BT_BOOL) ->
 237 // Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix>
 238 //
 239 class Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix>
 240   : Hexagon_Intrinsic<GCCIntSuffix,
 241                           [llvm_i1_ty], [llvm_i32_ty, llvm_i32_ty],
 242                           [IntrNoMem]>;
 243 //
 244 // DEF_FUNCTION_TYPE_2(QI_ftype_QIQIQI,BT_BOOL,BT_BOOL,BT_BOOL) ->
 245 // Hexagon_qi_qiqiqi_Intrinsic<string GCCIntSuffix>
 246 //
 247 class Hexagon_qi_qiqiqi_Intrinsic<string GCCIntSuffix>
 248   : Hexagon_Intrinsic<GCCIntSuffix,
 249                           [llvm_i1_ty], [llvm_i1_ty, llvm_i1_ty, llvm_i1_ty],
 250                           [IntrNoMem]>;
 251 //
 252 // DEF_FUNCTION_TYPE_2(SI_ftype_QIQI,BT_INT,BT_BOOL,BT_BOOL) ->
 253 // Hexagon_si_qiqi_Intrinsic<string GCCIntSuffix>
 254 //
 255 class Hexagon_si_qiqi_Intrinsic<string GCCIntSuffix>
 256   : Hexagon_Intrinsic<GCCIntSuffix,
 257                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 258                           [IntrNoMem]>;
 259 //
 260 // DEF_FUNCTION_TYPE_2(SI_ftype_QISI,BT_INT,BT_BOOL,BT_INT) ->
 261 // Hexagon_si_qisi_Intrinsic<string GCCIntSuffix>
 262 //
 263 class Hexagon_si_qisi_Intrinsic<string GCCIntSuffix>
 264   : Hexagon_Intrinsic<GCCIntSuffix,
 265                           [llvm_i32_ty], [llvm_i1_ty, llvm_i32_ty],
 266                           [IntrNoMem]>;
 267 //
 268 // DEF_FUNCTION_TYPE_3(void_ftype_SISISI,BT_VOID,BT_INT,BT_INT,BT_INT) ->
 269 // Hexagon_void_sisisi_Intrinsic<string GCCIntSuffix>
 270 //
 271 class Hexagon_void_sisisi_Intrinsic<string GCCIntSuffix>
 272   : Hexagon_Intrinsic<GCCIntSuffix,
 273                           [llvm_void_ty], [llvm_i32_ty, llvm_i32_ty,
 274                            llvm_i32_ty],
 275                           [IntrNoMem]>;
 276 //
 277 // DEF_FUNCTION_TYPE_3(SI_ftype_SISISI,BT_INT,BT_INT,BT_INT,BT_INT) ->
 278 // Hexagon_si_sisisi_Intrinsic<string GCCIntSuffix>
 279 //
 280 class Hexagon_si_sisisi_Intrinsic<string GCCIntSuffix>
 281   : Hexagon_Intrinsic<GCCIntSuffix,
 282                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
 283                            llvm_i32_ty],
 284                           [IntrNoMem]>;
 285 //
 286 // DEF_FUNCTION_TYPE_3(DI_ftype_SISISI,BT_LONGLONG,BT_INT,BT_INT,BT_INT) ->
 287 // Hexagon_di_sisisi_Intrinsic<string GCCIntSuffix>
 288 //
 289 class Hexagon_di_sisisi_Intrinsic<string GCCIntSuffix>
 290   : Hexagon_Intrinsic<GCCIntSuffix,
 291                           [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty,
 292                            llvm_i32_ty],
 293                           [IntrNoMem]>;
 294 //
 295 // DEF_FUNCTION_TYPE_3(SI_ftype_DISISI,BT_INT,BT_LONGLONG,BT_INT,BT_INT) ->
 296 // Hexagon_si_disisi_Intrinsic<string GCCIntSuffix>
 297 //
 298 class Hexagon_si_disisi_Intrinsic<string GCCIntSuffix>
 299   : Hexagon_Intrinsic<GCCIntSuffix,
 300                           [llvm_i32_ty], [llvm_i64_ty, llvm_i32_ty,
 301                            llvm_i32_ty],
 302                           [IntrNoMem]>;
 303 //
 304 // DEF_FUNCTION_TYPE_3(DI_ftype_DISISI,BT_LONGLONG,BT_LONGLONG,BT_INT,BT_INT) ->
 305 // Hexagon_di_disisi_Intrinsic<string GCCIntSuffix>
 306 //
 307 class Hexagon_di_disisi_Intrinsic<string GCCIntSuffix>
 308   : Hexagon_Intrinsic<GCCIntSuffix,
 309                           [llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty,
 310                            llvm_i32_ty],
 311                           [IntrNoMem]>;
 312 //
 313 // DEF_FUNCTION_TYPE_3(SI_ftype_SIDISI,BT_INT,BT_INT,BT_LONGLONG,BT_INT) ->
 314 // Hexagon_si_sidisi_Intrinsic<string GCCIntSuffix>
 315 //
 316 class Hexagon_si_sidisi_Intrinsic<string GCCIntSuffix>
 317   : Hexagon_Intrinsic<GCCIntSuffix,
 318                           [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty,
 319                            llvm_i32_ty],
 320                           [IntrNoMem]>;
 321 //
 322 // DEF_FUNCTION_TYPE_3(DI_ftype_DIDISI,BT_LONGLONG,BT_LONGLONG,
 323 //                     BT_LONGLONG,BT_INT) ->
 324 // Hexagon_di_didisi_Intrinsic<string GCCIntSuffix>
 325 //
 326 class Hexagon_di_didisi_Intrinsic<string GCCIntSuffix>
 327   : Hexagon_Intrinsic<GCCIntSuffix,
 328                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 329                            llvm_i32_ty],
 330                           [IntrNoMem]>;
 331 //
 332 // DEF_FUNCTION_TYPE_3(SI_ftype_SIDIDI,BT_INT,BT_INT,BT_LONGLONG,BT_LONGLONG) ->
 333 // Hexagon_si_sididi_Intrinsic<string GCCIntSuffix>
 334 //
 335 class Hexagon_si_sididi_Intrinsic<string GCCIntSuffix>
 336   : Hexagon_Intrinsic<GCCIntSuffix,
 337                           [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty,
 338                            llvm_i64_ty],
 339                           [IntrNoMem]>;
 340 //
 341 // DEF_FUNCTION_TYPE_3(DI_ftype_DIDIDI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG,
 342 //                     BT_LONGLONG) ->
 343 // Hexagon_di_dididi_Intrinsic<string GCCIntSuffix>
 344 //
 345 class Hexagon_di_dididi_Intrinsic<string GCCIntSuffix>
 346   : Hexagon_Intrinsic<GCCIntSuffix,
 347                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 348                            llvm_i64_ty],
 349                           [IntrNoMem]>;
 350 //
 351 // DEF_FUNCTION_TYPE_3(SI_ftype_SISIDI,BT_INT,BT_INT,BT_INT,BT_LONGLONG) ->
 352 // Hexagon_si_sisidi_Intrinsic<string GCCIntSuffix>
 353 //
 354 class Hexagon_si_sisidi_Intrinsic<string GCCIntSuffix>
 355   : Hexagon_Intrinsic<GCCIntSuffix,
 356                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
 357                            llvm_i64_ty],
 358                           [IntrNoMem]>;
 359 //
 360 // DEF_FUNCTION_TYPE_3(SI_ftype_QISISI,BT_INT,BT_BOOL,BT_INT,BT_INT) ->
 361 // Hexagon_si_qisisi_Intrinsic<string GCCIntSuffix>
 362 //
 363 class Hexagon_si_qisisi_Intrinsic<string GCCIntSuffix>
 364   : Hexagon_Intrinsic<GCCIntSuffix,
 365                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
 366                            llvm_i32_ty],
 367                           [IntrNoMem]>;
 368 //
 369 // DEF_FUNCTION_TYPE_3(DI_ftype_QISISI,BT_LONGLONG,BT_BOOL,BT_INT,BT_INT) ->
 370 // Hexagon_di_qisisi_Intrinsic<string GCCIntSuffix>
 371 //
 372 class Hexagon_di_qisisi_Intrinsic<string GCCIntSuffix>
 373   : Hexagon_Intrinsic<GCCIntSuffix,
 374                           [llvm_i64_ty], [llvm_i1_ty, llvm_i32_ty,
 375                            llvm_i32_ty],
 376                           [IntrNoMem]>;
 377 //
 378 // DEF_FUNCTION_TYPE_3(DI_ftype_QIDIDI,BT_LONGLONG,BT_BOOL,BT_LONGLONG,
 379 //                     BT_LONGLONG) ->
 380 // Hexagon_di_qididi_Intrinsic<string GCCIntSuffix>
 381 //
 382 class Hexagon_di_qididi_Intrinsic<string GCCIntSuffix>
 383   : Hexagon_Intrinsic<GCCIntSuffix,
 384                           [llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty,
 385                            llvm_i64_ty],
 386                           [IntrNoMem]>;
 387 //
 388 // DEF_FUNCTION_TYPE_3(DI_ftype_DIDIQI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG,
 389 //                     BT_BOOL) ->
 390 // Hexagon_di_didiqi_Intrinsic<string GCCIntSuffix>
 391 //
 392 class Hexagon_di_didiqi_Intrinsic<string GCCIntSuffix>
 393   : Hexagon_Intrinsic<GCCIntSuffix,
 394                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 395                            llvm_i32_ty],
 396                           [IntrNoMem]>;
 397 //
 398 // DEF_FUNCTION_TYPE_4(SI_ftype_SISISISI,BT_INT,BT_INT,BT_INT,BT_INT,BT_INT) ->
 399 // Hexagon_si_sisisisi_Intrinsic<string GCCIntSuffix>
 400 //
 401 class Hexagon_si_sisisisi_Intrinsic<string GCCIntSuffix>
 402   : Hexagon_Intrinsic<GCCIntSuffix,
 403                           [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
 404                            llvm_i32_ty, llvm_i32_ty],
 405                           [IntrNoMem]>;
 406 //
 407 // DEF_FUNCTION_TYPE_4(DI_ftype_DIDISISI,BT_LONGLONG,BT_LONGLONG,
 408 //                     BT_LONGLONG,BT_INT,BT_INT) ->
 409 // Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix>
 410 //
 411 class Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix>
 412   : Hexagon_Intrinsic<GCCIntSuffix,
 413                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 414                            llvm_i32_ty, llvm_i32_ty],
 415                           [IntrNoMem]>;
 416
 417 class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
 418   : Hexagon_Intrinsic<GCCIntSuffix,
 419                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
 420                            llvm_i32_ty],
 421                           [IntrArgMemOnly]>;
 422
 423 class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix>
 424   : Hexagon_Intrinsic<GCCIntSuffix,
 425                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
 426                            llvm_i32_ty],
 427                           [IntrArgMemOnly]>;
 428
 429 class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix>
 430   : Hexagon_Intrinsic<GCCIntSuffix,
 431                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
 432                            llvm_i32_ty],
 433                           [IntrArgMemOnly]>;
 434
 435 class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
 436   : Hexagon_Intrinsic<GCCIntSuffix,
 437                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
 438                            llvm_i32_ty, llvm_i32_ty],
 439                           [IntrArgMemOnly]>;
 440
 441 class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix>
 442   : Hexagon_Intrinsic<GCCIntSuffix,
 443                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
 444                            llvm_i32_ty, llvm_i32_ty],
 445                           [IntrArgMemOnly]>;
 446
 447 class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix>
 448   : Hexagon_Intrinsic<GCCIntSuffix,
 449                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
 450                            llvm_i32_ty, llvm_i32_ty],
 451                           [IntrArgMemOnly]>;
 452
 453 class Hexagon_v256_v256v256_Intrinsic<string GCCIntSuffix>
 454   : Hexagon_Intrinsic<GCCIntSuffix,
 455                           [llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
 456                           [IntrArgMemOnly]>;
 457
 458 //
 459 // Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
 460 //
 461 class Hexagon_sf_si_Intrinsic<string GCCIntSuffix>
 462   : Hexagon_Intrinsic<GCCIntSuffix,
 463                           [llvm_float_ty], [llvm_i32_ty],
 464                           [IntrNoMem, Throws]>;
 465 //
 466 // Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
 467 //
 468 class Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
 469   : Hexagon_Intrinsic<GCCIntSuffix,
 470                           [llvm_float_ty], [llvm_double_ty],
 471                           [IntrNoMem]>;
 472 //
 473 // Hexagon_sf_di_Intrinsic<string GCCIntSuffix>
 474 //
 475 class Hexagon_sf_di_Intrinsic<string GCCIntSuffix>
 476   : Hexagon_Intrinsic<GCCIntSuffix,
 477                           [llvm_float_ty], [llvm_i64_ty],
 478                           [IntrNoMem]>;
 479 //
 480 // Hexagon_df_sf_Intrinsic<string GCCIntSuffix>
 481 //
 482 class Hexagon_df_sf_Intrinsic<string GCCIntSuffix>
 483   : Hexagon_Intrinsic<GCCIntSuffix,
 484                           [llvm_double_ty], [llvm_float_ty],
 485                           [IntrNoMem]>;
 486 //
 487 // Hexagon_di_sf_Intrinsic<string GCCIntSuffix>
 488 //
 489 class Hexagon_di_sf_Intrinsic<string GCCIntSuffix>
 490   : Hexagon_Intrinsic<GCCIntSuffix,
 491                           [llvm_i64_ty], [llvm_float_ty],
 492                           [IntrNoMem]>;
 493 //
 494 // Hexagon_sf_sf_Intrinsic<string GCCIntSuffix>
 495 //
 496 class Hexagon_sf_sf_Intrinsic<string GCCIntSuffix>
 497   : Hexagon_Intrinsic<GCCIntSuffix,
 498                           [llvm_float_ty], [llvm_float_ty],
 499                           [IntrNoMem]>;
 500 //
 501 // Hexagon_si_sf_Intrinsic<string GCCIntSuffix>
 502 //
 503 class Hexagon_si_sf_Intrinsic<string GCCIntSuffix>
 504   : Hexagon_Intrinsic<GCCIntSuffix,
 505                           [llvm_i32_ty], [llvm_float_ty],
 506                           [IntrNoMem]>;
 507 //
 508 // Hexagon_si_df_Intrinsic<string GCCIntSuffix>
 509 //
 510 class Hexagon_si_df_Intrinsic<string GCCIntSuffix>
 511   : Hexagon_Intrinsic<GCCIntSuffix,
 512                           [llvm_i32_ty], [llvm_double_ty],
 513                           [IntrNoMem]>;
 514 //
 515 // Hexagon_sf_sfsf_Intrinsic<string GCCIntSuffix>
 516 //
 517 class Hexagon_sf_sfsf_Intrinsic<string GCCIntSuffix>
 518   : Hexagon_Intrinsic<GCCIntSuffix,
 519                           [llvm_float_ty], [llvm_float_ty, llvm_float_ty],
 520                           [IntrNoMem, Throws]>;
 521 //
 522 // Hexagon_si_sfsf_Intrinsic<string GCCIntSuffix>
 523 //
 524 class Hexagon_si_sfsf_Intrinsic<string GCCIntSuffix>
 525   : Hexagon_Intrinsic<GCCIntSuffix,
 526                           [llvm_i32_ty], [llvm_float_ty, llvm_float_ty],
 527                           [IntrNoMem, Throws]>;
 528 //
 529 // Hexagon_si_sfsi_Intrinsic<string GCCIntSuffix>
 530 //
 531 class Hexagon_si_sfsi_Intrinsic<string GCCIntSuffix>
 532   : Hexagon_Intrinsic<GCCIntSuffix,
 533                           [llvm_i32_ty], [llvm_float_ty, llvm_i32_ty],
 534                           [IntrNoMem, Throws]>;
 535 //
 536 // Hexagon_qi_sfqi_Intrinsic<string GCCIntSuffix>
 537 //
 538 class Hexagon_qi_sfqi_Intrinsic<string GCCIntSuffix>
 539   : Hexagon_Intrinsic<GCCIntSuffix,
 540                           [llvm_i1_ty], [llvm_float_ty, llvm_i32_ty],
 541                           [IntrNoMem]>;
 542 //
 543 // Hexagon_sf_sfsfsf_Intrinsic<string GCCIntSuffix>
 544 //
 545 class Hexagon_sf_sfsfsf_Intrinsic<string GCCIntSuffix>
 546   : Hexagon_Intrinsic<GCCIntSuffix,
 547                           [llvm_float_ty], [llvm_float_ty, llvm_float_ty,
 548                                             llvm_float_ty],
 549                           [IntrNoMem, Throws]>;
 550 //
 551 // Hexagon_sf_sfsfsfqi_Intrinsic<string GCCIntSuffix>
 552 //
 553 class Hexagon_sf_sfsfsfqi_Intrinsic<string GCCIntSuffix>
 554   : Hexagon_Intrinsic<GCCIntSuffix,
 555                           [llvm_float_ty], [llvm_float_ty, llvm_float_ty,
 556                                             llvm_float_ty,
 557                            llvm_i32_ty],
 558                           [IntrNoMem, Throws]>;
 559 //
 560 // Hexagon_di_dididi_Intrinsic<string GCCIntSuffix>
 561 //
 562 class Hexagon_di_dididisi_Intrinsic<string GCCIntSuffix>
 563   : Hexagon_Intrinsic<GCCIntSuffix,
 564                           [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
 565                            llvm_i64_ty, llvm_i32_ty],
 566                           [IntrNoMem]>;
 567 //
 568 // Hexagon_df_si_Intrinsic<string GCCIntSuffix>
 569 //
 570 class Hexagon_df_si_Intrinsic<string GCCIntSuffix>
 571   : Hexagon_Intrinsic<GCCIntSuffix,
 572                           [llvm_double_ty], [llvm_i32_ty],
 573                           [IntrNoMem, Throws]>;
 574 //
 575 // Hexagon_df_di_Intrinsic<string GCCIntSuffix>
 576 //
 577 class Hexagon_df_di_Intrinsic<string GCCIntSuffix>
 578   : Hexagon_Intrinsic<GCCIntSuffix,
 579                           [llvm_double_ty], [llvm_i64_ty],
 580                           [IntrNoMem]>;
 581 //
 582 // Hexagon_di_df_Intrinsic<string GCCIntSuffix>
 583 //
 584 class Hexagon_di_df_Intrinsic<string GCCIntSuffix>
 585   : Hexagon_Intrinsic<GCCIntSuffix,
 586                           [llvm_i64_ty], [llvm_double_ty],
 587                           [IntrNoMem]>;
 588 //
 589 // Hexagon_df_df_Intrinsic<string GCCIntSuffix>
 590 //
 591 class Hexagon_df_df_Intrinsic<string GCCIntSuffix>
 592   : Hexagon_Intrinsic<GCCIntSuffix,
 593                           [llvm_double_ty], [llvm_double_ty],
 594                           [IntrNoMem]>;
 595 //
 596 // Hexagon_df_dfdf_Intrinsic<string GCCIntSuffix>
 597 //
 598 class Hexagon_df_dfdf_Intrinsic<string GCCIntSuffix>
 599   : Hexagon_Intrinsic<GCCIntSuffix,
 600                           [llvm_double_ty], [llvm_double_ty, llvm_double_ty],
 601                           [IntrNoMem, Throws]>;
 602 //
 603 // Hexagon_si_dfdf_Intrinsic<string GCCIntSuffix>
 604 //
 605 class Hexagon_si_dfdf_Intrinsic<string GCCIntSuffix>
 606   : Hexagon_Intrinsic<GCCIntSuffix,
 607                           [llvm_i32_ty], [llvm_double_ty, llvm_double_ty],
 608                           [IntrNoMem, Throws]>;
 609 //
 610 // Hexagon_si_dfsi_Intrinsic<string GCCIntSuffix>
 611 //
 612 class Hexagon_si_dfsi_Intrinsic<string GCCIntSuffix>
 613   : Hexagon_Intrinsic<GCCIntSuffix,
 614                           [llvm_i32_ty], [llvm_double_ty, llvm_i32_ty],
 615                           [IntrNoMem, Throws]>;
 616 //
 617 //
 618 // Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
 619 //
 620 class Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
 621   : Hexagon_Intrinsic<GCCIntSuffix,
 622                           [llvm_double_ty], [llvm_double_ty, llvm_double_ty,
 623                                              llvm_double_ty],
 624                           [IntrNoMem, Throws]>;
 625 //
 626 // Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
 627 //
 628 class Hexagon_df_dfdfdfqi_Intrinsic<string GCCIntSuffix>
 629   : Hexagon_Intrinsic<GCCIntSuffix,
 630                           [llvm_double_ty], [llvm_double_ty, llvm_double_ty,
 631                                              llvm_double_ty,
 632                           llvm_i32_ty],
 633                           [IntrNoMem, Throws]>;
 634
 635
 636 // This one below will not be auto-generated,
 637 // so make sure, you don't overwrite this one.
 638 //
 639 // BUILTIN_INFO(SI_to_SXTHI_asrh,SI_ftype_SI,1)
 640 //
 641 def int_hexagon_SI_to_SXTHI_asrh :
 642 Hexagon_si_si_Intrinsic<"SI_to_SXTHI_asrh">;
 643 //
 644 // BUILTIN_INFO_NONCONST(brev_ldd,PTR_ftype_PTRPTRSI,3)
 645 //
 646 def int_hexagon_brev_ldd :
 647 Hexagon_mem_memmemsi_Intrinsic<"brev_ldd">;
 648 //
 649 // BUILTIN_INFO_NONCONST(brev_ldw,PTR_ftype_PTRPTRSI,3)
 650 //
 651 def int_hexagon_brev_ldw :
 652 Hexagon_mem_memmemsi_Intrinsic<"brev_ldw">;
 653 //
 654 // BUILTIN_INFO_NONCONST(brev_ldh,PTR_ftype_PTRPTRSI,3)
 655 //
 656 def int_hexagon_brev_ldh :
 657 Hexagon_mem_memmemsi_Intrinsic<"brev_ldh">;
 658 //
 659 // BUILTIN_INFO_NONCONST(brev_lduh,PTR_ftype_PTRPTRSI,3)
 660 //
 661 def int_hexagon_brev_lduh :
 662 Hexagon_mem_memmemsi_Intrinsic<"brev_lduh">;
 663 //
 664 // BUILTIN_INFO_NONCONST(brev_ldb,PTR_ftype_PTRPTRSI,3)
 665 //
 666 def int_hexagon_brev_ldb :
 667 Hexagon_mem_memmemsi_Intrinsic<"brev_ldb">;
 668 //
 669 // BUILTIN_INFO_NONCONST(brev_ldub,PTR_ftype_PTRPTRSI,3)
 670 //
 671 def int_hexagon_brev_ldub :
 672 Hexagon_mem_memmemsi_Intrinsic<"brev_ldub">;
 673 //
 674 // BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
 675 //
 676 def int_hexagon_circ_ldd :
 677 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
 678 //
 679 // BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4)
 680 //
 681 def int_hexagon_circ_ldw :
 682 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">;
 683 //
 684 // BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4)
 685 //
 686 def int_hexagon_circ_ldh :
 687 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">;
 688 //
 689 // BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4)
 690 //
 691 def int_hexagon_circ_lduh :
 692 Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">;
 693 //
 694 // BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4)
 695 //
 696 def int_hexagon_circ_ldb :
 697 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">;
 698 //
 699 // BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4)
 700 //
 701 def int_hexagon_circ_ldub :
 702 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">;
 703
 704 //
 705 // BUILTIN_INFO_NONCONST(brev_stb,PTR_ftype_PTRSISI,3)
 706 //
 707 def int_hexagon_brev_stb :
 708 Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
 709 //
 710 // BUILTIN_INFO_NONCONST(brev_sthhi,PTR_ftype_PTRSISI,3)
 711 //
 712 def int_hexagon_brev_sthhi :
 713 Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
 714 //
 715 // BUILTIN_INFO_NONCONST(brev_sth,PTR_ftype_PTRSISI,3)
 716 //
 717 def int_hexagon_brev_sth :
 718 Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
 719 //
 720 // BUILTIN_INFO_NONCONST(brev_stw,PTR_ftype_PTRSISI,3)
 721 //
 722 def int_hexagon_brev_stw :
 723 Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
 724 //
 725 // BUILTIN_INFO_NONCONST(brev_std,PTR_ftype_PTRSISI,3)
 726 //
 727 def int_hexagon_brev_std :
 728 Hexagon_mem_memdisi_Intrinsic<"brev_std">;
 729 //
 730 // BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4)
 731 //
 732 def int_hexagon_circ_std :
 733 Hexagon_mem_memdisisi_Intrinsic<"circ_std">;
 734 //
 735 // BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4)
 736 //
 737 def int_hexagon_circ_stw :
 738 Hexagon_mem_memsisisi_Intrinsic<"circ_stw">;
 739 //
 740 // BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4)
 741 //
 742 def int_hexagon_circ_sth :
 743 Hexagon_mem_memsisisi_Intrinsic<"circ_sth">;
 744 //
 745 // BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4)
 746 //
 747 def int_hexagon_circ_sthhi :
 748 Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">;
 749 //
 750 // BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4)
 751 //
 752 def int_hexagon_circ_stb :
 753 Hexagon_mem_memsisisi_Intrinsic<"circ_stb">;
 754
 755
 756 def int_hexagon_mm256i_vaddw :
 757 Hexagon_v256_v256v256_Intrinsic<"_mm256i_vaddw">;
 758
 759
 760 // This one above will not be auto-generated,
 761 // so make sure, you don't overwrite this one.
 762 //
 763 // BUILTIN_INFO(HEXAGON.C2_cmpeq,QI_ftype_SISI,2)
 764 //
 765 def int_hexagon_C2_cmpeq :
 766 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpeq">;
 767 //
 768 // BUILTIN_INFO(HEXAGON.C2_cmpgt,QI_ftype_SISI,2)
 769 //
 770 def int_hexagon_C2_cmpgt :
 771 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgt">;
 772 //
 773 // BUILTIN_INFO(HEXAGON.C2_cmpgtu,QI_ftype_SISI,2)
 774 //
 775 def int_hexagon_C2_cmpgtu :
 776 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgtu">;
 777 //
 778 // BUILTIN_INFO(HEXAGON.C2_cmpeqp,QI_ftype_DIDI,2)
 779 //
 780 def int_hexagon_C2_cmpeqp :
 781 Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpeqp">;
 782 //
 783 // BUILTIN_INFO(HEXAGON.C2_cmpgtp,QI_ftype_DIDI,2)
 784 //
 785 def int_hexagon_C2_cmpgtp :
 786 Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpgtp">;
 787 //
 788 // BUILTIN_INFO(HEXAGON.C2_cmpgtup,QI_ftype_DIDI,2)
 789 //
 790 def int_hexagon_C2_cmpgtup :
 791 Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpgtup">;
 792 //
 793 // BUILTIN_INFO(HEXAGON.A4_rcmpeqi,SI_ftype_SISI,2)
 794 //
 795 def int_hexagon_A4_rcmpeqi :
 796 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpeqi">;
 797 //
 798 // BUILTIN_INFO(HEXAGON.A4_rcmpneqi,SI_ftype_SISI,2)
 799 //
 800 def int_hexagon_A4_rcmpneqi :
 801 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneqi">;
 802 //
 803 // BUILTIN_INFO(HEXAGON.A4_rcmpeq,SI_ftype_SISI,2)
 804 //
 805 def int_hexagon_A4_rcmpeq :
 806 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpeq">;
 807 //
 808 // BUILTIN_INFO(HEXAGON.A4_rcmpneq,SI_ftype_SISI,2)
 809 //
 810 def int_hexagon_A4_rcmpneq :
 811 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneq">;
 812 //
 813 // BUILTIN_INFO(HEXAGON.C2_bitsset,QI_ftype_SISI,2)
 814 //
 815 def int_hexagon_C2_bitsset :
 816 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsset">;
 817 //
 818 // BUILTIN_INFO(HEXAGON.C2_bitsclr,QI_ftype_SISI,2)
 819 //
 820 def int_hexagon_C2_bitsclr :
 821 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsclr">;
 822 //
 823 // BUILTIN_INFO(HEXAGON.C4_nbitsset,QI_ftype_SISI,2)
 824 //
 825 def int_hexagon_C4_nbitsset :
 826 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsset">;
 827 //
 828 // BUILTIN_INFO(HEXAGON.C4_nbitsclr,QI_ftype_SISI,2)
 829 //
 830 def int_hexagon_C4_nbitsclr :
 831 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsclr">;
 832 //
 833 // BUILTIN_INFO(HEXAGON.C2_cmpeqi,QI_ftype_SISI,2)
 834 //
 835 def int_hexagon_C2_cmpeqi :
 836 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpeqi">;
 837 //
 838 // BUILTIN_INFO(HEXAGON.C2_cmpgti,QI_ftype_SISI,2)
 839 //
 840 def int_hexagon_C2_cmpgti :
 841 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgti">;
 842 //
 843 // BUILTIN_INFO(HEXAGON.C2_cmpgtui,QI_ftype_SISI,2)
 844 //
 845 def int_hexagon_C2_cmpgtui :
 846 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgtui">;
 847 //
 848 // BUILTIN_INFO(HEXAGON.C2_cmpgei,QI_ftype_SISI,2)
 849 //
 850 def int_hexagon_C2_cmpgei :
 851 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgei">;
 852 //
 853 // BUILTIN_INFO(HEXAGON.C2_cmpgeui,QI_ftype_SISI,2)
 854 //
 855 def int_hexagon_C2_cmpgeui :
 856 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgeui">;
 857 //
 858 // BUILTIN_INFO(HEXAGON.C2_cmplt,QI_ftype_SISI,2)
 859 //
 860 def int_hexagon_C2_cmplt :
 861 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmplt">;
 862 //
 863 // BUILTIN_INFO(HEXAGON.C2_cmpltu,QI_ftype_SISI,2)
 864 //
 865 def int_hexagon_C2_cmpltu :
 866 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpltu">;
 867 //
 868 // BUILTIN_INFO(HEXAGON.C2_bitsclri,QI_ftype_SISI,2)
 869 //
 870 def int_hexagon_C2_bitsclri :
 871 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsclri">;
 872 //
 873 // BUILTIN_INFO(HEXAGON.C4_nbitsclri,QI_ftype_SISI,2)
 874 //
 875 def int_hexagon_C4_nbitsclri :
 876 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsclri">;
 877 //
 878 // BUILTIN_INFO(HEXAGON.C4_cmpneqi,QI_ftype_SISI,2)
 879 //
 880 def int_hexagon_C4_cmpneqi :
 881 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpneqi">;
 882 //
 883 // BUILTIN_INFO(HEXAGON.C4_cmpltei,QI_ftype_SISI,2)
 884 //
 885 def int_hexagon_C4_cmpltei :
 886 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpltei">;
 887 //
 888 // BUILTIN_INFO(HEXAGON.C4_cmplteui,QI_ftype_SISI,2)
 889 //
 890 def int_hexagon_C4_cmplteui :
 891 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplteui">;
 892 //
 893 // BUILTIN_INFO(HEXAGON.C4_cmpneq,QI_ftype_SISI,2)
 894 //
 895 def int_hexagon_C4_cmpneq :
 896 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpneq">;
 897 //
 898 // BUILTIN_INFO(HEXAGON.C4_cmplte,QI_ftype_SISI,2)
 899 //
 900 def int_hexagon_C4_cmplte :
 901 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplte">;
 902 //
 903 // BUILTIN_INFO(HEXAGON.C4_cmplteu,QI_ftype_SISI,2)
 904 //
 905 def int_hexagon_C4_cmplteu :
 906 Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplteu">;
 907 //
 908 // BUILTIN_INFO(HEXAGON.C2_and,QI_ftype_QIQI,2)
 909 //
 910 def int_hexagon_C2_and :
 911 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_and">;
 912 //
 913 // BUILTIN_INFO(HEXAGON.C2_or,QI_ftype_QIQI,2)
 914 //
 915 def int_hexagon_C2_or :
 916 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_or">;
 917 //
 918 // BUILTIN_INFO(HEXAGON.C2_xor,QI_ftype_QIQI,2)
 919 //
 920 def int_hexagon_C2_xor :
 921 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_xor">;
 922 //
 923 // BUILTIN_INFO(HEXAGON.C2_andn,QI_ftype_QIQI,2)
 924 //
 925 def int_hexagon_C2_andn :
 926 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_andn">;
 927 //
 928 // BUILTIN_INFO(HEXAGON.C2_not,QI_ftype_QI,1)
 929 //
 930 def int_hexagon_C2_not :
 931 Hexagon_si_si_Intrinsic<"HEXAGON_C2_not">;
 932 //
 933 // BUILTIN_INFO(HEXAGON.C2_orn,QI_ftype_QIQI,2)
 934 //
 935 def int_hexagon_C2_orn :
 936 Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_orn">;
 937 //
 938 // BUILTIN_INFO(HEXAGON.C4_and_and,QI_ftype_QIQIQI,3)
 939 //
 940 def int_hexagon_C4_and_and :
 941 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_and">;
 942 //
 943 // BUILTIN_INFO(HEXAGON.C4_and_or,QI_ftype_QIQIQI,3)
 944 //
 945 def int_hexagon_C4_and_or :
 946 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_or">;
 947 //
 948 // BUILTIN_INFO(HEXAGON.C4_or_and,QI_ftype_QIQIQI,3)
 949 //
 950 def int_hexagon_C4_or_and :
 951 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_and">;
 952 //
 953 // BUILTIN_INFO(HEXAGON.C4_or_or,QI_ftype_QIQIQI,3)
 954 //
 955 def int_hexagon_C4_or_or :
 956 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_or">;
 957 //
 958 // BUILTIN_INFO(HEXAGON.C4_and_andn,QI_ftype_QIQIQI,3)
 959 //
 960 def int_hexagon_C4_and_andn :
 961 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_andn">;
 962 //
 963 // BUILTIN_INFO(HEXAGON.C4_and_orn,QI_ftype_QIQIQI,3)
 964 //
 965 def int_hexagon_C4_and_orn :
 966 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_orn">;
 967 //
 968 // BUILTIN_INFO(HEXAGON.C4_or_andn,QI_ftype_QIQIQI,3)
 969 //
 970 def int_hexagon_C4_or_andn :
 971 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_andn">;
 972 //
 973 // BUILTIN_INFO(HEXAGON.C4_or_orn,QI_ftype_QIQIQI,3)
 974 //
 975 def int_hexagon_C4_or_orn :
 976 Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_orn">;
 977 //
 978 // BUILTIN_INFO(HEXAGON.C2_pxfer_map,QI_ftype_QI,1)
 979 //
 980 def int_hexagon_C2_pxfer_map :
 981 Hexagon_si_qi_Intrinsic<"HEXAGON_C2_pxfer_map">;
 982 //
 983 // BUILTIN_INFO(HEXAGON.C2_any8,QI_ftype_QI,1)
 984 //
 985 def int_hexagon_C2_any8 :
 986 Hexagon_si_qi_Intrinsic<"HEXAGON_C2_any8">;
 987 //
 988 // BUILTIN_INFO(HEXAGON.C2_all8,QI_ftype_QI,1)
 989 //
 990 def int_hexagon_C2_all8 :
 991 Hexagon_si_qi_Intrinsic<"HEXAGON_C2_all8">;
 992 //
 993 // BUILTIN_INFO(HEXAGON.C2_vitpack,SI_ftype_QIQI,2)
 994 //
 995 def int_hexagon_C2_vitpack :
 996 Hexagon_si_qiqi_Intrinsic<"HEXAGON_C2_vitpack">;
 997 //
 998 // BUILTIN_INFO(HEXAGON.C2_mux,SI_ftype_QISISI,3)
 999 //
1000 def int_hexagon_C2_mux :
1001 Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_mux">;
1002 //
1003 // BUILTIN_INFO(HEXAGON.C2_muxii,SI_ftype_QISISI,3)
1004 //
1005 def int_hexagon_C2_muxii :
1006 Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxii">;
1007 //
1008 // BUILTIN_INFO(HEXAGON.C2_muxir,SI_ftype_QISISI,3)
1009 //
1010 def int_hexagon_C2_muxir :
1011 Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxir">;
1012 //
1013 // BUILTIN_INFO(HEXAGON.C2_muxri,SI_ftype_QISISI,3)
1014 //
1015 def int_hexagon_C2_muxri :
1016 Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxri">;
1017 //
1018 // BUILTIN_INFO(HEXAGON.C2_vmux,DI_ftype_QIDIDI,3)
1019 //
1020 def int_hexagon_C2_vmux :
1021 Hexagon_di_qididi_Intrinsic<"HEXAGON_C2_vmux">;
1022 //
1023 // BUILTIN_INFO(HEXAGON.C2_mask,DI_ftype_QI,1)
1024 //
1025 def int_hexagon_C2_mask :
1026 Hexagon_di_qi_Intrinsic<"HEXAGON_C2_mask">;
1027 //
1028 // BUILTIN_INFO(HEXAGON.A2_vcmpbeq,QI_ftype_DIDI,2)
1029 //
1030 def int_hexagon_A2_vcmpbeq :
1031 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpbeq">;
1032 //
1033 // BUILTIN_INFO(HEXAGON.A4_vcmpbeqi,QI_ftype_DISI,2)
1034 //
1035 def int_hexagon_A4_vcmpbeqi :
1036 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbeqi">;
1037 //
1038 // BUILTIN_INFO(HEXAGON.A4_vcmpbeq_any,QI_ftype_DIDI,2)
1039 //
1040 def int_hexagon_A4_vcmpbeq_any :
1041 Hexagon_si_didi_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;
1042 //
1043 // BUILTIN_INFO(HEXAGON.A2_vcmpbgtu,QI_ftype_DIDI,2)
1044 //
1045 def int_hexagon_A2_vcmpbgtu :
1046 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpbgtu">;
1047 //
1048 // BUILTIN_INFO(HEXAGON.A4_vcmpbgtui,QI_ftype_DISI,2)
1049 //
1050 def int_hexagon_A4_vcmpbgtui :
1051 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbgtui">;
1052 //
1053 // BUILTIN_INFO(HEXAGON.A4_vcmpbgt,QI_ftype_DIDI,2)
1054 //
1055 def int_hexagon_A4_vcmpbgt :
1056 Hexagon_si_didi_Intrinsic<"HEXAGON_A4_vcmpbgt">;
1057 //
1058 // BUILTIN_INFO(HEXAGON.A4_vcmpbgti,QI_ftype_DISI,2)
1059 //
1060 def int_hexagon_A4_vcmpbgti :
1061 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbgti">;
1062 //
1063 // BUILTIN_INFO(HEXAGON.A4_cmpbeq,QI_ftype_SISI,2)
1064 //
1065 def int_hexagon_A4_cmpbeq :
1066 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbeq">;
1067 //
1068 // BUILTIN_INFO(HEXAGON.A4_cmpbeqi,QI_ftype_SISI,2)
1069 //
1070 def int_hexagon_A4_cmpbeqi :
1071 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbeqi">;
1072 //
1073 // BUILTIN_INFO(HEXAGON.A4_cmpbgtu,QI_ftype_SISI,2)
1074 //
1075 def int_hexagon_A4_cmpbgtu :
1076 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgtu">;
1077 //
1078 // BUILTIN_INFO(HEXAGON.A4_cmpbgtui,QI_ftype_SISI,2)
1079 //
1080 def int_hexagon_A4_cmpbgtui :
1081 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgtui">;
1082 //
1083 // BUILTIN_INFO(HEXAGON.A4_cmpbgt,QI_ftype_SISI,2)
1084 //
1085 def int_hexagon_A4_cmpbgt :
1086 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgt">;
1087 //
1088 // BUILTIN_INFO(HEXAGON.A4_cmpbgti,QI_ftype_SISI,2)
1089 //
1090 def int_hexagon_A4_cmpbgti :
1091 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgti">;
1092 //
1093 // BUILTIN_INFO(HEXAGON.A2_vcmpheq,QI_ftype_DIDI,2)
1094 //
1095 def int_hexagon_A2_vcmpheq :
1096 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpheq">;
1097 //
1098 // BUILTIN_INFO(HEXAGON.A2_vcmphgt,QI_ftype_DIDI,2)
1099 //
1100 def int_hexagon_A2_vcmphgt :
1101 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmphgt">;
1102 //
1103 // BUILTIN_INFO(HEXAGON.A2_vcmphgtu,QI_ftype_DIDI,2)
1104 //
1105 def int_hexagon_A2_vcmphgtu :
1106 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmphgtu">;
1107 //
1108 // BUILTIN_INFO(HEXAGON.A4_vcmpheqi,QI_ftype_DISI,2)
1109 //
1110 def int_hexagon_A4_vcmpheqi :
1111 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpheqi">;
1112 //
1113 // BUILTIN_INFO(HEXAGON.A4_vcmphgti,QI_ftype_DISI,2)
1114 //
1115 def int_hexagon_A4_vcmphgti :
1116 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmphgti">;
1117 //
1118 // BUILTIN_INFO(HEXAGON.A4_vcmphgtui,QI_ftype_DISI,2)
1119 //
1120 def int_hexagon_A4_vcmphgtui :
1121 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmphgtui">;
1122 //
1123 // BUILTIN_INFO(HEXAGON.A4_cmpheq,QI_ftype_SISI,2)
1124 //
1125 def int_hexagon_A4_cmpheq :
1126 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpheq">;
1127 //
1128 // BUILTIN_INFO(HEXAGON.A4_cmphgt,QI_ftype_SISI,2)
1129 //
1130 def int_hexagon_A4_cmphgt :
1131 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgt">;
1132 //
1133 // BUILTIN_INFO(HEXAGON.A4_cmphgtu,QI_ftype_SISI,2)
1134 //
1135 def int_hexagon_A4_cmphgtu :
1136 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgtu">;
1137 //
1138 // BUILTIN_INFO(HEXAGON.A4_cmpheqi,QI_ftype_SISI,2)
1139 //
1140 def int_hexagon_A4_cmpheqi :
1141 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpheqi">;
1142 //
1143 // BUILTIN_INFO(HEXAGON.A4_cmphgti,QI_ftype_SISI,2)
1144 //
1145 def int_hexagon_A4_cmphgti :
1146 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgti">;
1147 //
1148 // BUILTIN_INFO(HEXAGON.A4_cmphgtui,QI_ftype_SISI,2)
1149 //
1150 def int_hexagon_A4_cmphgtui :
1151 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgtui">;
1152 //
1153 // BUILTIN_INFO(HEXAGON.A2_vcmpweq,QI_ftype_DIDI,2)
1154 //
1155 def int_hexagon_A2_vcmpweq :
1156 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpweq">;
1157 //
1158 // BUILTIN_INFO(HEXAGON.A2_vcmpwgt,QI_ftype_DIDI,2)
1159 //
1160 def int_hexagon_A2_vcmpwgt :
1161 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpwgt">;
1162 //
1163 // BUILTIN_INFO(HEXAGON.A2_vcmpwgtu,QI_ftype_DIDI,2)
1164 //
1165 def int_hexagon_A2_vcmpwgtu :
1166 Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpwgtu">;
1167 //
1168 // BUILTIN_INFO(HEXAGON.A4_vcmpweqi,QI_ftype_DISI,2)
1169 //
1170 def int_hexagon_A4_vcmpweqi :
1171 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpweqi">;
1172 //
1173 // BUILTIN_INFO(HEXAGON.A4_vcmpwgti,QI_ftype_DISI,2)
1174 //
1175 def int_hexagon_A4_vcmpwgti :
1176 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpwgti">;
1177 //
1178 // BUILTIN_INFO(HEXAGON.A4_vcmpwgtui,QI_ftype_DISI,2)
1179 //
1180 def int_hexagon_A4_vcmpwgtui :
1181 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpwgtui">;
1182 //
1183 // BUILTIN_INFO(HEXAGON.A4_boundscheck,QI_ftype_SIDI,2)
1184 //
1185 def int_hexagon_A4_boundscheck :
1186 Hexagon_si_sidi_Intrinsic<"HEXAGON_A4_boundscheck">;
1187 //
1188 // BUILTIN_INFO(HEXAGON.A4_tlbmatch,QI_ftype_DISI,2)
1189 //
1190 def int_hexagon_A4_tlbmatch :
1191 Hexagon_si_disi_Intrinsic<"HEXAGON_A4_tlbmatch">;
1192 //
1193 // BUILTIN_INFO(HEXAGON.C2_tfrpr,SI_ftype_QI,1)
1194 //
1195 def int_hexagon_C2_tfrpr :
1196 Hexagon_si_qi_Intrinsic<"HEXAGON_C2_tfrpr">;
1197 //
1198 // BUILTIN_INFO(HEXAGON.C2_tfrrp,QI_ftype_SI,1)
1199 //
1200 def int_hexagon_C2_tfrrp :
1201 Hexagon_si_si_Intrinsic<"HEXAGON_C2_tfrrp">;
1202 //
1203 // BUILTIN_INFO(HEXAGON.C4_fastcorner9,QI_ftype_QIQI,2)
1204 //
1205 def int_hexagon_C4_fastcorner9 :
1206 Hexagon_si_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9">;
1207 //
1208 // BUILTIN_INFO(HEXAGON.C4_fastcorner9_not,QI_ftype_QIQI,2)
1209 //
1210 def int_hexagon_C4_fastcorner9_not :
1211 Hexagon_si_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9_not">;
1212 //
1213 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s0,SI_ftype_SISISI,3)
1214 //
1215 def int_hexagon_M2_mpy_acc_hh_s0 :
1216 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;
1217 //
1218 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s1,SI_ftype_SISISI,3)
1219 //
1220 def int_hexagon_M2_mpy_acc_hh_s1 :
1221 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;
1222 //
1223 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s0,SI_ftype_SISISI,3)
1224 //
1225 def int_hexagon_M2_mpy_acc_hl_s0 :
1226 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;
1227 //
1228 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s1,SI_ftype_SISISI,3)
1229 //
1230 def int_hexagon_M2_mpy_acc_hl_s1 :
1231 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;
1232 //
1233 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s0,SI_ftype_SISISI,3)
1234 //
1235 def int_hexagon_M2_mpy_acc_lh_s0 :
1236 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;
1237 //
1238 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s1,SI_ftype_SISISI,3)
1239 //
1240 def int_hexagon_M2_mpy_acc_lh_s1 :
1241 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;
1242 //
1243 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s0,SI_ftype_SISISI,3)
1244 //
1245 def int_hexagon_M2_mpy_acc_ll_s0 :
1246 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;
1247 //
1248 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s1,SI_ftype_SISISI,3)
1249 //
1250 def int_hexagon_M2_mpy_acc_ll_s1 :
1251 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;
1252 //
1253 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s0,SI_ftype_SISISI,3)
1254 //
1255 def int_hexagon_M2_mpy_nac_hh_s0 :
1256 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;
1257 //
1258 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s1,SI_ftype_SISISI,3)
1259 //
1260 def int_hexagon_M2_mpy_nac_hh_s1 :
1261 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;
1262 //
1263 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s0,SI_ftype_SISISI,3)
1264 //
1265 def int_hexagon_M2_mpy_nac_hl_s0 :
1266 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;
1267 //
1268 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s1,SI_ftype_SISISI,3)
1269 //
1270 def int_hexagon_M2_mpy_nac_hl_s1 :
1271 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;
1272 //
1273 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s0,SI_ftype_SISISI,3)
1274 //
1275 def int_hexagon_M2_mpy_nac_lh_s0 :
1276 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">;
1277 //
1278 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s1,SI_ftype_SISISI,3)
1279 //
1280 def int_hexagon_M2_mpy_nac_lh_s1 :
1281 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">;
1282 //
1283 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s0,SI_ftype_SISISI,3)
1284 //
1285 def int_hexagon_M2_mpy_nac_ll_s0 :
1286 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">;
1287 //
1288 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s1,SI_ftype_SISISI,3)
1289 //
1290 def int_hexagon_M2_mpy_nac_ll_s1 :
1291 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">;
1292 //
1293 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s0,SI_ftype_SISISI,3)
1294 //
1295 def int_hexagon_M2_mpy_acc_sat_hh_s0 :
1296 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;
1297 //
1298 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s1,SI_ftype_SISISI,3)
1299 //
1300 def int_hexagon_M2_mpy_acc_sat_hh_s1 :
1301 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;
1302 //
1303 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s0,SI_ftype_SISISI,3)
1304 //
1305 def int_hexagon_M2_mpy_acc_sat_hl_s0 :
1306 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;
1307 //
1308 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s1,SI_ftype_SISISI,3)
1309 //
1310 def int_hexagon_M2_mpy_acc_sat_hl_s1 :
1311 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;
1312 //
1313 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s0,SI_ftype_SISISI,3)
1314 //
1315 def int_hexagon_M2_mpy_acc_sat_lh_s0 :
1316 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;
1317 //
1318 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s1,SI_ftype_SISISI,3)
1319 //
1320 def int_hexagon_M2_mpy_acc_sat_lh_s1 :
1321 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;
1322 //
1323 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s0,SI_ftype_SISISI,3)
1324 //
1325 def int_hexagon_M2_mpy_acc_sat_ll_s0 :
1326 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">;
1327 //
1328 // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s1,SI_ftype_SISISI,3)
1329 //
1330 def int_hexagon_M2_mpy_acc_sat_ll_s1 :
1331 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">;
1332 //
1333 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s0,SI_ftype_SISISI,3)
1334 //
1335 def int_hexagon_M2_mpy_nac_sat_hh_s0 :
1336 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;
1337 //
1338 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s1,SI_ftype_SISISI,3)
1339 //
1340 def int_hexagon_M2_mpy_nac_sat_hh_s1 :
1341 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;
1342 //
1343 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s0,SI_ftype_SISISI,3)
1344 //
1345 def int_hexagon_M2_mpy_nac_sat_hl_s0 :
1346 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;
1347 //
1348 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s1,SI_ftype_SISISI,3)
1349 //
1350 def int_hexagon_M2_mpy_nac_sat_hl_s1 :
1351 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;
1352 //
1353 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s0,SI_ftype_SISISI,3)
1354 //
1355 def int_hexagon_M2_mpy_nac_sat_lh_s0 :
1356 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;
1357 //
1358 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s1,SI_ftype_SISISI,3)
1359 //
1360 def int_hexagon_M2_mpy_nac_sat_lh_s1 :
1361 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;
1362 //
1363 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s0,SI_ftype_SISISI,3)
1364 //
1365 def int_hexagon_M2_mpy_nac_sat_ll_s0 :
1366 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;
1367 //
1368 // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s1,SI_ftype_SISISI,3)
1369 //
1370 def int_hexagon_M2_mpy_nac_sat_ll_s1 :
1371 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;
1372 //
1373 // BUILTIN_INFO(HEXAGON.M2_mpy_hh_s0,SI_ftype_SISI,2)
1374 //
1375 def int_hexagon_M2_mpy_hh_s0 :
1376 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;
1377 //
1378 // BUILTIN_INFO(HEXAGON.M2_mpy_hh_s1,SI_ftype_SISI,2)
1379 //
1380 def int_hexagon_M2_mpy_hh_s1 :
1381 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;
1382 //
1383 // BUILTIN_INFO(HEXAGON.M2_mpy_hl_s0,SI_ftype_SISI,2)
1384 //
1385 def int_hexagon_M2_mpy_hl_s0 :
1386 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;
1387 //
1388 // BUILTIN_INFO(HEXAGON.M2_mpy_hl_s1,SI_ftype_SISI,2)
1389 //
1390 def int_hexagon_M2_mpy_hl_s1 :
1391 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;
1392 //
1393 // BUILTIN_INFO(HEXAGON.M2_mpy_lh_s0,SI_ftype_SISI,2)
1394 //
1395 def int_hexagon_M2_mpy_lh_s0 :
1396 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;
1397 //
1398 // BUILTIN_INFO(HEXAGON.M2_mpy_lh_s1,SI_ftype_SISI,2)
1399 //
1400 def int_hexagon_M2_mpy_lh_s1 :
1401 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;
1402 //
1403 // BUILTIN_INFO(HEXAGON.M2_mpy_ll_s0,SI_ftype_SISI,2)
1404 //
1405 def int_hexagon_M2_mpy_ll_s0 :
1406 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;
1407 //
1408 // BUILTIN_INFO(HEXAGON.M2_mpy_ll_s1,SI_ftype_SISI,2)
1409 //
1410 def int_hexagon_M2_mpy_ll_s1 :
1411 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;
1412 //
1413 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s0,SI_ftype_SISI,2)
1414 //
1415 def int_hexagon_M2_mpy_sat_hh_s0 :
1416 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;
1417 //
1418 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s1,SI_ftype_SISI,2)
1419 //
1420 def int_hexagon_M2_mpy_sat_hh_s1 :
1421 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;
1422 //
1423 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s0,SI_ftype_SISI,2)
1424 //
1425 def int_hexagon_M2_mpy_sat_hl_s0 :
1426 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;
1427 //
1428 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s1,SI_ftype_SISI,2)
1429 //
1430 def int_hexagon_M2_mpy_sat_hl_s1 :
1431 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;
1432 //
1433 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s0,SI_ftype_SISI,2)
1434 //
1435 def int_hexagon_M2_mpy_sat_lh_s0 :
1436 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">;
1437 //
1438 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s1,SI_ftype_SISI,2)
1439 //
1440 def int_hexagon_M2_mpy_sat_lh_s1 :
1441 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;
1442 //
1443 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s0,SI_ftype_SISI,2)
1444 //
1445 def int_hexagon_M2_mpy_sat_ll_s0 :
1446 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;
1447 //
1448 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s1,SI_ftype_SISI,2)
1449 //
1450 def int_hexagon_M2_mpy_sat_ll_s1 :
1451 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;
1452 //
1453 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s0,SI_ftype_SISI,2)
1454 //
1455 def int_hexagon_M2_mpy_rnd_hh_s0 :
1456 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;
1457 //
1458 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s1,SI_ftype_SISI,2)
1459 //
1460 def int_hexagon_M2_mpy_rnd_hh_s1 :
1461 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;
1462 //
1463 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s0,SI_ftype_SISI,2)
1464 //
1465 def int_hexagon_M2_mpy_rnd_hl_s0 :
1466 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;
1467 //
1468 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s1,SI_ftype_SISI,2)
1469 //
1470 def int_hexagon_M2_mpy_rnd_hl_s1 :
1471 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;
1472 //
1473 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s0,SI_ftype_SISI,2)
1474 //
1475 def int_hexagon_M2_mpy_rnd_lh_s0 :
1476 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;
1477 //
1478 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s1,SI_ftype_SISI,2)
1479 //
1480 def int_hexagon_M2_mpy_rnd_lh_s1 :
1481 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;
1482 //
1483 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s0,SI_ftype_SISI,2)
1484 //
1485 def int_hexagon_M2_mpy_rnd_ll_s0 :
1486 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;
1487 //
1488 // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s1,SI_ftype_SISI,2)
1489 //
1490 def int_hexagon_M2_mpy_rnd_ll_s1 :
1491 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;
1492 //
1493 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s0,SI_ftype_SISI,2)
1494 //
1495 def int_hexagon_M2_mpy_sat_rnd_hh_s0 :
1496 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;
1497 //
1498 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s1,SI_ftype_SISI,2)
1499 //
1500 def int_hexagon_M2_mpy_sat_rnd_hh_s1 :
1501 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;
1502 //
1503 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s0,SI_ftype_SISI,2)
1504 //
1505 def int_hexagon_M2_mpy_sat_rnd_hl_s0 :
1506 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;
1507 //
1508 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s1,SI_ftype_SISI,2)
1509 //
1510 def int_hexagon_M2_mpy_sat_rnd_hl_s1 :
1511 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;
1512 //
1513 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s0,SI_ftype_SISI,2)
1514 //
1515 def int_hexagon_M2_mpy_sat_rnd_lh_s0 :
1516 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;
1517 //
1518 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s1,SI_ftype_SISI,2)
1519 //
1520 def int_hexagon_M2_mpy_sat_rnd_lh_s1 :
1521 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;
1522 //
1523 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s0,SI_ftype_SISI,2)
1524 //
1525 def int_hexagon_M2_mpy_sat_rnd_ll_s0 :
1526 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;
1527 //
1528 // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s1,SI_ftype_SISI,2)
1529 //
1530 def int_hexagon_M2_mpy_sat_rnd_ll_s1 :
1531 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;
1532 //
1533 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s0,DI_ftype_DISISI,3)
1534 //
1535 def int_hexagon_M2_mpyd_acc_hh_s0 :
1536 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;
1537 //
1538 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s1,DI_ftype_DISISI,3)
1539 //
1540 def int_hexagon_M2_mpyd_acc_hh_s1 :
1541 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;
1542 //
1543 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s0,DI_ftype_DISISI,3)
1544 //
1545 def int_hexagon_M2_mpyd_acc_hl_s0 :
1546 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;
1547 //
1548 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s1,DI_ftype_DISISI,3)
1549 //
1550 def int_hexagon_M2_mpyd_acc_hl_s1 :
1551 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;
1552 //
1553 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s0,DI_ftype_DISISI,3)
1554 //
1555 def int_hexagon_M2_mpyd_acc_lh_s0 :
1556 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;
1557 //
1558 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s1,DI_ftype_DISISI,3)
1559 //
1560 def int_hexagon_M2_mpyd_acc_lh_s1 :
1561 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;
1562 //
1563 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s0,DI_ftype_DISISI,3)
1564 //
1565 def int_hexagon_M2_mpyd_acc_ll_s0 :
1566 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;
1567 //
1568 // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s1,DI_ftype_DISISI,3)
1569 //
1570 def int_hexagon_M2_mpyd_acc_ll_s1 :
1571 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;
1572 //
1573 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s0,DI_ftype_DISISI,3)
1574 //
1575 def int_hexagon_M2_mpyd_nac_hh_s0 :
1576 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;
1577 //
1578 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s1,DI_ftype_DISISI,3)
1579 //
1580 def int_hexagon_M2_mpyd_nac_hh_s1 :
1581 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;
1582 //
1583 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s0,DI_ftype_DISISI,3)
1584 //
1585 def int_hexagon_M2_mpyd_nac_hl_s0 :
1586 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">;
1587 //
1588 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s1,DI_ftype_DISISI,3)
1589 //
1590 def int_hexagon_M2_mpyd_nac_hl_s1 :
1591 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">;
1592 //
1593 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s0,DI_ftype_DISISI,3)
1594 //
1595 def int_hexagon_M2_mpyd_nac_lh_s0 :
1596 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;
1597 //
1598 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s1,DI_ftype_DISISI,3)
1599 //
1600 def int_hexagon_M2_mpyd_nac_lh_s1 :
1601 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;
1602 //
1603 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s0,DI_ftype_DISISI,3)
1604 //
1605 def int_hexagon_M2_mpyd_nac_ll_s0 :
1606 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;
1607 //
1608 // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s1,DI_ftype_DISISI,3)
1609 //
1610 def int_hexagon_M2_mpyd_nac_ll_s1 :
1611 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;
1612 //
1613 // BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s0,DI_ftype_SISI,2)
1614 //
1615 def int_hexagon_M2_mpyd_hh_s0 :
1616 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;
1617 //
1618 // BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s1,DI_ftype_SISI,2)
1619 //
1620 def int_hexagon_M2_mpyd_hh_s1 :
1621 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;
1622 //
1623 // BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s0,DI_ftype_SISI,2)
1624 //
1625 def int_hexagon_M2_mpyd_hl_s0 :
1626 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;
1627 //
1628 // BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s1,DI_ftype_SISI,2)
1629 //
1630 def int_hexagon_M2_mpyd_hl_s1 :
1631 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;
1632 //
1633 // BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s0,DI_ftype_SISI,2)
1634 //
1635 def int_hexagon_M2_mpyd_lh_s0 :
1636 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;
1637 //
1638 // BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s1,DI_ftype_SISI,2)
1639 //
1640 def int_hexagon_M2_mpyd_lh_s1 :
1641 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;
1642 //
1643 // BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s0,DI_ftype_SISI,2)
1644 //
1645 def int_hexagon_M2_mpyd_ll_s0 :
1646 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;
1647 //
1648 // BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s1,DI_ftype_SISI,2)
1649 //
1650 def int_hexagon_M2_mpyd_ll_s1 :
1651 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;
1652 //
1653 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s0,DI_ftype_SISI,2)
1654 //
1655 def int_hexagon_M2_mpyd_rnd_hh_s0 :
1656 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">;
1657 //
1658 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s1,DI_ftype_SISI,2)
1659 //
1660 def int_hexagon_M2_mpyd_rnd_hh_s1 :
1661 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;
1662 //
1663 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s0,DI_ftype_SISI,2)
1664 //
1665 def int_hexagon_M2_mpyd_rnd_hl_s0 :
1666 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">;
1667 //
1668 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s1,DI_ftype_SISI,2)
1669 //
1670 def int_hexagon_M2_mpyd_rnd_hl_s1 :
1671 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">;
1672 //
1673 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s0,DI_ftype_SISI,2)
1674 //
1675 def int_hexagon_M2_mpyd_rnd_lh_s0 :
1676 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;
1677 //
1678 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s1,DI_ftype_SISI,2)
1679 //
1680 def int_hexagon_M2_mpyd_rnd_lh_s1 :
1681 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;
1682 //
1683 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s0,DI_ftype_SISI,2)
1684 //
1685 def int_hexagon_M2_mpyd_rnd_ll_s0 :
1686 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;
1687 //
1688 // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s1,DI_ftype_SISI,2)
1689 //
1690 def int_hexagon_M2_mpyd_rnd_ll_s1 :
1691 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;
1692 //
1693 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s0,SI_ftype_SISISI,3)
1694 //
1695 def int_hexagon_M2_mpyu_acc_hh_s0 :
1696 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;
1697 //
1698 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s1,SI_ftype_SISISI,3)
1699 //
1700 def int_hexagon_M2_mpyu_acc_hh_s1 :
1701 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;
1702 //
1703 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s0,SI_ftype_SISISI,3)
1704 //
1705 def int_hexagon_M2_mpyu_acc_hl_s0 :
1706 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">;
1707 //
1708 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s1,SI_ftype_SISISI,3)
1709 //
1710 def int_hexagon_M2_mpyu_acc_hl_s1 :
1711 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">;
1712 //
1713 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s0,SI_ftype_SISISI,3)
1714 //
1715 def int_hexagon_M2_mpyu_acc_lh_s0 :
1716 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;
1717 //
1718 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s1,SI_ftype_SISISI,3)
1719 //
1720 def int_hexagon_M2_mpyu_acc_lh_s1 :
1721 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;
1722 //
1723 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s0,SI_ftype_SISISI,3)
1724 //
1725 def int_hexagon_M2_mpyu_acc_ll_s0 :
1726 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">;
1727 //
1728 // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s1,SI_ftype_SISISI,3)
1729 //
1730 def int_hexagon_M2_mpyu_acc_ll_s1 :
1731 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;
1732 //
1733 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s0,SI_ftype_SISISI,3)
1734 //
1735 def int_hexagon_M2_mpyu_nac_hh_s0 :
1736 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;
1737 //
1738 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s1,SI_ftype_SISISI,3)
1739 //
1740 def int_hexagon_M2_mpyu_nac_hh_s1 :
1741 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;
1742 //
1743 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s0,SI_ftype_SISISI,3)
1744 //
1745 def int_hexagon_M2_mpyu_nac_hl_s0 :
1746 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;
1747 //
1748 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s1,SI_ftype_SISISI,3)
1749 //
1750 def int_hexagon_M2_mpyu_nac_hl_s1 :
1751 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;
1752 //
1753 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s0,SI_ftype_SISISI,3)
1754 //
1755 def int_hexagon_M2_mpyu_nac_lh_s0 :
1756 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;
1757 //
1758 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s1,SI_ftype_SISISI,3)
1759 //
1760 def int_hexagon_M2_mpyu_nac_lh_s1 :
1761 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;
1762 //
1763 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s0,SI_ftype_SISISI,3)
1764 //
1765 def int_hexagon_M2_mpyu_nac_ll_s0 :
1766 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;
1767 //
1768 // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s1,SI_ftype_SISISI,3)
1769 //
1770 def int_hexagon_M2_mpyu_nac_ll_s1 :
1771 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;
1772 //
1773 // BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s0,USI_ftype_SISI,2)
1774 //
1775 def int_hexagon_M2_mpyu_hh_s0 :
1776 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;
1777 //
1778 // BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s1,USI_ftype_SISI,2)
1779 //
1780 def int_hexagon_M2_mpyu_hh_s1 :
1781 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;
1782 //
1783 // BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s0,USI_ftype_SISI,2)
1784 //
1785 def int_hexagon_M2_mpyu_hl_s0 :
1786 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;
1787 //
1788 // BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s1,USI_ftype_SISI,2)
1789 //
1790 def int_hexagon_M2_mpyu_hl_s1 :
1791 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;
1792 //
1793 // BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s0,USI_ftype_SISI,2)
1794 //
1795 def int_hexagon_M2_mpyu_lh_s0 :
1796 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;
1797 //
1798 // BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s1,USI_ftype_SISI,2)
1799 //
1800 def int_hexagon_M2_mpyu_lh_s1 :
1801 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;
1802 //
1803 // BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s0,USI_ftype_SISI,2)
1804 //
1805 def int_hexagon_M2_mpyu_ll_s0 :
1806 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;
1807 //
1808 // BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s1,USI_ftype_SISI,2)
1809 //
1810 def int_hexagon_M2_mpyu_ll_s1 :
1811 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;
1812 //
1813 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s0,DI_ftype_DISISI,3)
1814 //
1815 def int_hexagon_M2_mpyud_acc_hh_s0 :
1816 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;
1817 //
1818 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s1,DI_ftype_DISISI,3)
1819 //
1820 def int_hexagon_M2_mpyud_acc_hh_s1 :
1821 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;
1822 //
1823 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s0,DI_ftype_DISISI,3)
1824 //
1825 def int_hexagon_M2_mpyud_acc_hl_s0 :
1826 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;
1827 //
1828 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s1,DI_ftype_DISISI,3)
1829 //
1830 def int_hexagon_M2_mpyud_acc_hl_s1 :
1831 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;
1832 //
1833 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s0,DI_ftype_DISISI,3)
1834 //
1835 def int_hexagon_M2_mpyud_acc_lh_s0 :
1836 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;
1837 //
1838 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s1,DI_ftype_DISISI,3)
1839 //
1840 def int_hexagon_M2_mpyud_acc_lh_s1 :
1841 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;
1842 //
1843 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s0,DI_ftype_DISISI,3)
1844 //
1845 def int_hexagon_M2_mpyud_acc_ll_s0 :
1846 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;
1847 //
1848 // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s1,DI_ftype_DISISI,3)
1849 //
1850 def int_hexagon_M2_mpyud_acc_ll_s1 :
1851 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;
1852 //
1853 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s0,DI_ftype_DISISI,3)
1854 //
1855 def int_hexagon_M2_mpyud_nac_hh_s0 :
1856 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;
1857 //
1858 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s1,DI_ftype_DISISI,3)
1859 //
1860 def int_hexagon_M2_mpyud_nac_hh_s1 :
1861 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;
1862 //
1863 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s0,DI_ftype_DISISI,3)
1864 //
1865 def int_hexagon_M2_mpyud_nac_hl_s0 :
1866 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;
1867 //
1868 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s1,DI_ftype_DISISI,3)
1869 //
1870 def int_hexagon_M2_mpyud_nac_hl_s1 :
1871 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;
1872 //
1873 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s0,DI_ftype_DISISI,3)
1874 //
1875 def int_hexagon_M2_mpyud_nac_lh_s0 :
1876 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;
1877 //
1878 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s1,DI_ftype_DISISI,3)
1879 //
1880 def int_hexagon_M2_mpyud_nac_lh_s1 :
1881 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;
1882 //
1883 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s0,DI_ftype_DISISI,3)
1884 //
1885 def int_hexagon_M2_mpyud_nac_ll_s0 :
1886 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">;
1887 //
1888 // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s1,DI_ftype_DISISI,3)
1889 //
1890 def int_hexagon_M2_mpyud_nac_ll_s1 :
1891 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">;
1892 //
1893 // BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s0,UDI_ftype_SISI,2)
1894 //
1895 def int_hexagon_M2_mpyud_hh_s0 :
1896 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;
1897 //
1898 // BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s1,UDI_ftype_SISI,2)
1899 //
1900 def int_hexagon_M2_mpyud_hh_s1 :
1901 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">;
1902 //
1903 // BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s0,UDI_ftype_SISI,2)
1904 //
1905 def int_hexagon_M2_mpyud_hl_s0 :
1906 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;
1907 //
1908 // BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s1,UDI_ftype_SISI,2)
1909 //
1910 def int_hexagon_M2_mpyud_hl_s1 :
1911 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;
1912 //
1913 // BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s0,UDI_ftype_SISI,2)
1914 //
1915 def int_hexagon_M2_mpyud_lh_s0 :
1916 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">;
1917 //
1918 // BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s1,UDI_ftype_SISI,2)
1919 //
1920 def int_hexagon_M2_mpyud_lh_s1 :
1921 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;
1922 //
1923 // BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s0,UDI_ftype_SISI,2)
1924 //
1925 def int_hexagon_M2_mpyud_ll_s0 :
1926 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">;
1927 //
1928 // BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s1,UDI_ftype_SISI,2)
1929 //
1930 def int_hexagon_M2_mpyud_ll_s1 :
1931 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">;
1932 //
1933 // BUILTIN_INFO(HEXAGON.M2_mpysmi,SI_ftype_SISI,2)
1934 //
1935 def int_hexagon_M2_mpysmi :
1936 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpysmi">;
1937 //
1938 // BUILTIN_INFO(HEXAGON.M2_macsip,SI_ftype_SISISI,3)
1939 //
1940 def int_hexagon_M2_macsip :
1941 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_macsip">;
1942 //
1943 // BUILTIN_INFO(HEXAGON.M2_macsin,SI_ftype_SISISI,3)
1944 //
1945 def int_hexagon_M2_macsin :
1946 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_macsin">;
1947 //
1948 // BUILTIN_INFO(HEXAGON.M2_dpmpyss_s0,DI_ftype_SISI,2)
1949 //
1950 def int_hexagon_M2_dpmpyss_s0 :
1951 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;
1952 //
1953 // BUILTIN_INFO(HEXAGON.M2_dpmpyss_acc_s0,DI_ftype_DISISI,3)
1954 //
1955 def int_hexagon_M2_dpmpyss_acc_s0 :
1956 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;
1957 //
1958 // BUILTIN_INFO(HEXAGON.M2_dpmpyss_nac_s0,DI_ftype_DISISI,3)
1959 //
1960 def int_hexagon_M2_dpmpyss_nac_s0 :
1961 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;
1962 //
1963 // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_s0,UDI_ftype_SISI,2)
1964 //
1965 def int_hexagon_M2_dpmpyuu_s0 :
1966 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">;
1967 //
1968 // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_acc_s0,DI_ftype_DISISI,3)
1969 //
1970 def int_hexagon_M2_dpmpyuu_acc_s0 :
1971 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;
1972 //
1973 // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_nac_s0,DI_ftype_DISISI,3)
1974 //
1975 def int_hexagon_M2_dpmpyuu_nac_s0 :
1976 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;
1977 //
1978 // BUILTIN_INFO(HEXAGON.M2_mpy_up,SI_ftype_SISI,2)
1979 //
1980 def int_hexagon_M2_mpy_up :
1981 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up">;
1982 //
1983 // BUILTIN_INFO(HEXAGON.M2_mpy_up_s1,SI_ftype_SISI,2)
1984 //
1985 def int_hexagon_M2_mpy_up_s1 :
1986 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up_s1">;
1987 //
1988 // BUILTIN_INFO(HEXAGON.M2_mpy_up_s1_sat,SI_ftype_SISI,2)
1989 //
1990 def int_hexagon_M2_mpy_up_s1_sat :
1991 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;
1992 //
1993 // BUILTIN_INFO(HEXAGON.M2_mpyu_up,USI_ftype_SISI,2)
1994 //
1995 def int_hexagon_M2_mpyu_up :
1996 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_up">;
1997 //
1998 // BUILTIN_INFO(HEXAGON.M2_mpysu_up,SI_ftype_SISI,2)
1999 //
2000 def int_hexagon_M2_mpysu_up :
2001 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpysu_up">;
2002 //
2003 // BUILTIN_INFO(HEXAGON.M2_dpmpyss_rnd_s0,SI_ftype_SISI,2)
2004 //
2005 def int_hexagon_M2_dpmpyss_rnd_s0 :
2006 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;
2007 //
2008 // BUILTIN_INFO(HEXAGON.M4_mac_up_s1_sat,SI_ftype_SISISI,3)
2009 //
2010 def int_hexagon_M4_mac_up_s1_sat :
2011 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;
2012 //
2013 // BUILTIN_INFO(HEXAGON.M4_nac_up_s1_sat,SI_ftype_SISISI,3)
2014 //
2015 def int_hexagon_M4_nac_up_s1_sat :
2016 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">;
2017 //
2018 // BUILTIN_INFO(HEXAGON.M2_mpyi,SI_ftype_SISI,2)
2019 //
2020 def int_hexagon_M2_mpyi :
2021 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyi">;
2022 //
2023 // BUILTIN_INFO(HEXAGON.M2_mpyui,SI_ftype_SISI,2)
2024 //
2025 def int_hexagon_M2_mpyui :
2026 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyui">;
2027 //
2028 // BUILTIN_INFO(HEXAGON.M2_maci,SI_ftype_SISISI,3)
2029 //
2030 def int_hexagon_M2_maci :
2031 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_maci">;
2032 //
2033 // BUILTIN_INFO(HEXAGON.M2_acci,SI_ftype_SISISI,3)
2034 //
2035 def int_hexagon_M2_acci :
2036 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_acci">;
2037 //
2038 // BUILTIN_INFO(HEXAGON.M2_accii,SI_ftype_SISISI,3)
2039 //
2040 def int_hexagon_M2_accii :
2041 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_accii">;
2042 //
2043 // BUILTIN_INFO(HEXAGON.M2_nacci,SI_ftype_SISISI,3)
2044 //
2045 def int_hexagon_M2_nacci :
2046 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_nacci">;
2047 //
2048 // BUILTIN_INFO(HEXAGON.M2_naccii,SI_ftype_SISISI,3)
2049 //
2050 def int_hexagon_M2_naccii :
2051 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_naccii">;
2052 //
2053 // BUILTIN_INFO(HEXAGON.M2_subacc,SI_ftype_SISISI,3)
2054 //
2055 def int_hexagon_M2_subacc :
2056 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_subacc">;
2057 //
2058 // BUILTIN_INFO(HEXAGON.M4_mpyrr_addr,SI_ftype_SISISI,3)
2059 //
2060 def int_hexagon_M4_mpyrr_addr :
2061 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyrr_addr">;
2062 //
2063 // BUILTIN_INFO(HEXAGON.M4_mpyri_addr_u2,SI_ftype_SISISI,3)
2064 //
2065 def int_hexagon_M4_mpyri_addr_u2 :
2066 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addr_u2">;
2067 //
2068 // BUILTIN_INFO(HEXAGON.M4_mpyri_addr,SI_ftype_SISISI,3)
2069 //
2070 def int_hexagon_M4_mpyri_addr :
2071 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addr">;
2072 //
2073 // BUILTIN_INFO(HEXAGON.M4_mpyri_addi,SI_ftype_SISISI,3)
2074 //
2075 def int_hexagon_M4_mpyri_addi :
2076 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addi">;
2077 //
2078 // BUILTIN_INFO(HEXAGON.M4_mpyrr_addi,SI_ftype_SISISI,3)
2079 //
2080 def int_hexagon_M4_mpyrr_addi :
2081 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyrr_addi">;
2082 //
2083 // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0,DI_ftype_SISI,2)
2084 //
2085 def int_hexagon_M2_vmpy2s_s0 :
2086 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;
2087 //
2088 // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1,DI_ftype_SISI,2)
2089 //
2090 def int_hexagon_M2_vmpy2s_s1 :
2091 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;
2092 //
2093 // BUILTIN_INFO(HEXAGON.M2_vmac2s_s0,DI_ftype_DISISI,3)
2094 //
2095 def int_hexagon_M2_vmac2s_s0 :
2096 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2s_s0">;
2097 //
2098 // BUILTIN_INFO(HEXAGON.M2_vmac2s_s1,DI_ftype_DISISI,3)
2099 //
2100 def int_hexagon_M2_vmac2s_s1 :
2101 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2s_s1">;
2102 //
2103 // BUILTIN_INFO(HEXAGON.M2_vmpy2su_s0,DI_ftype_SISI,2)
2104 //
2105 def int_hexagon_M2_vmpy2su_s0 :
2106 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;
2107 //
2108 // BUILTIN_INFO(HEXAGON.M2_vmpy2su_s1,DI_ftype_SISI,2)
2109 //
2110 def int_hexagon_M2_vmpy2su_s1 :
2111 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;
2112 //
2113 // BUILTIN_INFO(HEXAGON.M2_vmac2su_s0,DI_ftype_DISISI,3)
2114 //
2115 def int_hexagon_M2_vmac2su_s0 :
2116 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2su_s0">;
2117 //
2118 // BUILTIN_INFO(HEXAGON.M2_vmac2su_s1,DI_ftype_DISISI,3)
2119 //
2120 def int_hexagon_M2_vmac2su_s1 :
2121 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2su_s1">;
2122 //
2123 // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0pack,SI_ftype_SISI,2)
2124 //
2125 def int_hexagon_M2_vmpy2s_s0pack :
2126 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;
2127 //
2128 // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1pack,SI_ftype_SISI,2)
2129 //
2130 def int_hexagon_M2_vmpy2s_s1pack :
2131 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;
2132 //
2133 // BUILTIN_INFO(HEXAGON.M2_vmac2,DI_ftype_DISISI,3)
2134 //
2135 def int_hexagon_M2_vmac2 :
2136 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2">;
2137 //
2138 // BUILTIN_INFO(HEXAGON.M2_vmpy2es_s0,DI_ftype_DIDI,2)
2139 //
2140 def int_hexagon_M2_vmpy2es_s0 :
2141 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vmpy2es_s0">;
2142 //
2143 // BUILTIN_INFO(HEXAGON.M2_vmpy2es_s1,DI_ftype_DIDI,2)
2144 //
2145 def int_hexagon_M2_vmpy2es_s1 :
2146 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vmpy2es_s1">;
2147 //
2148 // BUILTIN_INFO(HEXAGON.M2_vmac2es_s0,DI_ftype_DIDIDI,3)
2149 //
2150 def int_hexagon_M2_vmac2es_s0 :
2151 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es_s0">;
2152 //
2153 // BUILTIN_INFO(HEXAGON.M2_vmac2es_s1,DI_ftype_DIDIDI,3)
2154 //
2155 def int_hexagon_M2_vmac2es_s1 :
2156 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es_s1">;
2157 //
2158 // BUILTIN_INFO(HEXAGON.M2_vmac2es,DI_ftype_DIDIDI,3)
2159 //
2160 def int_hexagon_M2_vmac2es :
2161 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es">;
2162 //
2163 // BUILTIN_INFO(HEXAGON.M2_vrmac_s0,DI_ftype_DIDIDI,3)
2164 //
2165 def int_hexagon_M2_vrmac_s0 :
2166 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrmac_s0">;
2167 //
2168 // BUILTIN_INFO(HEXAGON.M2_vrmpy_s0,DI_ftype_DIDI,2)
2169 //
2170 def int_hexagon_M2_vrmpy_s0 :
2171 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrmpy_s0">;
2172 //
2173 // BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s0,SI_ftype_DIDI,2)
2174 //
2175 def int_hexagon_M2_vdmpyrs_s0 :
2176 Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;
2177 //
2178 // BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s1,SI_ftype_DIDI,2)
2179 //
2180 def int_hexagon_M2_vdmpyrs_s1 :
2181 Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;
2182 //
2183 // BUILTIN_INFO(HEXAGON.M5_vrmpybuu,DI_ftype_DIDI,2)
2184 //
2185 def int_hexagon_M5_vrmpybuu :
2186 Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vrmpybuu">;
2187 //
2188 // BUILTIN_INFO(HEXAGON.M5_vrmacbuu,DI_ftype_DIDIDI,3)
2189 //
2190 def int_hexagon_M5_vrmacbuu :
2191 Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vrmacbuu">;
2192 //
2193 // BUILTIN_INFO(HEXAGON.M5_vrmpybsu,DI_ftype_DIDI,2)
2194 //
2195 def int_hexagon_M5_vrmpybsu :
2196 Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vrmpybsu">;
2197 //
2198 // BUILTIN_INFO(HEXAGON.M5_vrmacbsu,DI_ftype_DIDIDI,3)
2199 //
2200 def int_hexagon_M5_vrmacbsu :
2201 Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vrmacbsu">;
2202 //
2203 // BUILTIN_INFO(HEXAGON.M5_vmpybuu,DI_ftype_SISI,2)
2204 //
2205 def int_hexagon_M5_vmpybuu :
2206 Hexagon_di_sisi_Intrinsic<"HEXAGON_M5_vmpybuu">;
2207 //
2208 // BUILTIN_INFO(HEXAGON.M5_vmpybsu,DI_ftype_SISI,2)
2209 //
2210 def int_hexagon_M5_vmpybsu :
2211 Hexagon_di_sisi_Intrinsic<"HEXAGON_M5_vmpybsu">;
2212 //
2213 // BUILTIN_INFO(HEXAGON.M5_vmacbuu,DI_ftype_DISISI,3)
2214 //
2215 def int_hexagon_M5_vmacbuu :
2216 Hexagon_di_disisi_Intrinsic<"HEXAGON_M5_vmacbuu">;
2217 //
2218 // BUILTIN_INFO(HEXAGON.M5_vmacbsu,DI_ftype_DISISI,3)
2219 //
2220 def int_hexagon_M5_vmacbsu :
2221 Hexagon_di_disisi_Intrinsic<"HEXAGON_M5_vmacbsu">;
2222 //
2223 // BUILTIN_INFO(HEXAGON.M5_vdmpybsu,DI_ftype_DIDI,2)
2224 //
2225 def int_hexagon_M5_vdmpybsu :
2226 Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vdmpybsu">;
2227 //
2228 // BUILTIN_INFO(HEXAGON.M5_vdmacbsu,DI_ftype_DIDIDI,3)
2229 //
2230 def int_hexagon_M5_vdmacbsu :
2231 Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vdmacbsu">;
2232 //
2233 // BUILTIN_INFO(HEXAGON.M2_vdmacs_s0,DI_ftype_DIDIDI,3)
2234 //
2235 def int_hexagon_M2_vdmacs_s0 :
2236 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vdmacs_s0">;
2237 //
2238 // BUILTIN_INFO(HEXAGON.M2_vdmacs_s1,DI_ftype_DIDIDI,3)
2239 //
2240 def int_hexagon_M2_vdmacs_s1 :
2241 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vdmacs_s1">;
2242 //
2243 // BUILTIN_INFO(HEXAGON.M2_vdmpys_s0,DI_ftype_DIDI,2)
2244 //
2245 def int_hexagon_M2_vdmpys_s0 :
2246 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vdmpys_s0">;
2247 //
2248 // BUILTIN_INFO(HEXAGON.M2_vdmpys_s1,DI_ftype_DIDI,2)
2249 //
2250 def int_hexagon_M2_vdmpys_s1 :
2251 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vdmpys_s1">;
2252 //
2253 // BUILTIN_INFO(HEXAGON.M2_cmpyrs_s0,SI_ftype_SISI,2)
2254 //
2255 def int_hexagon_M2_cmpyrs_s0 :
2256 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;
2257 //
2258 // BUILTIN_INFO(HEXAGON.M2_cmpyrs_s1,SI_ftype_SISI,2)
2259 //
2260 def int_hexagon_M2_cmpyrs_s1 :
2261 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;
2262 //
2263 // BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s0,SI_ftype_SISI,2)
2264 //
2265 def int_hexagon_M2_cmpyrsc_s0 :
2266 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;
2267 //
2268 // BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s1,SI_ftype_SISI,2)
2269 //
2270 def int_hexagon_M2_cmpyrsc_s1 :
2271 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;
2272 //
2273 // BUILTIN_INFO(HEXAGON.M2_cmacs_s0,DI_ftype_DISISI,3)
2274 //
2275 def int_hexagon_M2_cmacs_s0 :
2276 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacs_s0">;
2277 //
2278 // BUILTIN_INFO(HEXAGON.M2_cmacs_s1,DI_ftype_DISISI,3)
2279 //
2280 def int_hexagon_M2_cmacs_s1 :
2281 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacs_s1">;
2282 //
2283 // BUILTIN_INFO(HEXAGON.M2_cmacsc_s0,DI_ftype_DISISI,3)
2284 //
2285 def int_hexagon_M2_cmacsc_s0 :
2286 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacsc_s0">;
2287 //
2288 // BUILTIN_INFO(HEXAGON.M2_cmacsc_s1,DI_ftype_DISISI,3)
2289 //
2290 def int_hexagon_M2_cmacsc_s1 :
2291 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacsc_s1">;
2292 //
2293 // BUILTIN_INFO(HEXAGON.M2_cmpys_s0,DI_ftype_SISI,2)
2294 //
2295 def int_hexagon_M2_cmpys_s0 :
2296 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpys_s0">;
2297 //
2298 // BUILTIN_INFO(HEXAGON.M2_cmpys_s1,DI_ftype_SISI,2)
2299 //
2300 def int_hexagon_M2_cmpys_s1 :
2301 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpys_s1">;
2302 //
2303 // BUILTIN_INFO(HEXAGON.M2_cmpysc_s0,DI_ftype_SISI,2)
2304 //
2305 def int_hexagon_M2_cmpysc_s0 :
2306 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpysc_s0">;
2307 //
2308 // BUILTIN_INFO(HEXAGON.M2_cmpysc_s1,DI_ftype_SISI,2)
2309 //
2310 def int_hexagon_M2_cmpysc_s1 :
2311 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpysc_s1">;
2312 //
2313 // BUILTIN_INFO(HEXAGON.M2_cnacs_s0,DI_ftype_DISISI,3)
2314 //
2315 def int_hexagon_M2_cnacs_s0 :
2316 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacs_s0">;
2317 //
2318 // BUILTIN_INFO(HEXAGON.M2_cnacs_s1,DI_ftype_DISISI,3)
2319 //
2320 def int_hexagon_M2_cnacs_s1 :
2321 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacs_s1">;
2322 //
2323 // BUILTIN_INFO(HEXAGON.M2_cnacsc_s0,DI_ftype_DISISI,3)
2324 //
2325 def int_hexagon_M2_cnacsc_s0 :
2326 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacsc_s0">;
2327 //
2328 // BUILTIN_INFO(HEXAGON.M2_cnacsc_s1,DI_ftype_DISISI,3)
2329 //
2330 def int_hexagon_M2_cnacsc_s1 :
2331 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacsc_s1">;
2332 //
2333 // BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1,DI_ftype_DISI,2)
2334 //
2335 def int_hexagon_M2_vrcmpys_s1 :
2336 Hexagon_di_disi_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;
2337 //
2338 // BUILTIN_INFO(HEXAGON.M2_vrcmpys_acc_s1,DI_ftype_DIDISI,3)
2339 //
2340 def int_hexagon_M2_vrcmpys_acc_s1 :
2341 Hexagon_di_didisi_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;
2342 //
2343 // BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1rp,SI_ftype_DISI,2)
2344 //
2345 def int_hexagon_M2_vrcmpys_s1rp :
2346 Hexagon_si_disi_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;
2347 //
2348 // BUILTIN_INFO(HEXAGON.M2_mmacls_s0,DI_ftype_DIDIDI,3)
2349 //
2350 def int_hexagon_M2_mmacls_s0 :
2351 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_s0">;
2352 //
2353 // BUILTIN_INFO(HEXAGON.M2_mmacls_s1,DI_ftype_DIDIDI,3)
2354 //
2355 def int_hexagon_M2_mmacls_s1 :
2356 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_s1">;
2357 //
2358 // BUILTIN_INFO(HEXAGON.M2_mmachs_s0,DI_ftype_DIDIDI,3)
2359 //
2360 def int_hexagon_M2_mmachs_s0 :
2361 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_s0">;
2362 //
2363 // BUILTIN_INFO(HEXAGON.M2_mmachs_s1,DI_ftype_DIDIDI,3)
2364 //
2365 def int_hexagon_M2_mmachs_s1 :
2366 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_s1">;
2367 //
2368 // BUILTIN_INFO(HEXAGON.M2_mmpyl_s0,DI_ftype_DIDI,2)
2369 //
2370 def int_hexagon_M2_mmpyl_s0 :
2371 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_s0">;
2372 //
2373 // BUILTIN_INFO(HEXAGON.M2_mmpyl_s1,DI_ftype_DIDI,2)
2374 //
2375 def int_hexagon_M2_mmpyl_s1 :
2376 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_s1">;
2377 //
2378 // BUILTIN_INFO(HEXAGON.M2_mmpyh_s0,DI_ftype_DIDI,2)
2379 //
2380 def int_hexagon_M2_mmpyh_s0 :
2381 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_s0">;
2382 //
2383 // BUILTIN_INFO(HEXAGON.M2_mmpyh_s1,DI_ftype_DIDI,2)
2384 //
2385 def int_hexagon_M2_mmpyh_s1 :
2386 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_s1">;
2387 //
2388 // BUILTIN_INFO(HEXAGON.M2_mmacls_rs0,DI_ftype_DIDIDI,3)
2389 //
2390 def int_hexagon_M2_mmacls_rs0 :
2391 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_rs0">;
2392 //
2393 // BUILTIN_INFO(HEXAGON.M2_mmacls_rs1,DI_ftype_DIDIDI,3)
2394 //
2395 def int_hexagon_M2_mmacls_rs1 :
2396 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_rs1">;
2397 //
2398 // BUILTIN_INFO(HEXAGON.M2_mmachs_rs0,DI_ftype_DIDIDI,3)
2399 //
2400 def int_hexagon_M2_mmachs_rs0 :
2401 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_rs0">;
2402 //
2403 // BUILTIN_INFO(HEXAGON.M2_mmachs_rs1,DI_ftype_DIDIDI,3)
2404 //
2405 def int_hexagon_M2_mmachs_rs1 :
2406 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_rs1">;
2407 //
2408 // BUILTIN_INFO(HEXAGON.M2_mmpyl_rs0,DI_ftype_DIDI,2)
2409 //
2410 def int_hexagon_M2_mmpyl_rs0 :
2411 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_rs0">;
2412 //
2413 // BUILTIN_INFO(HEXAGON.M2_mmpyl_rs1,DI_ftype_DIDI,2)
2414 //
2415 def int_hexagon_M2_mmpyl_rs1 :
2416 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;
2417 //
2418 // BUILTIN_INFO(HEXAGON.M2_mmpyh_rs0,DI_ftype_DIDI,2)
2419 //
2420 def int_hexagon_M2_mmpyh_rs0 :
2421 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;
2422 //
2423 // BUILTIN_INFO(HEXAGON.M2_mmpyh_rs1,DI_ftype_DIDI,2)
2424 //
2425 def int_hexagon_M2_mmpyh_rs1 :
2426 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;
2427 //
2428 // BUILTIN_INFO(HEXAGON.M4_vrmpyeh_s0,DI_ftype_DIDI,2)
2429 //
2430 def int_hexagon_M4_vrmpyeh_s0 :
2431 Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">;
2432 //
2433 // BUILTIN_INFO(HEXAGON.M4_vrmpyeh_s1,DI_ftype_DIDI,2)
2434 //
2435 def int_hexagon_M4_vrmpyeh_s1 :
2436 Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">;
2437 //
2438 // BUILTIN_INFO(HEXAGON.M4_vrmpyeh_acc_s0,DI_ftype_DIDIDI,3)
2439 //
2440 def int_hexagon_M4_vrmpyeh_acc_s0 :
2441 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;
2442 //
2443 // BUILTIN_INFO(HEXAGON.M4_vrmpyeh_acc_s1,DI_ftype_DIDIDI,3)
2444 //
2445 def int_hexagon_M4_vrmpyeh_acc_s1 :
2446 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;
2447 //
2448 // BUILTIN_INFO(HEXAGON.M4_vrmpyoh_s0,DI_ftype_DIDI,2)
2449 //
2450 def int_hexagon_M4_vrmpyoh_s0 :
2451 Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;
2452 //
2453 // BUILTIN_INFO(HEXAGON.M4_vrmpyoh_s1,DI_ftype_DIDI,2)
2454 //
2455 def int_hexagon_M4_vrmpyoh_s1 :
2456 Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;
2457 //
2458 // BUILTIN_INFO(HEXAGON.M4_vrmpyoh_acc_s0,DI_ftype_DIDIDI,3)
2459 //
2460 def int_hexagon_M4_vrmpyoh_acc_s0 :
2461 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;
2462 //
2463 // BUILTIN_INFO(HEXAGON.M4_vrmpyoh_acc_s1,DI_ftype_DIDIDI,3)
2464 //
2465 def int_hexagon_M4_vrmpyoh_acc_s1 :
2466 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;
2467 //
2468 // BUILTIN_INFO(HEXAGON.M2_hmmpyl_rs1,SI_ftype_SISI,2)
2469 //
2470 def int_hexagon_M2_hmmpyl_rs1 :
2471 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;
2472 //
2473 // BUILTIN_INFO(HEXAGON.M2_hmmpyh_rs1,SI_ftype_SISI,2)
2474 //
2475 def int_hexagon_M2_hmmpyh_rs1 :
2476 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;
2477 //
2478 // BUILTIN_INFO(HEXAGON.M2_hmmpyl_s1,SI_ftype_SISI,2)
2479 //
2480 def int_hexagon_M2_hmmpyl_s1 :
2481 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;
2482 //
2483 // BUILTIN_INFO(HEXAGON.M2_hmmpyh_s1,SI_ftype_SISI,2)
2484 //
2485 def int_hexagon_M2_hmmpyh_s1 :
2486 Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;
2487 //
2488 // BUILTIN_INFO(HEXAGON.M2_mmaculs_s0,DI_ftype_DIDIDI,3)
2489 //
2490 def int_hexagon_M2_mmaculs_s0 :
2491 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_s0">;
2492 //
2493 // BUILTIN_INFO(HEXAGON.M2_mmaculs_s1,DI_ftype_DIDIDI,3)
2494 //
2495 def int_hexagon_M2_mmaculs_s1 :
2496 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_s1">;
2497 //
2498 // BUILTIN_INFO(HEXAGON.M2_mmacuhs_s0,DI_ftype_DIDIDI,3)
2499 //
2500 def int_hexagon_M2_mmacuhs_s0 :
2501 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;
2502 //
2503 // BUILTIN_INFO(HEXAGON.M2_mmacuhs_s1,DI_ftype_DIDIDI,3)
2504 //
2505 def int_hexagon_M2_mmacuhs_s1 :
2506 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;
2507 //
2508 // BUILTIN_INFO(HEXAGON.M2_mmpyul_s0,DI_ftype_DIDI,2)
2509 //
2510 def int_hexagon_M2_mmpyul_s0 :
2511 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_s0">;
2512 //
2513 // BUILTIN_INFO(HEXAGON.M2_mmpyul_s1,DI_ftype_DIDI,2)
2514 //
2515 def int_hexagon_M2_mmpyul_s1 :
2516 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_s1">;
2517 //
2518 // BUILTIN_INFO(HEXAGON.M2_mmpyuh_s0,DI_ftype_DIDI,2)
2519 //
2520 def int_hexagon_M2_mmpyuh_s0 :
2521 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;
2522 //
2523 // BUILTIN_INFO(HEXAGON.M2_mmpyuh_s1,DI_ftype_DIDI,2)
2524 //
2525 def int_hexagon_M2_mmpyuh_s1 :
2526 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;
2527 //
2528 // BUILTIN_INFO(HEXAGON.M2_mmaculs_rs0,DI_ftype_DIDIDI,3)
2529 //
2530 def int_hexagon_M2_mmaculs_rs0 :
2531 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;
2532 //
2533 // BUILTIN_INFO(HEXAGON.M2_mmaculs_rs1,DI_ftype_DIDIDI,3)
2534 //
2535 def int_hexagon_M2_mmaculs_rs1 :
2536 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;
2537 //
2538 // BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs0,DI_ftype_DIDIDI,3)
2539 //
2540 def int_hexagon_M2_mmacuhs_rs0 :
2541 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;
2542 //
2543 // BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs1,DI_ftype_DIDIDI,3)
2544 //
2545 def int_hexagon_M2_mmacuhs_rs1 :
2546 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;
2547 //
2548 // BUILTIN_INFO(HEXAGON.M2_mmpyul_rs0,DI_ftype_DIDI,2)
2549 //
2550 def int_hexagon_M2_mmpyul_rs0 :
2551 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;
2552 //
2553 // BUILTIN_INFO(HEXAGON.M2_mmpyul_rs1,DI_ftype_DIDI,2)
2554 //
2555 def int_hexagon_M2_mmpyul_rs1 :
2556 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;
2557 //
2558 // BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs0,DI_ftype_DIDI,2)
2559 //
2560 def int_hexagon_M2_mmpyuh_rs0 :
2561 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;
2562 //
2563 // BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs1,DI_ftype_DIDI,2)
2564 //
2565 def int_hexagon_M2_mmpyuh_rs1 :
2566 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;
2567 //
2568 // BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0,DI_ftype_DIDIDI,3)
2569 //
2570 def int_hexagon_M2_vrcmaci_s0 :
2571 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmaci_s0">;
2572 //
2573 // BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0,DI_ftype_DIDIDI,3)
2574 //
2575 def int_hexagon_M2_vrcmacr_s0 :
2576 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;
2577 //
2578 // BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0c,DI_ftype_DIDIDI,3)
2579 //
2580 def int_hexagon_M2_vrcmaci_s0c :
2581 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;
2582 //
2583 // BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0c,DI_ftype_DIDIDI,3)
2584 //
2585 def int_hexagon_M2_vrcmacr_s0c :
2586 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;
2587 //
2588 // BUILTIN_INFO(HEXAGON.M2_cmaci_s0,DI_ftype_DISISI,3)
2589 //
2590 def int_hexagon_M2_cmaci_s0 :
2591 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmaci_s0">;
2592 //
2593 // BUILTIN_INFO(HEXAGON.M2_cmacr_s0,DI_ftype_DISISI,3)
2594 //
2595 def int_hexagon_M2_cmacr_s0 :
2596 Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacr_s0">;
2597 //
2598 // BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0,DI_ftype_DIDI,2)
2599 //
2600 def int_hexagon_M2_vrcmpyi_s0 :
2601 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;
2602 //
2603 // BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0,DI_ftype_DIDI,2)
2604 //
2605 def int_hexagon_M2_vrcmpyr_s0 :
2606 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">;
2607 //
2608 // BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0c,DI_ftype_DIDI,2)
2609 //
2610 def int_hexagon_M2_vrcmpyi_s0c :
2611 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;
2612 //
2613 // BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0c,DI_ftype_DIDI,2)
2614 //
2615 def int_hexagon_M2_vrcmpyr_s0c :
2616 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;
2617 //
2618 // BUILTIN_INFO(HEXAGON.M2_cmpyi_s0,DI_ftype_SISI,2)
2619 //
2620 def int_hexagon_M2_cmpyi_s0 :
2621 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpyi_s0">;
2622 //
2623 // BUILTIN_INFO(HEXAGON.M2_cmpyr_s0,DI_ftype_SISI,2)
2624 //
2625 def int_hexagon_M2_cmpyr_s0 :
2626 Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpyr_s0">;
2627 //
2628 // BUILTIN_INFO(HEXAGON.M4_cmpyi_wh,SI_ftype_DISI,2)
2629 //
2630 def int_hexagon_M4_cmpyi_wh :
2631 Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyi_wh">;
2632 //
2633 // BUILTIN_INFO(HEXAGON.M4_cmpyr_wh,SI_ftype_DISI,2)
2634 //
2635 def int_hexagon_M4_cmpyr_wh :
2636 Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyr_wh">;
2637 //
2638 // BUILTIN_INFO(HEXAGON.M4_cmpyi_whc,SI_ftype_DISI,2)
2639 //
2640 def int_hexagon_M4_cmpyi_whc :
2641 Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyi_whc">;
2642 //
2643 // BUILTIN_INFO(HEXAGON.M4_cmpyr_whc,SI_ftype_DISI,2)
2644 //
2645 def int_hexagon_M4_cmpyr_whc :
2646 Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyr_whc">;
2647 //
2648 // BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_i,DI_ftype_DIDI,2)
2649 //
2650 def int_hexagon_M2_vcmpy_s0_sat_i :
2651 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;
2652 //
2653 // BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_r,DI_ftype_DIDI,2)
2654 //
2655 def int_hexagon_M2_vcmpy_s0_sat_r :
2656 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;
2657 //
2658 // BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_i,DI_ftype_DIDI,2)
2659 //
2660 def int_hexagon_M2_vcmpy_s1_sat_i :
2661 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;
2662 //
2663 // BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_r,DI_ftype_DIDI,2)
2664 //
2665 def int_hexagon_M2_vcmpy_s1_sat_r :
2666 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;
2667 //
2668 // BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_i,DI_ftype_DIDIDI,3)
2669 //
2670 def int_hexagon_M2_vcmac_s0_sat_i :
2671 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">;
2672 //
2673 // BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_r,DI_ftype_DIDIDI,3)
2674 //
2675 def int_hexagon_M2_vcmac_s0_sat_r :
2676 Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;
2677 //
2678 // BUILTIN_INFO(HEXAGON.S2_vcrotate,DI_ftype_DISI,2)
2679 //
2680 def int_hexagon_S2_vcrotate :
2681 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_vcrotate">;
2682 //
2683 // BUILTIN_INFO(HEXAGON.S4_vrcrotate_acc,DI_ftype_DIDISISI,4)
2684 //
2685 def int_hexagon_S4_vrcrotate_acc :
2686 Hexagon_di_didisisi_Intrinsic<"HEXAGON_S4_vrcrotate_acc">;
2687 //
2688 // BUILTIN_INFO(HEXAGON.S4_vrcrotate,DI_ftype_DISISI,3)
2689 //
2690 def int_hexagon_S4_vrcrotate :
2691 Hexagon_di_disisi_Intrinsic<"HEXAGON_S4_vrcrotate">;
2692 //
2693 // BUILTIN_INFO(HEXAGON.S2_vcnegh,DI_ftype_DISI,2)
2694 //
2695 def int_hexagon_S2_vcnegh :
2696 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_vcnegh">;
2697 //
2698 // BUILTIN_INFO(HEXAGON.S2_vrcnegh,DI_ftype_DIDISI,3)
2699 //
2700 def int_hexagon_S2_vrcnegh :
2701 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_vrcnegh">;
2702 //
2703 // BUILTIN_INFO(HEXAGON.M4_pmpyw,DI_ftype_SISI,2)
2704 //
2705 def int_hexagon_M4_pmpyw :
2706 Hexagon_di_sisi_Intrinsic<"HEXAGON_M4_pmpyw">;
2707 //
2708 // BUILTIN_INFO(HEXAGON.M4_vpmpyh,DI_ftype_SISI,2)
2709 //
2710 def int_hexagon_M4_vpmpyh :
2711 Hexagon_di_sisi_Intrinsic<"HEXAGON_M4_vpmpyh">;
2712 //
2713 // BUILTIN_INFO(HEXAGON.M4_pmpyw_acc,DI_ftype_DISISI,3)
2714 //
2715 def int_hexagon_M4_pmpyw_acc :
2716 Hexagon_di_disisi_Intrinsic<"HEXAGON_M4_pmpyw_acc">;
2717 //
2718 // BUILTIN_INFO(HEXAGON.M4_vpmpyh_acc,DI_ftype_DISISI,3)
2719 //
2720 def int_hexagon_M4_vpmpyh_acc :
2721 Hexagon_di_disisi_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;
2722 //
2723 // BUILTIN_INFO(HEXAGON.A2_add,SI_ftype_SISI,2)
2724 //
2725 def int_hexagon_A2_add :
2726 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_add">;
2727 //
2728 // BUILTIN_INFO(HEXAGON.A2_sub,SI_ftype_SISI,2)
2729 //
2730 def int_hexagon_A2_sub :
2731 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_sub">;
2732 //
2733 // BUILTIN_INFO(HEXAGON.A2_addsat,SI_ftype_SISI,2)
2734 //
2735 def int_hexagon_A2_addsat :
2736 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addsat">;
2737 //
2738 // BUILTIN_INFO(HEXAGON.A2_subsat,SI_ftype_SISI,2)
2739 //
2740 def int_hexagon_A2_subsat :
2741 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subsat">;
2742 //
2743 // BUILTIN_INFO(HEXAGON.A2_addi,SI_ftype_SISI,2)
2744 //
2745 def int_hexagon_A2_addi :
2746 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addi">;
2747 //
2748 // BUILTIN_INFO(HEXAGON.A2_addh_l16_ll,SI_ftype_SISI,2)
2749 //
2750 def int_hexagon_A2_addh_l16_ll :
2751 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_ll">;
2752 //
2753 // BUILTIN_INFO(HEXAGON.A2_addh_l16_hl,SI_ftype_SISI,2)
2754 //
2755 def int_hexagon_A2_addh_l16_hl :
2756 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_hl">;
2757 //
2758 // BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_ll,SI_ftype_SISI,2)
2759 //
2760 def int_hexagon_A2_addh_l16_sat_ll :
2761 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;
2762 //
2763 // BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_hl,SI_ftype_SISI,2)
2764 //
2765 def int_hexagon_A2_addh_l16_sat_hl :
2766 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;
2767 //
2768 // BUILTIN_INFO(HEXAGON.A2_subh_l16_ll,SI_ftype_SISI,2)
2769 //
2770 def int_hexagon_A2_subh_l16_ll :
2771 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_ll">;
2772 //
2773 // BUILTIN_INFO(HEXAGON.A2_subh_l16_hl,SI_ftype_SISI,2)
2774 //
2775 def int_hexagon_A2_subh_l16_hl :
2776 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_hl">;
2777 //
2778 // BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_ll,SI_ftype_SISI,2)
2779 //
2780 def int_hexagon_A2_subh_l16_sat_ll :
2781 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">;
2782 //
2783 // BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_hl,SI_ftype_SISI,2)
2784 //
2785 def int_hexagon_A2_subh_l16_sat_hl :
2786 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;
2787 //
2788 // BUILTIN_INFO(HEXAGON.A2_addh_h16_ll,SI_ftype_SISI,2)
2789 //
2790 def int_hexagon_A2_addh_h16_ll :
2791 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_ll">;
2792 //
2793 // BUILTIN_INFO(HEXAGON.A2_addh_h16_lh,SI_ftype_SISI,2)
2794 //
2795 def int_hexagon_A2_addh_h16_lh :
2796 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_lh">;
2797 //
2798 // BUILTIN_INFO(HEXAGON.A2_addh_h16_hl,SI_ftype_SISI,2)
2799 //
2800 def int_hexagon_A2_addh_h16_hl :
2801 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_hl">;
2802 //
2803 // BUILTIN_INFO(HEXAGON.A2_addh_h16_hh,SI_ftype_SISI,2)
2804 //
2805 def int_hexagon_A2_addh_h16_hh :
2806 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_hh">;
2807 //
2808 // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_ll,SI_ftype_SISI,2)
2809 //
2810 def int_hexagon_A2_addh_h16_sat_ll :
2811 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">;
2812 //
2813 // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_lh,SI_ftype_SISI,2)
2814 //
2815 def int_hexagon_A2_addh_h16_sat_lh :
2816 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">;
2817 //
2818 // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hl,SI_ftype_SISI,2)
2819 //
2820 def int_hexagon_A2_addh_h16_sat_hl :
2821 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;
2822 //
2823 // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hh,SI_ftype_SISI,2)
2824 //
2825 def int_hexagon_A2_addh_h16_sat_hh :
2826 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;
2827 //
2828 // BUILTIN_INFO(HEXAGON.A2_subh_h16_ll,SI_ftype_SISI,2)
2829 //
2830 def int_hexagon_A2_subh_h16_ll :
2831 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_ll">;
2832 //
2833 // BUILTIN_INFO(HEXAGON.A2_subh_h16_lh,SI_ftype_SISI,2)
2834 //
2835 def int_hexagon_A2_subh_h16_lh :
2836 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_lh">;
2837 //
2838 // BUILTIN_INFO(HEXAGON.A2_subh_h16_hl,SI_ftype_SISI,2)
2839 //
2840 def int_hexagon_A2_subh_h16_hl :
2841 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_hl">;
2842 //
2843 // BUILTIN_INFO(HEXAGON.A2_subh_h16_hh,SI_ftype_SISI,2)
2844 //
2845 def int_hexagon_A2_subh_h16_hh :
2846 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_hh">;
2847 //
2848 // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_ll,SI_ftype_SISI,2)
2849 //
2850 def int_hexagon_A2_subh_h16_sat_ll :
2851 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;
2852 //
2853 // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_lh,SI_ftype_SISI,2)
2854 //
2855 def int_hexagon_A2_subh_h16_sat_lh :
2856 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;
2857 //
2858 // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hl,SI_ftype_SISI,2)
2859 //
2860 def int_hexagon_A2_subh_h16_sat_hl :
2861 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;
2862 //
2863 // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hh,SI_ftype_SISI,2)
2864 //
2865 def int_hexagon_A2_subh_h16_sat_hh :
2866 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;
2867 //
2868 // BUILTIN_INFO(HEXAGON.A2_aslh,SI_ftype_SI,1)
2869 //
2870 def int_hexagon_A2_aslh :
2871 Hexagon_si_si_Intrinsic<"HEXAGON_A2_aslh">;
2872 //
2873 // BUILTIN_INFO(HEXAGON.A2_asrh,SI_ftype_SI,1)
2874 //
2875 def int_hexagon_A2_asrh :
2876 Hexagon_si_si_Intrinsic<"HEXAGON_A2_asrh">;
2877 //
2878 // BUILTIN_INFO(HEXAGON.A2_addp,DI_ftype_DIDI,2)
2879 //
2880 def int_hexagon_A2_addp :
2881 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_addp">;
2882 //
2883 // BUILTIN_INFO(HEXAGON.A2_addpsat,DI_ftype_DIDI,2)
2884 //
2885 def int_hexagon_A2_addpsat :
2886 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_addpsat">;
2887 //
2888 // BUILTIN_INFO(HEXAGON.A2_addsp,DI_ftype_SIDI,2)
2889 //
2890 def int_hexagon_A2_addsp :
2891 Hexagon_di_sidi_Intrinsic<"HEXAGON_A2_addsp">;
2892 //
2893 // BUILTIN_INFO(HEXAGON.A2_subp,DI_ftype_DIDI,2)
2894 //
2895 def int_hexagon_A2_subp :
2896 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_subp">;
2897 //
2898 // BUILTIN_INFO(HEXAGON.A2_neg,SI_ftype_SI,1)
2899 //
2900 def int_hexagon_A2_neg :
2901 Hexagon_si_si_Intrinsic<"HEXAGON_A2_neg">;
2902 //
2903 // BUILTIN_INFO(HEXAGON.A2_negsat,SI_ftype_SI,1)
2904 //
2905 def int_hexagon_A2_negsat :
2906 Hexagon_si_si_Intrinsic<"HEXAGON_A2_negsat">;
2907 //
2908 // BUILTIN_INFO(HEXAGON.A2_abs,SI_ftype_SI,1)
2909 //
2910 def int_hexagon_A2_abs :
2911 Hexagon_si_si_Intrinsic<"HEXAGON_A2_abs">;
2912 //
2913 // BUILTIN_INFO(HEXAGON.A2_abssat,SI_ftype_SI,1)
2914 //
2915 def int_hexagon_A2_abssat :
2916 Hexagon_si_si_Intrinsic<"HEXAGON_A2_abssat">;
2917 //
2918 // BUILTIN_INFO(HEXAGON.A2_vconj,DI_ftype_DI,1)
2919 //
2920 def int_hexagon_A2_vconj :
2921 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vconj">;
2922 //
2923 // BUILTIN_INFO(HEXAGON.A2_negp,DI_ftype_DI,1)
2924 //
2925 def int_hexagon_A2_negp :
2926 Hexagon_di_di_Intrinsic<"HEXAGON_A2_negp">;
2927 //
2928 // BUILTIN_INFO(HEXAGON.A2_absp,DI_ftype_DI,1)
2929 //
2930 def int_hexagon_A2_absp :
2931 Hexagon_di_di_Intrinsic<"HEXAGON_A2_absp">;
2932 //
2933 // BUILTIN_INFO(HEXAGON.A2_max,SI_ftype_SISI,2)
2934 //
2935 def int_hexagon_A2_max :
2936 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_max">;
2937 //
2938 // BUILTIN_INFO(HEXAGON.A2_maxu,USI_ftype_SISI,2)
2939 //
2940 def int_hexagon_A2_maxu :
2941 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_maxu">;
2942 //
2943 // BUILTIN_INFO(HEXAGON.A2_min,SI_ftype_SISI,2)
2944 //
2945 def int_hexagon_A2_min :
2946 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_min">;
2947 //
2948 // BUILTIN_INFO(HEXAGON.A2_minu,USI_ftype_SISI,2)
2949 //
2950 def int_hexagon_A2_minu :
2951 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_minu">;
2952 //
2953 // BUILTIN_INFO(HEXAGON.A2_maxp,DI_ftype_DIDI,2)
2954 //
2955 def int_hexagon_A2_maxp :
2956 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_maxp">;
2957 //
2958 // BUILTIN_INFO(HEXAGON.A2_maxup,UDI_ftype_DIDI,2)
2959 //
2960 def int_hexagon_A2_maxup :
2961 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_maxup">;
2962 //
2963 // BUILTIN_INFO(HEXAGON.A2_minp,DI_ftype_DIDI,2)
2964 //
2965 def int_hexagon_A2_minp :
2966 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_minp">;
2967 //
2968 // BUILTIN_INFO(HEXAGON.A2_minup,UDI_ftype_DIDI,2)
2969 //
2970 def int_hexagon_A2_minup :
2971 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_minup">;
2972 //
2973 // BUILTIN_INFO(HEXAGON.A2_tfr,SI_ftype_SI,1)
2974 //
2975 def int_hexagon_A2_tfr :
2976 Hexagon_si_si_Intrinsic<"HEXAGON_A2_tfr">;
2977 //
2978 // BUILTIN_INFO(HEXAGON.A2_tfrsi,SI_ftype_SI,1)
2979 //
2980 def int_hexagon_A2_tfrsi :
2981 Hexagon_si_si_Intrinsic<"HEXAGON_A2_tfrsi">;
2982 //
2983 // BUILTIN_INFO(HEXAGON.A2_tfrp,DI_ftype_DI,1)
2984 //
2985 def int_hexagon_A2_tfrp :
2986 Hexagon_di_di_Intrinsic<"HEXAGON_A2_tfrp">;
2987 //
2988 // BUILTIN_INFO(HEXAGON.A2_tfrpi,DI_ftype_SI,1)
2989 //
2990 def int_hexagon_A2_tfrpi :
2991 Hexagon_di_si_Intrinsic<"HEXAGON_A2_tfrpi">;
2992 //
2993 // BUILTIN_INFO(HEXAGON.A2_zxtb,SI_ftype_SI,1)
2994 //
2995 def int_hexagon_A2_zxtb :
2996 Hexagon_si_si_Intrinsic<"HEXAGON_A2_zxtb">;
2997 //
2998 // BUILTIN_INFO(HEXAGON.A2_sxtb,SI_ftype_SI,1)
2999 //
3000 def int_hexagon_A2_sxtb :
3001 Hexagon_si_si_Intrinsic<"HEXAGON_A2_sxtb">;
3002 //
3003 // BUILTIN_INFO(HEXAGON.A2_zxth,SI_ftype_SI,1)
3004 //
3005 def int_hexagon_A2_zxth :
3006 Hexagon_si_si_Intrinsic<"HEXAGON_A2_zxth">;
3007 //
3008 // BUILTIN_INFO(HEXAGON.A2_sxth,SI_ftype_SI,1)
3009 //
3010 def int_hexagon_A2_sxth :
3011 Hexagon_si_si_Intrinsic<"HEXAGON_A2_sxth">;
3012 //
3013 // BUILTIN_INFO(HEXAGON.A2_combinew,DI_ftype_SISI,2)
3014 //
3015 def int_hexagon_A2_combinew :
3016 Hexagon_di_sisi_Intrinsic<"HEXAGON_A2_combinew">;
3017 //
3018 // BUILTIN_INFO(HEXAGON.A4_combineri,DI_ftype_SISI,2)
3019 //
3020 def int_hexagon_A4_combineri :
3021 Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_combineri">;
3022 //
3023 // BUILTIN_INFO(HEXAGON.A4_combineir,DI_ftype_SISI,2)
3024 //
3025 def int_hexagon_A4_combineir :
3026 Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_combineir">;
3027 //
3028 // BUILTIN_INFO(HEXAGON.A2_combineii,DI_ftype_SISI,2)
3029 //
3030 def int_hexagon_A2_combineii :
3031 Hexagon_di_sisi_Intrinsic<"HEXAGON_A2_combineii">;
3032 //
3033 // BUILTIN_INFO(HEXAGON.A2_combine_hh,SI_ftype_SISI,2)
3034 //
3035 def int_hexagon_A2_combine_hh :
3036 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_hh">;
3037 //
3038 // BUILTIN_INFO(HEXAGON.A2_combine_hl,SI_ftype_SISI,2)
3039 //
3040 def int_hexagon_A2_combine_hl :
3041 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_hl">;
3042 //
3043 // BUILTIN_INFO(HEXAGON.A2_combine_lh,SI_ftype_SISI,2)
3044 //
3045 def int_hexagon_A2_combine_lh :
3046 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_lh">;
3047 //
3048 // BUILTIN_INFO(HEXAGON.A2_combine_ll,SI_ftype_SISI,2)
3049 //
3050 def int_hexagon_A2_combine_ll :
3051 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_ll">;
3052 //
3053 // BUILTIN_INFO(HEXAGON.A2_tfril,SI_ftype_SISI,2)
3054 //
3055 def int_hexagon_A2_tfril :
3056 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_tfril">;
3057 //
3058 // BUILTIN_INFO(HEXAGON.A2_tfrih,SI_ftype_SISI,2)
3059 //
3060 def int_hexagon_A2_tfrih :
3061 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_tfrih">;
3062 //
3063 // BUILTIN_INFO(HEXAGON.A2_and,SI_ftype_SISI,2)
3064 //
3065 def int_hexagon_A2_and :
3066 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_and">;
3067 //
3068 // BUILTIN_INFO(HEXAGON.A2_or,SI_ftype_SISI,2)
3069 //
3070 def int_hexagon_A2_or :
3071 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_or">;
3072 //
3073 // BUILTIN_INFO(HEXAGON.A2_xor,SI_ftype_SISI,2)
3074 //
3075 def int_hexagon_A2_xor :
3076 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_xor">;
3077 //
3078 // BUILTIN_INFO(HEXAGON.A2_not,SI_ftype_SI,1)
3079 //
3080 def int_hexagon_A2_not :
3081 Hexagon_si_si_Intrinsic<"HEXAGON_A2_not">;
3082 //
3083 // BUILTIN_INFO(HEXAGON.M2_xor_xacc,SI_ftype_SISISI,3)
3084 //
3085 def int_hexagon_M2_xor_xacc :
3086 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_xor_xacc">;
3087 //
3088 // BUILTIN_INFO(HEXAGON.M4_xor_xacc,DI_ftype_DIDIDI,3)
3089 //
3090 def int_hexagon_M4_xor_xacc :
3091 Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_xor_xacc">;
3092 //
3093 // BUILTIN_INFO(HEXAGON.A4_andn,SI_ftype_SISI,2)
3094 //
3095 def int_hexagon_A4_andn :
3096 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_andn">;
3097 //
3098 // BUILTIN_INFO(HEXAGON.A4_orn,SI_ftype_SISI,2)
3099 //
3100 def int_hexagon_A4_orn :
3101 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_orn">;
3102 //
3103 // BUILTIN_INFO(HEXAGON.A4_andnp,DI_ftype_DIDI,2)
3104 //
3105 def int_hexagon_A4_andnp :
3106 Hexagon_di_didi_Intrinsic<"HEXAGON_A4_andnp">;
3107 //
3108 // BUILTIN_INFO(HEXAGON.A4_ornp,DI_ftype_DIDI,2)
3109 //
3110 def int_hexagon_A4_ornp :
3111 Hexagon_di_didi_Intrinsic<"HEXAGON_A4_ornp">;
3112 //
3113 // BUILTIN_INFO(HEXAGON.S4_addaddi,SI_ftype_SISISI,3)
3114 //
3115 def int_hexagon_S4_addaddi :
3116 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addaddi">;
3117 //
3118 // BUILTIN_INFO(HEXAGON.S4_subaddi,SI_ftype_SISISI,3)
3119 //
3120 def int_hexagon_S4_subaddi :
3121 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subaddi">;
3122 //
3123 // BUILTIN_INFO(HEXAGON.M4_and_and,SI_ftype_SISISI,3)
3124 //
3125 def int_hexagon_M4_and_and :
3126 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_and">;
3127 //
3128 // BUILTIN_INFO(HEXAGON.M4_and_andn,SI_ftype_SISISI,3)
3129 //
3130 def int_hexagon_M4_and_andn :
3131 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_andn">;
3132 //
3133 // BUILTIN_INFO(HEXAGON.M4_and_or,SI_ftype_SISISI,3)
3134 //
3135 def int_hexagon_M4_and_or :
3136 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_or">;
3137 //
3138 // BUILTIN_INFO(HEXAGON.M4_and_xor,SI_ftype_SISISI,3)
3139 //
3140 def int_hexagon_M4_and_xor :
3141 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_xor">;
3142 //
3143 // BUILTIN_INFO(HEXAGON.M4_or_and,SI_ftype_SISISI,3)
3144 //
3145 def int_hexagon_M4_or_and :
3146 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_and">;
3147 //
3148 // BUILTIN_INFO(HEXAGON.M4_or_andn,SI_ftype_SISISI,3)
3149 //
3150 def int_hexagon_M4_or_andn :
3151 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_andn">;
3152 //
3153 // BUILTIN_INFO(HEXAGON.M4_or_or,SI_ftype_SISISI,3)
3154 //
3155 def int_hexagon_M4_or_or :
3156 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_or">;
3157 //
3158 // BUILTIN_INFO(HEXAGON.M4_or_xor,SI_ftype_SISISI,3)
3159 //
3160 def int_hexagon_M4_or_xor :
3161 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_xor">;
3162 //
3163 // BUILTIN_INFO(HEXAGON.S4_or_andix,SI_ftype_SISISI,3)
3164 //
3165 def int_hexagon_S4_or_andix :
3166 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_andix">;
3167 //
3168 // BUILTIN_INFO(HEXAGON.S4_or_andi,SI_ftype_SISISI,3)
3169 //
3170 def int_hexagon_S4_or_andi :
3171 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_andi">;
3172 //
3173 // BUILTIN_INFO(HEXAGON.S4_or_ori,SI_ftype_SISISI,3)
3174 //
3175 def int_hexagon_S4_or_ori :
3176 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_ori">;
3177 //
3178 // BUILTIN_INFO(HEXAGON.M4_xor_and,SI_ftype_SISISI,3)
3179 //
3180 def int_hexagon_M4_xor_and :
3181 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_and">;
3182 //
3183 // BUILTIN_INFO(HEXAGON.M4_xor_or,SI_ftype_SISISI,3)
3184 //
3185 def int_hexagon_M4_xor_or :
3186 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_or">;
3187 //
3188 // BUILTIN_INFO(HEXAGON.M4_xor_andn,SI_ftype_SISISI,3)
3189 //
3190 def int_hexagon_M4_xor_andn :
3191 Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_andn">;
3192 //
3193 // BUILTIN_INFO(HEXAGON.A2_subri,SI_ftype_SISI,2)
3194 //
3195 def int_hexagon_A2_subri :
3196 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subri">;
3197 //
3198 // BUILTIN_INFO(HEXAGON.A2_andir,SI_ftype_SISI,2)
3199 //
3200 def int_hexagon_A2_andir :
3201 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_andir">;
3202 //
3203 // BUILTIN_INFO(HEXAGON.A2_orir,SI_ftype_SISI,2)
3204 //
3205 def int_hexagon_A2_orir :
3206 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_orir">;
3207 //
3208 // BUILTIN_INFO(HEXAGON.A2_andp,DI_ftype_DIDI,2)
3209 //
3210 def int_hexagon_A2_andp :
3211 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_andp">;
3212 //
3213 // BUILTIN_INFO(HEXAGON.A2_orp,DI_ftype_DIDI,2)
3214 //
3215 def int_hexagon_A2_orp :
3216 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_orp">;
3217 //
3218 // BUILTIN_INFO(HEXAGON.A2_xorp,DI_ftype_DIDI,2)
3219 //
3220 def int_hexagon_A2_xorp :
3221 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_xorp">;
3222 //
3223 // BUILTIN_INFO(HEXAGON.A2_notp,DI_ftype_DI,1)
3224 //
3225 def int_hexagon_A2_notp :
3226 Hexagon_di_di_Intrinsic<"HEXAGON_A2_notp">;
3227 //
3228 // BUILTIN_INFO(HEXAGON.A2_sxtw,DI_ftype_SI,1)
3229 //
3230 def int_hexagon_A2_sxtw :
3231 Hexagon_di_si_Intrinsic<"HEXAGON_A2_sxtw">;
3232 //
3233 // BUILTIN_INFO(HEXAGON.A2_sat,SI_ftype_DI,1)
3234 //
3235 def int_hexagon_A2_sat :
3236 Hexagon_si_di_Intrinsic<"HEXAGON_A2_sat">;
3237 //
3238 // BUILTIN_INFO(HEXAGON.A2_roundsat,SI_ftype_DI,1)
3239 //
3240 def int_hexagon_A2_roundsat :
3241 Hexagon_si_di_Intrinsic<"HEXAGON_A2_roundsat">;
3242 //
3243 // BUILTIN_INFO(HEXAGON.A2_sath,SI_ftype_SI,1)
3244 //
3245 def int_hexagon_A2_sath :
3246 Hexagon_si_si_Intrinsic<"HEXAGON_A2_sath">;
3247 //
3248 // BUILTIN_INFO(HEXAGON.A2_satuh,SI_ftype_SI,1)
3249 //
3250 def int_hexagon_A2_satuh :
3251 Hexagon_si_si_Intrinsic<"HEXAGON_A2_satuh">;
3252 //
3253 // BUILTIN_INFO(HEXAGON.A2_satub,SI_ftype_SI,1)
3254 //
3255 def int_hexagon_A2_satub :
3256 Hexagon_si_si_Intrinsic<"HEXAGON_A2_satub">;
3257 //
3258 // BUILTIN_INFO(HEXAGON.A2_satb,SI_ftype_SI,1)
3259 //
3260 def int_hexagon_A2_satb :
3261 Hexagon_si_si_Intrinsic<"HEXAGON_A2_satb">;
3262 //
3263 // BUILTIN_INFO(HEXAGON.A2_vaddub,DI_ftype_DIDI,2)
3264 //
3265 def int_hexagon_A2_vaddub :
3266 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddub">;
3267 //
3268 // BUILTIN_INFO(HEXAGON.A2_vaddb_map,DI_ftype_DIDI,2)
3269 //
3270 def int_hexagon_A2_vaddb_map :
3271 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddb_map">;
3272 //
3273 // BUILTIN_INFO(HEXAGON.A2_vaddubs,DI_ftype_DIDI,2)
3274 //
3275 def int_hexagon_A2_vaddubs :
3276 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddubs">;
3277 //
3278 // BUILTIN_INFO(HEXAGON.A2_vaddh,DI_ftype_DIDI,2)
3279 //
3280 def int_hexagon_A2_vaddh :
3281 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddh">;
3282 //
3283 // BUILTIN_INFO(HEXAGON.A2_vaddhs,DI_ftype_DIDI,2)
3284 //
3285 def int_hexagon_A2_vaddhs :
3286 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddhs">;
3287 //
3288 // BUILTIN_INFO(HEXAGON.A2_vadduhs,DI_ftype_DIDI,2)
3289 //
3290 def int_hexagon_A2_vadduhs :
3291 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vadduhs">;
3292 //
3293 // BUILTIN_INFO(HEXAGON.A5_vaddhubs,SI_ftype_DIDI,2)
3294 //
3295 def int_hexagon_A5_vaddhubs :
3296 Hexagon_si_didi_Intrinsic<"HEXAGON_A5_vaddhubs">;
3297 //
3298 // BUILTIN_INFO(HEXAGON.A2_vaddw,DI_ftype_DIDI,2)
3299 //
3300 def int_hexagon_A2_vaddw :
3301 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddw">;
3302 //
3303 // BUILTIN_INFO(HEXAGON.A2_vaddws,DI_ftype_DIDI,2)
3304 //
3305 def int_hexagon_A2_vaddws :
3306 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddws">;
3307 //
3308 // BUILTIN_INFO(HEXAGON.S4_vxaddsubw,DI_ftype_DIDI,2)
3309 //
3310 def int_hexagon_S4_vxaddsubw :
3311 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubw">;
3312 //
3313 // BUILTIN_INFO(HEXAGON.S4_vxsubaddw,DI_ftype_DIDI,2)
3314 //
3315 def int_hexagon_S4_vxsubaddw :
3316 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddw">;
3317 //
3318 // BUILTIN_INFO(HEXAGON.S4_vxaddsubh,DI_ftype_DIDI,2)
3319 //
3320 def int_hexagon_S4_vxaddsubh :
3321 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubh">;
3322 //
3323 // BUILTIN_INFO(HEXAGON.S4_vxsubaddh,DI_ftype_DIDI,2)
3324 //
3325 def int_hexagon_S4_vxsubaddh :
3326 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddh">;
3327 //
3328 // BUILTIN_INFO(HEXAGON.S4_vxaddsubhr,DI_ftype_DIDI,2)
3329 //
3330 def int_hexagon_S4_vxaddsubhr :
3331 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubhr">;
3332 //
3333 // BUILTIN_INFO(HEXAGON.S4_vxsubaddhr,DI_ftype_DIDI,2)
3334 //
3335 def int_hexagon_S4_vxsubaddhr :
3336 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddhr">;
3337 //
3338 // BUILTIN_INFO(HEXAGON.A2_svavgh,SI_ftype_SISI,2)
3339 //
3340 def int_hexagon_A2_svavgh :
3341 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svavgh">;
3342 //
3343 // BUILTIN_INFO(HEXAGON.A2_svavghs,SI_ftype_SISI,2)
3344 //
3345 def int_hexagon_A2_svavghs :
3346 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svavghs">;
3347 //
3348 // BUILTIN_INFO(HEXAGON.A2_svnavgh,SI_ftype_SISI,2)
3349 //
3350 def int_hexagon_A2_svnavgh :
3351 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svnavgh">;
3352 //
3353 // BUILTIN_INFO(HEXAGON.A2_svaddh,SI_ftype_SISI,2)
3354 //
3355 def int_hexagon_A2_svaddh :
3356 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svaddh">;
3357 //
3358 // BUILTIN_INFO(HEXAGON.A2_svaddhs,SI_ftype_SISI,2)
3359 //
3360 def int_hexagon_A2_svaddhs :
3361 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svaddhs">;
3362 //
3363 // BUILTIN_INFO(HEXAGON.A2_svadduhs,SI_ftype_SISI,2)
3364 //
3365 def int_hexagon_A2_svadduhs :
3366 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svadduhs">;
3367 //
3368 // BUILTIN_INFO(HEXAGON.A2_svsubh,SI_ftype_SISI,2)
3369 //
3370 def int_hexagon_A2_svsubh :
3371 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubh">;
3372 //
3373 // BUILTIN_INFO(HEXAGON.A2_svsubhs,SI_ftype_SISI,2)
3374 //
3375 def int_hexagon_A2_svsubhs :
3376 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubhs">;
3377 //
3378 // BUILTIN_INFO(HEXAGON.A2_svsubuhs,SI_ftype_SISI,2)
3379 //
3380 def int_hexagon_A2_svsubuhs :
3381 Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubuhs">;
3382 //
3383 // BUILTIN_INFO(HEXAGON.A2_vraddub,DI_ftype_DIDI,2)
3384 //
3385 def int_hexagon_A2_vraddub :
3386 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vraddub">;
3387 //
3388 // BUILTIN_INFO(HEXAGON.A2_vraddub_acc,DI_ftype_DIDIDI,3)
3389 //
3390 def int_hexagon_A2_vraddub_acc :
3391 Hexagon_di_dididi_Intrinsic<"HEXAGON_A2_vraddub_acc">;
3392 //
3393 // BUILTIN_INFO(HEXAGON.M2_vraddh,SI_ftype_DIDI,2)
3394 //
3395 def int_hexagon_M2_vraddh :
3396 Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vraddh">;
3397 //
3398 // BUILTIN_INFO(HEXAGON.M2_vradduh,SI_ftype_DIDI,2)
3399 //
3400 def int_hexagon_M2_vradduh :
3401 Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vradduh">;
3402 //
3403 // BUILTIN_INFO(HEXAGON.A2_vsubub,DI_ftype_DIDI,2)
3404 //
3405 def int_hexagon_A2_vsubub :
3406 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubub">;
3407 //
3408 // BUILTIN_INFO(HEXAGON.A2_vsubb_map,DI_ftype_DIDI,2)
3409 //
3410 def int_hexagon_A2_vsubb_map :
3411 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubb_map">;
3412 //
3413 // BUILTIN_INFO(HEXAGON.A2_vsububs,DI_ftype_DIDI,2)
3414 //
3415 def int_hexagon_A2_vsububs :
3416 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsububs">;
3417 //
3418 // BUILTIN_INFO(HEXAGON.A2_vsubh,DI_ftype_DIDI,2)
3419 //
3420 def int_hexagon_A2_vsubh :
3421 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubh">;
3422 //
3423 // BUILTIN_INFO(HEXAGON.A2_vsubhs,DI_ftype_DIDI,2)
3424 //
3425 def int_hexagon_A2_vsubhs :
3426 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubhs">;
3427 //
3428 // BUILTIN_INFO(HEXAGON.A2_vsubuhs,DI_ftype_DIDI,2)
3429 //
3430 def int_hexagon_A2_vsubuhs :
3431 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubuhs">;
3432 //
3433 // BUILTIN_INFO(HEXAGON.A2_vsubw,DI_ftype_DIDI,2)
3434 //
3435 def int_hexagon_A2_vsubw :
3436 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubw">;
3437 //
3438 // BUILTIN_INFO(HEXAGON.A2_vsubws,DI_ftype_DIDI,2)
3439 //
3440 def int_hexagon_A2_vsubws :
3441 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubws">;
3442 //
3443 // BUILTIN_INFO(HEXAGON.A2_vabsh,DI_ftype_DI,1)
3444 //
3445 def int_hexagon_A2_vabsh :
3446 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabsh">;
3447 //
3448 // BUILTIN_INFO(HEXAGON.A2_vabshsat,DI_ftype_DI,1)
3449 //
3450 def int_hexagon_A2_vabshsat :
3451 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabshsat">;
3452 //
3453 // BUILTIN_INFO(HEXAGON.A2_vabsw,DI_ftype_DI,1)
3454 //
3455 def int_hexagon_A2_vabsw :
3456 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabsw">;
3457 //
3458 // BUILTIN_INFO(HEXAGON.A2_vabswsat,DI_ftype_DI,1)
3459 //
3460 def int_hexagon_A2_vabswsat :
3461 Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabswsat">;
3462 //
3463 // BUILTIN_INFO(HEXAGON.M2_vabsdiffw,DI_ftype_DIDI,2)
3464 //
3465 def int_hexagon_M2_vabsdiffw :
3466 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vabsdiffw">;
3467 //
3468 // BUILTIN_INFO(HEXAGON.M2_vabsdiffh,DI_ftype_DIDI,2)
3469 //
3470 def int_hexagon_M2_vabsdiffh :
3471 Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vabsdiffh">;
3472 //
3473 // BUILTIN_INFO(HEXAGON.A2_vrsadub,DI_ftype_DIDI,2)
3474 //
3475 def int_hexagon_A2_vrsadub :
3476 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vrsadub">;
3477 //
3478 // BUILTIN_INFO(HEXAGON.A2_vrsadub_acc,DI_ftype_DIDIDI,3)
3479 //
3480 def int_hexagon_A2_vrsadub_acc :
3481 Hexagon_di_dididi_Intrinsic<"HEXAGON_A2_vrsadub_acc">;
3482 //
3483 // BUILTIN_INFO(HEXAGON.A2_vavgub,DI_ftype_DIDI,2)
3484 //
3485 def int_hexagon_A2_vavgub :
3486 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgub">;
3487 //
3488 // BUILTIN_INFO(HEXAGON.A2_vavguh,DI_ftype_DIDI,2)
3489 //
3490 def int_hexagon_A2_vavguh :
3491 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguh">;
3492 //
3493 // BUILTIN_INFO(HEXAGON.A2_vavgh,DI_ftype_DIDI,2)
3494 //
3495 def int_hexagon_A2_vavgh :
3496 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgh">;
3497 //
3498 // BUILTIN_INFO(HEXAGON.A2_vnavgh,DI_ftype_DIDI,2)
3499 //
3500 def int_hexagon_A2_vnavgh :
3501 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgh">;
3502 //
3503 // BUILTIN_INFO(HEXAGON.A2_vavgw,DI_ftype_DIDI,2)
3504 //
3505 def int_hexagon_A2_vavgw :
3506 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgw">;
3507 //
3508 // BUILTIN_INFO(HEXAGON.A2_vnavgw,DI_ftype_DIDI,2)
3509 //
3510 def int_hexagon_A2_vnavgw :
3511 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgw">;
3512 //
3513 // BUILTIN_INFO(HEXAGON.A2_vavgwr,DI_ftype_DIDI,2)
3514 //
3515 def int_hexagon_A2_vavgwr :
3516 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgwr">;
3517 //
3518 // BUILTIN_INFO(HEXAGON.A2_vnavgwr,DI_ftype_DIDI,2)
3519 //
3520 def int_hexagon_A2_vnavgwr :
3521 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgwr">;
3522 //
3523 // BUILTIN_INFO(HEXAGON.A2_vavgwcr,DI_ftype_DIDI,2)
3524 //
3525 def int_hexagon_A2_vavgwcr :
3526 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgwcr">;
3527 //
3528 // BUILTIN_INFO(HEXAGON.A2_vnavgwcr,DI_ftype_DIDI,2)
3529 //
3530 def int_hexagon_A2_vnavgwcr :
3531 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgwcr">;
3532 //
3533 // BUILTIN_INFO(HEXAGON.A2_vavghcr,DI_ftype_DIDI,2)
3534 //
3535 def int_hexagon_A2_vavghcr :
3536 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavghcr">;
3537 //
3538 // BUILTIN_INFO(HEXAGON.A2_vnavghcr,DI_ftype_DIDI,2)
3539 //
3540 def int_hexagon_A2_vnavghcr :
3541 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavghcr">;
3542 //
3543 // BUILTIN_INFO(HEXAGON.A2_vavguw,DI_ftype_DIDI,2)
3544 //
3545 def int_hexagon_A2_vavguw :
3546 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguw">;
3547 //
3548 // BUILTIN_INFO(HEXAGON.A2_vavguwr,DI_ftype_DIDI,2)
3549 //
3550 def int_hexagon_A2_vavguwr :
3551 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguwr">;
3552 //
3553 // BUILTIN_INFO(HEXAGON.A2_vavgubr,DI_ftype_DIDI,2)
3554 //
3555 def int_hexagon_A2_vavgubr :
3556 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgubr">;
3557 //
3558 // BUILTIN_INFO(HEXAGON.A2_vavguhr,DI_ftype_DIDI,2)
3559 //
3560 def int_hexagon_A2_vavguhr :
3561 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguhr">;
3562 //
3563 // BUILTIN_INFO(HEXAGON.A2_vavghr,DI_ftype_DIDI,2)
3564 //
3565 def int_hexagon_A2_vavghr :
3566 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavghr">;
3567 //
3568 // BUILTIN_INFO(HEXAGON.A2_vnavghr,DI_ftype_DIDI,2)
3569 //
3570 def int_hexagon_A2_vnavghr :
3571 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavghr">;
3572 //
3573 // BUILTIN_INFO(HEXAGON.A4_round_ri,SI_ftype_SISI,2)
3574 //
3575 def int_hexagon_A4_round_ri :
3576 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_ri">;
3577 //
3578 // BUILTIN_INFO(HEXAGON.A4_round_rr,SI_ftype_SISI,2)
3579 //
3580 def int_hexagon_A4_round_rr :
3581 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_rr">;
3582 //
3583 // BUILTIN_INFO(HEXAGON.A4_round_ri_sat,SI_ftype_SISI,2)
3584 //
3585 def int_hexagon_A4_round_ri_sat :
3586 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_ri_sat">;
3587 //
3588 // BUILTIN_INFO(HEXAGON.A4_round_rr_sat,SI_ftype_SISI,2)
3589 //
3590 def int_hexagon_A4_round_rr_sat :
3591 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_rr_sat">;
3592 //
3593 // BUILTIN_INFO(HEXAGON.A4_cround_ri,SI_ftype_SISI,2)
3594 //
3595 def int_hexagon_A4_cround_ri :
3596 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cround_ri">;
3597 //
3598 // BUILTIN_INFO(HEXAGON.A4_cround_rr,SI_ftype_SISI,2)
3599 //
3600 def int_hexagon_A4_cround_rr :
3601 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cround_rr">;
3602 //
3603 // BUILTIN_INFO(HEXAGON.A4_vrminh,DI_ftype_DIDISI,3)
3604 //
3605 def int_hexagon_A4_vrminh :
3606 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminh">;
3607 //
3608 // BUILTIN_INFO(HEXAGON.A4_vrmaxh,DI_ftype_DIDISI,3)
3609 //
3610 def int_hexagon_A4_vrmaxh :
3611 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxh">;
3612 //
3613 // BUILTIN_INFO(HEXAGON.A4_vrminuh,DI_ftype_DIDISI,3)
3614 //
3615 def int_hexagon_A4_vrminuh :
3616 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminuh">;
3617 //
3618 // BUILTIN_INFO(HEXAGON.A4_vrmaxuh,DI_ftype_DIDISI,3)
3619 //
3620 def int_hexagon_A4_vrmaxuh :
3621 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxuh">;
3622 //
3623 // BUILTIN_INFO(HEXAGON.A4_vrminw,DI_ftype_DIDISI,3)
3624 //
3625 def int_hexagon_A4_vrminw :
3626 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminw">;
3627 //
3628 // BUILTIN_INFO(HEXAGON.A4_vrmaxw,DI_ftype_DIDISI,3)
3629 //
3630 def int_hexagon_A4_vrmaxw :
3631 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxw">;
3632 //
3633 // BUILTIN_INFO(HEXAGON.A4_vrminuw,DI_ftype_DIDISI,3)
3634 //
3635 def int_hexagon_A4_vrminuw :
3636 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminuw">;
3637 //
3638 // BUILTIN_INFO(HEXAGON.A4_vrmaxuw,DI_ftype_DIDISI,3)
3639 //
3640 def int_hexagon_A4_vrmaxuw :
3641 Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxuw">;
3642 //
3643 // BUILTIN_INFO(HEXAGON.A2_vminb,DI_ftype_DIDI,2)
3644 //
3645 def int_hexagon_A2_vminb :
3646 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminb">;
3647 //
3648 // BUILTIN_INFO(HEXAGON.A2_vmaxb,DI_ftype_DIDI,2)
3649 //
3650 def int_hexagon_A2_vmaxb :
3651 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxb">;
3652 //
3653 // BUILTIN_INFO(HEXAGON.A2_vminub,DI_ftype_DIDI,2)
3654 //
3655 def int_hexagon_A2_vminub :
3656 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminub">;
3657 //
3658 // BUILTIN_INFO(HEXAGON.A2_vmaxub,DI_ftype_DIDI,2)
3659 //
3660 def int_hexagon_A2_vmaxub :
3661 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxub">;
3662 //
3663 // BUILTIN_INFO(HEXAGON.A2_vminh,DI_ftype_DIDI,2)
3664 //
3665 def int_hexagon_A2_vminh :
3666 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminh">;
3667 //
3668 // BUILTIN_INFO(HEXAGON.A2_vmaxh,DI_ftype_DIDI,2)
3669 //
3670 def int_hexagon_A2_vmaxh :
3671 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxh">;
3672 //
3673 // BUILTIN_INFO(HEXAGON.A2_vminuh,DI_ftype_DIDI,2)
3674 //
3675 def int_hexagon_A2_vminuh :
3676 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminuh">;
3677 //
3678 // BUILTIN_INFO(HEXAGON.A2_vmaxuh,DI_ftype_DIDI,2)
3679 //
3680 def int_hexagon_A2_vmaxuh :
3681 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxuh">;
3682 //
3683 // BUILTIN_INFO(HEXAGON.A2_vminw,DI_ftype_DIDI,2)
3684 //
3685 def int_hexagon_A2_vminw :
3686 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminw">;
3687 //
3688 // BUILTIN_INFO(HEXAGON.A2_vmaxw,DI_ftype_DIDI,2)
3689 //
3690 def int_hexagon_A2_vmaxw :
3691 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxw">;
3692 //
3693 // BUILTIN_INFO(HEXAGON.A2_vminuw,DI_ftype_DIDI,2)
3694 //
3695 def int_hexagon_A2_vminuw :
3696 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminuw">;
3697 //
3698 // BUILTIN_INFO(HEXAGON.A2_vmaxuw,DI_ftype_DIDI,2)
3699 //
3700 def int_hexagon_A2_vmaxuw :
3701 Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxuw">;
3702 //
3703 // BUILTIN_INFO(HEXAGON.A4_modwrapu,SI_ftype_SISI,2)
3704 //
3705 def int_hexagon_A4_modwrapu :
3706 Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_modwrapu">;
3707 //
3708 // BUILTIN_INFO(HEXAGON.F2_sfadd,SF_ftype_SFSF,2)
3709 //
3710 def int_hexagon_F2_sfadd :
3711 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfadd">;
3712 //
3713 // BUILTIN_INFO(HEXAGON.F2_sfsub,SF_ftype_SFSF,2)
3714 //
3715 def int_hexagon_F2_sfsub :
3716 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfsub">;
3717 //
3718 // BUILTIN_INFO(HEXAGON.F2_sfmpy,SF_ftype_SFSF,2)
3719 //
3720 def int_hexagon_F2_sfmpy :
3721 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmpy">;
3722 //
3723 // BUILTIN_INFO(HEXAGON.F2_sffma,SF_ftype_SFSFSF,3)
3724 //
3725 def int_hexagon_F2_sffma :
3726 Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffma">;
3727 //
3728 // BUILTIN_INFO(HEXAGON.F2_sffma_sc,SF_ftype_SFSFSFQI,4)
3729 //
3730 def int_hexagon_F2_sffma_sc :
3731 Hexagon_sf_sfsfsfqi_Intrinsic<"HEXAGON_F2_sffma_sc">;
3732 //
3733 // BUILTIN_INFO(HEXAGON.F2_sffms,SF_ftype_SFSFSF,3)
3734 //
3735 def int_hexagon_F2_sffms :
3736 Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms">;
3737 //
3738 // BUILTIN_INFO(HEXAGON.F2_sffma_lib,SF_ftype_SFSFSF,3)
3739 //
3740 def int_hexagon_F2_sffma_lib :
3741 Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffma_lib">;
3742 //
3743 // BUILTIN_INFO(HEXAGON.F2_sffms_lib,SF_ftype_SFSFSF,3)
3744 //
3745 def int_hexagon_F2_sffms_lib :
3746 Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms_lib">;
3747 //
3748 // BUILTIN_INFO(HEXAGON.F2_sfcmpeq,QI_ftype_SFSF,2)
3749 //
3750 def int_hexagon_F2_sfcmpeq :
3751 Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpeq">;
3752 //
3753 // BUILTIN_INFO(HEXAGON.F2_sfcmpgt,QI_ftype_SFSF,2)
3754 //
3755 def int_hexagon_F2_sfcmpgt :
3756 Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpgt">;
3757 //
3758 // BUILTIN_INFO(HEXAGON.F2_sfcmpge,QI_ftype_SFSF,2)
3759 //
3760 def int_hexagon_F2_sfcmpge :
3761 Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpge">;
3762 //
3763 // BUILTIN_INFO(HEXAGON.F2_sfcmpuo,QI_ftype_SFSF,2)
3764 //
3765 def int_hexagon_F2_sfcmpuo :
3766 Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpuo">;
3767 //
3768 // BUILTIN_INFO(HEXAGON.F2_sfmax,SF_ftype_SFSF,2)
3769 //
3770 def int_hexagon_F2_sfmax :
3771 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmax">;
3772 //
3773 // BUILTIN_INFO(HEXAGON.F2_sfmin,SF_ftype_SFSF,2)
3774 //
3775 def int_hexagon_F2_sfmin :
3776 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmin">;
3777 //
3778 // BUILTIN_INFO(HEXAGON.F2_sfclass,QI_ftype_SFSI,2)
3779 //
3780 def int_hexagon_F2_sfclass :
3781 Hexagon_si_sfsi_Intrinsic<"HEXAGON_F2_sfclass">;
3782 //
3783 // BUILTIN_INFO(HEXAGON.F2_sfimm_p,SF_ftype_SI,1)
3784 //
3785 def int_hexagon_F2_sfimm_p :
3786 Hexagon_sf_si_Intrinsic<"HEXAGON_F2_sfimm_p">;
3787 //
3788 // BUILTIN_INFO(HEXAGON.F2_sfimm_n,SF_ftype_SI,1)
3789 //
3790 def int_hexagon_F2_sfimm_n :
3791 Hexagon_sf_si_Intrinsic<"HEXAGON_F2_sfimm_n">;
3792 //
3793 // BUILTIN_INFO(HEXAGON.F2_sffixupn,SF_ftype_SFSF,2)
3794 //
3795 def int_hexagon_F2_sffixupn :
3796 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sffixupn">;
3797 //
3798 // BUILTIN_INFO(HEXAGON.F2_sffixupd,SF_ftype_SFSF,2)
3799 //
3800 def int_hexagon_F2_sffixupd :
3801 Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sffixupd">;
3802 //
3803 // BUILTIN_INFO(HEXAGON.F2_sffixupr,SF_ftype_SF,1)
3804 //
3805 def int_hexagon_F2_sffixupr :
3806 Hexagon_sf_sf_Intrinsic<"HEXAGON_F2_sffixupr">;
3807 //
3808 // BUILTIN_INFO(HEXAGON.F2_dfcmpeq,QI_ftype_DFDF,2)
3809 //
3810 def int_hexagon_F2_dfcmpeq :
3811 Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpeq">;
3812 //
3813 // BUILTIN_INFO(HEXAGON.F2_dfcmpgt,QI_ftype_DFDF,2)
3814 //
3815 def int_hexagon_F2_dfcmpgt :
3816 Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpgt">;
3817 //
3818 // BUILTIN_INFO(HEXAGON.F2_dfcmpge,QI_ftype_DFDF,2)
3819 //
3820 def int_hexagon_F2_dfcmpge :
3821 Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpge">;
3822 //
3823 // BUILTIN_INFO(HEXAGON.F2_dfcmpuo,QI_ftype_DFDF,2)
3824 //
3825 def int_hexagon_F2_dfcmpuo :
3826 Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpuo">;
3827 //
3828 // BUILTIN_INFO(HEXAGON.F2_dfclass,QI_ftype_DFSI,2)
3829 //
3830 def int_hexagon_F2_dfclass :
3831 Hexagon_si_dfsi_Intrinsic<"HEXAGON_F2_dfclass">;
3832 //
3833 // BUILTIN_INFO(HEXAGON.F2_dfimm_p,DF_ftype_SI,1)
3834 //
3835 def int_hexagon_F2_dfimm_p :
3836 Hexagon_df_si_Intrinsic<"HEXAGON_F2_dfimm_p">;
3837 //
3838 // BUILTIN_INFO(HEXAGON.F2_dfimm_n,DF_ftype_SI,1)
3839 //
3840 def int_hexagon_F2_dfimm_n :
3841 Hexagon_df_si_Intrinsic<"HEXAGON_F2_dfimm_n">;
3842 //
3843 // BUILTIN_INFO(HEXAGON.F2_conv_sf2df,DF_ftype_SF,1)
3844 //
3845 def int_hexagon_F2_conv_sf2df :
3846 Hexagon_df_sf_Intrinsic<"HEXAGON_F2_conv_sf2df">;
3847 //
3848 // BUILTIN_INFO(HEXAGON.F2_conv_df2sf,SF_ftype_DF,1)
3849 //
3850 def int_hexagon_F2_conv_df2sf :
3851 Hexagon_sf_df_Intrinsic<"HEXAGON_F2_conv_df2sf">;
3852 //
3853 // BUILTIN_INFO(HEXAGON.F2_conv_uw2sf,SF_ftype_SI,1)
3854 //
3855 def int_hexagon_F2_conv_uw2sf :
3856 Hexagon_sf_si_Intrinsic<"HEXAGON_F2_conv_uw2sf">;
3857 //
3858 // BUILTIN_INFO(HEXAGON.F2_conv_uw2df,DF_ftype_SI,1)
3859 //
3860 def int_hexagon_F2_conv_uw2df :
3861 Hexagon_df_si_Intrinsic<"HEXAGON_F2_conv_uw2df">;
3862 //
3863 // BUILTIN_INFO(HEXAGON.F2_conv_w2sf,SF_ftype_SI,1)
3864 //
3865 def int_hexagon_F2_conv_w2sf :
3866 Hexagon_sf_si_Intrinsic<"HEXAGON_F2_conv_w2sf">;
3867 //
3868 // BUILTIN_INFO(HEXAGON.F2_conv_w2df,DF_ftype_SI,1)
3869 //
3870 def int_hexagon_F2_conv_w2df :
3871 Hexagon_df_si_Intrinsic<"HEXAGON_F2_conv_w2df">;
3872 //
3873 // BUILTIN_INFO(HEXAGON.F2_conv_ud2sf,SF_ftype_DI,1)
3874 //
3875 def int_hexagon_F2_conv_ud2sf :
3876 Hexagon_sf_di_Intrinsic<"HEXAGON_F2_conv_ud2sf">;
3877 //
3878 // BUILTIN_INFO(HEXAGON.F2_conv_ud2df,DF_ftype_DI,1)
3879 //
3880 def int_hexagon_F2_conv_ud2df :
3881 Hexagon_df_di_Intrinsic<"HEXAGON_F2_conv_ud2df">;
3882 //
3883 // BUILTIN_INFO(HEXAGON.F2_conv_d2sf,SF_ftype_DI,1)
3884 //
3885 def int_hexagon_F2_conv_d2sf :
3886 Hexagon_sf_di_Intrinsic<"HEXAGON_F2_conv_d2sf">;
3887 //
3888 // BUILTIN_INFO(HEXAGON.F2_conv_d2df,DF_ftype_DI,1)
3889 //
3890 def int_hexagon_F2_conv_d2df :
3891 Hexagon_df_di_Intrinsic<"HEXAGON_F2_conv_d2df">;
3892 //
3893 // BUILTIN_INFO(HEXAGON.F2_conv_sf2uw,SI_ftype_SF,1)
3894 //
3895 def int_hexagon_F2_conv_sf2uw :
3896 Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2uw">;
3897 //
3898 // BUILTIN_INFO(HEXAGON.F2_conv_sf2w,SI_ftype_SF,1)
3899 //
3900 def int_hexagon_F2_conv_sf2w :
3901 Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2w">;
3902 //
3903 // BUILTIN_INFO(HEXAGON.F2_conv_sf2ud,DI_ftype_SF,1)
3904 //
3905 def int_hexagon_F2_conv_sf2ud :
3906 Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2ud">;
3907 //
3908 // BUILTIN_INFO(HEXAGON.F2_conv_sf2d,DI_ftype_SF,1)
3909 //
3910 def int_hexagon_F2_conv_sf2d :
3911 Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2d">;
3912 //
3913 // BUILTIN_INFO(HEXAGON.F2_conv_df2uw,SI_ftype_DF,1)
3914 //
3915 def int_hexagon_F2_conv_df2uw :
3916 Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2uw">;
3917 //
3918 // BUILTIN_INFO(HEXAGON.F2_conv_df2w,SI_ftype_DF,1)
3919 //
3920 def int_hexagon_F2_conv_df2w :
3921 Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2w">;
3922 //
3923 // BUILTIN_INFO(HEXAGON.F2_conv_df2ud,DI_ftype_DF,1)
3924 //
3925 def int_hexagon_F2_conv_df2ud :
3926 Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2ud">;
3927 //
3928 // BUILTIN_INFO(HEXAGON.F2_conv_df2d,DI_ftype_DF,1)
3929 //
3930 def int_hexagon_F2_conv_df2d :
3931 Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2d">;
3932 //
3933 // BUILTIN_INFO(HEXAGON.F2_conv_sf2uw_chop,SI_ftype_SF,1)
3934 //
3935 def int_hexagon_F2_conv_sf2uw_chop :
3936 Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">;
3937 //
3938 // BUILTIN_INFO(HEXAGON.F2_conv_sf2w_chop,SI_ftype_SF,1)
3939 //
3940 def int_hexagon_F2_conv_sf2w_chop :
3941 Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">;
3942 //
3943 // BUILTIN_INFO(HEXAGON.F2_conv_sf2ud_chop,DI_ftype_SF,1)
3944 //
3945 def int_hexagon_F2_conv_sf2ud_chop :
3946 Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;
3947 //
3948 // BUILTIN_INFO(HEXAGON.F2_conv_sf2d_chop,DI_ftype_SF,1)
3949 //
3950 def int_hexagon_F2_conv_sf2d_chop :
3951 Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">;
3952 //
3953 // BUILTIN_INFO(HEXAGON.F2_conv_df2uw_chop,SI_ftype_DF,1)
3954 //
3955 def int_hexagon_F2_conv_df2uw_chop :
3956 Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;
3957 //
3958 // BUILTIN_INFO(HEXAGON.F2_conv_df2w_chop,SI_ftype_DF,1)
3959 //
3960 def int_hexagon_F2_conv_df2w_chop :
3961 Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2w_chop">;
3962 //
3963 // BUILTIN_INFO(HEXAGON.F2_conv_df2ud_chop,DI_ftype_DF,1)
3964 //
3965 def int_hexagon_F2_conv_df2ud_chop :
3966 Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;
3967 //
3968 // BUILTIN_INFO(HEXAGON.F2_conv_df2d_chop,DI_ftype_DF,1)
3969 //
3970 def int_hexagon_F2_conv_df2d_chop :
3971 Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;
3972 //
3973 // BUILTIN_INFO(HEXAGON.S2_asr_r_r,SI_ftype_SISI,2)
3974 //
3975 def int_hexagon_S2_asr_r_r :
3976 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_r_r">;
3977 //
3978 // BUILTIN_INFO(HEXAGON.S2_asl_r_r,SI_ftype_SISI,2)
3979 //
3980 def int_hexagon_S2_asl_r_r :
3981 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_r_r">;
3982 //
3983 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r,SI_ftype_SISI,2)
3984 //
3985 def int_hexagon_S2_lsr_r_r :
3986 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsr_r_r">;
3987 //
3988 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r,SI_ftype_SISI,2)
3989 //
3990 def int_hexagon_S2_lsl_r_r :
3991 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsl_r_r">;
3992 //
3993 // BUILTIN_INFO(HEXAGON.S2_asr_r_p,DI_ftype_DISI,2)
3994 //
3995 def int_hexagon_S2_asr_r_p :
3996 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_p">;
3997 //
3998 // BUILTIN_INFO(HEXAGON.S2_asl_r_p,DI_ftype_DISI,2)
3999 //
4000 def int_hexagon_S2_asl_r_p :
4001 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_p">;
4002 //
4003 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p,DI_ftype_DISI,2)
4004 //
4005 def int_hexagon_S2_lsr_r_p :
4006 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_p">;
4007 //
4008 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p,DI_ftype_DISI,2)
4009 //
4010 def int_hexagon_S2_lsl_r_p :
4011 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_p">;
4012 //
4013 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_acc,SI_ftype_SISISI,3)
4014 //
4015 def int_hexagon_S2_asr_r_r_acc :
4016 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;
4017 //
4018 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_acc,SI_ftype_SISISI,3)
4019 //
4020 def int_hexagon_S2_asl_r_r_acc :
4021 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;
4022 //
4023 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_acc,SI_ftype_SISISI,3)
4024 //
4025 def int_hexagon_S2_lsr_r_r_acc :
4026 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;
4027 //
4028 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_acc,SI_ftype_SISISI,3)
4029 //
4030 def int_hexagon_S2_lsl_r_r_acc :
4031 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;
4032 //
4033 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_acc,DI_ftype_DIDISI,3)
4034 //
4035 def int_hexagon_S2_asr_r_p_acc :
4036 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_acc">;
4037 //
4038 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_acc,DI_ftype_DIDISI,3)
4039 //
4040 def int_hexagon_S2_asl_r_p_acc :
4041 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;
4042 //
4043 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_acc,DI_ftype_DIDISI,3)
4044 //
4045 def int_hexagon_S2_lsr_r_p_acc :
4046 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;
4047 //
4048 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_acc,DI_ftype_DIDISI,3)
4049 //
4050 def int_hexagon_S2_lsl_r_p_acc :
4051 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;
4052 //
4053 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_nac,SI_ftype_SISISI,3)
4054 //
4055 def int_hexagon_S2_asr_r_r_nac :
4056 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;
4057 //
4058 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_nac,SI_ftype_SISISI,3)
4059 //
4060 def int_hexagon_S2_asl_r_r_nac :
4061 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;
4062 //
4063 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_nac,SI_ftype_SISISI,3)
4064 //
4065 def int_hexagon_S2_lsr_r_r_nac :
4066 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;
4067 //
4068 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_nac,SI_ftype_SISISI,3)
4069 //
4070 def int_hexagon_S2_lsl_r_r_nac :
4071 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;
4072 //
4073 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_nac,DI_ftype_DIDISI,3)
4074 //
4075 def int_hexagon_S2_asr_r_p_nac :
4076 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;
4077 //
4078 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_nac,DI_ftype_DIDISI,3)
4079 //
4080 def int_hexagon_S2_asl_r_p_nac :
4081 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;
4082 //
4083 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_nac,DI_ftype_DIDISI,3)
4084 //
4085 def int_hexagon_S2_lsr_r_p_nac :
4086 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;
4087 //
4088 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_nac,DI_ftype_DIDISI,3)
4089 //
4090 def int_hexagon_S2_lsl_r_p_nac :
4091 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;
4092 //
4093 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_and,SI_ftype_SISISI,3)
4094 //
4095 def int_hexagon_S2_asr_r_r_and :
4096 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_and">;
4097 //
4098 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_and,SI_ftype_SISISI,3)
4099 //
4100 def int_hexagon_S2_asl_r_r_and :
4101 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_and">;
4102 //
4103 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_and,SI_ftype_SISISI,3)
4104 //
4105 def int_hexagon_S2_lsr_r_r_and :
4106 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;
4107 //
4108 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_and,SI_ftype_SISISI,3)
4109 //
4110 def int_hexagon_S2_lsl_r_r_and :
4111 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;
4112 //
4113 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_or,SI_ftype_SISISI,3)
4114 //
4115 def int_hexagon_S2_asr_r_r_or :
4116 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_or">;
4117 //
4118 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_or,SI_ftype_SISISI,3)
4119 //
4120 def int_hexagon_S2_asl_r_r_or :
4121 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_or">;
4122 //
4123 // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_or,SI_ftype_SISISI,3)
4124 //
4125 def int_hexagon_S2_lsr_r_r_or :
4126 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;
4127 //
4128 // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_or,SI_ftype_SISISI,3)
4129 //
4130 def int_hexagon_S2_lsl_r_r_or :
4131 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;
4132 //
4133 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_and,DI_ftype_DIDISI,3)
4134 //
4135 def int_hexagon_S2_asr_r_p_and :
4136 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_and">;
4137 //
4138 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_and,DI_ftype_DIDISI,3)
4139 //
4140 def int_hexagon_S2_asl_r_p_and :
4141 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_and">;
4142 //
4143 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_and,DI_ftype_DIDISI,3)
4144 //
4145 def int_hexagon_S2_lsr_r_p_and :
4146 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_and">;
4147 //
4148 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_and,DI_ftype_DIDISI,3)
4149 //
4150 def int_hexagon_S2_lsl_r_p_and :
4151 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;
4152 //
4153 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_or,DI_ftype_DIDISI,3)
4154 //
4155 def int_hexagon_S2_asr_r_p_or :
4156 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_or">;
4157 //
4158 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_or,DI_ftype_DIDISI,3)
4159 //
4160 def int_hexagon_S2_asl_r_p_or :
4161 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_or">;
4162 //
4163 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_or,DI_ftype_DIDISI,3)
4164 //
4165 def int_hexagon_S2_lsr_r_p_or :
4166 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;
4167 //
4168 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_or,DI_ftype_DIDISI,3)
4169 //
4170 def int_hexagon_S2_lsl_r_p_or :
4171 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;
4172 //
4173 // BUILTIN_INFO(HEXAGON.S2_asr_r_p_xor,DI_ftype_DIDISI,3)
4174 //
4175 def int_hexagon_S2_asr_r_p_xor :
4176 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;
4177 //
4178 // BUILTIN_INFO(HEXAGON.S2_asl_r_p_xor,DI_ftype_DIDISI,3)
4179 //
4180 def int_hexagon_S2_asl_r_p_xor :
4181 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;
4182 //
4183 // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_xor,DI_ftype_DIDISI,3)
4184 //
4185 def int_hexagon_S2_lsr_r_p_xor :
4186 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;
4187 //
4188 // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_xor,DI_ftype_DIDISI,3)
4189 //
4190 def int_hexagon_S2_lsl_r_p_xor :
4191 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;
4192 //
4193 // BUILTIN_INFO(HEXAGON.S2_asr_r_r_sat,SI_ftype_SISI,2)
4194 //
4195 def int_hexagon_S2_asr_r_r_sat :
4196 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;
4197 //
4198 // BUILTIN_INFO(HEXAGON.S2_asl_r_r_sat,SI_ftype_SISI,2)
4199 //
4200 def int_hexagon_S2_asl_r_r_sat :
4201 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_r_r_sat">;
4202 //
4203 // BUILTIN_INFO(HEXAGON.S2_asr_i_r,SI_ftype_SISI,2)
4204 //
4205 def int_hexagon_S2_asr_i_r :
4206 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r">;
4207 //
4208 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r,SI_ftype_SISI,2)
4209 //
4210 def int_hexagon_S2_lsr_i_r :
4211 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsr_i_r">;
4212 //
4213 // BUILTIN_INFO(HEXAGON.S2_asl_i_r,SI_ftype_SISI,2)
4214 //
4215 def int_hexagon_S2_asl_i_r :
4216 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_i_r">;
4217 //
4218 // BUILTIN_INFO(HEXAGON.S2_asr_i_p,DI_ftype_DISI,2)
4219 //
4220 def int_hexagon_S2_asr_i_p :
4221 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p">;
4222 //
4223 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p,DI_ftype_DISI,2)
4224 //
4225 def int_hexagon_S2_lsr_i_p :
4226 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_p">;
4227 //
4228 // BUILTIN_INFO(HEXAGON.S2_asl_i_p,DI_ftype_DISI,2)
4229 //
4230 def int_hexagon_S2_asl_i_p :
4231 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_p">;
4232 //
4233 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_acc,SI_ftype_SISISI,3)
4234 //
4235 def int_hexagon_S2_asr_i_r_acc :
4236 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_acc">;
4237 //
4238 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_acc,SI_ftype_SISISI,3)
4239 //
4240 def int_hexagon_S2_lsr_i_r_acc :
4241 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_acc">;
4242 //
4243 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_acc,SI_ftype_SISISI,3)
4244 //
4245 def int_hexagon_S2_asl_i_r_acc :
4246 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_acc">;
4247 //
4248 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_acc,DI_ftype_DIDISI,3)
4249 //
4250 def int_hexagon_S2_asr_i_p_acc :
4251 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_acc">;
4252 //
4253 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_acc,DI_ftype_DIDISI,3)
4254 //
4255 def int_hexagon_S2_lsr_i_p_acc :
4256 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_acc">;
4257 //
4258 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_acc,DI_ftype_DIDISI,3)
4259 //
4260 def int_hexagon_S2_asl_i_p_acc :
4261 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_acc">;
4262 //
4263 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_nac,SI_ftype_SISISI,3)
4264 //
4265 def int_hexagon_S2_asr_i_r_nac :
4266 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_nac">;
4267 //
4268 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_nac,SI_ftype_SISISI,3)
4269 //
4270 def int_hexagon_S2_lsr_i_r_nac :
4271 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_nac">;
4272 //
4273 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_nac,SI_ftype_SISISI,3)
4274 //
4275 def int_hexagon_S2_asl_i_r_nac :
4276 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_nac">;
4277 //
4278 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_nac,DI_ftype_DIDISI,3)
4279 //
4280 def int_hexagon_S2_asr_i_p_nac :
4281 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_nac">;
4282 //
4283 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_nac,DI_ftype_DIDISI,3)
4284 //
4285 def int_hexagon_S2_lsr_i_p_nac :
4286 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_nac">;
4287 //
4288 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_nac,DI_ftype_DIDISI,3)
4289 //
4290 def int_hexagon_S2_asl_i_p_nac :
4291 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_nac">;
4292 //
4293 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_xacc,SI_ftype_SISISI,3)
4294 //
4295 def int_hexagon_S2_lsr_i_r_xacc :
4296 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc">;
4297 //
4298 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_xacc,SI_ftype_SISISI,3)
4299 //
4300 def int_hexagon_S2_asl_i_r_xacc :
4301 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_xacc">;
4302 //
4303 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_xacc,DI_ftype_DIDISI,3)
4304 //
4305 def int_hexagon_S2_lsr_i_p_xacc :
4306 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc">;
4307 //
4308 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_xacc,DI_ftype_DIDISI,3)
4309 //
4310 def int_hexagon_S2_asl_i_p_xacc :
4311 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_xacc">;
4312 //
4313 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_and,SI_ftype_SISISI,3)
4314 //
4315 def int_hexagon_S2_asr_i_r_and :
4316 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_and">;
4317 //
4318 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_and,SI_ftype_SISISI,3)
4319 //
4320 def int_hexagon_S2_lsr_i_r_and :
4321 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_and">;
4322 //
4323 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_and,SI_ftype_SISISI,3)
4324 //
4325 def int_hexagon_S2_asl_i_r_and :
4326 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_and">;
4327 //
4328 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_or,SI_ftype_SISISI,3)
4329 //
4330 def int_hexagon_S2_asr_i_r_or :
4331 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_or">;
4332 //
4333 // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_or,SI_ftype_SISISI,3)
4334 //
4335 def int_hexagon_S2_lsr_i_r_or :
4336 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_or">;
4337 //
4338 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_or,SI_ftype_SISISI,3)
4339 //
4340 def int_hexagon_S2_asl_i_r_or :
4341 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_or">;
4342 //
4343 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_and,DI_ftype_DIDISI,3)
4344 //
4345 def int_hexagon_S2_asr_i_p_and :
4346 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_and">;
4347 //
4348 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_and,DI_ftype_DIDISI,3)
4349 //
4350 def int_hexagon_S2_lsr_i_p_and :
4351 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_and">;
4352 //
4353 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_and,DI_ftype_DIDISI,3)
4354 //
4355 def int_hexagon_S2_asl_i_p_and :
4356 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_and">;
4357 //
4358 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_or,DI_ftype_DIDISI,3)
4359 //
4360 def int_hexagon_S2_asr_i_p_or :
4361 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_or">;
4362 //
4363 // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_or,DI_ftype_DIDISI,3)
4364 //
4365 def int_hexagon_S2_lsr_i_p_or :
4366 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_or">;
4367 //
4368 // BUILTIN_INFO(HEXAGON.S2_asl_i_p_or,DI_ftype_DIDISI,3)
4369 //
4370 def int_hexagon_S2_asl_i_p_or :
4371 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_or">;
4372 //
4373 // BUILTIN_INFO(HEXAGON.S2_asl_i_r_sat,SI_ftype_SISI,2)
4374 //
4375 def int_hexagon_S2_asl_i_r_sat :
4376 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_i_r_sat">;
4377 //
4378 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd,SI_ftype_SISI,2)
4379 //
4380 def int_hexagon_S2_asr_i_r_rnd :
4381 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r_rnd">;
4382 //
4383 // BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd_goodsyntax,SI_ftype_SISI,2)
4384 //
4385 def int_hexagon_S2_asr_i_r_rnd_goodsyntax :
4386 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax">;
4387 //
4388 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_rnd,DI_ftype_DISI,2)
4389 //
4390 def int_hexagon_S2_asr_i_p_rnd :
4391 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p_rnd">;
4392 //
4393 // BUILTIN_INFO(HEXAGON.S2_asr_i_p_rnd_goodsyntax,DI_ftype_DISI,2)
4394 //
4395 def int_hexagon_S2_asr_i_p_rnd_goodsyntax :
4396 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax">;
4397 //
4398 // BUILTIN_INFO(HEXAGON.S4_lsli,SI_ftype_SISI,2)
4399 //
4400 def int_hexagon_S4_lsli :
4401 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_lsli">;
4402 //
4403 // BUILTIN_INFO(HEXAGON.S2_addasl_rrri,SI_ftype_SISISI,3)
4404 //
4405 def int_hexagon_S2_addasl_rrri :
4406 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_addasl_rrri">;
4407 //
4408 // BUILTIN_INFO(HEXAGON.S4_andi_asl_ri,SI_ftype_SISISI,3)
4409 //
4410 def int_hexagon_S4_andi_asl_ri :
4411 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_andi_asl_ri">;
4412 //
4413 // BUILTIN_INFO(HEXAGON.S4_ori_asl_ri,SI_ftype_SISISI,3)
4414 //
4415 def int_hexagon_S4_ori_asl_ri :
4416 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_ori_asl_ri">;
4417 //
4418 // BUILTIN_INFO(HEXAGON.S4_addi_asl_ri,SI_ftype_SISISI,3)
4419 //
4420 def int_hexagon_S4_addi_asl_ri :
4421 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addi_asl_ri">;
4422 //
4423 // BUILTIN_INFO(HEXAGON.S4_subi_asl_ri,SI_ftype_SISISI,3)
4424 //
4425 def int_hexagon_S4_subi_asl_ri :
4426 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subi_asl_ri">;
4427 //
4428 // BUILTIN_INFO(HEXAGON.S4_andi_lsr_ri,SI_ftype_SISISI,3)
4429 //
4430 def int_hexagon_S4_andi_lsr_ri :
4431 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_andi_lsr_ri">;
4432 //
4433 // BUILTIN_INFO(HEXAGON.S4_ori_lsr_ri,SI_ftype_SISISI,3)
4434 //
4435 def int_hexagon_S4_ori_lsr_ri :
4436 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_ori_lsr_ri">;
4437 //
4438 // BUILTIN_INFO(HEXAGON.S4_addi_lsr_ri,SI_ftype_SISISI,3)
4439 //
4440 def int_hexagon_S4_addi_lsr_ri :
4441 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addi_lsr_ri">;
4442 //
4443 // BUILTIN_INFO(HEXAGON.S4_subi_lsr_ri,SI_ftype_SISISI,3)
4444 //
4445 def int_hexagon_S4_subi_lsr_ri :
4446 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subi_lsr_ri">;
4447 //
4448 // BUILTIN_INFO(HEXAGON.S2_valignib,DI_ftype_DIDISI,3)
4449 //
4450 def int_hexagon_S2_valignib :
4451 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_valignib">;
4452 //
4453 // BUILTIN_INFO(HEXAGON.S2_valignrb,DI_ftype_DIDIQI,3)
4454 //
4455 def int_hexagon_S2_valignrb :
4456 Hexagon_di_didiqi_Intrinsic<"HEXAGON_S2_valignrb">;
4457 //
4458 // BUILTIN_INFO(HEXAGON.S2_vspliceib,DI_ftype_DIDISI,3)
4459 //
4460 def int_hexagon_S2_vspliceib :
4461 Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_vspliceib">;
4462 //
4463 // BUILTIN_INFO(HEXAGON.S2_vsplicerb,DI_ftype_DIDIQI,3)
4464 //
4465 def int_hexagon_S2_vsplicerb :
4466 Hexagon_di_didiqi_Intrinsic<"HEXAGON_S2_vsplicerb">;
4467 //
4468 // BUILTIN_INFO(HEXAGON.S2_vsplatrh,DI_ftype_SI,1)
4469 //
4470 def int_hexagon_S2_vsplatrh :
4471 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsplatrh">;
4472 //
4473 // BUILTIN_INFO(HEXAGON.S2_vsplatrb,SI_ftype_SI,1)
4474 //
4475 def int_hexagon_S2_vsplatrb :
4476 Hexagon_si_si_Intrinsic<"HEXAGON_S2_vsplatrb">;
4477 //
4478 // BUILTIN_INFO(HEXAGON.S2_insert,SI_ftype_SISISISI,4)
4479 //
4480 def int_hexagon_S2_insert :
4481 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_insert">;
4482 //
4483 // BUILTIN_INFO(HEXAGON.S2_tableidxb_goodsyntax,SI_ftype_SISISISI,4)
4484 //
4485 def int_hexagon_S2_tableidxb_goodsyntax :
4486 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">;
4487 //
4488 // BUILTIN_INFO(HEXAGON.S2_tableidxh_goodsyntax,SI_ftype_SISISISI,4)
4489 //
4490 def int_hexagon_S2_tableidxh_goodsyntax :
4491 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">;
4492 //
4493 // BUILTIN_INFO(HEXAGON.S2_tableidxw_goodsyntax,SI_ftype_SISISISI,4)
4494 //
4495 def int_hexagon_S2_tableidxw_goodsyntax :
4496 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">;
4497 //
4498 // BUILTIN_INFO(HEXAGON.S2_tableidxd_goodsyntax,SI_ftype_SISISISI,4)
4499 //
4500 def int_hexagon_S2_tableidxd_goodsyntax :
4501 Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">;
4502 //
4503 // BUILTIN_INFO(HEXAGON.A4_bitspliti,DI_ftype_SISI,2)
4504 //
4505 def int_hexagon_A4_bitspliti :
4506 Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_bitspliti">;
4507 //
4508 // BUILTIN_INFO(HEXAGON.A4_bitsplit,DI_ftype_SISI,2)
4509 //
4510 def int_hexagon_A4_bitsplit :
4511 Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_bitsplit">;
4512 //
4513 // BUILTIN_INFO(HEXAGON.S4_extract,SI_ftype_SISISI,3)
4514 //
4515 def int_hexagon_S4_extract :
4516 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_extract">;
4517 //
4518 // BUILTIN_INFO(HEXAGON.S2_extractu,SI_ftype_SISISI,3)
4519 //
4520 def int_hexagon_S2_extractu :
4521 Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_extractu">;
4522 //
4523 // BUILTIN_INFO(HEXAGON.S2_insertp,DI_ftype_DIDISISI,4)
4524 //
4525 def int_hexagon_S2_insertp :
4526 Hexagon_di_didisisi_Intrinsic<"HEXAGON_S2_insertp">;
4527 //
4528 // BUILTIN_INFO(HEXAGON.S4_extractp,DI_ftype_DISISI,3)
4529 //
4530 def int_hexagon_S4_extractp :
4531 Hexagon_di_disisi_Intrinsic<"HEXAGON_S4_extractp">;
4532 //
4533 // BUILTIN_INFO(HEXAGON.S2_extractup,DI_ftype_DISISI,3)
4534 //
4535 def int_hexagon_S2_extractup :
4536 Hexagon_di_disisi_Intrinsic<"HEXAGON_S2_extractup">;
4537 //
4538 // BUILTIN_INFO(HEXAGON.S2_insert_rp,SI_ftype_SISIDI,3)
4539 //
4540 def int_hexagon_S2_insert_rp :
4541 Hexagon_si_sisidi_Intrinsic<"HEXAGON_S2_insert_rp">;
4542 //
4543 // BUILTIN_INFO(HEXAGON.S4_extract_rp,SI_ftype_SIDI,2)
4544 //
4545 def int_hexagon_S4_extract_rp :
4546 Hexagon_si_sidi_Intrinsic<"HEXAGON_S4_extract_rp">;
4547 //
4548 // BUILTIN_INFO(HEXAGON.S2_extractu_rp,SI_ftype_SIDI,2)
4549 //
4550 def int_hexagon_S2_extractu_rp :
4551 Hexagon_si_sidi_Intrinsic<"HEXAGON_S2_extractu_rp">;
4552 //
4553 // BUILTIN_INFO(HEXAGON.S2_insertp_rp,DI_ftype_DIDIDI,3)
4554 //
4555 def int_hexagon_S2_insertp_rp :
4556 Hexagon_di_dididi_Intrinsic<"HEXAGON_S2_insertp_rp">;
4557 //
4558 // BUILTIN_INFO(HEXAGON.S4_extractp_rp,DI_ftype_DIDI,2)
4559 //
4560 def int_hexagon_S4_extractp_rp :
4561 Hexagon_di_didi_Intrinsic<"HEXAGON_S4_extractp_rp">;
4562 //
4563 // BUILTIN_INFO(HEXAGON.S2_extractup_rp,DI_ftype_DIDI,2)
4564 //
4565 def int_hexagon_S2_extractup_rp :
4566 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_extractup_rp">;
4567 //
4568 // BUILTIN_INFO(HEXAGON.S2_tstbit_i,QI_ftype_SISI,2)
4569 //
4570 def int_hexagon_S2_tstbit_i :
4571 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_tstbit_i">;
4572 //
4573 // BUILTIN_INFO(HEXAGON.S4_ntstbit_i,QI_ftype_SISI,2)
4574 //
4575 def int_hexagon_S4_ntstbit_i :
4576 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_ntstbit_i">;
4577 //
4578 // BUILTIN_INFO(HEXAGON.S2_setbit_i,SI_ftype_SISI,2)
4579 //
4580 def int_hexagon_S2_setbit_i :
4581 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_setbit_i">;
4582 //
4583 // BUILTIN_INFO(HEXAGON.S2_togglebit_i,SI_ftype_SISI,2)
4584 //
4585 def int_hexagon_S2_togglebit_i :
4586 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_togglebit_i">;
4587 //
4588 // BUILTIN_INFO(HEXAGON.S2_clrbit_i,SI_ftype_SISI,2)
4589 //
4590 def int_hexagon_S2_clrbit_i :
4591 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_i">;
4592 //
4593 // BUILTIN_INFO(HEXAGON.S2_tstbit_r,QI_ftype_SISI,2)
4594 //
4595 def int_hexagon_S2_tstbit_r :
4596 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_tstbit_r">;
4597 //
4598 // BUILTIN_INFO(HEXAGON.S4_ntstbit_r,QI_ftype_SISI,2)
4599 //
4600 def int_hexagon_S4_ntstbit_r :
4601 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_ntstbit_r">;
4602 //
4603 // BUILTIN_INFO(HEXAGON.S2_setbit_r,SI_ftype_SISI,2)
4604 //
4605 def int_hexagon_S2_setbit_r :
4606 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_setbit_r">;
4607 //
4608 // BUILTIN_INFO(HEXAGON.S2_togglebit_r,SI_ftype_SISI,2)
4609 //
4610 def int_hexagon_S2_togglebit_r :
4611 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_togglebit_r">;
4612 //
4613 // BUILTIN_INFO(HEXAGON.S2_clrbit_r,SI_ftype_SISI,2)
4614 //
4615 def int_hexagon_S2_clrbit_r :
4616 Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_r">;
4617 //
4618 // BUILTIN_INFO(HEXAGON.S2_asr_i_vh,DI_ftype_DISI,2)
4619 //
4620 def int_hexagon_S2_asr_i_vh :
4621 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_vh">;
4622 //
4623 // BUILTIN_INFO(HEXAGON.S2_lsr_i_vh,DI_ftype_DISI,2)
4624 //
4625 def int_hexagon_S2_lsr_i_vh :
4626 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_vh">;
4627 //
4628 // BUILTIN_INFO(HEXAGON.S2_asl_i_vh,DI_ftype_DISI,2)
4629 //
4630 def int_hexagon_S2_asl_i_vh :
4631 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_vh">;
4632 //
4633 // BUILTIN_INFO(HEXAGON.S2_asr_r_vh,DI_ftype_DISI,2)
4634 //
4635 def int_hexagon_S2_asr_r_vh :
4636 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_vh">;
4637 //
4638 // BUILTIN_INFO(HEXAGON.S5_asrhub_rnd_sat_goodsyntax,SI_ftype_DISI,2)
4639 //
4640 def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :
4641 Hexagon_si_disi_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax">;
4642 //
4643 // BUILTIN_INFO(HEXAGON.S5_asrhub_sat,SI_ftype_DISI,2)
4644 //
4645 def int_hexagon_S5_asrhub_sat :
4646 Hexagon_si_disi_Intrinsic<"HEXAGON_S5_asrhub_sat">;
4647 //
4648 // BUILTIN_INFO(HEXAGON.S5_vasrhrnd_goodsyntax,DI_ftype_DISI,2)
4649 //
4650 def int_hexagon_S5_vasrhrnd_goodsyntax :
4651 Hexagon_di_disi_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax">;
4652 //
4653 // BUILTIN_INFO(HEXAGON.S2_asl_r_vh,DI_ftype_DISI,2)
4654 //
4655 def int_hexagon_S2_asl_r_vh :
4656 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_vh">;
4657 //
4658 // BUILTIN_INFO(HEXAGON.S2_lsr_r_vh,DI_ftype_DISI,2)
4659 //
4660 def int_hexagon_S2_lsr_r_vh :
4661 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_vh">;
4662 //
4663 // BUILTIN_INFO(HEXAGON.S2_lsl_r_vh,DI_ftype_DISI,2)
4664 //
4665 def int_hexagon_S2_lsl_r_vh :
4666 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_vh">;
4667 //
4668 // BUILTIN_INFO(HEXAGON.S2_asr_i_vw,DI_ftype_DISI,2)
4669 //
4670 def int_hexagon_S2_asr_i_vw :
4671 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_vw">;
4672 //
4673 // BUILTIN_INFO(HEXAGON.S2_asr_i_svw_trun,SI_ftype_DISI,2)
4674 //
4675 def int_hexagon_S2_asr_i_svw_trun :
4676 Hexagon_si_disi_Intrinsic<"HEXAGON_S2_asr_i_svw_trun">;
4677 //
4678 // BUILTIN_INFO(HEXAGON.S2_asr_r_svw_trun,SI_ftype_DISI,2)
4679 //
4680 def int_hexagon_S2_asr_r_svw_trun :
4681 Hexagon_si_disi_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">;
4682 //
4683 // BUILTIN_INFO(HEXAGON.S2_lsr_i_vw,DI_ftype_DISI,2)
4684 //
4685 def int_hexagon_S2_lsr_i_vw :
4686 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_vw">;
4687 //
4688 // BUILTIN_INFO(HEXAGON.S2_asl_i_vw,DI_ftype_DISI,2)
4689 //
4690 def int_hexagon_S2_asl_i_vw :
4691 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_vw">;
4692 //
4693 // BUILTIN_INFO(HEXAGON.S2_asr_r_vw,DI_ftype_DISI,2)
4694 //
4695 def int_hexagon_S2_asr_r_vw :
4696 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_vw">;
4697 //
4698 // BUILTIN_INFO(HEXAGON.S2_asl_r_vw,DI_ftype_DISI,2)
4699 //
4700 def int_hexagon_S2_asl_r_vw :
4701 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_vw">;
4702 //
4703 // BUILTIN_INFO(HEXAGON.S2_lsr_r_vw,DI_ftype_DISI,2)
4704 //
4705 def int_hexagon_S2_lsr_r_vw :
4706 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_vw">;
4707 //
4708 // BUILTIN_INFO(HEXAGON.S2_lsl_r_vw,DI_ftype_DISI,2)
4709 //
4710 def int_hexagon_S2_lsl_r_vw :
4711 Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_vw">;
4712 //
4713 // BUILTIN_INFO(HEXAGON.S2_vrndpackwh,SI_ftype_DI,1)
4714 //
4715 def int_hexagon_S2_vrndpackwh :
4716 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vrndpackwh">;
4717 //
4718 // BUILTIN_INFO(HEXAGON.S2_vrndpackwhs,SI_ftype_DI,1)
4719 //
4720 def int_hexagon_S2_vrndpackwhs :
4721 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vrndpackwhs">;
4722 //
4723 // BUILTIN_INFO(HEXAGON.S2_vsxtbh,DI_ftype_SI,1)
4724 //
4725 def int_hexagon_S2_vsxtbh :
4726 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsxtbh">;
4727 //
4728 // BUILTIN_INFO(HEXAGON.S2_vzxtbh,DI_ftype_SI,1)
4729 //
4730 def int_hexagon_S2_vzxtbh :
4731 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vzxtbh">;
4732 //
4733 // BUILTIN_INFO(HEXAGON.S2_vsathub,SI_ftype_DI,1)
4734 //
4735 def int_hexagon_S2_vsathub :
4736 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsathub">;
4737 //
4738 // BUILTIN_INFO(HEXAGON.S2_svsathub,SI_ftype_SI,1)
4739 //
4740 def int_hexagon_S2_svsathub :
4741 Hexagon_si_si_Intrinsic<"HEXAGON_S2_svsathub">;
4742 //
4743 // BUILTIN_INFO(HEXAGON.S2_svsathb,SI_ftype_SI,1)
4744 //
4745 def int_hexagon_S2_svsathb :
4746 Hexagon_si_si_Intrinsic<"HEXAGON_S2_svsathb">;
4747 //
4748 // BUILTIN_INFO(HEXAGON.S2_vsathb,SI_ftype_DI,1)
4749 //
4750 def int_hexagon_S2_vsathb :
4751 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsathb">;
4752 //
4753 // BUILTIN_INFO(HEXAGON.S2_vtrunohb,SI_ftype_DI,1)
4754 //
4755 def int_hexagon_S2_vtrunohb :
4756 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vtrunohb">;
4757 //
4758 // BUILTIN_INFO(HEXAGON.S2_vtrunewh,DI_ftype_DIDI,2)
4759 //
4760 def int_hexagon_S2_vtrunewh :
4761 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_vtrunewh">;
4762 //
4763 // BUILTIN_INFO(HEXAGON.S2_vtrunowh,DI_ftype_DIDI,2)
4764 //
4765 def int_hexagon_S2_vtrunowh :
4766 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_vtrunowh">;
4767 //
4768 // BUILTIN_INFO(HEXAGON.S2_vtrunehb,SI_ftype_DI,1)
4769 //
4770 def int_hexagon_S2_vtrunehb :
4771 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vtrunehb">;
4772 //
4773 // BUILTIN_INFO(HEXAGON.S2_vsxthw,DI_ftype_SI,1)
4774 //
4775 def int_hexagon_S2_vsxthw :
4776 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsxthw">;
4777 //
4778 // BUILTIN_INFO(HEXAGON.S2_vzxthw,DI_ftype_SI,1)
4779 //
4780 def int_hexagon_S2_vzxthw :
4781 Hexagon_di_si_Intrinsic<"HEXAGON_S2_vzxthw">;
4782 //
4783 // BUILTIN_INFO(HEXAGON.S2_vsatwh,SI_ftype_DI,1)
4784 //
4785 def int_hexagon_S2_vsatwh :
4786 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsatwh">;
4787 //
4788 // BUILTIN_INFO(HEXAGON.S2_vsatwuh,SI_ftype_DI,1)
4789 //
4790 def int_hexagon_S2_vsatwuh :
4791 Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsatwuh">;
4792 //
4793 // BUILTIN_INFO(HEXAGON.S2_packhl,DI_ftype_SISI,2)
4794 //
4795 def int_hexagon_S2_packhl :
4796 Hexagon_di_sisi_Intrinsic<"HEXAGON_S2_packhl">;
4797 //
4798 // BUILTIN_INFO(HEXAGON.A2_swiz,SI_ftype_SI,1)
4799 //
4800 def int_hexagon_A2_swiz :
4801 Hexagon_si_si_Intrinsic<"HEXAGON_A2_swiz">;
4802 //
4803 // BUILTIN_INFO(HEXAGON.S2_vsathub_nopack,DI_ftype_DI,1)
4804 //
4805 def int_hexagon_S2_vsathub_nopack :
4806 Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsathub_nopack">;
4807 //
4808 // BUILTIN_INFO(HEXAGON.S2_vsathb_nopack,DI_ftype_DI,1)
4809 //
4810 def int_hexagon_S2_vsathb_nopack :
4811 Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsathb_nopack">;
4812 //
4813 // BUILTIN_INFO(HEXAGON.S2_vsatwh_nopack,DI_ftype_DI,1)
4814 //
4815 def int_hexagon_S2_vsatwh_nopack :
4816 Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;
4817 //
4818 // BUILTIN_INFO(HEXAGON.S2_vsatwuh_nopack,DI_ftype_DI,1)
4819 //
4820 def int_hexagon_S2_vsatwuh_nopack :
4821 Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">;
4822 //
4823 // BUILTIN_INFO(HEXAGON.S2_shuffob,DI_ftype_DIDI,2)
4824 //
4825 def int_hexagon_S2_shuffob :
4826 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffob">;
4827 //
4828 // BUILTIN_INFO(HEXAGON.S2_shuffeb,DI_ftype_DIDI,2)
4829 //
4830 def int_hexagon_S2_shuffeb :
4831 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffeb">;
4832 //
4833 // BUILTIN_INFO(HEXAGON.S2_shuffoh,DI_ftype_DIDI,2)
4834 //
4835 def int_hexagon_S2_shuffoh :
4836 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffoh">;
4837 //
4838 // BUILTIN_INFO(HEXAGON.S2_shuffeh,DI_ftype_DIDI,2)
4839 //
4840 def int_hexagon_S2_shuffeh :
4841 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffeh">;
4842 //
4843 // BUILTIN_INFO(HEXAGON.S5_popcountp,SI_ftype_DI,1)
4844 //
4845 def int_hexagon_S5_popcountp :
4846 Hexagon_si_di_Intrinsic<"HEXAGON_S5_popcountp">;
4847 //
4848 // BUILTIN_INFO(HEXAGON.S4_parity,SI_ftype_SISI,2)
4849 //
4850 def int_hexagon_S4_parity :
4851 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_parity">;
4852 //
4853 // BUILTIN_INFO(HEXAGON.S2_parityp,SI_ftype_DIDI,2)
4854 //
4855 def int_hexagon_S2_parityp :
4856 Hexagon_si_didi_Intrinsic<"HEXAGON_S2_parityp">;
4857 //
4858 // BUILTIN_INFO(HEXAGON.S2_lfsp,DI_ftype_DIDI,2)
4859 //
4860 def int_hexagon_S2_lfsp :
4861 Hexagon_di_didi_Intrinsic<"HEXAGON_S2_lfsp">;
4862 //
4863 // BUILTIN_INFO(HEXAGON.S2_clbnorm,SI_ftype_SI,1)
4864 //
4865 def int_hexagon_S2_clbnorm :
4866 Hexagon_si_si_Intrinsic<"HEXAGON_S2_clbnorm">;
4867 //
4868 // BUILTIN_INFO(HEXAGON.S4_clbaddi,SI_ftype_SISI,2)
4869 //
4870 def int_hexagon_S4_clbaddi :
4871 Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_clbaddi">;
4872 //
4873 // BUILTIN_INFO(HEXAGON.S4_clbpnorm,SI_ftype_DI,1)
4874 //
4875 def int_hexagon_S4_clbpnorm :
4876 Hexagon_si_di_Intrinsic<"HEXAGON_S4_clbpnorm">;
4877 //
4878 // BUILTIN_INFO(HEXAGON.S4_clbpaddi,SI_ftype_DISI,2)
4879 //
4880 def int_hexagon_S4_clbpaddi :
4881 Hexagon_si_disi_Intrinsic<"HEXAGON_S4_clbpaddi">;
4882 //
4883 // BUILTIN_INFO(HEXAGON.S2_clb,SI_ftype_SI,1)
4884 //
4885 def int_hexagon_S2_clb :
4886 Hexagon_si_si_Intrinsic<"HEXAGON_S2_clb">;
4887 //
4888 // BUILTIN_INFO(HEXAGON.S2_cl0,SI_ftype_SI,1)
4889 //
4890 def int_hexagon_S2_cl0 :
4891 Hexagon_si_si_Intrinsic<"HEXAGON_S2_cl0">;
4892 //
4893 // BUILTIN_INFO(HEXAGON.S2_cl1,SI_ftype_SI,1)
4894 //
4895 def int_hexagon_S2_cl1 :
4896 Hexagon_si_si_Intrinsic<"HEXAGON_S2_cl1">;
4897 //
4898 // BUILTIN_INFO(HEXAGON.S2_clbp,SI_ftype_DI,1)
4899 //
4900 def int_hexagon_S2_clbp :
4901 Hexagon_si_di_Intrinsic<"HEXAGON_S2_clbp">;
4902 //
4903 // BUILTIN_INFO(HEXAGON.S2_cl0p,SI_ftype_DI,1)
4904 //
4905 def int_hexagon_S2_cl0p :
4906 Hexagon_si_di_Intrinsic<"HEXAGON_S2_cl0p">;
4907 //
4908 // BUILTIN_INFO(HEXAGON.S2_cl1p,SI_ftype_DI,1)
4909 //
4910 def int_hexagon_S2_cl1p :
4911 Hexagon_si_di_Intrinsic<"HEXAGON_S2_cl1p">;
4912 //
4913 // BUILTIN_INFO(HEXAGON.S2_brev,SI_ftype_SI,1)
4914 //
4915 def int_hexagon_S2_brev :
4916 Hexagon_si_si_Intrinsic<"HEXAGON_S2_brev">;
4917 //
4918 // BUILTIN_INFO(HEXAGON.S2_brevp,DI_ftype_DI,1)
4919 //
4920 def int_hexagon_S2_brevp :
4921 Hexagon_di_di_Intrinsic<"HEXAGON_S2_brevp">;
4922 //
4923 // BUILTIN_INFO(HEXAGON.S2_ct0,SI_ftype_SI,1)
4924 //
4925 def int_hexagon_S2_ct0 :
4926 Hexagon_si_si_Intrinsic<"HEXAGON_S2_ct0">;
4927 //
4928 // BUILTIN_INFO(HEXAGON.S2_ct1,SI_ftype_SI,1)
4929 //
4930 def int_hexagon_S2_ct1 :
4931 Hexagon_si_si_Intrinsic<"HEXAGON_S2_ct1">;
4932 //
4933 // BUILTIN_INFO(HEXAGON.S2_ct0p,SI_ftype_DI,1)
4934 //
4935 def int_hexagon_S2_ct0p :
4936 Hexagon_si_di_Intrinsic<"HEXAGON_S2_ct0p">;
4937 //
4938 // BUILTIN_INFO(HEXAGON.S2_ct1p,SI_ftype_DI,1)
4939 //
4940 def int_hexagon_S2_ct1p :
4941 Hexagon_si_di_Intrinsic<"HEXAGON_S2_ct1p">;
4942 //
4943 // BUILTIN_INFO(HEXAGON.S2_interleave,DI_ftype_DI,1)
4944 //
4945 def int_hexagon_S2_interleave :
4946 Hexagon_di_di_Intrinsic<"HEXAGON_S2_interleave">;
4947 //
4948 // BUILTIN_INFO(HEXAGON.S2_deinterleave,DI_ftype_DI,1)
4949 //
4950 def int_hexagon_S2_deinterleave :
4951 Hexagon_di_di_Intrinsic<"HEXAGON_S2_deinterleave">;
4952
4953 //
4954 // BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1)
4955 //
4956 def int_hexagon_prefetch :
4957 Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>;
4958 def int_hexagon_Y2_dccleana :
4959 Hexagon_Intrinsic<"HEXAGON_Y2_dccleana", [], [llvm_ptr_ty], []>;
4960 def int_hexagon_Y2_dccleaninva :
4961 Hexagon_Intrinsic<"HEXAGON_Y2_dccleaninva", [], [llvm_ptr_ty], []>;
4962 def int_hexagon_Y2_dcinva :
4963 Hexagon_Intrinsic<"HEXAGON_Y2_dcinva", [], [llvm_ptr_ty], []>;
4964 def int_hexagon_Y2_dczeroa :
4965 Hexagon_Intrinsic<"HEXAGON_Y2_dczeroa", [], [llvm_ptr_ty],
4966       [IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects]>;
4967 def int_hexagon_Y4_l2fetch :
4968 Hexagon_Intrinsic<"HEXAGON_Y4_l2fetch", [], [llvm_ptr_ty, llvm_i32_ty], []>;
4969 def int_hexagon_Y5_l2fetch :
4970 Hexagon_Intrinsic<"HEXAGON_Y5_l2fetch", [], [llvm_ptr_ty, llvm_i64_ty], []>;
4971
4972 def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;
4973 def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
4974
4975 // Mark locked loads as read/write to prevent any accidental reordering.
4976 def int_hexagon_L2_loadw_locked :
4977 Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
4978       [IntrArgMemOnly, NoCapture<0>]>;
4979 def int_hexagon_L4_loadd_locked :
4980 Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
4981       [IntrArgMemOnly, NoCapture<0>]>;
4982
4983 def int_hexagon_S2_storew_locked :
4984 Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
4985       [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<0>]>;
4986 def int_hexagon_S4_stored_locked :
4987 Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
4988       [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<0>]>;
4989
4990 // V60
4991
4992 class Hexagon_v2048v2048_Intrinsic_T<string GCCIntSuffix>
4993  : Hexagon_Intrinsic<GCCIntSuffix,
4994                           [llvm_v64i32_ty], [llvm_v64i32_ty],
4995                           [IntrNoMem]>;
4996
4997 // tag : V6_hi_W
4998 // tag : V6_lo_W
4999 class Hexagon_v512v1024_Intrinsic_T<string GCCIntSuffix>
5000  : Hexagon_Intrinsic<GCCIntSuffix,
5001                           [llvm_v16i32_ty], [llvm_v32i32_ty],
5002                           [IntrNoMem]>;
5003
5004 // tag : V6_hi_W_128B
5005 // tag : V6_lo_W_128B
5006 class Hexagon_v1024v2048_Intrinsic_T<string GCCIntSuffix>
5007  : Hexagon_Intrinsic<GCCIntSuffix,
5008                           [llvm_v32i32_ty], [llvm_v64i32_ty],
5009                           [IntrNoMem]>;
5010
5011 class Hexagon_v1024v1024_Intrinsic_T<string GCCIntSuffix>
5012  : Hexagon_Intrinsic<GCCIntSuffix,
5013                           [llvm_v32i32_ty], [llvm_v32i32_ty],
5014                           [IntrNoMem]>;
5015
5016 // BUILTIN_INFO(HEXAGON.V6_hi_W,VI_ftype_VI,1)
5017 // tag : V6_hi
5018 def int_hexagon_V6_hi :
5019 Hexagon_v512v1024_Intrinsic_T<"HEXAGON_V6_hi">;
5020
5021 // BUILTIN_INFO(HEXAGON.V6_lo_W,VI_ftype_VI,1)
5022 // tag : V6_lo
5023 def int_hexagon_V6_lo :
5024 Hexagon_v512v1024_Intrinsic_T<"HEXAGON_V6_lo">;
5025
5026 // BUILTIN_INFO(HEXAGON.V6_hi_W,VI_ftype_VI,1)
5027 // tag : V6_hi_128B
5028 def int_hexagon_V6_hi_128B :
5029 Hexagon_v1024v2048_Intrinsic_T<"HEXAGON_V6_hi_128B">;
5030
5031 // BUILTIN_INFO(HEXAGON.V6_lo_W,VI_ftype_VI,1)
5032 // tag : V6_lo_128B
5033 def int_hexagon_V6_lo_128B :
5034 Hexagon_v1024v2048_Intrinsic_T<"HEXAGON_V6_lo_128B">;
5035
5036 // BUILTIN_INFO(HEXAGON.V6_vassignp,VI_ftype_VI,1)
5037 // tag : V6_vassignp
5038 def int_hexagon_V6_vassignp :
5039 Hexagon_v1024v1024_Intrinsic_T<"HEXAGON_V6_vassignp">;
5040
5041 // BUILTIN_INFO(HEXAGON.V6_vassignp,VI_ftype_VI,1)
5042 // tag : V6_vassignp_128B
5043 def int_hexagon_V6_vassignp_128B :
5044 Hexagon_v2048v2048_Intrinsic_T<"HEXAGON_V6_vassignp_128B">;
5045
5046
5047 //
5048 // Hexagon_iii_Intrinsic<string GCCIntSuffix>
5049 // tag : S6_rol_i_r
5050 class Hexagon_iii_Intrinsic<string GCCIntSuffix>
5051  : Hexagon_Intrinsic<GCCIntSuffix,
5052                           [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],
5053                           [IntrNoMem]>;
5054
5055 //
5056 // Hexagon_LLiLLii_Intrinsic<string GCCIntSuffix>
5057 // tag : S6_rol_i_p
5058 class Hexagon_LLiLLii_Intrinsic<string GCCIntSuffix>
5059  : Hexagon_Intrinsic<GCCIntSuffix,
5060                           [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],
5061                           [IntrNoMem]>;
5062
5063 //
5064 // Hexagon_iiii_Intrinsic<string GCCIntSuffix>
5065 // tag : S6_rol_i_r_acc
5066 class Hexagon_iiii_Intrinsic<string GCCIntSuffix>
5067  : Hexagon_Intrinsic<GCCIntSuffix,
5068                           [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
5069                           [IntrNoMem]>;
5070
5071 //
5072 // Hexagon_LLiLLiLLii_Intrinsic<string GCCIntSuffix>
5073 // tag : S6_rol_i_p_acc
5074 class Hexagon_LLiLLiLLii_Intrinsic<string GCCIntSuffix>
5075  : Hexagon_Intrinsic<GCCIntSuffix,
5076                           [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
5077                           [IntrNoMem]>;
5078
5079 //
5080 // Hexagon_v512v512v512i_Intrinsic<string GCCIntSuffix>
5081 // tag : V6_valignb
5082 class Hexagon_v512v512v512i_Intrinsic<string GCCIntSuffix>
5083  : Hexagon_Intrinsic<GCCIntSuffix,
5084                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5085                           [IntrNoMem]>;
5086
5087 //
5088 // Hexagon_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
5089 // tag : V6_valignb_128B
5090 class Hexagon_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
5091  : Hexagon_Intrinsic<GCCIntSuffix,
5092                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5093                           [IntrNoMem]>;
5094
5095 //
5096 // Hexagon_v512v512i_Intrinsic<string GCCIntSuffix>
5097 // tag : V6_vror
5098 class Hexagon_v512v512i_Intrinsic<string GCCIntSuffix>
5099  : Hexagon_Intrinsic<GCCIntSuffix,
5100                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
5101                           [IntrNoMem]>;
5102
5103 //
5104 // Hexagon_v1024v1024i_Intrinsic<string GCCIntSuffix>
5105 // tag : V6_vror_128B
5106 class Hexagon_v1024v1024i_Intrinsic<string GCCIntSuffix>
5107  : Hexagon_Intrinsic<GCCIntSuffix,
5108                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
5109                           [IntrNoMem]>;
5110
5111 //
5112 // Hexagon_v1024v512_Intrinsic<string GCCIntSuffix>
5113 // tag : V6_vunpackub
5114 class Hexagon_v1024v512_Intrinsic<string GCCIntSuffix>
5115  : Hexagon_Intrinsic<GCCIntSuffix,
5116                           [llvm_v32i32_ty], [llvm_v16i32_ty],
5117                           [IntrNoMem]>;
5118
5119 //
5120 // Hexagon_v2048v1024_Intrinsic<string GCCIntSuffix>
5121 // tag : V6_vunpackub_128B
5122 class Hexagon_v2048v1024_Intrinsic<string GCCIntSuffix>
5123  : Hexagon_Intrinsic<GCCIntSuffix,
5124                           [llvm_v64i32_ty], [llvm_v32i32_ty],
5125                           [IntrNoMem]>;
5126
5127 //
5128 // Hexagon_v1024v1024v512_Intrinsic<string GCCIntSuffix>
5129 // tag : V6_vunpackob
5130 class Hexagon_v1024v1024v512_Intrinsic<string GCCIntSuffix>
5131  : Hexagon_Intrinsic<GCCIntSuffix,
5132                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],
5133                           [IntrNoMem]>;
5134
5135 //
5136 // Hexagon_v2048v2048v1024_Intrinsic<string GCCIntSuffix>
5137 // tag : V6_vunpackob_128B
5138 class Hexagon_v2048v2048v1024_Intrinsic<string GCCIntSuffix>
5139  : Hexagon_Intrinsic<GCCIntSuffix,
5140                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],
5141                           [IntrNoMem]>;
5142
5143 //
5144 // Hexagon_v512v512v512_Intrinsic<string GCCIntSuffix>
5145 // tag : V6_vpackeb
5146 class Hexagon_v512v512v512_Intrinsic<string GCCIntSuffix>
5147  : Hexagon_Intrinsic<GCCIntSuffix,
5148                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
5149                           [IntrNoMem]>;
5150
5151 //
5152 // Hexagon_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
5153 // tag : V6_vpackeb_128B
5154 class Hexagon_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
5155  : Hexagon_Intrinsic<GCCIntSuffix,
5156                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
5157                           [IntrNoMem]>;
5158
5159 //
5160 // Hexagon_v2048v2048i_Intrinsic<string GCCIntSuffix>
5161 // tag : V6_vdmpybus_dv_128B
5162 class Hexagon_v2048v2048i_Intrinsic<string GCCIntSuffix>
5163  : Hexagon_Intrinsic<GCCIntSuffix,
5164                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
5165                           [IntrNoMem]>;
5166
5167 //
5168 // Hexagon_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
5169 // tag : V6_vdmpybus_dv_acc_128B
5170 class Hexagon_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
5171  : Hexagon_Intrinsic<GCCIntSuffix,
5172                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
5173                           [IntrNoMem]>;
5174
5175 //
5176 // Hexagon_v512v512v512v512_Intrinsic<string GCCIntSuffix>
5177 // tag : V6_vdmpyhvsat_acc
5178 class Hexagon_v512v512v512v512_Intrinsic<string GCCIntSuffix>
5179  : Hexagon_Intrinsic<GCCIntSuffix,
5180                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5181                           [IntrNoMem]>;
5182
5183 //
5184 // Hexagon_v1024v1024v1024v1024_Intrinsic<string GCCIntSuffix>
5185 // tag : V6_vdmpyhvsat_acc_128B
5186 class Hexagon_v1024v1024v1024v1024_Intrinsic<string GCCIntSuffix>
5187  : Hexagon_Intrinsic<GCCIntSuffix,
5188                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5189                           [IntrNoMem]>;
5190
5191 //
5192 // Hexagon_v512v1024i_Intrinsic<string GCCIntSuffix>
5193 // tag : V6_vdmpyhisat
5194 class Hexagon_v512v1024i_Intrinsic<string GCCIntSuffix>
5195  : Hexagon_Intrinsic<GCCIntSuffix,
5196                           [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
5197                           [IntrNoMem]>;
5198
5199 //
5200 // Hexagon_v1024v2048i_Intrinsic<string GCCIntSuffix>
5201 // tag : V6_vdmpyhisat_128B
5202 class Hexagon_v1024v2048i_Intrinsic<string GCCIntSuffix>
5203  : Hexagon_Intrinsic<GCCIntSuffix,
5204                           [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
5205                           [IntrNoMem]>;
5206
5207 //
5208 // Hexagon_v512v512v1024i_Intrinsic<string GCCIntSuffix>
5209 // tag : V6_vdmpyhisat_acc
5210 class Hexagon_v512v512v1024i_Intrinsic<string GCCIntSuffix>
5211  : Hexagon_Intrinsic<GCCIntSuffix,
5212                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5213                           [IntrNoMem]>;
5214
5215 //
5216 // Hexagon_v1024v1024v2048i_Intrinsic<string GCCIntSuffix>
5217 // tag : V6_vdmpyhisat_acc_128B
5218 class Hexagon_v1024v1024v2048i_Intrinsic<string GCCIntSuffix>
5219  : Hexagon_Intrinsic<GCCIntSuffix,
5220                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty],
5221                           [IntrNoMem]>;
5222
5223 //
5224 // Hexagon_v1024v1024ii_Intrinsic<string GCCIntSuffix>
5225 // tag : V6_vrmpyubi
5226 class Hexagon_v1024v1024ii_Intrinsic<string GCCIntSuffix>
5227  : Hexagon_Intrinsic<GCCIntSuffix,
5228                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
5229                           [IntrNoMem]>;
5230
5231 //
5232 // Hexagon_v2048v2048ii_Intrinsic<string GCCIntSuffix>
5233 // tag : V6_vrmpyubi_128B
5234 class Hexagon_v2048v2048ii_Intrinsic<string GCCIntSuffix>
5235  : Hexagon_Intrinsic<GCCIntSuffix,
5236                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
5237                           [IntrNoMem]>;
5238
5239 //
5240 // Hexagon_v1024v1024v1024ii_Intrinsic<string GCCIntSuffix>
5241 // tag : V6_vrmpyubi_acc
5242 class Hexagon_v1024v1024v1024ii_Intrinsic<string GCCIntSuffix>
5243  : Hexagon_Intrinsic<GCCIntSuffix,
5244                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
5245                           [IntrNoMem]>;
5246
5247 //
5248 // Hexagon_v2048v2048v2048ii_Intrinsic<string GCCIntSuffix>
5249 // tag : V6_vrmpyubi_acc_128B
5250 class Hexagon_v2048v2048v2048ii_Intrinsic<string GCCIntSuffix>
5251  : Hexagon_Intrinsic<GCCIntSuffix,
5252                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
5253                           [IntrNoMem]>;
5254
5255 //
5256 // Hexagon_v2048v2048v2048_Intrinsic<string GCCIntSuffix>
5257 // tag : V6_vaddb_dv_128B
5258 class Hexagon_v2048v2048v2048_Intrinsic<string GCCIntSuffix>
5259  : Hexagon_Intrinsic<GCCIntSuffix,
5260                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
5261                           [IntrNoMem]>;
5262
5263 //
5264 // Hexagon_v1024v512v512_Intrinsic<string GCCIntSuffix>
5265 // tag : V6_vaddubh
5266 class Hexagon_v1024v512v512_Intrinsic<string GCCIntSuffix>
5267  : Hexagon_Intrinsic<GCCIntSuffix,
5268                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
5269                           [IntrNoMem]>;
5270
5271 //
5272 // Hexagon_v2048v1024v1024_Intrinsic<string GCCIntSuffix>
5273 // tag : V6_vaddubh_128B
5274 class Hexagon_v2048v1024v1024_Intrinsic<string GCCIntSuffix>
5275  : Hexagon_Intrinsic<GCCIntSuffix,
5276                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
5277                           [IntrNoMem]>;
5278
5279 //
5280 // Hexagon_v512_Intrinsic<string GCCIntSuffix>
5281 // tag : V6_vd0
5282 class Hexagon_v512_Intrinsic<string GCCIntSuffix>
5283  : Hexagon_Intrinsic<GCCIntSuffix,
5284                           [llvm_v16i32_ty], [],
5285                           [IntrNoMem]>;
5286
5287 //
5288 // Hexagon_v1024_Intrinsic<string GCCIntSuffix>
5289 // tag : V6_vd0_128B
5290 class Hexagon_v1024_Intrinsic<string GCCIntSuffix>
5291  : Hexagon_Intrinsic<GCCIntSuffix,
5292                           [llvm_v32i32_ty], [],
5293                           [IntrNoMem]>;
5294
5295 //
5296 // Hexagon_v512v64iv512v512_Intrinsic<string GCCIntSuffix>
5297 // tag : V6_vaddbq
5298 class Hexagon_v512v64iv512v512_Intrinsic<string GCCIntSuffix>
5299  : Hexagon_Intrinsic<GCCIntSuffix,
5300                           [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5301                           [IntrNoMem]>;
5302
5303 //
5304 // Hexagon_v1024v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5305 // tag : V6_vaddbq_128B
5306 class Hexagon_v1024v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5307  : Hexagon_Intrinsic<GCCIntSuffix,
5308                           [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5309                           [IntrNoMem]>;
5310
5311 //
5312 // Hexagon_v512v512_Intrinsic<string GCCIntSuffix>
5313 // tag : V6_vabsh
5314 class Hexagon_v512v512_Intrinsic<string GCCIntSuffix>
5315  : Hexagon_Intrinsic<GCCIntSuffix,
5316                           [llvm_v16i32_ty], [llvm_v16i32_ty],
5317                           [IntrNoMem]>;
5318
5319 //
5320 // Hexagon_v1024v1024_Intrinsic<string GCCIntSuffix>
5321 // tag : V6_vabsh_128B
5322 class Hexagon_v1024v1024_Intrinsic<string GCCIntSuffix>
5323  : Hexagon_Intrinsic<GCCIntSuffix,
5324                           [llvm_v32i32_ty], [llvm_v32i32_ty],
5325                           [IntrNoMem]>;
5326
5327 //
5328 // Hexagon_v1024v1024v512v512_Intrinsic<string GCCIntSuffix>
5329 // tag : V6_vmpybv_acc
5330 class Hexagon_v1024v1024v512v512_Intrinsic<string GCCIntSuffix>
5331  : Hexagon_Intrinsic<GCCIntSuffix,
5332                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5333                           [IntrNoMem]>;
5334
5335 //
5336 // Hexagon_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix>
5337 // tag : V6_vmpybv_acc_128B
5338 class Hexagon_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix>
5339  : Hexagon_Intrinsic<GCCIntSuffix,
5340                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5341                           [IntrNoMem]>;
5342
5343 //
5344 // Hexagon_v1024v512i_Intrinsic<string GCCIntSuffix>
5345 // tag : V6_vmpyub
5346 class Hexagon_v1024v512i_Intrinsic<string GCCIntSuffix>
5347  : Hexagon_Intrinsic<GCCIntSuffix,
5348                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
5349                           [IntrNoMem]>;
5350
5351 //
5352 // Hexagon_v2048v1024i_Intrinsic<string GCCIntSuffix>
5353 // tag : V6_vmpyub_128B
5354 class Hexagon_v2048v1024i_Intrinsic<string GCCIntSuffix>
5355  : Hexagon_Intrinsic<GCCIntSuffix,
5356                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
5357                           [IntrNoMem]>;
5358
5359 //
5360 // Hexagon_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
5361 // tag : V6_vmpyub_acc
5362 class Hexagon_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
5363  : Hexagon_Intrinsic<GCCIntSuffix,
5364                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5365                           [IntrNoMem]>;
5366
5367 //
5368 // Hexagon_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
5369 // tag : V6_vmpyub_acc_128B
5370 class Hexagon_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
5371  : Hexagon_Intrinsic<GCCIntSuffix,
5372                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5373                           [IntrNoMem]>;
5374
5375 //
5376 // Hexagon_v512v64ii_Intrinsic<string GCCIntSuffix>
5377 // tag : V6_vandqrt
5378 class Hexagon_v512v64ii_Intrinsic<string GCCIntSuffix>
5379  : Hexagon_Intrinsic<GCCIntSuffix,
5380                           [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],
5381                           [IntrNoMem]>;
5382
5383 //
5384 // Hexagon_v1024v128ii_Intrinsic<string GCCIntSuffix>
5385 // tag : V6_vandqrt_128B
5386 class Hexagon_v1024v128ii_Intrinsic<string GCCIntSuffix>
5387  : Hexagon_Intrinsic<GCCIntSuffix,
5388                           [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],
5389                           [IntrNoMem]>;
5390
5391 //
5392 // Hexagon_v512v512v64ii_Intrinsic<string GCCIntSuffix>
5393 // tag : V6_vandqrt_acc
5394 class Hexagon_v512v512v64ii_Intrinsic<string GCCIntSuffix>
5395  : Hexagon_Intrinsic<GCCIntSuffix,
5396                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],
5397                           [IntrNoMem]>;
5398
5399 //
5400 // Hexagon_v1024v1024v128ii_Intrinsic<string GCCIntSuffix>
5401 // tag : V6_vandqrt_acc_128B
5402 class Hexagon_v1024v1024v128ii_Intrinsic<string GCCIntSuffix>
5403  : Hexagon_Intrinsic<GCCIntSuffix,
5404                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],
5405                           [IntrNoMem]>;
5406
5407 //
5408 // Hexagon_v64iv512i_Intrinsic<string GCCIntSuffix>
5409 // tag : V6_vandvrt
5410 class Hexagon_v64iv512i_Intrinsic<string GCCIntSuffix>
5411  : Hexagon_Intrinsic<GCCIntSuffix,
5412                           [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty],
5413                           [IntrNoMem]>;
5414
5415 //
5416 // Hexagon_v128iv1024i_Intrinsic<string GCCIntSuffix>
5417 // tag : V6_vandvrt_128B
5418 class Hexagon_v128iv1024i_Intrinsic<string GCCIntSuffix>
5419  : Hexagon_Intrinsic<GCCIntSuffix,
5420                           [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty],
5421                           [IntrNoMem]>;
5422
5423 //
5424 // Hexagon_v64iv64iv512i_Intrinsic<string GCCIntSuffix>
5425 // tag : V6_vandvrt_acc
5426 class Hexagon_v64iv64iv512i_Intrinsic<string GCCIntSuffix>
5427  : Hexagon_Intrinsic<GCCIntSuffix,
5428                           [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty],
5429                           [IntrNoMem]>;
5430
5431 //
5432 // Hexagon_v128iv128iv1024i_Intrinsic<string GCCIntSuffix>
5433 // tag : V6_vandvrt_acc_128B
5434 class Hexagon_v128iv128iv1024i_Intrinsic<string GCCIntSuffix>
5435  : Hexagon_Intrinsic<GCCIntSuffix,
5436                           [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty],
5437                           [IntrNoMem]>;
5438
5439 //
5440 // Hexagon_v64iv512v512_Intrinsic<string GCCIntSuffix>
5441 // tag : V6_vgtw
5442 class Hexagon_v64iv512v512_Intrinsic<string GCCIntSuffix>
5443  : Hexagon_Intrinsic<GCCIntSuffix,
5444                           [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
5445                           [IntrNoMem]>;
5446
5447 //
5448 // Hexagon_v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5449 // tag : V6_vgtw_128B
5450 class Hexagon_v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5451  : Hexagon_Intrinsic<GCCIntSuffix,
5452                           [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
5453                           [IntrNoMem]>;
5454
5455 //
5456 // Hexagon_v64iv64iv512v512_Intrinsic<string GCCIntSuffix>
5457 // tag : V6_vgtw_and
5458 class Hexagon_v64iv64iv512v512_Intrinsic<string GCCIntSuffix>
5459  : Hexagon_Intrinsic<GCCIntSuffix,
5460                           [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5461                           [IntrNoMem]>;
5462
5463 //
5464 // Hexagon_v128iv128iv1024v1024_Intrinsic<string GCCIntSuffix>
5465 // tag : V6_vgtw_and_128B
5466 class Hexagon_v128iv128iv1024v1024_Intrinsic<string GCCIntSuffix>
5467  : Hexagon_Intrinsic<GCCIntSuffix,
5468                           [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5469                           [IntrNoMem]>;
5470
5471 //
5472 // Hexagon_v64iv64iv64i_Intrinsic<string GCCIntSuffix>
5473 // tag : V6_pred_or
5474 class Hexagon_v64iv64iv64i_Intrinsic<string GCCIntSuffix>
5475  : Hexagon_Intrinsic<GCCIntSuffix,
5476                           [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],
5477                           [IntrNoMem]>;
5478
5479 //
5480 // Hexagon_v128iv128iv128i_Intrinsic<string GCCIntSuffix>
5481 // tag : V6_pred_or_128B
5482 class Hexagon_v128iv128iv128i_Intrinsic<string GCCIntSuffix>
5483  : Hexagon_Intrinsic<GCCIntSuffix,
5484                           [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],
5485                           [IntrNoMem]>;
5486
5487 //
5488 // Hexagon_v64iv64i_Intrinsic<string GCCIntSuffix>
5489 // tag : V6_pred_not
5490 class Hexagon_v64iv64i_Intrinsic<string GCCIntSuffix>
5491  : Hexagon_Intrinsic<GCCIntSuffix,
5492                           [llvm_v512i1_ty], [llvm_v512i1_ty],
5493                           [IntrNoMem]>;
5494
5495 //
5496 // Hexagon_v128iv128i_Intrinsic<string GCCIntSuffix>
5497 // tag : V6_pred_not_128B
5498 class Hexagon_v128iv128i_Intrinsic<string GCCIntSuffix>
5499  : Hexagon_Intrinsic<GCCIntSuffix,
5500                           [llvm_v1024i1_ty], [llvm_v1024i1_ty],
5501                           [IntrNoMem]>;
5502
5503 //
5504 // Hexagon_v64ii_Intrinsic<string GCCIntSuffix>
5505 // tag : V6_pred_scalar2
5506 class Hexagon_v64ii_Intrinsic<string GCCIntSuffix>
5507  : Hexagon_Intrinsic<GCCIntSuffix,
5508                           [llvm_v512i1_ty], [llvm_i32_ty],
5509                           [IntrNoMem]>;
5510
5511 //
5512 // Hexagon_v128ii_Intrinsic<string GCCIntSuffix>
5513 // tag : V6_pred_scalar2_128B
5514 class Hexagon_v128ii_Intrinsic<string GCCIntSuffix>
5515  : Hexagon_Intrinsic<GCCIntSuffix,
5516                           [llvm_v1024i1_ty], [llvm_i32_ty],
5517                           [IntrNoMem]>;
5518
5519 //
5520 // Hexagon_v1024v64iv512v512_Intrinsic<string GCCIntSuffix>
5521 // tag : V6_vswap
5522 class Hexagon_v1024v64iv512v512_Intrinsic<string GCCIntSuffix>
5523  : Hexagon_Intrinsic<GCCIntSuffix,
5524                           [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
5525                           [IntrNoMem]>;
5526
5527 //
5528 // Hexagon_v2048v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5529 // tag : V6_vswap_128B
5530 class Hexagon_v2048v128iv1024v1024_Intrinsic<string GCCIntSuffix>
5531  : Hexagon_Intrinsic<GCCIntSuffix,
5532                           [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
5533                           [IntrNoMem]>;
5534
5535 //
5536 // Hexagon_v1024v512v512i_Intrinsic<string GCCIntSuffix>
5537 // tag : V6_vshuffvdd
5538 class Hexagon_v1024v512v512i_Intrinsic<string GCCIntSuffix>
5539  : Hexagon_Intrinsic<GCCIntSuffix,
5540                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5541                           [IntrNoMem]>;
5542
5543 //
5544 // Hexagon_v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
5545 // tag : V6_vshuffvdd_128B
5546 class Hexagon_v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
5547  : Hexagon_Intrinsic<GCCIntSuffix,
5548                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5549                           [IntrNoMem]>;
5550
5551
5552 //
5553 // Hexagon_iv512i_Intrinsic<string GCCIntSuffix>
5554 // tag : V6_extractw
5555 class Hexagon_iv512i_Intrinsic<string GCCIntSuffix>
5556  : Hexagon_Intrinsic<GCCIntSuffix,
5557                           [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
5558                           [IntrNoMem]>;
5559
5560 //
5561 // Hexagon_iv1024i_Intrinsic<string GCCIntSuffix>
5562 // tag : V6_extractw_128B
5563 class Hexagon_iv1024i_Intrinsic<string GCCIntSuffix>
5564  : Hexagon_Intrinsic<GCCIntSuffix,
5565                           [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
5566                           [IntrNoMem]>;
5567
5568 //
5569 // Hexagon_v512i_Intrinsic<string GCCIntSuffix>
5570 // tag : V6_lvsplatw
5571 class Hexagon_v512i_Intrinsic<string GCCIntSuffix>
5572  : Hexagon_Intrinsic<GCCIntSuffix,
5573                           [llvm_v16i32_ty], [llvm_i32_ty],
5574                           [IntrNoMem]>;
5575
5576 //
5577 // Hexagon_v1024i_Intrinsic<string GCCIntSuffix>
5578 // tag : V6_lvsplatw_128B
5579 class Hexagon_v1024i_Intrinsic<string GCCIntSuffix>
5580  : Hexagon_Intrinsic<GCCIntSuffix,
5581                           [llvm_v32i32_ty], [llvm_i32_ty],
5582                           [IntrNoMem]>;
5583
5584 //
5585 // Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
5586 // tag : V6_vlutvvb_oracc
5587 class Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
5588  : Hexagon_Intrinsic<GCCIntSuffix,
5589                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5590                           [IntrNoMem]>;
5591
5592 //
5593 // Hexagon_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
5594 // tag : V6_vlutvvb_oracc_128B
5595 class Hexagon_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
5596  : Hexagon_Intrinsic<GCCIntSuffix,
5597                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5598                           [IntrNoMem]>;
5599
5600 //
5601 // Hexagon_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix>
5602 // tag : V6_vlutvwh_oracc
5603 class Hexagon_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix>
5604  : Hexagon_Intrinsic<GCCIntSuffix,
5605                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
5606                           [IntrNoMem]>;
5607
5608 //
5609 // Hexagon_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
5610 // tag : V6_vlutvwh_oracc_128B
5611 class Hexagon_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
5612  : Hexagon_Intrinsic<GCCIntSuffix,
5613                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
5614                           [IntrNoMem]>;
5615
5616 //
5617 // Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
5618 // tag: V6_vS32b_qpred_ai
5619 class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
5620  : Hexagon_Intrinsic<GCCIntSuffix,
5621                           [], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty],
5622                           [IntrArgMemOnly]>;
5623
5624 //
5625 // Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
5626 // tag: V6_vS32b_qpred_ai_128B
5627 class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
5628  : Hexagon_Intrinsic<GCCIntSuffix,
5629                           [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty],
5630                           [IntrArgMemOnly]>;
5631
5632 //
5633 // BUILTIN_INFO(HEXAGON.S6_rol_i_r,SI_ftype_SISI,2)
5634 // tag : S6_rol_i_r
5635 def int_hexagon_S6_rol_i_r :
5636 Hexagon_iii_Intrinsic<"HEXAGON_S6_rol_i_r">;
5637
5638 //
5639 // BUILTIN_INFO(HEXAGON.S6_rol_i_p,DI_ftype_DISI,2)
5640 // tag : S6_rol_i_p
5641 def int_hexagon_S6_rol_i_p :
5642 Hexagon_LLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p">;
5643
5644 //
5645 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_acc,SI_ftype_SISISI,3)
5646 // tag : S6_rol_i_r_acc
5647 def int_hexagon_S6_rol_i_r_acc :
5648 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_acc">;
5649
5650 //
5651 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_acc,DI_ftype_DIDISI,3)
5652 // tag : S6_rol_i_p_acc
5653 def int_hexagon_S6_rol_i_p_acc :
5654 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_acc">;
5655
5656 //
5657 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_nac,SI_ftype_SISISI,3)
5658 // tag : S6_rol_i_r_nac
5659 def int_hexagon_S6_rol_i_r_nac :
5660 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_nac">;
5661
5662 //
5663 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_nac,DI_ftype_DIDISI,3)
5664 // tag : S6_rol_i_p_nac
5665 def int_hexagon_S6_rol_i_p_nac :
5666 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_nac">;
5667
5668 //
5669 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_xacc,SI_ftype_SISISI,3)
5670 // tag : S6_rol_i_r_xacc
5671 def int_hexagon_S6_rol_i_r_xacc :
5672 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_xacc">;
5673
5674 //
5675 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_xacc,DI_ftype_DIDISI,3)
5676 // tag : S6_rol_i_p_xacc
5677 def int_hexagon_S6_rol_i_p_xacc :
5678 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_xacc">;
5679
5680 //
5681 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_and,SI_ftype_SISISI,3)
5682 // tag : S6_rol_i_r_and
5683 def int_hexagon_S6_rol_i_r_and :
5684 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_and">;
5685
5686 //
5687 // BUILTIN_INFO(HEXAGON.S6_rol_i_r_or,SI_ftype_SISISI,3)
5688 // tag : S6_rol_i_r_or
5689 def int_hexagon_S6_rol_i_r_or :
5690 Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_or">;
5691
5692 //
5693 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_and,DI_ftype_DIDISI,3)
5694 // tag : S6_rol_i_p_and
5695 def int_hexagon_S6_rol_i_p_and :
5696 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_and">;
5697
5698 //
5699 // BUILTIN_INFO(HEXAGON.S6_rol_i_p_or,DI_ftype_DIDISI,3)
5700 // tag : S6_rol_i_p_or
5701 def int_hexagon_S6_rol_i_p_or :
5702 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_or">;
5703
5704 //
5705 // BUILTIN_INFO(HEXAGON.S2_cabacencbin,DI_ftype_DIDIQI,3)
5706 // tag : S2_cabacencbin
5707 def int_hexagon_S2_cabacencbin :
5708 Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S2_cabacencbin">;
5709
5710 //
5711 // BUILTIN_INFO(HEXAGON.V6_valignb,VI_ftype_VIVISI,3)
5712 // tag : V6_valignb
5713 def int_hexagon_V6_valignb :
5714 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_valignb">;
5715
5716 //
5717 // BUILTIN_INFO(HEXAGON.V6_valignb_128B,VI_ftype_VIVISI,3)
5718 // tag : V6_valignb_128B
5719 def int_hexagon_V6_valignb_128B :
5720 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_valignb_128B">;
5721
5722 //
5723 // BUILTIN_INFO(HEXAGON.V6_vlalignb,VI_ftype_VIVISI,3)
5724 // tag : V6_vlalignb
5725 def int_hexagon_V6_vlalignb :
5726 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlalignb">;
5727
5728 //
5729 // BUILTIN_INFO(HEXAGON.V6_vlalignb_128B,VI_ftype_VIVISI,3)
5730 // tag : V6_vlalignb_128B
5731 def int_hexagon_V6_vlalignb_128B :
5732 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlalignb_128B">;
5733
5734 //
5735 // BUILTIN_INFO(HEXAGON.V6_valignbi,VI_ftype_VIVISI,3)
5736 // tag : V6_valignbi
5737 def int_hexagon_V6_valignbi :
5738 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_valignbi">;
5739
5740 //
5741 // BUILTIN_INFO(HEXAGON.V6_valignbi_128B,VI_ftype_VIVISI,3)
5742 // tag : V6_valignbi_128B
5743 def int_hexagon_V6_valignbi_128B :
5744 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_valignbi_128B">;
5745
5746 //
5747 // BUILTIN_INFO(HEXAGON.V6_vlalignbi,VI_ftype_VIVISI,3)
5748 // tag : V6_vlalignbi
5749 def int_hexagon_V6_vlalignbi :
5750 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlalignbi">;
5751
5752 //
5753 // BUILTIN_INFO(HEXAGON.V6_vlalignbi_128B,VI_ftype_VIVISI,3)
5754 // tag : V6_vlalignbi_128B
5755 def int_hexagon_V6_vlalignbi_128B :
5756 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlalignbi_128B">;
5757
5758 //
5759 // BUILTIN_INFO(HEXAGON.V6_vror,VI_ftype_VISI,2)
5760 // tag : V6_vror
5761 def int_hexagon_V6_vror :
5762 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vror">;
5763
5764 //
5765 // BUILTIN_INFO(HEXAGON.V6_vror_128B,VI_ftype_VISI,2)
5766 // tag : V6_vror_128B
5767 def int_hexagon_V6_vror_128B :
5768 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vror_128B">;
5769
5770 //
5771 // BUILTIN_INFO(HEXAGON.V6_vunpackub,VD_ftype_VI,1)
5772 // tag : V6_vunpackub
5773 def int_hexagon_V6_vunpackub :
5774 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackub">;
5775
5776 //
5777 // BUILTIN_INFO(HEXAGON.V6_vunpackub_128B,VD_ftype_VI,1)
5778 // tag : V6_vunpackub_128B
5779 def int_hexagon_V6_vunpackub_128B :
5780 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackub_128B">;
5781
5782 //
5783 // BUILTIN_INFO(HEXAGON.V6_vunpackb,VD_ftype_VI,1)
5784 // tag : V6_vunpackb
5785 def int_hexagon_V6_vunpackb :
5786 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackb">;
5787
5788 //
5789 // BUILTIN_INFO(HEXAGON.V6_vunpackb_128B,VD_ftype_VI,1)
5790 // tag : V6_vunpackb_128B
5791 def int_hexagon_V6_vunpackb_128B :
5792 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackb_128B">;
5793
5794 //
5795 // BUILTIN_INFO(HEXAGON.V6_vunpackuh,VD_ftype_VI,1)
5796 // tag : V6_vunpackuh
5797 def int_hexagon_V6_vunpackuh :
5798 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackuh">;
5799
5800 //
5801 // BUILTIN_INFO(HEXAGON.V6_vunpackuh_128B,VD_ftype_VI,1)
5802 // tag : V6_vunpackuh_128B
5803 def int_hexagon_V6_vunpackuh_128B :
5804 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackuh_128B">;
5805
5806 //
5807 // BUILTIN_INFO(HEXAGON.V6_vunpackh,VD_ftype_VI,1)
5808 // tag : V6_vunpackh
5809 def int_hexagon_V6_vunpackh :
5810 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackh">;
5811
5812 //
5813 // BUILTIN_INFO(HEXAGON.V6_vunpackh_128B,VD_ftype_VI,1)
5814 // tag : V6_vunpackh_128B
5815 def int_hexagon_V6_vunpackh_128B :
5816 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackh_128B">;
5817
5818 //
5819 // BUILTIN_INFO(HEXAGON.V6_vunpackob,VD_ftype_VDVI,2)
5820 // tag : V6_vunpackob
5821 def int_hexagon_V6_vunpackob :
5822 Hexagon_v1024v1024v512_Intrinsic<"HEXAGON_V6_vunpackob">;
5823
5824 //
5825 // BUILTIN_INFO(HEXAGON.V6_vunpackob_128B,VD_ftype_VDVI,2)
5826 // tag : V6_vunpackob_128B
5827 def int_hexagon_V6_vunpackob_128B :
5828 Hexagon_v2048v2048v1024_Intrinsic<"HEXAGON_V6_vunpackob_128B">;
5829
5830 //
5831 // BUILTIN_INFO(HEXAGON.V6_vunpackoh,VD_ftype_VDVI,2)
5832 // tag : V6_vunpackoh
5833 def int_hexagon_V6_vunpackoh :
5834 Hexagon_v1024v1024v512_Intrinsic<"HEXAGON_V6_vunpackoh">;
5835
5836 //
5837 // BUILTIN_INFO(HEXAGON.V6_vunpackoh_128B,VD_ftype_VDVI,2)
5838 // tag : V6_vunpackoh_128B
5839 def int_hexagon_V6_vunpackoh_128B :
5840 Hexagon_v2048v2048v1024_Intrinsic<"HEXAGON_V6_vunpackoh_128B">;
5841
5842 //
5843 // BUILTIN_INFO(HEXAGON.V6_vpackeb,VI_ftype_VIVI,2)
5844 // tag : V6_vpackeb
5845 def int_hexagon_V6_vpackeb :
5846 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackeb">;
5847
5848 //
5849 // BUILTIN_INFO(HEXAGON.V6_vpackeb_128B,VI_ftype_VIVI,2)
5850 // tag : V6_vpackeb_128B
5851 def int_hexagon_V6_vpackeb_128B :
5852 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackeb_128B">;
5853
5854 //
5855 // BUILTIN_INFO(HEXAGON.V6_vpackeh,VI_ftype_VIVI,2)
5856 // tag : V6_vpackeh
5857 def int_hexagon_V6_vpackeh :
5858 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackeh">;
5859
5860 //
5861 // BUILTIN_INFO(HEXAGON.V6_vpackeh_128B,VI_ftype_VIVI,2)
5862 // tag : V6_vpackeh_128B
5863 def int_hexagon_V6_vpackeh_128B :
5864 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackeh_128B">;
5865
5866 //
5867 // BUILTIN_INFO(HEXAGON.V6_vpackob,VI_ftype_VIVI,2)
5868 // tag : V6_vpackob
5869 def int_hexagon_V6_vpackob :
5870 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackob">;
5871
5872 //
5873 // BUILTIN_INFO(HEXAGON.V6_vpackob_128B,VI_ftype_VIVI,2)
5874 // tag : V6_vpackob_128B
5875 def int_hexagon_V6_vpackob_128B :
5876 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackob_128B">;
5877
5878 //
5879 // BUILTIN_INFO(HEXAGON.V6_vpackoh,VI_ftype_VIVI,2)
5880 // tag : V6_vpackoh
5881 def int_hexagon_V6_vpackoh :
5882 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackoh">;
5883
5884 //
5885 // BUILTIN_INFO(HEXAGON.V6_vpackoh_128B,VI_ftype_VIVI,2)
5886 // tag : V6_vpackoh_128B
5887 def int_hexagon_V6_vpackoh_128B :
5888 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackoh_128B">;
5889
5890 //
5891 // BUILTIN_INFO(HEXAGON.V6_vpackhub_sat,VI_ftype_VIVI,2)
5892 // tag : V6_vpackhub_sat
5893 def int_hexagon_V6_vpackhub_sat :
5894 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackhub_sat">;
5895
5896 //
5897 // BUILTIN_INFO(HEXAGON.V6_vpackhub_sat_128B,VI_ftype_VIVI,2)
5898 // tag : V6_vpackhub_sat_128B
5899 def int_hexagon_V6_vpackhub_sat_128B :
5900 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">;
5901
5902 //
5903 // BUILTIN_INFO(HEXAGON.V6_vpackhb_sat,VI_ftype_VIVI,2)
5904 // tag : V6_vpackhb_sat
5905 def int_hexagon_V6_vpackhb_sat :
5906 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackhb_sat">;
5907
5908 //
5909 // BUILTIN_INFO(HEXAGON.V6_vpackhb_sat_128B,VI_ftype_VIVI,2)
5910 // tag : V6_vpackhb_sat_128B
5911 def int_hexagon_V6_vpackhb_sat_128B :
5912 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">;
5913
5914 //
5915 // BUILTIN_INFO(HEXAGON.V6_vpackwuh_sat,VI_ftype_VIVI,2)
5916 // tag : V6_vpackwuh_sat
5917 def int_hexagon_V6_vpackwuh_sat :
5918 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackwuh_sat">;
5919
5920 //
5921 // BUILTIN_INFO(HEXAGON.V6_vpackwuh_sat_128B,VI_ftype_VIVI,2)
5922 // tag : V6_vpackwuh_sat_128B
5923 def int_hexagon_V6_vpackwuh_sat_128B :
5924 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">;
5925
5926 //
5927 // BUILTIN_INFO(HEXAGON.V6_vpackwh_sat,VI_ftype_VIVI,2)
5928 // tag : V6_vpackwh_sat
5929 def int_hexagon_V6_vpackwh_sat :
5930 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackwh_sat">;
5931
5932 //
5933 // BUILTIN_INFO(HEXAGON.V6_vpackwh_sat_128B,VI_ftype_VIVI,2)
5934 // tag : V6_vpackwh_sat_128B
5935 def int_hexagon_V6_vpackwh_sat_128B :
5936 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">;
5937
5938 //
5939 // BUILTIN_INFO(HEXAGON.V6_vzb,VD_ftype_VI,1)
5940 // tag : V6_vzb
5941 def int_hexagon_V6_vzb :
5942 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vzb">;
5943
5944 //
5945 // BUILTIN_INFO(HEXAGON.V6_vzb_128B,VD_ftype_VI,1)
5946 // tag : V6_vzb_128B
5947 def int_hexagon_V6_vzb_128B :
5948 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vzb_128B">;
5949
5950 //
5951 // BUILTIN_INFO(HEXAGON.V6_vsb,VD_ftype_VI,1)
5952 // tag : V6_vsb
5953 def int_hexagon_V6_vsb :
5954 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vsb">;
5955
5956 //
5957 // BUILTIN_INFO(HEXAGON.V6_vsb_128B,VD_ftype_VI,1)
5958 // tag : V6_vsb_128B
5959 def int_hexagon_V6_vsb_128B :
5960 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vsb_128B">;
5961
5962 //
5963 // BUILTIN_INFO(HEXAGON.V6_vzh,VD_ftype_VI,1)
5964 // tag : V6_vzh
5965 def int_hexagon_V6_vzh :
5966 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vzh">;
5967
5968 //
5969 // BUILTIN_INFO(HEXAGON.V6_vzh_128B,VD_ftype_VI,1)
5970 // tag : V6_vzh_128B
5971 def int_hexagon_V6_vzh_128B :
5972 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vzh_128B">;
5973
5974 //
5975 // BUILTIN_INFO(HEXAGON.V6_vsh,VD_ftype_VI,1)
5976 // tag : V6_vsh
5977 def int_hexagon_V6_vsh :
5978 Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vsh">;
5979
5980 //
5981 // BUILTIN_INFO(HEXAGON.V6_vsh_128B,VD_ftype_VI,1)
5982 // tag : V6_vsh_128B
5983 def int_hexagon_V6_vsh_128B :
5984 Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vsh_128B">;
5985
5986 //
5987 // BUILTIN_INFO(HEXAGON.V6_vdmpybus,VI_ftype_VISI,2)
5988 // tag : V6_vdmpybus
5989 def int_hexagon_V6_vdmpybus :
5990 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpybus">;
5991
5992 //
5993 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_128B,VI_ftype_VISI,2)
5994 // tag : V6_vdmpybus_128B
5995 def int_hexagon_V6_vdmpybus_128B :
5996 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_128B">;
5997
5998 //
5999 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_acc,VI_ftype_VIVISI,3)
6000 // tag : V6_vdmpybus_acc
6001 def int_hexagon_V6_vdmpybus_acc :
6002 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpybus_acc">;
6003
6004 //
6005 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_acc_128B,VI_ftype_VIVISI,3)
6006 // tag : V6_vdmpybus_acc_128B
6007 def int_hexagon_V6_vdmpybus_acc_128B :
6008 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">;
6009
6010 //
6011 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv,VD_ftype_VDSI,2)
6012 // tag : V6_vdmpybus_dv
6013 def int_hexagon_V6_vdmpybus_dv :
6014 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_dv">;
6015
6016 //
6017 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_128B,VD_ftype_VDSI,2)
6018 // tag : V6_vdmpybus_dv_128B
6019 def int_hexagon_V6_vdmpybus_dv_128B :
6020 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">;
6021
6022 //
6023 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_acc,VD_ftype_VDVDSI,3)
6024 // tag : V6_vdmpybus_dv_acc
6025 def int_hexagon_V6_vdmpybus_dv_acc :
6026 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">;
6027
6028 //
6029 // BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_acc_128B,VD_ftype_VDVDSI,3)
6030 // tag : V6_vdmpybus_dv_acc_128B
6031 def int_hexagon_V6_vdmpybus_dv_acc_128B :
6032 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">;
6033
6034 //
6035 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb,VI_ftype_VISI,2)
6036 // tag : V6_vdmpyhb
6037 def int_hexagon_V6_vdmpyhb :
6038 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhb">;
6039
6040 //
6041 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_128B,VI_ftype_VISI,2)
6042 // tag : V6_vdmpyhb_128B
6043 def int_hexagon_V6_vdmpyhb_128B :
6044 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">;
6045
6046 //
6047 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_acc,VI_ftype_VIVISI,3)
6048 // tag : V6_vdmpyhb_acc
6049 def int_hexagon_V6_vdmpyhb_acc :
6050 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">;
6051
6052 //
6053 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_acc_128B,VI_ftype_VIVISI,3)
6054 // tag : V6_vdmpyhb_acc_128B
6055 def int_hexagon_V6_vdmpyhb_acc_128B :
6056 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">;
6057
6058 //
6059 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv,VD_ftype_VDSI,2)
6060 // tag : V6_vdmpyhb_dv
6061 def int_hexagon_V6_vdmpyhb_dv :
6062 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">;
6063
6064 //
6065 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_128B,VD_ftype_VDSI,2)
6066 // tag : V6_vdmpyhb_dv_128B
6067 def int_hexagon_V6_vdmpyhb_dv_128B :
6068 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">;
6069
6070 //
6071 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_acc,VD_ftype_VDVDSI,3)
6072 // tag : V6_vdmpyhb_dv_acc
6073 def int_hexagon_V6_vdmpyhb_dv_acc :
6074 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">;
6075
6076 //
6077 // BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_acc_128B,VD_ftype_VDVDSI,3)
6078 // tag : V6_vdmpyhb_dv_acc_128B
6079 def int_hexagon_V6_vdmpyhb_dv_acc_128B :
6080 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">;
6081
6082 //
6083 // BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat,VI_ftype_VIVI,2)
6084 // tag : V6_vdmpyhvsat
6085 def int_hexagon_V6_vdmpyhvsat :
6086 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdmpyhvsat">;
6087
6088 //
6089 // BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_128B,VI_ftype_VIVI,2)
6090 // tag : V6_vdmpyhvsat_128B
6091 def int_hexagon_V6_vdmpyhvsat_128B :
6092 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">;
6093
6094 //
6095 // BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_acc,VI_ftype_VIVIVI,3)
6096 // tag : V6_vdmpyhvsat_acc
6097 def int_hexagon_V6_vdmpyhvsat_acc :
6098 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">;
6099
6100 //
6101 // BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_acc_128B,VI_ftype_VIVIVI,3)
6102 // tag : V6_vdmpyhvsat_acc_128B
6103 def int_hexagon_V6_vdmpyhvsat_acc_128B :
6104 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">;
6105
6106 //
6107 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsat,VI_ftype_VISI,2)
6108 // tag : V6_vdmpyhsat
6109 def int_hexagon_V6_vdmpyhsat :
6110 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsat">;
6111
6112 //
6113 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_128B,VI_ftype_VISI,2)
6114 // tag : V6_vdmpyhsat_128B
6115 def int_hexagon_V6_vdmpyhsat_128B :
6116 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">;
6117
6118 //
6119 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_acc,VI_ftype_VIVISI,3)
6120 // tag : V6_vdmpyhsat_acc
6121 def int_hexagon_V6_vdmpyhsat_acc :
6122 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">;
6123
6124 //
6125 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_acc_128B,VI_ftype_VIVISI,3)
6126 // tag : V6_vdmpyhsat_acc_128B
6127 def int_hexagon_V6_vdmpyhsat_acc_128B :
6128 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">;
6129
6130 //
6131 // BUILTIN_INFO(HEXAGON.V6_vdmpyhisat,VI_ftype_VDSI,2)
6132 // tag : V6_vdmpyhisat
6133 def int_hexagon_V6_vdmpyhisat :
6134 Hexagon_v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhisat">;
6135
6136 //
6137 // BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_128B,VI_ftype_VDSI,2)
6138 // tag : V6_vdmpyhisat_128B
6139 def int_hexagon_V6_vdmpyhisat_128B :
6140 Hexagon_v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">;
6141
6142 //
6143 // BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_acc,VI_ftype_VIVDSI,3)
6144 // tag : V6_vdmpyhisat_acc
6145 def int_hexagon_V6_vdmpyhisat_acc :
6146 Hexagon_v512v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">;
6147
6148 //
6149 // BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_acc_128B,VI_ftype_VIVDSI,3)
6150 // tag : V6_vdmpyhisat_acc_128B
6151 def int_hexagon_V6_vdmpyhisat_acc_128B :
6152 Hexagon_v1024v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">;
6153
6154 //
6155 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat,VI_ftype_VISI,2)
6156 // tag : V6_vdmpyhsusat
6157 def int_hexagon_V6_vdmpyhsusat :
6158 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsusat">;
6159
6160 //
6161 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_128B,VI_ftype_VISI,2)
6162 // tag : V6_vdmpyhsusat_128B
6163 def int_hexagon_V6_vdmpyhsusat_128B :
6164 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">;
6165
6166 //
6167 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_acc,VI_ftype_VIVISI,3)
6168 // tag : V6_vdmpyhsusat_acc
6169 def int_hexagon_V6_vdmpyhsusat_acc :
6170 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">;
6171
6172 //
6173 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_acc_128B,VI_ftype_VIVISI,3)
6174 // tag : V6_vdmpyhsusat_acc_128B
6175 def int_hexagon_V6_vdmpyhsusat_acc_128B :
6176 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">;
6177
6178 //
6179 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat,VI_ftype_VDSI,2)
6180 // tag : V6_vdmpyhsuisat
6181 def int_hexagon_V6_vdmpyhsuisat :
6182 Hexagon_v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">;
6183
6184 //
6185 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_128B,VI_ftype_VDSI,2)
6186 // tag : V6_vdmpyhsuisat_128B
6187 def int_hexagon_V6_vdmpyhsuisat_128B :
6188 Hexagon_v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">;
6189
6190 //
6191 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_acc,VI_ftype_VIVDSI,3)
6192 // tag : V6_vdmpyhsuisat_acc
6193 def int_hexagon_V6_vdmpyhsuisat_acc :
6194 Hexagon_v512v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">;
6195
6196 //
6197 // BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_acc_128B,VI_ftype_VIVDSI,3)
6198 // tag : V6_vdmpyhsuisat_acc_128B
6199 def int_hexagon_V6_vdmpyhsuisat_acc_128B :
6200 Hexagon_v1024v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">;
6201
6202 //
6203 // BUILTIN_INFO(HEXAGON.V6_vtmpyb,VD_ftype_VDSI,2)
6204 // tag : V6_vtmpyb
6205 def int_hexagon_V6_vtmpyb :
6206 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyb">;
6207
6208 //
6209 // BUILTIN_INFO(HEXAGON.V6_vtmpyb_128B,VD_ftype_VDSI,2)
6210 // tag : V6_vtmpyb_128B
6211 def int_hexagon_V6_vtmpyb_128B :
6212 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyb_128B">;
6213
6214 //
6215 // BUILTIN_INFO(HEXAGON.V6_vtmpyb_acc,VD_ftype_VDVDSI,3)
6216 // tag : V6_vtmpyb_acc
6217 def int_hexagon_V6_vtmpyb_acc :
6218 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyb_acc">;
6219
6220 //
6221 // BUILTIN_INFO(HEXAGON.V6_vtmpyb_acc_128B,VD_ftype_VDVDSI,3)
6222 // tag : V6_vtmpyb_acc_128B
6223 def int_hexagon_V6_vtmpyb_acc_128B :
6224 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">;
6225
6226 //
6227 // BUILTIN_INFO(HEXAGON.V6_vtmpybus,VD_ftype_VDSI,2)
6228 // tag : V6_vtmpybus
6229 def int_hexagon_V6_vtmpybus :
6230 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpybus">;
6231
6232 //
6233 // BUILTIN_INFO(HEXAGON.V6_vtmpybus_128B,VD_ftype_VDSI,2)
6234 // tag : V6_vtmpybus_128B
6235 def int_hexagon_V6_vtmpybus_128B :
6236 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpybus_128B">;
6237
6238 //
6239 // BUILTIN_INFO(HEXAGON.V6_vtmpybus_acc,VD_ftype_VDVDSI,3)
6240 // tag : V6_vtmpybus_acc
6241 def int_hexagon_V6_vtmpybus_acc :
6242 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpybus_acc">;
6243
6244 //
6245 // BUILTIN_INFO(HEXAGON.V6_vtmpybus_acc_128B,VD_ftype_VDVDSI,3)
6246 // tag : V6_vtmpybus_acc_128B
6247 def int_hexagon_V6_vtmpybus_acc_128B :
6248 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">;
6249
6250 //
6251 // BUILTIN_INFO(HEXAGON.V6_vtmpyhb,VD_ftype_VDSI,2)
6252 // tag : V6_vtmpyhb
6253 def int_hexagon_V6_vtmpyhb :
6254 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyhb">;
6255
6256 //
6257 // BUILTIN_INFO(HEXAGON.V6_vtmpyhb_128B,VD_ftype_VDSI,2)
6258 // tag : V6_vtmpyhb_128B
6259 def int_hexagon_V6_vtmpyhb_128B :
6260 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">;
6261
6262 //
6263 // BUILTIN_INFO(HEXAGON.V6_vtmpyhb_acc,VD_ftype_VDVDSI,3)
6264 // tag : V6_vtmpyhb_acc
6265 def int_hexagon_V6_vtmpyhb_acc :
6266 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">;
6267
6268 //
6269 // BUILTIN_INFO(HEXAGON.V6_vtmpyhb_acc_128B,VD_ftype_VDVDSI,3)
6270 // tag : V6_vtmpyhb_acc_128B
6271 def int_hexagon_V6_vtmpyhb_acc_128B :
6272 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">;
6273
6274 //
6275 // BUILTIN_INFO(HEXAGON.V6_vrmpyub,VI_ftype_VISI,2)
6276 // tag : V6_vrmpyub
6277 def int_hexagon_V6_vrmpyub :
6278 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vrmpyub">;
6279
6280 //
6281 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_128B,VI_ftype_VISI,2)
6282 // tag : V6_vrmpyub_128B
6283 def int_hexagon_V6_vrmpyub_128B :
6284 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpyub_128B">;
6285
6286 //
6287 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_acc,VI_ftype_VIVISI,3)
6288 // tag : V6_vrmpyub_acc
6289 def int_hexagon_V6_vrmpyub_acc :
6290 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vrmpyub_acc">;
6291
6292 //
6293 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_acc_128B,VI_ftype_VIVISI,3)
6294 // tag : V6_vrmpyub_acc_128B
6295 def int_hexagon_V6_vrmpyub_acc_128B :
6296 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">;
6297
6298 //
6299 // BUILTIN_INFO(HEXAGON.V6_vrmpyubv,VI_ftype_VIVI,2)
6300 // tag : V6_vrmpyubv
6301 def int_hexagon_V6_vrmpyubv :
6302 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpyubv">;
6303
6304 //
6305 // BUILTIN_INFO(HEXAGON.V6_vrmpyubv_128B,VI_ftype_VIVI,2)
6306 // tag : V6_vrmpyubv_128B
6307 def int_hexagon_V6_vrmpyubv_128B :
6308 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">;
6309
6310 //
6311 // BUILTIN_INFO(HEXAGON.V6_vrmpyubv_acc,VI_ftype_VIVIVI,3)
6312 // tag : V6_vrmpyubv_acc
6313 def int_hexagon_V6_vrmpyubv_acc :
6314 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">;
6315
6316 //
6317 // BUILTIN_INFO(HEXAGON.V6_vrmpyubv_acc_128B,VI_ftype_VIVIVI,3)
6318 // tag : V6_vrmpyubv_acc_128B
6319 def int_hexagon_V6_vrmpyubv_acc_128B :
6320 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">;
6321
6322 //
6323 // BUILTIN_INFO(HEXAGON.V6_vrmpybv,VI_ftype_VIVI,2)
6324 // tag : V6_vrmpybv
6325 def int_hexagon_V6_vrmpybv :
6326 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybv">;
6327
6328 //
6329 // BUILTIN_INFO(HEXAGON.V6_vrmpybv_128B,VI_ftype_VIVI,2)
6330 // tag : V6_vrmpybv_128B
6331 def int_hexagon_V6_vrmpybv_128B :
6332 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybv_128B">;
6333
6334 //
6335 // BUILTIN_INFO(HEXAGON.V6_vrmpybv_acc,VI_ftype_VIVIVI,3)
6336 // tag : V6_vrmpybv_acc
6337 def int_hexagon_V6_vrmpybv_acc :
6338 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybv_acc">;
6339
6340 //
6341 // BUILTIN_INFO(HEXAGON.V6_vrmpybv_acc_128B,VI_ftype_VIVIVI,3)
6342 // tag : V6_vrmpybv_acc_128B
6343 def int_hexagon_V6_vrmpybv_acc_128B :
6344 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">;
6345
6346 //
6347 // BUILTIN_INFO(HEXAGON.V6_vrmpyubi,VD_ftype_VDSISI,3)
6348 // tag : V6_vrmpyubi
6349 def int_hexagon_V6_vrmpyubi :
6350 Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpyubi">;
6351
6352 //
6353 // BUILTIN_INFO(HEXAGON.V6_vrmpyubi_128B,VD_ftype_VDSISI,3)
6354 // tag : V6_vrmpyubi_128B
6355 def int_hexagon_V6_vrmpyubi_128B :
6356 Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpyubi_128B">;
6357
6358 //
6359 // BUILTIN_INFO(HEXAGON.V6_vrmpyubi_acc,VD_ftype_VDVDSISI,4)
6360 // tag : V6_vrmpyubi_acc
6361 def int_hexagon_V6_vrmpyubi_acc :
6362 Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpyubi_acc">;
6363
6364 //
6365 // BUILTIN_INFO(HEXAGON.V6_vrmpyubi_acc_128B,VD_ftype_VDVDSISI,4)
6366 // tag : V6_vrmpyubi_acc_128B
6367 def int_hexagon_V6_vrmpyubi_acc_128B :
6368 Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B">;
6369
6370 //
6371 // BUILTIN_INFO(HEXAGON.V6_vrmpybus,VI_ftype_VISI,2)
6372 // tag : V6_vrmpybus
6373 def int_hexagon_V6_vrmpybus :
6374 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vrmpybus">;
6375
6376 //
6377 // BUILTIN_INFO(HEXAGON.V6_vrmpybus_128B,VI_ftype_VISI,2)
6378 // tag : V6_vrmpybus_128B
6379 def int_hexagon_V6_vrmpybus_128B :
6380 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpybus_128B">;
6381
6382 //
6383 // BUILTIN_INFO(HEXAGON.V6_vrmpybus_acc,VI_ftype_VIVISI,3)
6384 // tag : V6_vrmpybus_acc
6385 def int_hexagon_V6_vrmpybus_acc :
6386 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vrmpybus_acc">;
6387
6388 //
6389 // BUILTIN_INFO(HEXAGON.V6_vrmpybus_acc_128B,VI_ftype_VIVISI,3)
6390 // tag : V6_vrmpybus_acc_128B
6391 def int_hexagon_V6_vrmpybus_acc_128B :
6392 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">;
6393
6394 //
6395 // BUILTIN_INFO(HEXAGON.V6_vrmpybusi,VD_ftype_VDSISI,3)
6396 // tag : V6_vrmpybusi
6397 def int_hexagon_V6_vrmpybusi :
6398 Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpybusi">;
6399
6400 //
6401 // BUILTIN_INFO(HEXAGON.V6_vrmpybusi_128B,VD_ftype_VDSISI,3)
6402 // tag : V6_vrmpybusi_128B
6403 def int_hexagon_V6_vrmpybusi_128B :
6404 Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpybusi_128B">;
6405
6406 //
6407 // BUILTIN_INFO(HEXAGON.V6_vrmpybusi_acc,VD_ftype_VDVDSISI,4)
6408 // tag : V6_vrmpybusi_acc
6409 def int_hexagon_V6_vrmpybusi_acc :
6410 Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpybusi_acc">;
6411
6412 //
6413 // BUILTIN_INFO(HEXAGON.V6_vrmpybusi_acc_128B,VD_ftype_VDVDSISI,4)
6414 // tag : V6_vrmpybusi_acc_128B
6415 def int_hexagon_V6_vrmpybusi_acc_128B :
6416 Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B">;
6417
6418 //
6419 // BUILTIN_INFO(HEXAGON.V6_vrmpybusv,VI_ftype_VIVI,2)
6420 // tag : V6_vrmpybusv
6421 def int_hexagon_V6_vrmpybusv :
6422 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybusv">;
6423
6424 //
6425 // BUILTIN_INFO(HEXAGON.V6_vrmpybusv_128B,VI_ftype_VIVI,2)
6426 // tag : V6_vrmpybusv_128B
6427 def int_hexagon_V6_vrmpybusv_128B :
6428 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">;
6429
6430 //
6431 // BUILTIN_INFO(HEXAGON.V6_vrmpybusv_acc,VI_ftype_VIVIVI,3)
6432 // tag : V6_vrmpybusv_acc
6433 def int_hexagon_V6_vrmpybusv_acc :
6434 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">;
6435
6436 //
6437 // BUILTIN_INFO(HEXAGON.V6_vrmpybusv_acc_128B,VI_ftype_VIVIVI,3)
6438 // tag : V6_vrmpybusv_acc_128B
6439 def int_hexagon_V6_vrmpybusv_acc_128B :
6440 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">;
6441
6442 //
6443 // BUILTIN_INFO(HEXAGON.V6_vdsaduh,VD_ftype_VDSI,2)
6444 // tag : V6_vdsaduh
6445 def int_hexagon_V6_vdsaduh :
6446 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdsaduh">;
6447
6448 //
6449 // BUILTIN_INFO(HEXAGON.V6_vdsaduh_128B,VD_ftype_VDSI,2)
6450 // tag : V6_vdsaduh_128B
6451 def int_hexagon_V6_vdsaduh_128B :
6452 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdsaduh_128B">;
6453
6454 //
6455 // BUILTIN_INFO(HEXAGON.V6_vdsaduh_acc,VD_ftype_VDVDSI,3)
6456 // tag : V6_vdsaduh_acc
6457 def int_hexagon_V6_vdsaduh_acc :
6458 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdsaduh_acc">;
6459
6460 //
6461 // BUILTIN_INFO(HEXAGON.V6_vdsaduh_acc_128B,VD_ftype_VDVDSI,3)
6462 // tag : V6_vdsaduh_acc_128B
6463 def int_hexagon_V6_vdsaduh_acc_128B :
6464 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">;
6465
6466 //
6467 // BUILTIN_INFO(HEXAGON.V6_vrsadubi,VD_ftype_VDSISI,3)
6468 // tag : V6_vrsadubi
6469 def int_hexagon_V6_vrsadubi :
6470 Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrsadubi">;
6471
6472 //
6473 // BUILTIN_INFO(HEXAGON.V6_vrsadubi_128B,VD_ftype_VDSISI,3)
6474 // tag : V6_vrsadubi_128B
6475 def int_hexagon_V6_vrsadubi_128B :
6476 Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrsadubi_128B">;
6477
6478 //
6479 // BUILTIN_INFO(HEXAGON.V6_vrsadubi_acc,VD_ftype_VDVDSISI,4)
6480 // tag : V6_vrsadubi_acc
6481 def int_hexagon_V6_vrsadubi_acc :
6482 Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrsadubi_acc">;
6483
6484 //
6485 // BUILTIN_INFO(HEXAGON.V6_vrsadubi_acc_128B,VD_ftype_VDVDSISI,4)
6486 // tag : V6_vrsadubi_acc_128B
6487 def int_hexagon_V6_vrsadubi_acc_128B :
6488 Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B">;
6489
6490 //
6491 // BUILTIN_INFO(HEXAGON.V6_vasrw,VI_ftype_VISI,2)
6492 // tag : V6_vasrw
6493 def int_hexagon_V6_vasrw :
6494 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vasrw">;
6495
6496 //
6497 // BUILTIN_INFO(HEXAGON.V6_vasrw_128B,VI_ftype_VISI,2)
6498 // tag : V6_vasrw_128B
6499 def int_hexagon_V6_vasrw_128B :
6500 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vasrw_128B">;
6501
6502
6503 //
6504 // BUILTIN_INFO(HEXAGON.V6_vaslw,VI_ftype_VISI,2)
6505 // tag : V6_vaslw
6506 def int_hexagon_V6_vaslw :
6507 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vaslw">;
6508
6509 //
6510 // BUILTIN_INFO(HEXAGON.V6_vaslw_128B,VI_ftype_VISI,2)
6511 // tag : V6_vaslw_128B
6512 def int_hexagon_V6_vaslw_128B :
6513 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vaslw_128B">;
6514
6515 //
6516 // BUILTIN_INFO(HEXAGON.V6_vlsrw,VI_ftype_VISI,2)
6517 // tag : V6_vlsrw
6518 def int_hexagon_V6_vlsrw :
6519 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vlsrw">;
6520
6521 //
6522 // BUILTIN_INFO(HEXAGON.V6_vlsrw_128B,VI_ftype_VISI,2)
6523 // tag : V6_vlsrw_128B
6524 def int_hexagon_V6_vlsrw_128B :
6525 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrw_128B">;
6526
6527 //
6528 // BUILTIN_INFO(HEXAGON.V6_vasrwv,VI_ftype_VIVI,2)
6529 // tag : V6_vasrwv
6530 def int_hexagon_V6_vasrwv :
6531 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vasrwv">;
6532
6533 //
6534 // BUILTIN_INFO(HEXAGON.V6_vasrwv_128B,VI_ftype_VIVI,2)
6535 // tag : V6_vasrwv_128B
6536 def int_hexagon_V6_vasrwv_128B :
6537 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vasrwv_128B">;
6538
6539 //
6540 // BUILTIN_INFO(HEXAGON.V6_vaslwv,VI_ftype_VIVI,2)
6541 // tag : V6_vaslwv
6542 def int_hexagon_V6_vaslwv :
6543 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaslwv">;
6544
6545 //
6546 // BUILTIN_INFO(HEXAGON.V6_vaslwv_128B,VI_ftype_VIVI,2)
6547 // tag : V6_vaslwv_128B
6548 def int_hexagon_V6_vaslwv_128B :
6549 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaslwv_128B">;
6550
6551 //
6552 // BUILTIN_INFO(HEXAGON.V6_vlsrwv,VI_ftype_VIVI,2)
6553 // tag : V6_vlsrwv
6554 def int_hexagon_V6_vlsrwv :
6555 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vlsrwv">;
6556
6557 //
6558 // BUILTIN_INFO(HEXAGON.V6_vlsrwv_128B,VI_ftype_VIVI,2)
6559 // tag : V6_vlsrwv_128B
6560 def int_hexagon_V6_vlsrwv_128B :
6561 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vlsrwv_128B">;
6562
6563 //
6564 // BUILTIN_INFO(HEXAGON.V6_vasrh,VI_ftype_VISI,2)
6565 // tag : V6_vasrh
6566 def int_hexagon_V6_vasrh :
6567 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vasrh">;
6568
6569 //
6570 // BUILTIN_INFO(HEXAGON.V6_vasrh_128B,VI_ftype_VISI,2)
6571 // tag : V6_vasrh_128B
6572 def int_hexagon_V6_vasrh_128B :
6573 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_128B">;
6574
6575 //
6576 // BUILTIN_INFO(HEXAGON.V6_vaslh,VI_ftype_VISI,2)
6577 // tag : V6_vaslh
6578 def int_hexagon_V6_vaslh :
6579 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vaslh">;
6580
6581 //
6582 // BUILTIN_INFO(HEXAGON.V6_vaslh_128B,VI_ftype_VISI,2)
6583 // tag : V6_vaslh_128B
6584 def int_hexagon_V6_vaslh_128B :
6585 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_128B">;
6586
6587 //
6588 // BUILTIN_INFO(HEXAGON.V6_vlsrh,VI_ftype_VISI,2)
6589 // tag : V6_vlsrh
6590 def int_hexagon_V6_vlsrh :
6591 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vlsrh">;
6592
6593 //
6594 // BUILTIN_INFO(HEXAGON.V6_vlsrh_128B,VI_ftype_VISI,2)
6595 // tag : V6_vlsrh_128B
6596 def int_hexagon_V6_vlsrh_128B :
6597 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrh_128B">;
6598
6599 //
6600 // BUILTIN_INFO(HEXAGON.V6_vasrhv,VI_ftype_VIVI,2)
6601 // tag : V6_vasrhv
6602 def int_hexagon_V6_vasrhv :
6603 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vasrhv">;
6604
6605 //
6606 // BUILTIN_INFO(HEXAGON.V6_vasrhv_128B,VI_ftype_VIVI,2)
6607 // tag : V6_vasrhv_128B
6608 def int_hexagon_V6_vasrhv_128B :
6609 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vasrhv_128B">;
6610
6611 //
6612 // BUILTIN_INFO(HEXAGON.V6_vaslhv,VI_ftype_VIVI,2)
6613 // tag : V6_vaslhv
6614 def int_hexagon_V6_vaslhv :
6615 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaslhv">;
6616
6617 //
6618 // BUILTIN_INFO(HEXAGON.V6_vaslhv_128B,VI_ftype_VIVI,2)
6619 // tag : V6_vaslhv_128B
6620 def int_hexagon_V6_vaslhv_128B :
6621 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaslhv_128B">;
6622
6623 //
6624 // BUILTIN_INFO(HEXAGON.V6_vlsrhv,VI_ftype_VIVI,2)
6625 // tag : V6_vlsrhv
6626 def int_hexagon_V6_vlsrhv :
6627 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vlsrhv">;
6628
6629 //
6630 // BUILTIN_INFO(HEXAGON.V6_vlsrhv_128B,VI_ftype_VIVI,2)
6631 // tag : V6_vlsrhv_128B
6632 def int_hexagon_V6_vlsrhv_128B :
6633 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vlsrhv_128B">;
6634
6635 //
6636 // BUILTIN_INFO(HEXAGON.V6_vasrwh,VI_ftype_VIVISI,3)
6637 // tag : V6_vasrwh
6638 def int_hexagon_V6_vasrwh :
6639 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwh">;
6640
6641 //
6642 // BUILTIN_INFO(HEXAGON.V6_vasrwh_128B,VI_ftype_VIVISI,3)
6643 // tag : V6_vasrwh_128B
6644 def int_hexagon_V6_vasrwh_128B :
6645 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwh_128B">;
6646
6647 //
6648 // BUILTIN_INFO(HEXAGON.V6_vasrwhsat,VI_ftype_VIVISI,3)
6649 // tag : V6_vasrwhsat
6650 def int_hexagon_V6_vasrwhsat :
6651 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwhsat">;
6652
6653 //
6654 // BUILTIN_INFO(HEXAGON.V6_vasrwhsat_128B,VI_ftype_VIVISI,3)
6655 // tag : V6_vasrwhsat_128B
6656 def int_hexagon_V6_vasrwhsat_128B :
6657 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">;
6658
6659 //
6660 // BUILTIN_INFO(HEXAGON.V6_vasrwhrndsat,VI_ftype_VIVISI,3)
6661 // tag : V6_vasrwhrndsat
6662 def int_hexagon_V6_vasrwhrndsat :
6663 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwhrndsat">;
6664
6665 //
6666 // BUILTIN_INFO(HEXAGON.V6_vasrwhrndsat_128B,VI_ftype_VIVISI,3)
6667 // tag : V6_vasrwhrndsat_128B
6668 def int_hexagon_V6_vasrwhrndsat_128B :
6669 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">;
6670
6671 //
6672 // BUILTIN_INFO(HEXAGON.V6_vasrwuhsat,VI_ftype_VIVISI,3)
6673 // tag : V6_vasrwuhsat
6674 def int_hexagon_V6_vasrwuhsat :
6675 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwuhsat">;
6676
6677 //
6678 // BUILTIN_INFO(HEXAGON.V6_vasrwuhsat_128B,VI_ftype_VIVISI,3)
6679 // tag : V6_vasrwuhsat_128B
6680 def int_hexagon_V6_vasrwuhsat_128B :
6681 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">;
6682
6683 //
6684 // BUILTIN_INFO(HEXAGON.V6_vroundwh,VI_ftype_VIVI,2)
6685 // tag : V6_vroundwh
6686 def int_hexagon_V6_vroundwh :
6687 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundwh">;
6688
6689 //
6690 // BUILTIN_INFO(HEXAGON.V6_vroundwh_128B,VI_ftype_VIVI,2)
6691 // tag : V6_vroundwh_128B
6692 def int_hexagon_V6_vroundwh_128B :
6693 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundwh_128B">;
6694
6695 //
6696 // BUILTIN_INFO(HEXAGON.V6_vroundwuh,VI_ftype_VIVI,2)
6697 // tag : V6_vroundwuh
6698 def int_hexagon_V6_vroundwuh :
6699 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundwuh">;
6700
6701 //
6702 // BUILTIN_INFO(HEXAGON.V6_vroundwuh_128B,VI_ftype_VIVI,2)
6703 // tag : V6_vroundwuh_128B
6704 def int_hexagon_V6_vroundwuh_128B :
6705 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundwuh_128B">;
6706
6707 //
6708 // BUILTIN_INFO(HEXAGON.V6_vasrhubsat,VI_ftype_VIVISI,3)
6709 // tag : V6_vasrhubsat
6710 def int_hexagon_V6_vasrhubsat :
6711 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhubsat">;
6712
6713 //
6714 // BUILTIN_INFO(HEXAGON.V6_vasrhubsat_128B,VI_ftype_VIVISI,3)
6715 // tag : V6_vasrhubsat_128B
6716 def int_hexagon_V6_vasrhubsat_128B :
6717 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">;
6718
6719 //
6720 // BUILTIN_INFO(HEXAGON.V6_vasrhubrndsat,VI_ftype_VIVISI,3)
6721 // tag : V6_vasrhubrndsat
6722 def int_hexagon_V6_vasrhubrndsat :
6723 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhubrndsat">;
6724
6725 //
6726 // BUILTIN_INFO(HEXAGON.V6_vasrhubrndsat_128B,VI_ftype_VIVISI,3)
6727 // tag : V6_vasrhubrndsat_128B
6728 def int_hexagon_V6_vasrhubrndsat_128B :
6729 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">;
6730
6731 //
6732 // BUILTIN_INFO(HEXAGON.V6_vasrhbrndsat,VI_ftype_VIVISI,3)
6733 // tag : V6_vasrhbrndsat
6734 def int_hexagon_V6_vasrhbrndsat :
6735 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhbrndsat">;
6736
6737 //
6738 // BUILTIN_INFO(HEXAGON.V6_vasrhbrndsat_128B,VI_ftype_VIVISI,3)
6739 // tag : V6_vasrhbrndsat_128B
6740 def int_hexagon_V6_vasrhbrndsat_128B :
6741 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">;
6742
6743 //
6744 // BUILTIN_INFO(HEXAGON.V6_vroundhb,VI_ftype_VIVI,2)
6745 // tag : V6_vroundhb
6746 def int_hexagon_V6_vroundhb :
6747 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundhb">;
6748
6749 //
6750 // BUILTIN_INFO(HEXAGON.V6_vroundhb_128B,VI_ftype_VIVI,2)
6751 // tag : V6_vroundhb_128B
6752 def int_hexagon_V6_vroundhb_128B :
6753 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundhb_128B">;
6754
6755 //
6756 // BUILTIN_INFO(HEXAGON.V6_vroundhub,VI_ftype_VIVI,2)
6757 // tag : V6_vroundhub
6758 def int_hexagon_V6_vroundhub :
6759 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundhub">;
6760
6761 //
6762 // BUILTIN_INFO(HEXAGON.V6_vroundhub_128B,VI_ftype_VIVI,2)
6763 // tag : V6_vroundhub_128B
6764 def int_hexagon_V6_vroundhub_128B :
6765 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundhub_128B">;
6766
6767 //
6768 // BUILTIN_INFO(HEXAGON.V6_vaslw_acc,VI_ftype_VIVISI,3)
6769 // tag : V6_vaslw_acc
6770 def int_hexagon_V6_vaslw_acc :
6771 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslw_acc">;
6772
6773 //
6774 // BUILTIN_INFO(HEXAGON.V6_vaslw_acc_128B,VI_ftype_VIVISI,3)
6775 // tag : V6_vaslw_acc_128B
6776 def int_hexagon_V6_vaslw_acc_128B :
6777 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">;
6778
6779 //
6780 // BUILTIN_INFO(HEXAGON.V6_vasrw_acc,VI_ftype_VIVISI,3)
6781 // tag : V6_vasrw_acc
6782 def int_hexagon_V6_vasrw_acc :
6783 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrw_acc">;
6784
6785 //
6786 // BUILTIN_INFO(HEXAGON.V6_vasrw_acc_128B,VI_ftype_VIVISI,3)
6787 // tag : V6_vasrw_acc_128B
6788 def int_hexagon_V6_vasrw_acc_128B :
6789 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">;
6790
6791 //
6792 // BUILTIN_INFO(HEXAGON.V6_vaddb,VI_ftype_VIVI,2)
6793 // tag : V6_vaddb
6794 def int_hexagon_V6_vaddb :
6795 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddb">;
6796
6797 //
6798 // BUILTIN_INFO(HEXAGON.V6_vaddb_128B,VI_ftype_VIVI,2)
6799 // tag : V6_vaddb_128B
6800 def int_hexagon_V6_vaddb_128B :
6801 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddb_128B">;
6802
6803 //
6804 // BUILTIN_INFO(HEXAGON.V6_vsubb,VI_ftype_VIVI,2)
6805 // tag : V6_vsubb
6806 def int_hexagon_V6_vsubb :
6807 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubb">;
6808
6809 //
6810 // BUILTIN_INFO(HEXAGON.V6_vsubb_128B,VI_ftype_VIVI,2)
6811 // tag : V6_vsubb_128B
6812 def int_hexagon_V6_vsubb_128B :
6813 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubb_128B">;
6814
6815 //
6816 // BUILTIN_INFO(HEXAGON.V6_vaddb_dv,VD_ftype_VDVD,2)
6817 // tag : V6_vaddb_dv
6818 def int_hexagon_V6_vaddb_dv :
6819 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddb_dv">;
6820
6821 //
6822 // BUILTIN_INFO(HEXAGON.V6_vaddb_dv_128B,VD_ftype_VDVD,2)
6823 // tag : V6_vaddb_dv_128B
6824 def int_hexagon_V6_vaddb_dv_128B :
6825 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">;
6826
6827 //
6828 // BUILTIN_INFO(HEXAGON.V6_vsubb_dv,VD_ftype_VDVD,2)
6829 // tag : V6_vsubb_dv
6830 def int_hexagon_V6_vsubb_dv :
6831 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubb_dv">;
6832
6833 //
6834 // BUILTIN_INFO(HEXAGON.V6_vsubb_dv_128B,VD_ftype_VDVD,2)
6835 // tag : V6_vsubb_dv_128B
6836 def int_hexagon_V6_vsubb_dv_128B :
6837 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">;
6838
6839 //
6840 // BUILTIN_INFO(HEXAGON.V6_vaddh,VI_ftype_VIVI,2)
6841 // tag : V6_vaddh
6842 def int_hexagon_V6_vaddh :
6843 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddh">;
6844
6845 //
6846 // BUILTIN_INFO(HEXAGON.V6_vaddh_128B,VI_ftype_VIVI,2)
6847 // tag : V6_vaddh_128B
6848 def int_hexagon_V6_vaddh_128B :
6849 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddh_128B">;
6850
6851 //
6852 // BUILTIN_INFO(HEXAGON.V6_vsubh,VI_ftype_VIVI,2)
6853 // tag : V6_vsubh
6854 def int_hexagon_V6_vsubh :
6855 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubh">;
6856
6857 //
6858 // BUILTIN_INFO(HEXAGON.V6_vsubh_128B,VI_ftype_VIVI,2)
6859 // tag : V6_vsubh_128B
6860 def int_hexagon_V6_vsubh_128B :
6861 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubh_128B">;
6862
6863 //
6864 // BUILTIN_INFO(HEXAGON.V6_vaddh_dv,VD_ftype_VDVD,2)
6865 // tag : V6_vaddh_dv
6866 def int_hexagon_V6_vaddh_dv :
6867 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddh_dv">;
6868
6869 //
6870 // BUILTIN_INFO(HEXAGON.V6_vaddh_dv_128B,VD_ftype_VDVD,2)
6871 // tag : V6_vaddh_dv_128B
6872 def int_hexagon_V6_vaddh_dv_128B :
6873 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">;
6874
6875 //
6876 // BUILTIN_INFO(HEXAGON.V6_vsubh_dv,VD_ftype_VDVD,2)
6877 // tag : V6_vsubh_dv
6878 def int_hexagon_V6_vsubh_dv :
6879 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubh_dv">;
6880
6881 //
6882 // BUILTIN_INFO(HEXAGON.V6_vsubh_dv_128B,VD_ftype_VDVD,2)
6883 // tag : V6_vsubh_dv_128B
6884 def int_hexagon_V6_vsubh_dv_128B :
6885 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">;
6886
6887 //
6888 // BUILTIN_INFO(HEXAGON.V6_vaddw,VI_ftype_VIVI,2)
6889 // tag : V6_vaddw
6890 def int_hexagon_V6_vaddw :
6891 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddw">;
6892
6893 //
6894 // BUILTIN_INFO(HEXAGON.V6_vaddw_128B,VI_ftype_VIVI,2)
6895 // tag : V6_vaddw_128B
6896 def int_hexagon_V6_vaddw_128B :
6897 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddw_128B">;
6898
6899 //
6900 // BUILTIN_INFO(HEXAGON.V6_vsubw,VI_ftype_VIVI,2)
6901 // tag : V6_vsubw
6902 def int_hexagon_V6_vsubw :
6903 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubw">;
6904
6905 //
6906 // BUILTIN_INFO(HEXAGON.V6_vsubw_128B,VI_ftype_VIVI,2)
6907 // tag : V6_vsubw_128B
6908 def int_hexagon_V6_vsubw_128B :
6909 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubw_128B">;
6910
6911 //
6912 // BUILTIN_INFO(HEXAGON.V6_vaddw_dv,VD_ftype_VDVD,2)
6913 // tag : V6_vaddw_dv
6914 def int_hexagon_V6_vaddw_dv :
6915 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddw_dv">;
6916
6917 //
6918 // BUILTIN_INFO(HEXAGON.V6_vaddw_dv_128B,VD_ftype_VDVD,2)
6919 // tag : V6_vaddw_dv_128B
6920 def int_hexagon_V6_vaddw_dv_128B :
6921 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">;
6922
6923 //
6924 // BUILTIN_INFO(HEXAGON.V6_vsubw_dv,VD_ftype_VDVD,2)
6925 // tag : V6_vsubw_dv
6926 def int_hexagon_V6_vsubw_dv :
6927 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubw_dv">;
6928
6929 //
6930 // BUILTIN_INFO(HEXAGON.V6_vsubw_dv_128B,VD_ftype_VDVD,2)
6931 // tag : V6_vsubw_dv_128B
6932 def int_hexagon_V6_vsubw_dv_128B :
6933 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">;
6934
6935 //
6936 // BUILTIN_INFO(HEXAGON.V6_vaddubsat,VI_ftype_VIVI,2)
6937 // tag : V6_vaddubsat
6938 def int_hexagon_V6_vaddubsat :
6939 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddubsat">;
6940
6941 //
6942 // BUILTIN_INFO(HEXAGON.V6_vaddubsat_128B,VI_ftype_VIVI,2)
6943 // tag : V6_vaddubsat_128B
6944 def int_hexagon_V6_vaddubsat_128B :
6945 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddubsat_128B">;
6946
6947 //
6948 // BUILTIN_INFO(HEXAGON.V6_vaddubsat_dv,VD_ftype_VDVD,2)
6949 // tag : V6_vaddubsat_dv
6950 def int_hexagon_V6_vaddubsat_dv :
6951 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddubsat_dv">;
6952
6953 //
6954 // BUILTIN_INFO(HEXAGON.V6_vaddubsat_dv_128B,VD_ftype_VDVD,2)
6955 // tag : V6_vaddubsat_dv_128B
6956 def int_hexagon_V6_vaddubsat_dv_128B :
6957 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">;
6958
6959 //
6960 // BUILTIN_INFO(HEXAGON.V6_vsububsat,VI_ftype_VIVI,2)
6961 // tag : V6_vsububsat
6962 def int_hexagon_V6_vsububsat :
6963 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsububsat">;
6964
6965 //
6966 // BUILTIN_INFO(HEXAGON.V6_vsububsat_128B,VI_ftype_VIVI,2)
6967 // tag : V6_vsububsat_128B
6968 def int_hexagon_V6_vsububsat_128B :
6969 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsububsat_128B">;
6970
6971 //
6972 // BUILTIN_INFO(HEXAGON.V6_vsububsat_dv,VD_ftype_VDVD,2)
6973 // tag : V6_vsububsat_dv
6974 def int_hexagon_V6_vsububsat_dv :
6975 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsububsat_dv">;
6976
6977 //
6978 // BUILTIN_INFO(HEXAGON.V6_vsububsat_dv_128B,VD_ftype_VDVD,2)
6979 // tag : V6_vsububsat_dv_128B
6980 def int_hexagon_V6_vsububsat_dv_128B :
6981 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">;
6982
6983 //
6984 // BUILTIN_INFO(HEXAGON.V6_vadduhsat,VI_ftype_VIVI,2)
6985 // tag : V6_vadduhsat
6986 def int_hexagon_V6_vadduhsat :
6987 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vadduhsat">;
6988
6989 //
6990 // BUILTIN_INFO(HEXAGON.V6_vadduhsat_128B,VI_ftype_VIVI,2)
6991 // tag : V6_vadduhsat_128B
6992 def int_hexagon_V6_vadduhsat_128B :
6993 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduhsat_128B">;
6994
6995 //
6996 // BUILTIN_INFO(HEXAGON.V6_vadduhsat_dv,VD_ftype_VDVD,2)
6997 // tag : V6_vadduhsat_dv
6998 def int_hexagon_V6_vadduhsat_dv :
6999 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduhsat_dv">;
7000
7001 //
7002 // BUILTIN_INFO(HEXAGON.V6_vadduhsat_dv_128B,VD_ftype_VDVD,2)
7003 // tag : V6_vadduhsat_dv_128B
7004 def int_hexagon_V6_vadduhsat_dv_128B :
7005 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">;
7006
7007 //
7008 // BUILTIN_INFO(HEXAGON.V6_vsubuhsat,VI_ftype_VIVI,2)
7009 // tag : V6_vsubuhsat
7010 def int_hexagon_V6_vsubuhsat :
7011 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubuhsat">;
7012
7013 //
7014 // BUILTIN_INFO(HEXAGON.V6_vsubuhsat_128B,VI_ftype_VIVI,2)
7015 // tag : V6_vsubuhsat_128B
7016 def int_hexagon_V6_vsubuhsat_128B :
7017 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">;
7018
7019 //
7020 // BUILTIN_INFO(HEXAGON.V6_vsubuhsat_dv,VD_ftype_VDVD,2)
7021 // tag : V6_vsubuhsat_dv
7022 def int_hexagon_V6_vsubuhsat_dv :
7023 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">;
7024
7025 //
7026 // BUILTIN_INFO(HEXAGON.V6_vsubuhsat_dv_128B,VD_ftype_VDVD,2)
7027 // tag : V6_vsubuhsat_dv_128B
7028 def int_hexagon_V6_vsubuhsat_dv_128B :
7029 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">;
7030
7031 //
7032 // BUILTIN_INFO(HEXAGON.V6_vaddhsat,VI_ftype_VIVI,2)
7033 // tag : V6_vaddhsat
7034 def int_hexagon_V6_vaddhsat :
7035 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddhsat">;
7036
7037 //
7038 // BUILTIN_INFO(HEXAGON.V6_vaddhsat_128B,VI_ftype_VIVI,2)
7039 // tag : V6_vaddhsat_128B
7040 def int_hexagon_V6_vaddhsat_128B :
7041 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddhsat_128B">;
7042
7043 //
7044 // BUILTIN_INFO(HEXAGON.V6_vaddhsat_dv,VD_ftype_VDVD,2)
7045 // tag : V6_vaddhsat_dv
7046 def int_hexagon_V6_vaddhsat_dv :
7047 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddhsat_dv">;
7048
7049 //
7050 // BUILTIN_INFO(HEXAGON.V6_vaddhsat_dv_128B,VD_ftype_VDVD,2)
7051 // tag : V6_vaddhsat_dv_128B
7052 def int_hexagon_V6_vaddhsat_dv_128B :
7053 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">;
7054
7055 //
7056 // BUILTIN_INFO(HEXAGON.V6_vsubhsat,VI_ftype_VIVI,2)
7057 // tag : V6_vsubhsat
7058 def int_hexagon_V6_vsubhsat :
7059 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubhsat">;
7060
7061 //
7062 // BUILTIN_INFO(HEXAGON.V6_vsubhsat_128B,VI_ftype_VIVI,2)
7063 // tag : V6_vsubhsat_128B
7064 def int_hexagon_V6_vsubhsat_128B :
7065 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubhsat_128B">;
7066
7067 //
7068 // BUILTIN_INFO(HEXAGON.V6_vsubhsat_dv,VD_ftype_VDVD,2)
7069 // tag : V6_vsubhsat_dv
7070 def int_hexagon_V6_vsubhsat_dv :
7071 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubhsat_dv">;
7072
7073 //
7074 // BUILTIN_INFO(HEXAGON.V6_vsubhsat_dv_128B,VD_ftype_VDVD,2)
7075 // tag : V6_vsubhsat_dv_128B
7076 def int_hexagon_V6_vsubhsat_dv_128B :
7077 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">;
7078
7079 //
7080 // BUILTIN_INFO(HEXAGON.V6_vaddwsat,VI_ftype_VIVI,2)
7081 // tag : V6_vaddwsat
7082 def int_hexagon_V6_vaddwsat :
7083 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddwsat">;
7084
7085 //
7086 // BUILTIN_INFO(HEXAGON.V6_vaddwsat_128B,VI_ftype_VIVI,2)
7087 // tag : V6_vaddwsat_128B
7088 def int_hexagon_V6_vaddwsat_128B :
7089 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddwsat_128B">;
7090
7091 //
7092 // BUILTIN_INFO(HEXAGON.V6_vaddwsat_dv,VD_ftype_VDVD,2)
7093 // tag : V6_vaddwsat_dv
7094 def int_hexagon_V6_vaddwsat_dv :
7095 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddwsat_dv">;
7096
7097 //
7098 // BUILTIN_INFO(HEXAGON.V6_vaddwsat_dv_128B,VD_ftype_VDVD,2)
7099 // tag : V6_vaddwsat_dv_128B
7100 def int_hexagon_V6_vaddwsat_dv_128B :
7101 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">;
7102
7103 //
7104 // BUILTIN_INFO(HEXAGON.V6_vsubwsat,VI_ftype_VIVI,2)
7105 // tag : V6_vsubwsat
7106 def int_hexagon_V6_vsubwsat :
7107 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubwsat">;
7108
7109 //
7110 // BUILTIN_INFO(HEXAGON.V6_vsubwsat_128B,VI_ftype_VIVI,2)
7111 // tag : V6_vsubwsat_128B
7112 def int_hexagon_V6_vsubwsat_128B :
7113 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubwsat_128B">;
7114
7115 //
7116 // BUILTIN_INFO(HEXAGON.V6_vsubwsat_dv,VD_ftype_VDVD,2)
7117 // tag : V6_vsubwsat_dv
7118 def int_hexagon_V6_vsubwsat_dv :
7119 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubwsat_dv">;
7120
7121 //
7122 // BUILTIN_INFO(HEXAGON.V6_vsubwsat_dv_128B,VD_ftype_VDVD,2)
7123 // tag : V6_vsubwsat_dv_128B
7124 def int_hexagon_V6_vsubwsat_dv_128B :
7125 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">;
7126
7127 //
7128 // BUILTIN_INFO(HEXAGON.V6_vavgub,VI_ftype_VIVI,2)
7129 // tag : V6_vavgub
7130 def int_hexagon_V6_vavgub :
7131 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgub">;
7132
7133 //
7134 // BUILTIN_INFO(HEXAGON.V6_vavgub_128B,VI_ftype_VIVI,2)
7135 // tag : V6_vavgub_128B
7136 def int_hexagon_V6_vavgub_128B :
7137 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgub_128B">;
7138
7139 //
7140 // BUILTIN_INFO(HEXAGON.V6_vavgubrnd,VI_ftype_VIVI,2)
7141 // tag : V6_vavgubrnd
7142 def int_hexagon_V6_vavgubrnd :
7143 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgubrnd">;
7144
7145 //
7146 // BUILTIN_INFO(HEXAGON.V6_vavgubrnd_128B,VI_ftype_VIVI,2)
7147 // tag : V6_vavgubrnd_128B
7148 def int_hexagon_V6_vavgubrnd_128B :
7149 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">;
7150
7151 //
7152 // BUILTIN_INFO(HEXAGON.V6_vavguh,VI_ftype_VIVI,2)
7153 // tag : V6_vavguh
7154 def int_hexagon_V6_vavguh :
7155 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavguh">;
7156
7157 //
7158 // BUILTIN_INFO(HEXAGON.V6_vavguh_128B,VI_ftype_VIVI,2)
7159 // tag : V6_vavguh_128B
7160 def int_hexagon_V6_vavguh_128B :
7161 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguh_128B">;
7162
7163 //
7164 // BUILTIN_INFO(HEXAGON.V6_vavguhrnd,VI_ftype_VIVI,2)
7165 // tag : V6_vavguhrnd
7166 def int_hexagon_V6_vavguhrnd :
7167 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavguhrnd">;
7168
7169 //
7170 // BUILTIN_INFO(HEXAGON.V6_vavguhrnd_128B,VI_ftype_VIVI,2)
7171 // tag : V6_vavguhrnd_128B
7172 def int_hexagon_V6_vavguhrnd_128B :
7173 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">;
7174
7175 //
7176 // BUILTIN_INFO(HEXAGON.V6_vavgh,VI_ftype_VIVI,2)
7177 // tag : V6_vavgh
7178 def int_hexagon_V6_vavgh :
7179 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgh">;
7180
7181 //
7182 // BUILTIN_INFO(HEXAGON.V6_vavgh_128B,VI_ftype_VIVI,2)
7183 // tag : V6_vavgh_128B
7184 def int_hexagon_V6_vavgh_128B :
7185 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgh_128B">;
7186
7187 //
7188 // BUILTIN_INFO(HEXAGON.V6_vavghrnd,VI_ftype_VIVI,2)
7189 // tag : V6_vavghrnd
7190 def int_hexagon_V6_vavghrnd :
7191 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavghrnd">;
7192
7193 //
7194 // BUILTIN_INFO(HEXAGON.V6_vavghrnd_128B,VI_ftype_VIVI,2)
7195 // tag : V6_vavghrnd_128B
7196 def int_hexagon_V6_vavghrnd_128B :
7197 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavghrnd_128B">;
7198
7199 //
7200 // BUILTIN_INFO(HEXAGON.V6_vnavgh,VI_ftype_VIVI,2)
7201 // tag : V6_vnavgh
7202 def int_hexagon_V6_vnavgh :
7203 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgh">;
7204
7205 //
7206 // BUILTIN_INFO(HEXAGON.V6_vnavgh_128B,VI_ftype_VIVI,2)
7207 // tag : V6_vnavgh_128B
7208 def int_hexagon_V6_vnavgh_128B :
7209 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgh_128B">;
7210
7211 //
7212 // BUILTIN_INFO(HEXAGON.V6_vavgw,VI_ftype_VIVI,2)
7213 // tag : V6_vavgw
7214 def int_hexagon_V6_vavgw :
7215 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgw">;
7216
7217 //
7218 // BUILTIN_INFO(HEXAGON.V6_vavgw_128B,VI_ftype_VIVI,2)
7219 // tag : V6_vavgw_128B
7220 def int_hexagon_V6_vavgw_128B :
7221 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgw_128B">;
7222
7223 //
7224 // BUILTIN_INFO(HEXAGON.V6_vavgwrnd,VI_ftype_VIVI,2)
7225 // tag : V6_vavgwrnd
7226 def int_hexagon_V6_vavgwrnd :
7227 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgwrnd">;
7228
7229 //
7230 // BUILTIN_INFO(HEXAGON.V6_vavgwrnd_128B,VI_ftype_VIVI,2)
7231 // tag : V6_vavgwrnd_128B
7232 def int_hexagon_V6_vavgwrnd_128B :
7233 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">;
7234
7235 //
7236 // BUILTIN_INFO(HEXAGON.V6_vnavgw,VI_ftype_VIVI,2)
7237 // tag : V6_vnavgw
7238 def int_hexagon_V6_vnavgw :
7239 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgw">;
7240
7241 //
7242 // BUILTIN_INFO(HEXAGON.V6_vnavgw_128B,VI_ftype_VIVI,2)
7243 // tag : V6_vnavgw_128B
7244 def int_hexagon_V6_vnavgw_128B :
7245 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgw_128B">;
7246
7247 //
7248 // BUILTIN_INFO(HEXAGON.V6_vabsdiffub,VI_ftype_VIVI,2)
7249 // tag : V6_vabsdiffub
7250 def int_hexagon_V6_vabsdiffub :
7251 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffub">;
7252
7253 //
7254 // BUILTIN_INFO(HEXAGON.V6_vabsdiffub_128B,VI_ftype_VIVI,2)
7255 // tag : V6_vabsdiffub_128B
7256 def int_hexagon_V6_vabsdiffub_128B :
7257 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">;
7258
7259 //
7260 // BUILTIN_INFO(HEXAGON.V6_vabsdiffuh,VI_ftype_VIVI,2)
7261 // tag : V6_vabsdiffuh
7262 def int_hexagon_V6_vabsdiffuh :
7263 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffuh">;
7264
7265 //
7266 // BUILTIN_INFO(HEXAGON.V6_vabsdiffuh_128B,VI_ftype_VIVI,2)
7267 // tag : V6_vabsdiffuh_128B
7268 def int_hexagon_V6_vabsdiffuh_128B :
7269 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">;
7270
7271 //
7272 // BUILTIN_INFO(HEXAGON.V6_vabsdiffh,VI_ftype_VIVI,2)
7273 // tag : V6_vabsdiffh
7274 def int_hexagon_V6_vabsdiffh :
7275 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffh">;
7276
7277 //
7278 // BUILTIN_INFO(HEXAGON.V6_vabsdiffh_128B,VI_ftype_VIVI,2)
7279 // tag : V6_vabsdiffh_128B
7280 def int_hexagon_V6_vabsdiffh_128B :
7281 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">;
7282
7283 //
7284 // BUILTIN_INFO(HEXAGON.V6_vabsdiffw,VI_ftype_VIVI,2)
7285 // tag : V6_vabsdiffw
7286 def int_hexagon_V6_vabsdiffw :
7287 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffw">;
7288
7289 //
7290 // BUILTIN_INFO(HEXAGON.V6_vabsdiffw_128B,VI_ftype_VIVI,2)
7291 // tag : V6_vabsdiffw_128B
7292 def int_hexagon_V6_vabsdiffw_128B :
7293 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">;
7294
7295 //
7296 // BUILTIN_INFO(HEXAGON.V6_vnavgub,VI_ftype_VIVI,2)
7297 // tag : V6_vnavgub
7298 def int_hexagon_V6_vnavgub :
7299 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgub">;
7300
7301 //
7302 // BUILTIN_INFO(HEXAGON.V6_vnavgub_128B,VI_ftype_VIVI,2)
7303 // tag : V6_vnavgub_128B
7304 def int_hexagon_V6_vnavgub_128B :
7305 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgub_128B">;
7306
7307 //
7308 // BUILTIN_INFO(HEXAGON.V6_vaddubh,VD_ftype_VIVI,2)
7309 // tag : V6_vaddubh
7310 def int_hexagon_V6_vaddubh :
7311 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vaddubh">;
7312
7313 //
7314 // BUILTIN_INFO(HEXAGON.V6_vaddubh_128B,VD_ftype_VIVI,2)
7315 // tag : V6_vaddubh_128B
7316 def int_hexagon_V6_vaddubh_128B :
7317 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddubh_128B">;
7318
7319 //
7320 // BUILTIN_INFO(HEXAGON.V6_vsububh,VD_ftype_VIVI,2)
7321 // tag : V6_vsububh
7322 def int_hexagon_V6_vsububh :
7323 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsububh">;
7324
7325 //
7326 // BUILTIN_INFO(HEXAGON.V6_vsububh_128B,VD_ftype_VIVI,2)
7327 // tag : V6_vsububh_128B
7328 def int_hexagon_V6_vsububh_128B :
7329 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsububh_128B">;
7330
7331 //
7332 // BUILTIN_INFO(HEXAGON.V6_vaddhw,VD_ftype_VIVI,2)
7333 // tag : V6_vaddhw
7334 def int_hexagon_V6_vaddhw :
7335 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vaddhw">;
7336
7337 //
7338 // BUILTIN_INFO(HEXAGON.V6_vaddhw_128B,VD_ftype_VIVI,2)
7339 // tag : V6_vaddhw_128B
7340 def int_hexagon_V6_vaddhw_128B :
7341 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddhw_128B">;
7342
7343 //
7344 // BUILTIN_INFO(HEXAGON.V6_vsubhw,VD_ftype_VIVI,2)
7345 // tag : V6_vsubhw
7346 def int_hexagon_V6_vsubhw :
7347 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsubhw">;
7348
7349 //
7350 // BUILTIN_INFO(HEXAGON.V6_vsubhw_128B,VD_ftype_VIVI,2)
7351 // tag : V6_vsubhw_128B
7352 def int_hexagon_V6_vsubhw_128B :
7353 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsubhw_128B">;
7354
7355 //
7356 // BUILTIN_INFO(HEXAGON.V6_vadduhw,VD_ftype_VIVI,2)
7357 // tag : V6_vadduhw
7358 def int_hexagon_V6_vadduhw :
7359 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vadduhw">;
7360
7361 //
7362 // BUILTIN_INFO(HEXAGON.V6_vadduhw_128B,VD_ftype_VIVI,2)
7363 // tag : V6_vadduhw_128B
7364 def int_hexagon_V6_vadduhw_128B :
7365 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vadduhw_128B">;
7366
7367 //
7368 // BUILTIN_INFO(HEXAGON.V6_vsubuhw,VD_ftype_VIVI,2)
7369 // tag : V6_vsubuhw
7370 def int_hexagon_V6_vsubuhw :
7371 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsubuhw">;
7372
7373 //
7374 // BUILTIN_INFO(HEXAGON.V6_vsubuhw_128B,VD_ftype_VIVI,2)
7375 // tag : V6_vsubuhw_128B
7376 def int_hexagon_V6_vsubuhw_128B :
7377 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhw_128B">;
7378
7379 //
7380 // BUILTIN_INFO(HEXAGON.V6_vd0,VI_ftype_,0)
7381 // tag : V6_vd0
7382 def int_hexagon_V6_vd0 :
7383 Hexagon_v512_Intrinsic<"HEXAGON_V6_vd0">;
7384
7385 //
7386 // BUILTIN_INFO(HEXAGON.V6_vd0_128B,VI_ftype_,0)
7387 // tag : V6_vd0_128B
7388 def int_hexagon_V6_vd0_128B :
7389 Hexagon_v1024_Intrinsic<"HEXAGON_V6_vd0_128B">;
7390
7391 //
7392 // BUILTIN_INFO(HEXAGON.V6_vaddbq,VI_ftype_QVVIVI,3)
7393 // tag : V6_vaddbq
7394 def int_hexagon_V6_vaddbq :
7395 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddbq">;
7396
7397 //
7398 // BUILTIN_INFO(HEXAGON.V6_vaddbq_128B,VI_ftype_QVVIVI,3)
7399 // tag : V6_vaddbq_128B
7400 def int_hexagon_V6_vaddbq_128B :
7401 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddbq_128B">;
7402
7403
7404 //
7405 // BUILTIN_INFO(HEXAGON.V6_vsubbq,VI_ftype_QVVIVI,3)
7406 // tag : V6_vsubbq
7407 def int_hexagon_V6_vsubbq :
7408 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubbq">;
7409
7410 //
7411 // BUILTIN_INFO(HEXAGON.V6_vsubbq_128B,VI_ftype_QVVIVI,3)
7412 // tag : V6_vsubbq_128B
7413 def int_hexagon_V6_vsubbq_128B :
7414 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubbq_128B">;
7415
7416 //
7417 // BUILTIN_INFO(HEXAGON.V6_vaddbnq,VI_ftype_QVVIVI,3)
7418 // tag : V6_vaddbnq
7419 def int_hexagon_V6_vaddbnq :
7420 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddbnq">;
7421
7422 //
7423 // BUILTIN_INFO(HEXAGON.V6_vaddbnq_128B,VI_ftype_QVVIVI,3)
7424 // tag : V6_vaddbnq_128B
7425 def int_hexagon_V6_vaddbnq_128B :
7426 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddbnq_128B">;
7427
7428 //
7429 // BUILTIN_INFO(HEXAGON.V6_vsubbnq,VI_ftype_QVVIVI,3)
7430 // tag : V6_vsubbnq
7431 def int_hexagon_V6_vsubbnq :
7432 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubbnq">;
7433
7434 //
7435 // BUILTIN_INFO(HEXAGON.V6_vsubbnq_128B,VI_ftype_QVVIVI,3)
7436 // tag : V6_vsubbnq_128B
7437 def int_hexagon_V6_vsubbnq_128B :
7438 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubbnq_128B">;
7439
7440 //
7441 // BUILTIN_INFO(HEXAGON.V6_vaddhq,VI_ftype_QVVIVI,3)
7442 // tag : V6_vaddhq
7443 def int_hexagon_V6_vaddhq :
7444 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddhq">;
7445
7446 //
7447 // BUILTIN_INFO(HEXAGON.V6_vaddhq_128B,VI_ftype_QVVIVI,3)
7448 // tag : V6_vaddhq_128B
7449 def int_hexagon_V6_vaddhq_128B :
7450 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddhq_128B">;
7451
7452 //
7453 // BUILTIN_INFO(HEXAGON.V6_vsubhq,VI_ftype_QVVIVI,3)
7454 // tag : V6_vsubhq
7455 def int_hexagon_V6_vsubhq :
7456 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubhq">;
7457
7458 //
7459 // BUILTIN_INFO(HEXAGON.V6_vsubhq_128B,VI_ftype_QVVIVI,3)
7460 // tag : V6_vsubhq_128B
7461 def int_hexagon_V6_vsubhq_128B :
7462 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubhq_128B">;
7463
7464 //
7465 // BUILTIN_INFO(HEXAGON.V6_vaddhnq,VI_ftype_QVVIVI,3)
7466 // tag : V6_vaddhnq
7467 def int_hexagon_V6_vaddhnq :
7468 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddhnq">;
7469
7470 //
7471 // BUILTIN_INFO(HEXAGON.V6_vaddhnq_128B,VI_ftype_QVVIVI,3)
7472 // tag : V6_vaddhnq_128B
7473 def int_hexagon_V6_vaddhnq_128B :
7474 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddhnq_128B">;
7475
7476 //
7477 // BUILTIN_INFO(HEXAGON.V6_vsubhnq,VI_ftype_QVVIVI,3)
7478 // tag : V6_vsubhnq
7479 def int_hexagon_V6_vsubhnq :
7480 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubhnq">;
7481
7482 //
7483 // BUILTIN_INFO(HEXAGON.V6_vsubhnq_128B,VI_ftype_QVVIVI,3)
7484 // tag : V6_vsubhnq_128B
7485 def int_hexagon_V6_vsubhnq_128B :
7486 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubhnq_128B">;
7487
7488 //
7489 // BUILTIN_INFO(HEXAGON.V6_vaddwq,VI_ftype_QVVIVI,3)
7490 // tag : V6_vaddwq
7491 def int_hexagon_V6_vaddwq :
7492 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddwq">;
7493
7494 //
7495 // BUILTIN_INFO(HEXAGON.V6_vaddwq_128B,VI_ftype_QVVIVI,3)
7496 // tag : V6_vaddwq_128B
7497 def int_hexagon_V6_vaddwq_128B :
7498 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddwq_128B">;
7499
7500 //
7501 // BUILTIN_INFO(HEXAGON.V6_vsubwq,VI_ftype_QVVIVI,3)
7502 // tag : V6_vsubwq
7503 def int_hexagon_V6_vsubwq :
7504 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubwq">;
7505
7506 //
7507 // BUILTIN_INFO(HEXAGON.V6_vsubwq_128B,VI_ftype_QVVIVI,3)
7508 // tag : V6_vsubwq_128B
7509 def int_hexagon_V6_vsubwq_128B :
7510 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubwq_128B">;
7511
7512 //
7513 // BUILTIN_INFO(HEXAGON.V6_vaddwnq,VI_ftype_QVVIVI,3)
7514 // tag : V6_vaddwnq
7515 def int_hexagon_V6_vaddwnq :
7516 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddwnq">;
7517
7518 //
7519 // BUILTIN_INFO(HEXAGON.V6_vaddwnq_128B,VI_ftype_QVVIVI,3)
7520 // tag : V6_vaddwnq_128B
7521 def int_hexagon_V6_vaddwnq_128B :
7522 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddwnq_128B">;
7523
7524 //
7525 // BUILTIN_INFO(HEXAGON.V6_vsubwnq,VI_ftype_QVVIVI,3)
7526 // tag : V6_vsubwnq
7527 def int_hexagon_V6_vsubwnq :
7528 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubwnq">;
7529
7530 //
7531 // BUILTIN_INFO(HEXAGON.V6_vsubwnq_128B,VI_ftype_QVVIVI,3)
7532 // tag : V6_vsubwnq_128B
7533 def int_hexagon_V6_vsubwnq_128B :
7534 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubwnq_128B">;
7535
7536 //
7537 // BUILTIN_INFO(HEXAGON.V6_vabsh,VI_ftype_VI,1)
7538 // tag : V6_vabsh
7539 def int_hexagon_V6_vabsh :
7540 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsh">;
7541
7542 //
7543 // BUILTIN_INFO(HEXAGON.V6_vabsh_128B,VI_ftype_VI,1)
7544 // tag : V6_vabsh_128B
7545 def int_hexagon_V6_vabsh_128B :
7546 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsh_128B">;
7547
7548 //
7549 // BUILTIN_INFO(HEXAGON.V6_vabsh_sat,VI_ftype_VI,1)
7550 // tag : V6_vabsh_sat
7551 def int_hexagon_V6_vabsh_sat :
7552 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsh_sat">;
7553
7554 //
7555 // BUILTIN_INFO(HEXAGON.V6_vabsh_sat_128B,VI_ftype_VI,1)
7556 // tag : V6_vabsh_sat_128B
7557 def int_hexagon_V6_vabsh_sat_128B :
7558 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">;
7559
7560 //
7561 // BUILTIN_INFO(HEXAGON.V6_vabsw,VI_ftype_VI,1)
7562 // tag : V6_vabsw
7563 def int_hexagon_V6_vabsw :
7564 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsw">;
7565
7566 //
7567 // BUILTIN_INFO(HEXAGON.V6_vabsw_128B,VI_ftype_VI,1)
7568 // tag : V6_vabsw_128B
7569 def int_hexagon_V6_vabsw_128B :
7570 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsw_128B">;
7571
7572 //
7573 // BUILTIN_INFO(HEXAGON.V6_vabsw_sat,VI_ftype_VI,1)
7574 // tag : V6_vabsw_sat
7575 def int_hexagon_V6_vabsw_sat :
7576 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsw_sat">;
7577
7578 //
7579 // BUILTIN_INFO(HEXAGON.V6_vabsw_sat_128B,VI_ftype_VI,1)
7580 // tag : V6_vabsw_sat_128B
7581 def int_hexagon_V6_vabsw_sat_128B :
7582 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">;
7583
7584 //
7585 // BUILTIN_INFO(HEXAGON.V6_vmpybv,VD_ftype_VIVI,2)
7586 // tag : V6_vmpybv
7587 def int_hexagon_V6_vmpybv :
7588 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybv">;
7589
7590 //
7591 // BUILTIN_INFO(HEXAGON.V6_vmpybv_128B,VD_ftype_VIVI,2)
7592 // tag : V6_vmpybv_128B
7593 def int_hexagon_V6_vmpybv_128B :
7594 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybv_128B">;
7595
7596 //
7597 // BUILTIN_INFO(HEXAGON.V6_vmpybv_acc,VD_ftype_VDVIVI,3)
7598 // tag : V6_vmpybv_acc
7599 def int_hexagon_V6_vmpybv_acc :
7600 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybv_acc">;
7601
7602 //
7603 // BUILTIN_INFO(HEXAGON.V6_vmpybv_acc_128B,VD_ftype_VDVIVI,3)
7604 // tag : V6_vmpybv_acc_128B
7605 def int_hexagon_V6_vmpybv_acc_128B :
7606 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">;
7607
7608 //
7609 // BUILTIN_INFO(HEXAGON.V6_vmpyubv,VD_ftype_VIVI,2)
7610 // tag : V6_vmpyubv
7611 def int_hexagon_V6_vmpyubv :
7612 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyubv">;
7613
7614 //
7615 // BUILTIN_INFO(HEXAGON.V6_vmpyubv_128B,VD_ftype_VIVI,2)
7616 // tag : V6_vmpyubv_128B
7617 def int_hexagon_V6_vmpyubv_128B :
7618 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyubv_128B">;
7619
7620 //
7621 // BUILTIN_INFO(HEXAGON.V6_vmpyubv_acc,VD_ftype_VDVIVI,3)
7622 // tag : V6_vmpyubv_acc
7623 def int_hexagon_V6_vmpyubv_acc :
7624 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyubv_acc">;
7625
7626 //
7627 // BUILTIN_INFO(HEXAGON.V6_vmpyubv_acc_128B,VD_ftype_VDVIVI,3)
7628 // tag : V6_vmpyubv_acc_128B
7629 def int_hexagon_V6_vmpyubv_acc_128B :
7630 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">;
7631
7632 //
7633 // BUILTIN_INFO(HEXAGON.V6_vmpybusv,VD_ftype_VIVI,2)
7634 // tag : V6_vmpybusv
7635 def int_hexagon_V6_vmpybusv :
7636 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybusv">;
7637
7638 //
7639 // BUILTIN_INFO(HEXAGON.V6_vmpybusv_128B,VD_ftype_VIVI,2)
7640 // tag : V6_vmpybusv_128B
7641 def int_hexagon_V6_vmpybusv_128B :
7642 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybusv_128B">;
7643
7644 //
7645 // BUILTIN_INFO(HEXAGON.V6_vmpybusv_acc,VD_ftype_VDVIVI,3)
7646 // tag : V6_vmpybusv_acc
7647 def int_hexagon_V6_vmpybusv_acc :
7648 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybusv_acc">;
7649
7650 //
7651 // BUILTIN_INFO(HEXAGON.V6_vmpybusv_acc_128B,VD_ftype_VDVIVI,3)
7652 // tag : V6_vmpybusv_acc_128B
7653 def int_hexagon_V6_vmpybusv_acc_128B :
7654 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">;
7655
7656 //
7657 // BUILTIN_INFO(HEXAGON.V6_vmpabusv,VD_ftype_VDVD,2)
7658 // tag : V6_vmpabusv
7659 def int_hexagon_V6_vmpabusv :
7660 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpabusv">;
7661
7662 //
7663 // BUILTIN_INFO(HEXAGON.V6_vmpabusv_128B,VD_ftype_VDVD,2)
7664 // tag : V6_vmpabusv_128B
7665 def int_hexagon_V6_vmpabusv_128B :
7666 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vmpabusv_128B">;
7667
7668 //
7669 // BUILTIN_INFO(HEXAGON.V6_vmpabuuv,VD_ftype_VDVD,2)
7670 // tag : V6_vmpabuuv
7671 def int_hexagon_V6_vmpabuuv :
7672 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpabuuv">;
7673
7674 //
7675 // BUILTIN_INFO(HEXAGON.V6_vmpabuuv_128B,VD_ftype_VDVD,2)
7676 // tag : V6_vmpabuuv_128B
7677 def int_hexagon_V6_vmpabuuv_128B :
7678 Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">;
7679
7680 //
7681 // BUILTIN_INFO(HEXAGON.V6_vmpyhv,VD_ftype_VIVI,2)
7682 // tag : V6_vmpyhv
7683 def int_hexagon_V6_vmpyhv :
7684 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhv">;
7685
7686 //
7687 // BUILTIN_INFO(HEXAGON.V6_vmpyhv_128B,VD_ftype_VIVI,2)
7688 // tag : V6_vmpyhv_128B
7689 def int_hexagon_V6_vmpyhv_128B :
7690 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhv_128B">;
7691
7692 //
7693 // BUILTIN_INFO(HEXAGON.V6_vmpyhv_acc,VD_ftype_VDVIVI,3)
7694 // tag : V6_vmpyhv_acc
7695 def int_hexagon_V6_vmpyhv_acc :
7696 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhv_acc">;
7697
7698 //
7699 // BUILTIN_INFO(HEXAGON.V6_vmpyhv_acc_128B,VD_ftype_VDVIVI,3)
7700 // tag : V6_vmpyhv_acc_128B
7701 def int_hexagon_V6_vmpyhv_acc_128B :
7702 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">;
7703
7704 //
7705 // BUILTIN_INFO(HEXAGON.V6_vmpyuhv,VD_ftype_VIVI,2)
7706 // tag : V6_vmpyuhv
7707 def int_hexagon_V6_vmpyuhv :
7708 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyuhv">;
7709
7710 //
7711 // BUILTIN_INFO(HEXAGON.V6_vmpyuhv_128B,VD_ftype_VIVI,2)
7712 // tag : V6_vmpyuhv_128B
7713 def int_hexagon_V6_vmpyuhv_128B :
7714 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">;
7715
7716 //
7717 // BUILTIN_INFO(HEXAGON.V6_vmpyuhv_acc,VD_ftype_VDVIVI,3)
7718 // tag : V6_vmpyuhv_acc
7719 def int_hexagon_V6_vmpyuhv_acc :
7720 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">;
7721
7722 //
7723 // BUILTIN_INFO(HEXAGON.V6_vmpyuhv_acc_128B,VD_ftype_VDVIVI,3)
7724 // tag : V6_vmpyuhv_acc_128B
7725 def int_hexagon_V6_vmpyuhv_acc_128B :
7726 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">;
7727
7728 //
7729 // BUILTIN_INFO(HEXAGON.V6_vmpyhvsrs,VI_ftype_VIVI,2)
7730 // tag : V6_vmpyhvsrs
7731 def int_hexagon_V6_vmpyhvsrs :
7732 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyhvsrs">;
7733
7734 //
7735 // BUILTIN_INFO(HEXAGON.V6_vmpyhvsrs_128B,VI_ftype_VIVI,2)
7736 // tag : V6_vmpyhvsrs_128B
7737 def int_hexagon_V6_vmpyhvsrs_128B :
7738 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">;
7739
7740 //
7741 // BUILTIN_INFO(HEXAGON.V6_vmpyhus,VD_ftype_VIVI,2)
7742 // tag : V6_vmpyhus
7743 def int_hexagon_V6_vmpyhus :
7744 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhus">;
7745
7746 //
7747 // BUILTIN_INFO(HEXAGON.V6_vmpyhus_128B,VD_ftype_VIVI,2)
7748 // tag : V6_vmpyhus_128B
7749 def int_hexagon_V6_vmpyhus_128B :
7750 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhus_128B">;
7751
7752 //
7753 // BUILTIN_INFO(HEXAGON.V6_vmpyhus_acc,VD_ftype_VDVIVI,3)
7754 // tag : V6_vmpyhus_acc
7755 def int_hexagon_V6_vmpyhus_acc :
7756 Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhus_acc">;
7757
7758 //
7759 // BUILTIN_INFO(HEXAGON.V6_vmpyhus_acc_128B,VD_ftype_VDVIVI,3)
7760 // tag : V6_vmpyhus_acc_128B
7761 def int_hexagon_V6_vmpyhus_acc_128B :
7762 Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">;
7763
7764 //
7765 // BUILTIN_INFO(HEXAGON.V6_vmpyih,VI_ftype_VIVI,2)
7766 // tag : V6_vmpyih
7767 def int_hexagon_V6_vmpyih :
7768 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyih">;
7769
7770 //
7771 // BUILTIN_INFO(HEXAGON.V6_vmpyih_128B,VI_ftype_VIVI,2)
7772 // tag : V6_vmpyih_128B
7773 def int_hexagon_V6_vmpyih_128B :
7774 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyih_128B">;
7775
7776 //
7777 // BUILTIN_INFO(HEXAGON.V6_vmpyih_acc,VI_ftype_VIVIVI,3)
7778 // tag : V6_vmpyih_acc
7779 def int_hexagon_V6_vmpyih_acc :
7780 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyih_acc">;
7781
7782 //
7783 // BUILTIN_INFO(HEXAGON.V6_vmpyih_acc_128B,VI_ftype_VIVIVI,3)
7784 // tag : V6_vmpyih_acc_128B
7785 def int_hexagon_V6_vmpyih_acc_128B :
7786 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">;
7787
7788 //
7789 // BUILTIN_INFO(HEXAGON.V6_vmpyewuh,VI_ftype_VIVI,2)
7790 // tag : V6_vmpyewuh
7791 def int_hexagon_V6_vmpyewuh :
7792 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyewuh">;
7793
7794 //
7795 // BUILTIN_INFO(HEXAGON.V6_vmpyewuh_128B,VI_ftype_VIVI,2)
7796 // tag : V6_vmpyewuh_128B
7797 def int_hexagon_V6_vmpyewuh_128B :
7798 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">;
7799
7800 //
7801 // BUILTIN_INFO(HEXAGON.V6_vmpyowh,VI_ftype_VIVI,2)
7802 // tag : V6_vmpyowh
7803 def int_hexagon_V6_vmpyowh :
7804 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh">;
7805
7806 //
7807 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_128B,VI_ftype_VIVI,2)
7808 // tag : V6_vmpyowh_128B
7809 def int_hexagon_V6_vmpyowh_128B :
7810 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_128B">;
7811
7812 //
7813 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd,VI_ftype_VIVI,2)
7814 // tag : V6_vmpyowh_rnd
7815 def int_hexagon_V6_vmpyowh_rnd :
7816 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">;
7817
7818 //
7819 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_128B,VI_ftype_VIVI,2)
7820 // tag : V6_vmpyowh_rnd_128B
7821 def int_hexagon_V6_vmpyowh_rnd_128B :
7822 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">;
7823
7824 //
7825 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_sacc,VI_ftype_VIVIVI,3)
7826 // tag : V6_vmpyowh_sacc
7827 def int_hexagon_V6_vmpyowh_sacc :
7828 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">;
7829
7830 //
7831 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_sacc_128B,VI_ftype_VIVIVI,3)
7832 // tag : V6_vmpyowh_sacc_128B
7833 def int_hexagon_V6_vmpyowh_sacc_128B :
7834 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">;
7835
7836 //
7837 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_sacc,VI_ftype_VIVIVI,3)
7838 // tag : V6_vmpyowh_rnd_sacc
7839 def int_hexagon_V6_vmpyowh_rnd_sacc :
7840 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">;
7841
7842 //
7843 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_sacc_128B,VI_ftype_VIVIVI,3)
7844 // tag : V6_vmpyowh_rnd_sacc_128B
7845 def int_hexagon_V6_vmpyowh_rnd_sacc_128B :
7846 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">;
7847
7848 //
7849 // BUILTIN_INFO(HEXAGON.V6_vmpyieoh,VI_ftype_VIVI,2)
7850 // tag : V6_vmpyieoh
7851 def int_hexagon_V6_vmpyieoh :
7852 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyieoh">;
7853
7854 //
7855 // BUILTIN_INFO(HEXAGON.V6_vmpyieoh_128B,VI_ftype_VIVI,2)
7856 // tag : V6_vmpyieoh_128B
7857 def int_hexagon_V6_vmpyieoh_128B :
7858 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">;
7859
7860 //
7861 // BUILTIN_INFO(HEXAGON.V6_vmpyiewuh,VI_ftype_VIVI,2)
7862 // tag : V6_vmpyiewuh
7863 def int_hexagon_V6_vmpyiewuh :
7864 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewuh">;
7865
7866 //
7867 // BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_128B,VI_ftype_VIVI,2)
7868 // tag : V6_vmpyiewuh_128B
7869 def int_hexagon_V6_vmpyiewuh_128B :
7870 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">;
7871
7872 //
7873 // BUILTIN_INFO(HEXAGON.V6_vmpyiowh,VI_ftype_VIVI,2)
7874 // tag : V6_vmpyiowh
7875 def int_hexagon_V6_vmpyiowh :
7876 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiowh">;
7877
7878 //
7879 // BUILTIN_INFO(HEXAGON.V6_vmpyiowh_128B,VI_ftype_VIVI,2)
7880 // tag : V6_vmpyiowh_128B
7881 def int_hexagon_V6_vmpyiowh_128B :
7882 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">;
7883
7884 //
7885 // BUILTIN_INFO(HEXAGON.V6_vmpyiewh_acc,VI_ftype_VIVIVI,3)
7886 // tag : V6_vmpyiewh_acc
7887 def int_hexagon_V6_vmpyiewh_acc :
7888 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">;
7889
7890 //
7891 // BUILTIN_INFO(HEXAGON.V6_vmpyiewh_acc_128B,VI_ftype_VIVIVI,3)
7892 // tag : V6_vmpyiewh_acc_128B
7893 def int_hexagon_V6_vmpyiewh_acc_128B :
7894 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">;
7895
7896 //
7897 // BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_acc,VI_ftype_VIVIVI,3)
7898 // tag : V6_vmpyiewuh_acc
7899 def int_hexagon_V6_vmpyiewuh_acc :
7900 Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">;
7901
7902 //
7903 // BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_acc_128B,VI_ftype_VIVIVI,3)
7904 // tag : V6_vmpyiewuh_acc_128B
7905 def int_hexagon_V6_vmpyiewuh_acc_128B :
7906 Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">;
7907
7908 //
7909 // BUILTIN_INFO(HEXAGON.V6_vmpyub,VD_ftype_VISI,2)
7910 // tag : V6_vmpyub
7911 def int_hexagon_V6_vmpyub :
7912 Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyub">;
7913
7914 //
7915 // BUILTIN_INFO(HEXAGON.V6_vmpyub_128B,VD_ftype_VISI,2)
7916 // tag : V6_vmpyub_128B
7917 def int_hexagon_V6_vmpyub_128B :
7918 Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyub_128B">;
7919
7920 //
7921 // BUILTIN_INFO(HEXAGON.V6_vmpyub_acc,VD_ftype_VDVISI,3)
7922 // tag : V6_vmpyub_acc
7923 def int_hexagon_V6_vmpyub_acc :
7924 Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyub_acc">;
7925
7926 //
7927 // BUILTIN_INFO(HEXAGON.V6_vmpyub_acc_128B,VD_ftype_VDVISI,3)
7928 // tag : V6_vmpyub_acc_128B
7929 def int_hexagon_V6_vmpyub_acc_128B :
7930 Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">;
7931
7932 //
7933 // BUILTIN_INFO(HEXAGON.V6_vmpybus,VD_ftype_VISI,2)
7934 // tag : V6_vmpybus
7935 def int_hexagon_V6_vmpybus :
7936 Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpybus">;
7937
7938 //
7939 // BUILTIN_INFO(HEXAGON.V6_vmpybus_128B,VD_ftype_VISI,2)
7940 // tag : V6_vmpybus_128B
7941 def int_hexagon_V6_vmpybus_128B :
7942 Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpybus_128B">;
7943
7944 //
7945 // BUILTIN_INFO(HEXAGON.V6_vmpybus_acc,VD_ftype_VDVISI,3)
7946 // tag : V6_vmpybus_acc
7947 def int_hexagon_V6_vmpybus_acc :
7948 Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpybus_acc">;
7949
7950 //
7951 // BUILTIN_INFO(HEXAGON.V6_vmpybus_acc_128B,VD_ftype_VDVISI,3)
7952 // tag : V6_vmpybus_acc_128B
7953 def int_hexagon_V6_vmpybus_acc_128B :
7954 Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">;
7955
7956 //
7957 // BUILTIN_INFO(HEXAGON.V6_vmpabus,VD_ftype_VDSI,2)
7958 // tag : V6_vmpabus
7959 def int_hexagon_V6_vmpabus :
7960 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabus">;
7961
7962 //
7963 // BUILTIN_INFO(HEXAGON.V6_vmpabus_128B,VD_ftype_VDSI,2)
7964 // tag : V6_vmpabus_128B
7965 def int_hexagon_V6_vmpabus_128B :
7966 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabus_128B">;
7967
7968 //
7969 // BUILTIN_INFO(HEXAGON.V6_vmpabus_acc,VD_ftype_VDVDSI,3)
7970 // tag : V6_vmpabus_acc
7971 def int_hexagon_V6_vmpabus_acc :
7972 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabus_acc">;
7973
7974 //
7975 // BUILTIN_INFO(HEXAGON.V6_vmpabus_acc_128B,VD_ftype_VDVDSI,3)
7976 // tag : V6_vmpabus_acc_128B
7977 def int_hexagon_V6_vmpabus_acc_128B :
7978 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">;
7979
7980 //
7981 // BUILTIN_INFO(HEXAGON.V6_vmpahb,VD_ftype_VDSI,2)
7982 // tag : V6_vmpahb
7983 def int_hexagon_V6_vmpahb :
7984 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpahb">;
7985
7986 //
7987 // BUILTIN_INFO(HEXAGON.V6_vmpahb_128B,VD_ftype_VDSI,2)
7988 // tag : V6_vmpahb_128B
7989 def int_hexagon_V6_vmpahb_128B :
7990 Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpahb_128B">;
7991
7992 //
7993 // BUILTIN_INFO(HEXAGON.V6_vmpahb_acc,VD_ftype_VDVDSI,3)
7994 // tag : V6_vmpahb_acc
7995 def int_hexagon_V6_vmpahb_acc :
7996 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpahb_acc">;
7997
7998 //
7999 // BUILTIN_INFO(HEXAGON.V6_vmpahb_acc_128B,VD_ftype_VDVDSI,3)
8000 // tag : V6_vmpahb_acc_128B
8001 def int_hexagon_V6_vmpahb_acc_128B :
8002 Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">;
8003
8004 //
8005 // BUILTIN_INFO(HEXAGON.V6_vmpyh,VD_ftype_VISI,2)
8006 // tag : V6_vmpyh
8007 def int_hexagon_V6_vmpyh :
8008 Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh">;
8009
8010 //
8011 // BUILTIN_INFO(HEXAGON.V6_vmpyh_128B,VD_ftype_VISI,2)
8012 // tag : V6_vmpyh_128B
8013 def int_hexagon_V6_vmpyh_128B :
8014 Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_128B">;
8015
8016 //
8017 // BUILTIN_INFO(HEXAGON.V6_vmpyhsat_acc,VD_ftype_VDVISI,3)
8018 // tag : V6_vmpyhsat_acc
8019 def int_hexagon_V6_vmpyhsat_acc :
8020 Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">;
8021
8022 //
8023 // BUILTIN_INFO(HEXAGON.V6_vmpyhsat_acc_128B,VD_ftype_VDVISI,3)
8024 // tag : V6_vmpyhsat_acc_128B
8025 def int_hexagon_V6_vmpyhsat_acc_128B :
8026 Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">;
8027
8028 //
8029 // BUILTIN_INFO(HEXAGON.V6_vmpyhss,VI_ftype_VISI,2)
8030 // tag : V6_vmpyhss
8031 def int_hexagon_V6_vmpyhss :
8032 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyhss">;
8033
8034 //
8035 // BUILTIN_INFO(HEXAGON.V6_vmpyhss_128B,VI_ftype_VISI,2)
8036 // tag : V6_vmpyhss_128B
8037 def int_hexagon_V6_vmpyhss_128B :
8038 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyhss_128B">;
8039
8040 //
8041 // BUILTIN_INFO(HEXAGON.V6_vmpyhsrs,VI_ftype_VISI,2)
8042 // tag : V6_vmpyhsrs
8043 def int_hexagon_V6_vmpyhsrs :
8044 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyhsrs">;
8045
8046 //
8047 // BUILTIN_INFO(HEXAGON.V6_vmpyhsrs_128B,VI_ftype_VISI,2)
8048 // tag : V6_vmpyhsrs_128B
8049 def int_hexagon_V6_vmpyhsrs_128B :
8050 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">;
8051
8052 //
8053 // BUILTIN_INFO(HEXAGON.V6_vmpyuh,VD_ftype_VISI,2)
8054 // tag : V6_vmpyuh
8055 def int_hexagon_V6_vmpyuh :
8056 Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyuh">;
8057
8058 //
8059 // BUILTIN_INFO(HEXAGON.V6_vmpyuh_128B,VD_ftype_VISI,2)
8060 // tag : V6_vmpyuh_128B
8061 def int_hexagon_V6_vmpyuh_128B :
8062 Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyuh_128B">;
8063
8064 //
8065 // BUILTIN_INFO(HEXAGON.V6_vmpyuh_acc,VD_ftype_VDVISI,3)
8066 // tag : V6_vmpyuh_acc
8067 def int_hexagon_V6_vmpyuh_acc :
8068 Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyuh_acc">;
8069
8070 //
8071 // BUILTIN_INFO(HEXAGON.V6_vmpyuh_acc_128B,VD_ftype_VDVISI,3)
8072 // tag : V6_vmpyuh_acc_128B
8073 def int_hexagon_V6_vmpyuh_acc_128B :
8074 Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">;
8075
8076 //
8077 // BUILTIN_INFO(HEXAGON.V6_vmpyihb,VI_ftype_VISI,2)
8078 // tag : V6_vmpyihb
8079 def int_hexagon_V6_vmpyihb :
8080 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyihb">;
8081
8082 //
8083 // BUILTIN_INFO(HEXAGON.V6_vmpyihb_128B,VI_ftype_VISI,2)
8084 // tag : V6_vmpyihb_128B
8085 def int_hexagon_V6_vmpyihb_128B :
8086 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyihb_128B">;
8087
8088 //
8089 // BUILTIN_INFO(HEXAGON.V6_vmpyihb_acc,VI_ftype_VIVISI,3)
8090 // tag : V6_vmpyihb_acc
8091 def int_hexagon_V6_vmpyihb_acc :
8092 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyihb_acc">;
8093
8094 //
8095 // BUILTIN_INFO(HEXAGON.V6_vmpyihb_acc_128B,VI_ftype_VIVISI,3)
8096 // tag : V6_vmpyihb_acc_128B
8097 def int_hexagon_V6_vmpyihb_acc_128B :
8098 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">;
8099
8100 //
8101 // BUILTIN_INFO(HEXAGON.V6_vmpyiwb,VI_ftype_VISI,2)
8102 // tag : V6_vmpyiwb
8103 def int_hexagon_V6_vmpyiwb :
8104 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwb">;
8105
8106 //
8107 // BUILTIN_INFO(HEXAGON.V6_vmpyiwb_128B,VI_ftype_VISI,2)
8108 // tag : V6_vmpyiwb_128B
8109 def int_hexagon_V6_vmpyiwb_128B :
8110 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">;
8111
8112 //
8113 // BUILTIN_INFO(HEXAGON.V6_vmpyiwb_acc,VI_ftype_VIVISI,3)
8114 // tag : V6_vmpyiwb_acc
8115 def int_hexagon_V6_vmpyiwb_acc :
8116 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">;
8117
8118 //
8119 // BUILTIN_INFO(HEXAGON.V6_vmpyiwb_acc_128B,VI_ftype_VIVISI,3)
8120 // tag : V6_vmpyiwb_acc_128B
8121 def int_hexagon_V6_vmpyiwb_acc_128B :
8122 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">;
8123
8124 //
8125 // BUILTIN_INFO(HEXAGON.V6_vmpyiwh,VI_ftype_VISI,2)
8126 // tag : V6_vmpyiwh
8127 def int_hexagon_V6_vmpyiwh :
8128 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwh">;
8129
8130 //
8131 // BUILTIN_INFO(HEXAGON.V6_vmpyiwh_128B,VI_ftype_VISI,2)
8132 // tag : V6_vmpyiwh_128B
8133 def int_hexagon_V6_vmpyiwh_128B :
8134 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">;
8135
8136 //
8137 // BUILTIN_INFO(HEXAGON.V6_vmpyiwh_acc,VI_ftype_VIVISI,3)
8138 // tag : V6_vmpyiwh_acc
8139 def int_hexagon_V6_vmpyiwh_acc :
8140 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">;
8141
8142 //
8143 // BUILTIN_INFO(HEXAGON.V6_vmpyiwh_acc_128B,VI_ftype_VIVISI,3)
8144 // tag : V6_vmpyiwh_acc_128B
8145 def int_hexagon_V6_vmpyiwh_acc_128B :
8146 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">;
8147
8148 //
8149 // BUILTIN_INFO(HEXAGON.V6_vand,VI_ftype_VIVI,2)
8150 // tag : V6_vand
8151 def int_hexagon_V6_vand :
8152 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vand">;
8153
8154 //
8155 // BUILTIN_INFO(HEXAGON.V6_vand_128B,VI_ftype_VIVI,2)
8156 // tag : V6_vand_128B
8157 def int_hexagon_V6_vand_128B :
8158 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vand_128B">;
8159
8160 //
8161 // BUILTIN_INFO(HEXAGON.V6_vor,VI_ftype_VIVI,2)
8162 // tag : V6_vor
8163 def int_hexagon_V6_vor :
8164 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vor">;
8165
8166 //
8167 // BUILTIN_INFO(HEXAGON.V6_vor_128B,VI_ftype_VIVI,2)
8168 // tag : V6_vor_128B
8169 def int_hexagon_V6_vor_128B :
8170 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vor_128B">;
8171
8172 //
8173 // BUILTIN_INFO(HEXAGON.V6_vxor,VI_ftype_VIVI,2)
8174 // tag : V6_vxor
8175 def int_hexagon_V6_vxor :
8176 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vxor">;
8177
8178 //
8179 // BUILTIN_INFO(HEXAGON.V6_vxor_128B,VI_ftype_VIVI,2)
8180 // tag : V6_vxor_128B
8181 def int_hexagon_V6_vxor_128B :
8182 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vxor_128B">;
8183
8184 //
8185 // BUILTIN_INFO(HEXAGON.V6_vnot,VI_ftype_VI,1)
8186 // tag : V6_vnot
8187 def int_hexagon_V6_vnot :
8188 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnot">;
8189
8190 //
8191 // BUILTIN_INFO(HEXAGON.V6_vnot_128B,VI_ftype_VI,1)
8192 // tag : V6_vnot_128B
8193 def int_hexagon_V6_vnot_128B :
8194 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnot_128B">;
8195
8196 //
8197 // BUILTIN_INFO(HEXAGON.V6_vandqrt,VI_ftype_QVSI,2)
8198 // tag : V6_vandqrt
8199 def int_hexagon_V6_vandqrt :
8200 Hexagon_v512v64ii_Intrinsic<"HEXAGON_V6_vandqrt">;
8201
8202 //
8203 // BUILTIN_INFO(HEXAGON.V6_vandqrt_128B,VI_ftype_QVSI,2)
8204 // tag : V6_vandqrt_128B
8205 def int_hexagon_V6_vandqrt_128B :
8206 Hexagon_v1024v128ii_Intrinsic<"HEXAGON_V6_vandqrt_128B">;
8207
8208 //
8209 // BUILTIN_INFO(HEXAGON.V6_vandqrt_acc,VI_ftype_VIQVSI,3)
8210 // tag : V6_vandqrt_acc
8211 def int_hexagon_V6_vandqrt_acc :
8212 Hexagon_v512v512v64ii_Intrinsic<"HEXAGON_V6_vandqrt_acc">;
8213
8214 //
8215 // BUILTIN_INFO(HEXAGON.V6_vandqrt_acc_128B,VI_ftype_VIQVSI,3)
8216 // tag : V6_vandqrt_acc_128B
8217 def int_hexagon_V6_vandqrt_acc_128B :
8218 Hexagon_v1024v1024v128ii_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">;
8219
8220 //
8221 // BUILTIN_INFO(HEXAGON.V6_vandvrt,QV_ftype_VISI,2)
8222 // tag : V6_vandvrt
8223 def int_hexagon_V6_vandvrt :
8224 Hexagon_v64iv512i_Intrinsic<"HEXAGON_V6_vandvrt">;
8225
8226 //
8227 // BUILTIN_INFO(HEXAGON.V6_vandvrt_128B,QV_ftype_VISI,2)
8228 // tag : V6_vandvrt_128B
8229 def int_hexagon_V6_vandvrt_128B :
8230 Hexagon_v128iv1024i_Intrinsic<"HEXAGON_V6_vandvrt_128B">;
8231
8232 //
8233 // BUILTIN_INFO(HEXAGON.V6_vandvrt_acc,QV_ftype_QVVISI,3)
8234 // tag : V6_vandvrt_acc
8235 def int_hexagon_V6_vandvrt_acc :
8236 Hexagon_v64iv64iv512i_Intrinsic<"HEXAGON_V6_vandvrt_acc">;
8237
8238 //
8239 // BUILTIN_INFO(HEXAGON.V6_vandvrt_acc_128B,QV_ftype_QVVISI,3)
8240 // tag : V6_vandvrt_acc_128B
8241 def int_hexagon_V6_vandvrt_acc_128B :
8242 Hexagon_v128iv128iv1024i_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">;
8243
8244 //
8245 // BUILTIN_INFO(HEXAGON.V6_vgtw,QV_ftype_VIVI,2)
8246 // tag : V6_vgtw
8247 def int_hexagon_V6_vgtw :
8248 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtw">;
8249
8250 //
8251 // BUILTIN_INFO(HEXAGON.V6_vgtw_128B,QV_ftype_VIVI,2)
8252 // tag : V6_vgtw_128B
8253 def int_hexagon_V6_vgtw_128B :
8254 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_128B">;
8255
8256 //
8257 // BUILTIN_INFO(HEXAGON.V6_vgtw_and,QV_ftype_QVVIVI,3)
8258 // tag : V6_vgtw_and
8259 def int_hexagon_V6_vgtw_and :
8260 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_and">;
8261
8262 //
8263 // BUILTIN_INFO(HEXAGON.V6_vgtw_and_128B,QV_ftype_QVVIVI,3)
8264 // tag : V6_vgtw_and_128B
8265 def int_hexagon_V6_vgtw_and_128B :
8266 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_and_128B">;
8267
8268 //
8269 // BUILTIN_INFO(HEXAGON.V6_vgtw_or,QV_ftype_QVVIVI,3)
8270 // tag : V6_vgtw_or
8271 def int_hexagon_V6_vgtw_or :
8272 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_or">;
8273
8274 //
8275 // BUILTIN_INFO(HEXAGON.V6_vgtw_or_128B,QV_ftype_QVVIVI,3)
8276 // tag : V6_vgtw_or_128B
8277 def int_hexagon_V6_vgtw_or_128B :
8278 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_or_128B">;
8279
8280 //
8281 // BUILTIN_INFO(HEXAGON.V6_vgtw_xor,QV_ftype_QVVIVI,3)
8282 // tag : V6_vgtw_xor
8283 def int_hexagon_V6_vgtw_xor :
8284 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_xor">;
8285
8286 //
8287 // BUILTIN_INFO(HEXAGON.V6_vgtw_xor_128B,QV_ftype_QVVIVI,3)
8288 // tag : V6_vgtw_xor_128B
8289 def int_hexagon_V6_vgtw_xor_128B :
8290 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">;
8291
8292 //
8293 // BUILTIN_INFO(HEXAGON.V6_veqw,QV_ftype_VIVI,2)
8294 // tag : V6_veqw
8295 def int_hexagon_V6_veqw :
8296 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqw">;
8297
8298 //
8299 // BUILTIN_INFO(HEXAGON.V6_veqw_128B,QV_ftype_VIVI,2)
8300 // tag : V6_veqw_128B
8301 def int_hexagon_V6_veqw_128B :
8302 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_128B">;
8303
8304 //
8305 // BUILTIN_INFO(HEXAGON.V6_veqw_and,QV_ftype_QVVIVI,3)
8306 // tag : V6_veqw_and
8307 def int_hexagon_V6_veqw_and :
8308 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_and">;
8309
8310 //
8311 // BUILTIN_INFO(HEXAGON.V6_veqw_and_128B,QV_ftype_QVVIVI,3)
8312 // tag : V6_veqw_and_128B
8313 def int_hexagon_V6_veqw_and_128B :
8314 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_and_128B">;
8315
8316 //
8317 // BUILTIN_INFO(HEXAGON.V6_veqw_or,QV_ftype_QVVIVI,3)
8318 // tag : V6_veqw_or
8319 def int_hexagon_V6_veqw_or :
8320 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_or">;
8321
8322 //
8323 // BUILTIN_INFO(HEXAGON.V6_veqw_or_128B,QV_ftype_QVVIVI,3)
8324 // tag : V6_veqw_or_128B
8325 def int_hexagon_V6_veqw_or_128B :
8326 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_or_128B">;
8327
8328 //
8329 // BUILTIN_INFO(HEXAGON.V6_veqw_xor,QV_ftype_QVVIVI,3)
8330 // tag : V6_veqw_xor
8331 def int_hexagon_V6_veqw_xor :
8332 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_xor">;
8333
8334 //
8335 // BUILTIN_INFO(HEXAGON.V6_veqw_xor_128B,QV_ftype_QVVIVI,3)
8336 // tag : V6_veqw_xor_128B
8337 def int_hexagon_V6_veqw_xor_128B :
8338 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_xor_128B">;
8339
8340 //
8341 // BUILTIN_INFO(HEXAGON.V6_vgth,QV_ftype_VIVI,2)
8342 // tag : V6_vgth
8343 def int_hexagon_V6_vgth :
8344 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgth">;
8345
8346 //
8347 // BUILTIN_INFO(HEXAGON.V6_vgth_128B,QV_ftype_VIVI,2)
8348 // tag : V6_vgth_128B
8349 def int_hexagon_V6_vgth_128B :
8350 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_128B">;
8351
8352 //
8353 // BUILTIN_INFO(HEXAGON.V6_vgth_and,QV_ftype_QVVIVI,3)
8354 // tag : V6_vgth_and
8355 def int_hexagon_V6_vgth_and :
8356 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_and">;
8357
8358 //
8359 // BUILTIN_INFO(HEXAGON.V6_vgth_and_128B,QV_ftype_QVVIVI,3)
8360 // tag : V6_vgth_and_128B
8361 def int_hexagon_V6_vgth_and_128B :
8362 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_and_128B">;
8363
8364 //
8365 // BUILTIN_INFO(HEXAGON.V6_vgth_or,QV_ftype_QVVIVI,3)
8366 // tag : V6_vgth_or
8367 def int_hexagon_V6_vgth_or :
8368 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_or">;
8369
8370 //
8371 // BUILTIN_INFO(HEXAGON.V6_vgth_or_128B,QV_ftype_QVVIVI,3)
8372 // tag : V6_vgth_or_128B
8373 def int_hexagon_V6_vgth_or_128B :
8374 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_or_128B">;
8375
8376 //
8377 // BUILTIN_INFO(HEXAGON.V6_vgth_xor,QV_ftype_QVVIVI,3)
8378 // tag : V6_vgth_xor
8379 def int_hexagon_V6_vgth_xor :
8380 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_xor">;
8381
8382 //
8383 // BUILTIN_INFO(HEXAGON.V6_vgth_xor_128B,QV_ftype_QVVIVI,3)
8384 // tag : V6_vgth_xor_128B
8385 def int_hexagon_V6_vgth_xor_128B :
8386 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_xor_128B">;
8387
8388 //
8389 // BUILTIN_INFO(HEXAGON.V6_veqh,QV_ftype_VIVI,2)
8390 // tag : V6_veqh
8391 def int_hexagon_V6_veqh :
8392 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqh">;
8393
8394 //
8395 // BUILTIN_INFO(HEXAGON.V6_veqh_128B,QV_ftype_VIVI,2)
8396 // tag : V6_veqh_128B
8397 def int_hexagon_V6_veqh_128B :
8398 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_128B">;
8399
8400 //
8401 // BUILTIN_INFO(HEXAGON.V6_veqh_and,QV_ftype_QVVIVI,3)
8402 // tag : V6_veqh_and
8403 def int_hexagon_V6_veqh_and :
8404 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_and">;
8405
8406 //
8407 // BUILTIN_INFO(HEXAGON.V6_veqh_and_128B,QV_ftype_QVVIVI,3)
8408 // tag : V6_veqh_and_128B
8409 def int_hexagon_V6_veqh_and_128B :
8410 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_and_128B">;
8411
8412 //
8413 // BUILTIN_INFO(HEXAGON.V6_veqh_or,QV_ftype_QVVIVI,3)
8414 // tag : V6_veqh_or
8415 def int_hexagon_V6_veqh_or :
8416 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_or">;
8417
8418 //
8419 // BUILTIN_INFO(HEXAGON.V6_veqh_or_128B,QV_ftype_QVVIVI,3)
8420 // tag : V6_veqh_or_128B
8421 def int_hexagon_V6_veqh_or_128B :
8422 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_or_128B">;
8423
8424 //
8425 // BUILTIN_INFO(HEXAGON.V6_veqh_xor,QV_ftype_QVVIVI,3)
8426 // tag : V6_veqh_xor
8427 def int_hexagon_V6_veqh_xor :
8428 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_xor">;
8429
8430 //
8431 // BUILTIN_INFO(HEXAGON.V6_veqh_xor_128B,QV_ftype_QVVIVI,3)
8432 // tag : V6_veqh_xor_128B
8433 def int_hexagon_V6_veqh_xor_128B :
8434 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_xor_128B">;
8435
8436 //
8437 // BUILTIN_INFO(HEXAGON.V6_vgtb,QV_ftype_VIVI,2)
8438 // tag : V6_vgtb
8439 def int_hexagon_V6_vgtb :
8440 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtb">;
8441
8442 //
8443 // BUILTIN_INFO(HEXAGON.V6_vgtb_128B,QV_ftype_VIVI,2)
8444 // tag : V6_vgtb_128B
8445 def int_hexagon_V6_vgtb_128B :
8446 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_128B">;
8447
8448 //
8449 // BUILTIN_INFO(HEXAGON.V6_vgtb_and,QV_ftype_QVVIVI,3)
8450 // tag : V6_vgtb_and
8451 def int_hexagon_V6_vgtb_and :
8452 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_and">;
8453
8454 //
8455 // BUILTIN_INFO(HEXAGON.V6_vgtb_and_128B,QV_ftype_QVVIVI,3)
8456 // tag : V6_vgtb_and_128B
8457 def int_hexagon_V6_vgtb_and_128B :
8458 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_and_128B">;
8459
8460 //
8461 // BUILTIN_INFO(HEXAGON.V6_vgtb_or,QV_ftype_QVVIVI,3)
8462 // tag : V6_vgtb_or
8463 def int_hexagon_V6_vgtb_or :
8464 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_or">;
8465
8466 //
8467 // BUILTIN_INFO(HEXAGON.V6_vgtb_or_128B,QV_ftype_QVVIVI,3)
8468 // tag : V6_vgtb_or_128B
8469 def int_hexagon_V6_vgtb_or_128B :
8470 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_or_128B">;
8471
8472 //
8473 // BUILTIN_INFO(HEXAGON.V6_vgtb_xor,QV_ftype_QVVIVI,3)
8474 // tag : V6_vgtb_xor
8475 def int_hexagon_V6_vgtb_xor :
8476 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_xor">;
8477
8478 //
8479 // BUILTIN_INFO(HEXAGON.V6_vgtb_xor_128B,QV_ftype_QVVIVI,3)
8480 // tag : V6_vgtb_xor_128B
8481 def int_hexagon_V6_vgtb_xor_128B :
8482 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">;
8483
8484 //
8485 // BUILTIN_INFO(HEXAGON.V6_veqb,QV_ftype_VIVI,2)
8486 // tag : V6_veqb
8487 def int_hexagon_V6_veqb :
8488 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqb">;
8489
8490 //
8491 // BUILTIN_INFO(HEXAGON.V6_veqb_128B,QV_ftype_VIVI,2)
8492 // tag : V6_veqb_128B
8493 def int_hexagon_V6_veqb_128B :
8494 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_128B">;
8495
8496 //
8497 // BUILTIN_INFO(HEXAGON.V6_veqb_and,QV_ftype_QVVIVI,3)
8498 // tag : V6_veqb_and
8499 def int_hexagon_V6_veqb_and :
8500 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_and">;
8501
8502 //
8503 // BUILTIN_INFO(HEXAGON.V6_veqb_and_128B,QV_ftype_QVVIVI,3)
8504 // tag : V6_veqb_and_128B
8505 def int_hexagon_V6_veqb_and_128B :
8506 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_and_128B">;
8507
8508 //
8509 // BUILTIN_INFO(HEXAGON.V6_veqb_or,QV_ftype_QVVIVI,3)
8510 // tag : V6_veqb_or
8511 def int_hexagon_V6_veqb_or :
8512 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_or">;
8513
8514 //
8515 // BUILTIN_INFO(HEXAGON.V6_veqb_or_128B,QV_ftype_QVVIVI,3)
8516 // tag : V6_veqb_or_128B
8517 def int_hexagon_V6_veqb_or_128B :
8518 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_or_128B">;
8519
8520 //
8521 // BUILTIN_INFO(HEXAGON.V6_veqb_xor,QV_ftype_QVVIVI,3)
8522 // tag : V6_veqb_xor
8523 def int_hexagon_V6_veqb_xor :
8524 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_xor">;
8525
8526 //
8527 // BUILTIN_INFO(HEXAGON.V6_veqb_xor_128B,QV_ftype_QVVIVI,3)
8528 // tag : V6_veqb_xor_128B
8529 def int_hexagon_V6_veqb_xor_128B :
8530 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_xor_128B">;
8531
8532 //
8533 // BUILTIN_INFO(HEXAGON.V6_vgtuw,QV_ftype_VIVI,2)
8534 // tag : V6_vgtuw
8535 def int_hexagon_V6_vgtuw :
8536 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw">;
8537
8538 //
8539 // BUILTIN_INFO(HEXAGON.V6_vgtuw_128B,QV_ftype_VIVI,2)
8540 // tag : V6_vgtuw_128B
8541 def int_hexagon_V6_vgtuw_128B :
8542 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_128B">;
8543
8544 //
8545 // BUILTIN_INFO(HEXAGON.V6_vgtuw_and,QV_ftype_QVVIVI,3)
8546 // tag : V6_vgtuw_and
8547 def int_hexagon_V6_vgtuw_and :
8548 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_and">;
8549
8550 //
8551 // BUILTIN_INFO(HEXAGON.V6_vgtuw_and_128B,QV_ftype_QVVIVI,3)
8552 // tag : V6_vgtuw_and_128B
8553 def int_hexagon_V6_vgtuw_and_128B :
8554 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">;
8555
8556 //
8557 // BUILTIN_INFO(HEXAGON.V6_vgtuw_or,QV_ftype_QVVIVI,3)
8558 // tag : V6_vgtuw_or
8559 def int_hexagon_V6_vgtuw_or :
8560 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_or">;
8561
8562 //
8563 // BUILTIN_INFO(HEXAGON.V6_vgtuw_or_128B,QV_ftype_QVVIVI,3)
8564 // tag : V6_vgtuw_or_128B
8565 def int_hexagon_V6_vgtuw_or_128B :
8566 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">;
8567
8568 //
8569 // BUILTIN_INFO(HEXAGON.V6_vgtuw_xor,QV_ftype_QVVIVI,3)
8570 // tag : V6_vgtuw_xor
8571 def int_hexagon_V6_vgtuw_xor :
8572 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_xor">;
8573
8574 //
8575 // BUILTIN_INFO(HEXAGON.V6_vgtuw_xor_128B,QV_ftype_QVVIVI,3)
8576 // tag : V6_vgtuw_xor_128B
8577 def int_hexagon_V6_vgtuw_xor_128B :
8578 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">;
8579
8580 //
8581 // BUILTIN_INFO(HEXAGON.V6_vgtuh,QV_ftype_VIVI,2)
8582 // tag : V6_vgtuh
8583 def int_hexagon_V6_vgtuh :
8584 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh">;
8585
8586 //
8587 // BUILTIN_INFO(HEXAGON.V6_vgtuh_128B,QV_ftype_VIVI,2)
8588 // tag : V6_vgtuh_128B
8589 def int_hexagon_V6_vgtuh_128B :
8590 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_128B">;
8591
8592 //
8593 // BUILTIN_INFO(HEXAGON.V6_vgtuh_and,QV_ftype_QVVIVI,3)
8594 // tag : V6_vgtuh_and
8595 def int_hexagon_V6_vgtuh_and :
8596 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_and">;
8597
8598 //
8599 // BUILTIN_INFO(HEXAGON.V6_vgtuh_and_128B,QV_ftype_QVVIVI,3)
8600 // tag : V6_vgtuh_and_128B
8601 def int_hexagon_V6_vgtuh_and_128B :
8602 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">;
8603
8604 //
8605 // BUILTIN_INFO(HEXAGON.V6_vgtuh_or,QV_ftype_QVVIVI,3)
8606 // tag : V6_vgtuh_or
8607 def int_hexagon_V6_vgtuh_or :
8608 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_or">;
8609
8610 //
8611 // BUILTIN_INFO(HEXAGON.V6_vgtuh_or_128B,QV_ftype_QVVIVI,3)
8612 // tag : V6_vgtuh_or_128B
8613 def int_hexagon_V6_vgtuh_or_128B :
8614 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">;
8615
8616 //
8617 // BUILTIN_INFO(HEXAGON.V6_vgtuh_xor,QV_ftype_QVVIVI,3)
8618 // tag : V6_vgtuh_xor
8619 def int_hexagon_V6_vgtuh_xor :
8620 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_xor">;
8621
8622 //
8623 // BUILTIN_INFO(HEXAGON.V6_vgtuh_xor_128B,QV_ftype_QVVIVI,3)
8624 // tag : V6_vgtuh_xor_128B
8625 def int_hexagon_V6_vgtuh_xor_128B :
8626 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">;
8627
8628 //
8629 // BUILTIN_INFO(HEXAGON.V6_vgtub,QV_ftype_VIVI,2)
8630 // tag : V6_vgtub
8631 def int_hexagon_V6_vgtub :
8632 Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtub">;
8633
8634 //
8635 // BUILTIN_INFO(HEXAGON.V6_vgtub_128B,QV_ftype_VIVI,2)
8636 // tag : V6_vgtub_128B
8637 def int_hexagon_V6_vgtub_128B :
8638 Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_128B">;
8639
8640 //
8641 // BUILTIN_INFO(HEXAGON.V6_vgtub_and,QV_ftype_QVVIVI,3)
8642 // tag : V6_vgtub_and
8643 def int_hexagon_V6_vgtub_and :
8644 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_and">;
8645
8646 //
8647 // BUILTIN_INFO(HEXAGON.V6_vgtub_and_128B,QV_ftype_QVVIVI,3)
8648 // tag : V6_vgtub_and_128B
8649 def int_hexagon_V6_vgtub_and_128B :
8650 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_and_128B">;
8651
8652 //
8653 // BUILTIN_INFO(HEXAGON.V6_vgtub_or,QV_ftype_QVVIVI,3)
8654 // tag : V6_vgtub_or
8655 def int_hexagon_V6_vgtub_or :
8656 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_or">;
8657
8658 //
8659 // BUILTIN_INFO(HEXAGON.V6_vgtub_or_128B,QV_ftype_QVVIVI,3)
8660 // tag : V6_vgtub_or_128B
8661 def int_hexagon_V6_vgtub_or_128B :
8662 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_or_128B">;
8663
8664 //
8665 // BUILTIN_INFO(HEXAGON.V6_vgtub_xor,QV_ftype_QVVIVI,3)
8666 // tag : V6_vgtub_xor
8667 def int_hexagon_V6_vgtub_xor :
8668 Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_xor">;
8669
8670 //
8671 // BUILTIN_INFO(HEXAGON.V6_vgtub_xor_128B,QV_ftype_QVVIVI,3)
8672 // tag : V6_vgtub_xor_128B
8673 def int_hexagon_V6_vgtub_xor_128B :
8674 Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">;
8675
8676 //
8677 // BUILTIN_INFO(HEXAGON.V6_pred_or,QV_ftype_QVQV,2)
8678 // tag : V6_pred_or
8679 def int_hexagon_V6_pred_or :
8680 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_or">;
8681
8682 //
8683 // BUILTIN_INFO(HEXAGON.V6_pred_or_128B,QV_ftype_QVQV,2)
8684 // tag : V6_pred_or_128B
8685 def int_hexagon_V6_pred_or_128B :
8686 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_or_128B">;
8687
8688 //
8689 // BUILTIN_INFO(HEXAGON.V6_pred_and,QV_ftype_QVQV,2)
8690 // tag : V6_pred_and
8691 def int_hexagon_V6_pred_and :
8692 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_and">;
8693
8694 //
8695 // BUILTIN_INFO(HEXAGON.V6_pred_and_128B,QV_ftype_QVQV,2)
8696 // tag : V6_pred_and_128B
8697 def int_hexagon_V6_pred_and_128B :
8698 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_and_128B">;
8699
8700 //
8701 // BUILTIN_INFO(HEXAGON.V6_pred_not,QV_ftype_QV,1)
8702 // tag : V6_pred_not
8703 def int_hexagon_V6_pred_not :
8704 Hexagon_v64iv64i_Intrinsic<"HEXAGON_V6_pred_not">;
8705
8706 //
8707 // BUILTIN_INFO(HEXAGON.V6_pred_not_128B,QV_ftype_QV,1)
8708 // tag : V6_pred_not_128B
8709 def int_hexagon_V6_pred_not_128B :
8710 Hexagon_v128iv128i_Intrinsic<"HEXAGON_V6_pred_not_128B">;
8711
8712 //
8713 // BUILTIN_INFO(HEXAGON.V6_pred_xor,QV_ftype_QVQV,2)
8714 // tag : V6_pred_xor
8715 def int_hexagon_V6_pred_xor :
8716 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_xor">;
8717
8718 //
8719 // BUILTIN_INFO(HEXAGON.V6_pred_xor_128B,QV_ftype_QVQV,2)
8720 // tag : V6_pred_xor_128B
8721 def int_hexagon_V6_pred_xor_128B :
8722 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_xor_128B">;
8723
8724 //
8725 // BUILTIN_INFO(HEXAGON.V6_pred_and_n,QV_ftype_QVQV,2)
8726 // tag : V6_pred_and_n
8727 def int_hexagon_V6_pred_and_n :
8728 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_and_n">;
8729
8730 //
8731 // BUILTIN_INFO(HEXAGON.V6_pred_and_n_128B,QV_ftype_QVQV,2)
8732 // tag : V6_pred_and_n_128B
8733 def int_hexagon_V6_pred_and_n_128B :
8734 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_and_n_128B">;
8735
8736 //
8737 // BUILTIN_INFO(HEXAGON.V6_pred_or_n,QV_ftype_QVQV,2)
8738 // tag : V6_pred_or_n
8739 def int_hexagon_V6_pred_or_n :
8740 Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_or_n">;
8741
8742 //
8743 // BUILTIN_INFO(HEXAGON.V6_pred_or_n_128B,QV_ftype_QVQV,2)
8744 // tag : V6_pred_or_n_128B
8745 def int_hexagon_V6_pred_or_n_128B :
8746 Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_or_n_128B">;
8747
8748 //
8749 // BUILTIN_INFO(HEXAGON.V6_pred_scalar2,QV_ftype_SI,1)
8750 // tag : V6_pred_scalar2
8751 def int_hexagon_V6_pred_scalar2 :
8752 Hexagon_v64ii_Intrinsic<"HEXAGON_V6_pred_scalar2">;
8753
8754 //
8755 // BUILTIN_INFO(HEXAGON.V6_pred_scalar2_128B,QV_ftype_SI,1)
8756 // tag : V6_pred_scalar2_128B
8757 def int_hexagon_V6_pred_scalar2_128B :
8758 Hexagon_v128ii_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">;
8759
8760 //
8761 // BUILTIN_INFO(HEXAGON.V6_vmux,VI_ftype_QVVIVI,3)
8762 // tag : V6_vmux
8763 def int_hexagon_V6_vmux :
8764 Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vmux">;
8765
8766 //
8767 // BUILTIN_INFO(HEXAGON.V6_vmux_128B,VI_ftype_QVVIVI,3)
8768 // tag : V6_vmux_128B
8769 def int_hexagon_V6_vmux_128B :
8770 Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vmux_128B">;
8771
8772 //
8773 // BUILTIN_INFO(HEXAGON.V6_vswap,VD_ftype_QVVIVI,3)
8774 // tag : V6_vswap
8775 def int_hexagon_V6_vswap :
8776 Hexagon_v1024v64iv512v512_Intrinsic<"HEXAGON_V6_vswap">;
8777
8778 //
8779 // BUILTIN_INFO(HEXAGON.V6_vswap_128B,VD_ftype_QVVIVI,3)
8780 // tag : V6_vswap_128B
8781 def int_hexagon_V6_vswap_128B :
8782 Hexagon_v2048v128iv1024v1024_Intrinsic<"HEXAGON_V6_vswap_128B">;
8783
8784 //
8785 // BUILTIN_INFO(HEXAGON.V6_vmaxub,VI_ftype_VIVI,2)
8786 // tag : V6_vmaxub
8787 def int_hexagon_V6_vmaxub :
8788 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxub">;
8789
8790 //
8791 // BUILTIN_INFO(HEXAGON.V6_vmaxub_128B,VI_ftype_VIVI,2)
8792 // tag : V6_vmaxub_128B
8793 def int_hexagon_V6_vmaxub_128B :
8794 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxub_128B">;
8795
8796 //
8797 // BUILTIN_INFO(HEXAGON.V6_vminub,VI_ftype_VIVI,2)
8798 // tag : V6_vminub
8799 def int_hexagon_V6_vminub :
8800 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminub">;
8801
8802 //
8803 // BUILTIN_INFO(HEXAGON.V6_vminub_128B,VI_ftype_VIVI,2)
8804 // tag : V6_vminub_128B
8805 def int_hexagon_V6_vminub_128B :
8806 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminub_128B">;
8807
8808 //
8809 // BUILTIN_INFO(HEXAGON.V6_vmaxuh,VI_ftype_VIVI,2)
8810 // tag : V6_vmaxuh
8811 def int_hexagon_V6_vmaxuh :
8812 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxuh">;
8813
8814 //
8815 // BUILTIN_INFO(HEXAGON.V6_vmaxuh_128B,VI_ftype_VIVI,2)
8816 // tag : V6_vmaxuh_128B
8817 def int_hexagon_V6_vmaxuh_128B :
8818 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxuh_128B">;
8819
8820 //
8821 // BUILTIN_INFO(HEXAGON.V6_vminuh,VI_ftype_VIVI,2)
8822 // tag : V6_vminuh
8823 def int_hexagon_V6_vminuh :
8824 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminuh">;
8825
8826 //
8827 // BUILTIN_INFO(HEXAGON.V6_vminuh_128B,VI_ftype_VIVI,2)
8828 // tag : V6_vminuh_128B
8829 def int_hexagon_V6_vminuh_128B :
8830 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminuh_128B">;
8831
8832 //
8833 // BUILTIN_INFO(HEXAGON.V6_vmaxh,VI_ftype_VIVI,2)
8834 // tag : V6_vmaxh
8835 def int_hexagon_V6_vmaxh :
8836 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxh">;
8837
8838 //
8839 // BUILTIN_INFO(HEXAGON.V6_vmaxh_128B,VI_ftype_VIVI,2)
8840 // tag : V6_vmaxh_128B
8841 def int_hexagon_V6_vmaxh_128B :
8842 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxh_128B">;
8843
8844 //
8845 // BUILTIN_INFO(HEXAGON.V6_vminh,VI_ftype_VIVI,2)
8846 // tag : V6_vminh
8847 def int_hexagon_V6_vminh :
8848 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminh">;
8849
8850 //
8851 // BUILTIN_INFO(HEXAGON.V6_vminh_128B,VI_ftype_VIVI,2)
8852 // tag : V6_vminh_128B
8853 def int_hexagon_V6_vminh_128B :
8854 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminh_128B">;
8855
8856 //
8857 // BUILTIN_INFO(HEXAGON.V6_vmaxw,VI_ftype_VIVI,2)
8858 // tag : V6_vmaxw
8859 def int_hexagon_V6_vmaxw :
8860 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxw">;
8861
8862 //
8863 // BUILTIN_INFO(HEXAGON.V6_vmaxw_128B,VI_ftype_VIVI,2)
8864 // tag : V6_vmaxw_128B
8865 def int_hexagon_V6_vmaxw_128B :
8866 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxw_128B">;
8867
8868 //
8869 // BUILTIN_INFO(HEXAGON.V6_vminw,VI_ftype_VIVI,2)
8870 // tag : V6_vminw
8871 def int_hexagon_V6_vminw :
8872 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminw">;
8873
8874 //
8875 // BUILTIN_INFO(HEXAGON.V6_vminw_128B,VI_ftype_VIVI,2)
8876 // tag : V6_vminw_128B
8877 def int_hexagon_V6_vminw_128B :
8878 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminw_128B">;
8879
8880 //
8881 // BUILTIN_INFO(HEXAGON.V6_vsathub,VI_ftype_VIVI,2)
8882 // tag : V6_vsathub
8883 def int_hexagon_V6_vsathub :
8884 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsathub">;
8885
8886 //
8887 // BUILTIN_INFO(HEXAGON.V6_vsathub_128B,VI_ftype_VIVI,2)
8888 // tag : V6_vsathub_128B
8889 def int_hexagon_V6_vsathub_128B :
8890 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsathub_128B">;
8891
8892 //
8893 // BUILTIN_INFO(HEXAGON.V6_vsatwh,VI_ftype_VIVI,2)
8894 // tag : V6_vsatwh
8895 def int_hexagon_V6_vsatwh :
8896 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsatwh">;
8897
8898 //
8899 // BUILTIN_INFO(HEXAGON.V6_vsatwh_128B,VI_ftype_VIVI,2)
8900 // tag : V6_vsatwh_128B
8901 def int_hexagon_V6_vsatwh_128B :
8902 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsatwh_128B">;
8903
8904 //
8905 // BUILTIN_INFO(HEXAGON.V6_vshuffeb,VI_ftype_VIVI,2)
8906 // tag : V6_vshuffeb
8907 def int_hexagon_V6_vshuffeb :
8908 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshuffeb">;
8909
8910 //
8911 // BUILTIN_INFO(HEXAGON.V6_vshuffeb_128B,VI_ftype_VIVI,2)
8912 // tag : V6_vshuffeb_128B
8913 def int_hexagon_V6_vshuffeb_128B :
8914 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshuffeb_128B">;
8915
8916 //
8917 // BUILTIN_INFO(HEXAGON.V6_vshuffob,VI_ftype_VIVI,2)
8918 // tag : V6_vshuffob
8919 def int_hexagon_V6_vshuffob :
8920 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshuffob">;
8921
8922 //
8923 // BUILTIN_INFO(HEXAGON.V6_vshuffob_128B,VI_ftype_VIVI,2)
8924 // tag : V6_vshuffob_128B
8925 def int_hexagon_V6_vshuffob_128B :
8926 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshuffob_128B">;
8927
8928 //
8929 // BUILTIN_INFO(HEXAGON.V6_vshufeh,VI_ftype_VIVI,2)
8930 // tag : V6_vshufeh
8931 def int_hexagon_V6_vshufeh :
8932 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshufeh">;
8933
8934 //
8935 // BUILTIN_INFO(HEXAGON.V6_vshufeh_128B,VI_ftype_VIVI,2)
8936 // tag : V6_vshufeh_128B
8937 def int_hexagon_V6_vshufeh_128B :
8938 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshufeh_128B">;
8939
8940 //
8941 // BUILTIN_INFO(HEXAGON.V6_vshufoh,VI_ftype_VIVI,2)
8942 // tag : V6_vshufoh
8943 def int_hexagon_V6_vshufoh :
8944 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshufoh">;
8945
8946 //
8947 // BUILTIN_INFO(HEXAGON.V6_vshufoh_128B,VI_ftype_VIVI,2)
8948 // tag : V6_vshufoh_128B
8949 def int_hexagon_V6_vshufoh_128B :
8950 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshufoh_128B">;
8951
8952 //
8953 // BUILTIN_INFO(HEXAGON.V6_vshuffvdd,VD_ftype_VIVISI,3)
8954 // tag : V6_vshuffvdd
8955 def int_hexagon_V6_vshuffvdd :
8956 Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vshuffvdd">;
8957
8958 //
8959 // BUILTIN_INFO(HEXAGON.V6_vshuffvdd_128B,VD_ftype_VIVISI,3)
8960 // tag : V6_vshuffvdd_128B
8961 def int_hexagon_V6_vshuffvdd_128B :
8962 Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">;
8963
8964 //
8965 // BUILTIN_INFO(HEXAGON.V6_vdealvdd,VD_ftype_VIVISI,3)
8966 // tag : V6_vdealvdd
8967 def int_hexagon_V6_vdealvdd :
8968 Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vdealvdd">;
8969
8970 //
8971 // BUILTIN_INFO(HEXAGON.V6_vdealvdd_128B,VD_ftype_VIVISI,3)
8972 // tag : V6_vdealvdd_128B
8973 def int_hexagon_V6_vdealvdd_128B :
8974 Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vdealvdd_128B">;
8975
8976 //
8977 // BUILTIN_INFO(HEXAGON.V6_vshufoeh,VD_ftype_VIVI,2)
8978 // tag : V6_vshufoeh
8979 def int_hexagon_V6_vshufoeh :
8980 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vshufoeh">;
8981
8982 //
8983 // BUILTIN_INFO(HEXAGON.V6_vshufoeh_128B,VD_ftype_VIVI,2)
8984 // tag : V6_vshufoeh_128B
8985 def int_hexagon_V6_vshufoeh_128B :
8986 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vshufoeh_128B">;
8987
8988 //
8989 // BUILTIN_INFO(HEXAGON.V6_vshufoeb,VD_ftype_VIVI,2)
8990 // tag : V6_vshufoeb
8991 def int_hexagon_V6_vshufoeb :
8992 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vshufoeb">;
8993
8994 //
8995 // BUILTIN_INFO(HEXAGON.V6_vshufoeb_128B,VD_ftype_VIVI,2)
8996 // tag : V6_vshufoeb_128B
8997 def int_hexagon_V6_vshufoeb_128B :
8998 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vshufoeb_128B">;
8999
9000 //
9001 // BUILTIN_INFO(HEXAGON.V6_vdealh,VI_ftype_VI,1)
9002 // tag : V6_vdealh
9003 def int_hexagon_V6_vdealh :
9004 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vdealh">;
9005
9006 //
9007 // BUILTIN_INFO(HEXAGON.V6_vdealh_128B,VI_ftype_VI,1)
9008 // tag : V6_vdealh_128B
9009 def int_hexagon_V6_vdealh_128B :
9010 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vdealh_128B">;
9011
9012 //
9013 // BUILTIN_INFO(HEXAGON.V6_vdealb,VI_ftype_VI,1)
9014 // tag : V6_vdealb
9015 def int_hexagon_V6_vdealb :
9016 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vdealb">;
9017
9018 //
9019 // BUILTIN_INFO(HEXAGON.V6_vdealb_128B,VI_ftype_VI,1)
9020 // tag : V6_vdealb_128B
9021 def int_hexagon_V6_vdealb_128B :
9022 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vdealb_128B">;
9023
9024 //
9025 // BUILTIN_INFO(HEXAGON.V6_vdealb4w,VI_ftype_VIVI,2)
9026 // tag : V6_vdealb4w
9027 def int_hexagon_V6_vdealb4w :
9028 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdealb4w">;
9029
9030 //
9031 // BUILTIN_INFO(HEXAGON.V6_vdealb4w_128B,VI_ftype_VIVI,2)
9032 // tag : V6_vdealb4w_128B
9033 def int_hexagon_V6_vdealb4w_128B :
9034 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdealb4w_128B">;
9035
9036 //
9037 // BUILTIN_INFO(HEXAGON.V6_vshuffh,VI_ftype_VI,1)
9038 // tag : V6_vshuffh
9039 def int_hexagon_V6_vshuffh :
9040 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vshuffh">;
9041
9042 //
9043 // BUILTIN_INFO(HEXAGON.V6_vshuffh_128B,VI_ftype_VI,1)
9044 // tag : V6_vshuffh_128B
9045 def int_hexagon_V6_vshuffh_128B :
9046 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vshuffh_128B">;
9047
9048 //
9049 // BUILTIN_INFO(HEXAGON.V6_vshuffb,VI_ftype_VI,1)
9050 // tag : V6_vshuffb
9051 def int_hexagon_V6_vshuffb :
9052 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vshuffb">;
9053
9054 //
9055 // BUILTIN_INFO(HEXAGON.V6_vshuffb_128B,VI_ftype_VI,1)
9056 // tag : V6_vshuffb_128B
9057 def int_hexagon_V6_vshuffb_128B :
9058 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vshuffb_128B">;
9059
9060 //
9061 // BUILTIN_INFO(HEXAGON.V6_extractw,SI_ftype_VISI,2)
9062 // tag : V6_extractw
9063 def int_hexagon_V6_extractw :
9064 Hexagon_iv512i_Intrinsic<"HEXAGON_V6_extractw">;
9065
9066 //
9067 // BUILTIN_INFO(HEXAGON.V6_extractw_128B,SI_ftype_VISI,2)
9068 // tag : V6_extractw_128B
9069 def int_hexagon_V6_extractw_128B :
9070 Hexagon_iv1024i_Intrinsic<"HEXAGON_V6_extractw_128B">;
9071
9072 //
9073 // BUILTIN_INFO(HEXAGON.V6_vinsertwr,VI_ftype_VISI,2)
9074 // tag : V6_vinsertwr
9075 def int_hexagon_V6_vinsertwr :
9076 Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vinsertwr">;
9077
9078 //
9079 // BUILTIN_INFO(HEXAGON.V6_vinsertwr_128B,VI_ftype_VISI,2)
9080 // tag : V6_vinsertwr_128B
9081 def int_hexagon_V6_vinsertwr_128B :
9082 Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vinsertwr_128B">;
9083
9084 //
9085 // BUILTIN_INFO(HEXAGON.V6_lvsplatw,VI_ftype_SI,1)
9086 // tag : V6_lvsplatw
9087 def int_hexagon_V6_lvsplatw :
9088 Hexagon_v512i_Intrinsic<"HEXAGON_V6_lvsplatw">;
9089
9090 //
9091 // BUILTIN_INFO(HEXAGON.V6_lvsplatw_128B,VI_ftype_SI,1)
9092 // tag : V6_lvsplatw_128B
9093 def int_hexagon_V6_lvsplatw_128B :
9094 Hexagon_v1024i_Intrinsic<"HEXAGON_V6_lvsplatw_128B">;
9095
9096 //
9097 // BUILTIN_INFO(HEXAGON.V6_vassign,VI_ftype_VI,1)
9098 // tag : V6_vassign
9099 def int_hexagon_V6_vassign :
9100 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vassign">;
9101
9102 //
9103 // BUILTIN_INFO(HEXAGON.V6_vassign_128B,VI_ftype_VI,1)
9104 // tag : V6_vassign_128B
9105 def int_hexagon_V6_vassign_128B :
9106 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vassign_128B">;
9107
9108 //
9109 // BUILTIN_INFO(HEXAGON.V6_vcombine,VD_ftype_VIVI,2)
9110 // tag : V6_vcombine
9111 def int_hexagon_V6_vcombine :
9112 Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vcombine">;
9113
9114 //
9115 // BUILTIN_INFO(HEXAGON.V6_vcombine_128B,VD_ftype_VIVI,2)
9116 // tag : V6_vcombine_128B
9117 def int_hexagon_V6_vcombine_128B :
9118 Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vcombine_128B">;
9119
9120 //
9121 // BUILTIN_INFO(HEXAGON.V6_vdelta,VI_ftype_VIVI,2)
9122 // tag : V6_vdelta
9123 def int_hexagon_V6_vdelta :
9124 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdelta">;
9125
9126 //
9127 // BUILTIN_INFO(HEXAGON.V6_vdelta_128B,VI_ftype_VIVI,2)
9128 // tag : V6_vdelta_128B
9129 def int_hexagon_V6_vdelta_128B :
9130 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdelta_128B">;
9131
9132 //
9133 // BUILTIN_INFO(HEXAGON.V6_vrdelta,VI_ftype_VIVI,2)
9134 // tag : V6_vrdelta
9135 def int_hexagon_V6_vrdelta :
9136 Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrdelta">;
9137
9138 //
9139 // BUILTIN_INFO(HEXAGON.V6_vrdelta_128B,VI_ftype_VIVI,2)
9140 // tag : V6_vrdelta_128B
9141 def int_hexagon_V6_vrdelta_128B :
9142 Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrdelta_128B">;
9143
9144 //
9145 // BUILTIN_INFO(HEXAGON.V6_vcl0w,VI_ftype_VI,1)
9146 // tag : V6_vcl0w
9147 def int_hexagon_V6_vcl0w :
9148 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vcl0w">;
9149
9150 //
9151 // BUILTIN_INFO(HEXAGON.V6_vcl0w_128B,VI_ftype_VI,1)
9152 // tag : V6_vcl0w_128B
9153 def int_hexagon_V6_vcl0w_128B :
9154 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vcl0w_128B">;
9155
9156 //
9157 // BUILTIN_INFO(HEXAGON.V6_vcl0h,VI_ftype_VI,1)
9158 // tag : V6_vcl0h
9159 def int_hexagon_V6_vcl0h :
9160 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vcl0h">;
9161
9162 //
9163 // BUILTIN_INFO(HEXAGON.V6_vcl0h_128B,VI_ftype_VI,1)
9164 // tag : V6_vcl0h_128B
9165 def int_hexagon_V6_vcl0h_128B :
9166 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vcl0h_128B">;
9167
9168 //
9169 // BUILTIN_INFO(HEXAGON.V6_vnormamtw,VI_ftype_VI,1)
9170 // tag : V6_vnormamtw
9171 def int_hexagon_V6_vnormamtw :
9172 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnormamtw">;
9173
9174 //
9175 // BUILTIN_INFO(HEXAGON.V6_vnormamtw_128B,VI_ftype_VI,1)
9176 // tag : V6_vnormamtw_128B
9177 def int_hexagon_V6_vnormamtw_128B :
9178 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnormamtw_128B">;
9179
9180 //
9181 // BUILTIN_INFO(HEXAGON.V6_vnormamth,VI_ftype_VI,1)
9182 // tag : V6_vnormamth
9183 def int_hexagon_V6_vnormamth :
9184 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnormamth">;
9185
9186 //
9187 // BUILTIN_INFO(HEXAGON.V6_vnormamth_128B,VI_ftype_VI,1)
9188 // tag : V6_vnormamth_128B
9189 def int_hexagon_V6_vnormamth_128B :
9190 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnormamth_128B">;
9191
9192 //
9193 // BUILTIN_INFO(HEXAGON.V6_vpopcounth,VI_ftype_VI,1)
9194 // tag : V6_vpopcounth
9195 def int_hexagon_V6_vpopcounth :
9196 Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vpopcounth">;
9197
9198 //
9199 // BUILTIN_INFO(HEXAGON.V6_vpopcounth_128B,VI_ftype_VI,1)
9200 // tag : V6_vpopcounth_128B
9201 def int_hexagon_V6_vpopcounth_128B :
9202 Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vpopcounth_128B">;
9203
9204 //
9205 // BUILTIN_INFO(HEXAGON.V6_vlutvvb,VI_ftype_VIVISI,3)
9206 // tag : V6_vlutvvb
9207 def int_hexagon_V6_vlutvvb :
9208 Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb">;
9209
9210 //
9211 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_128B,VI_ftype_VIVISI,3)
9212 // tag : V6_vlutvvb_128B
9213 def int_hexagon_V6_vlutvvb_128B :
9214 Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_128B">;
9215
9216 //
9217 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracc,VI_ftype_VIVIVISI,4)
9218 // tag : V6_vlutvvb_oracc
9219 def int_hexagon_V6_vlutvvb_oracc :
9220 Hexagon_v512v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">;
9221
9222 //
9223 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracc_128B,VI_ftype_VIVIVISI,4)
9224 // tag : V6_vlutvvb_oracc_128B
9225 def int_hexagon_V6_vlutvvb_oracc_128B :
9226 Hexagon_v1024v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">;
9227
9228 //
9229 // BUILTIN_INFO(HEXAGON.V6_vlutvwh,VD_ftype_VIVISI,3)
9230 // tag : V6_vlutvwh
9231 def int_hexagon_V6_vlutvwh :
9232 Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh">;
9233
9234 //
9235 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_128B,VD_ftype_VIVISI,3)
9236 // tag : V6_vlutvwh_128B
9237 def int_hexagon_V6_vlutvwh_128B :
9238 Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_128B">;
9239
9240 //
9241 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracc,VD_ftype_VDVIVISI,4)
9242 // tag : V6_vlutvwh_oracc
9243 def int_hexagon_V6_vlutvwh_oracc :
9244 Hexagon_v1024v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">;
9245
9246 //
9247 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracc_128B,VD_ftype_VDVIVISI,4)
9248 // tag : V6_vlutvwh_oracc_128B
9249 def int_hexagon_V6_vlutvwh_oracc_128B :
9250 Hexagon_v2048v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">;
9251
9252 //
9253 // Masked vector stores
9254 //
9255 def int_hexagon_V6_vS32b_qpred_ai :
9256 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;
9257
9258 def int_hexagon_V6_vS32b_nqpred_ai :
9259 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;
9260
9261 def int_hexagon_V6_vS32b_nt_qpred_ai :
9262 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;
9263
9264 def int_hexagon_V6_vS32b_nt_nqpred_ai :
9265 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;
9266
9267 def int_hexagon_V6_vS32b_qpred_ai_128B :
9268 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;
9269
9270 def int_hexagon_V6_vS32b_nqpred_ai_128B :
9271 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;
9272
9273 def int_hexagon_V6_vS32b_nt_qpred_ai_128B :
9274 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;
9275
9276 def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :
9277 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;
9278
9279 def int_hexagon_V6_vmaskedstoreq :
9280 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;
9281
9282 def int_hexagon_V6_vmaskedstorenq :
9283 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">;
9284
9285 def int_hexagon_V6_vmaskedstorentq :
9286 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">;
9287
9288 def int_hexagon_V6_vmaskedstorentnq :
9289 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">;
9290
9291 def int_hexagon_V6_vmaskedstoreq_128B :
9292 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">;
9293
9294 def int_hexagon_V6_vmaskedstorenq_128B :
9295 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">;
9296
9297 def int_hexagon_V6_vmaskedstorentq_128B :
9298 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">;
9299
9300 def int_hexagon_V6_vmaskedstorentnq_128B :
9301 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">;
9302
9303
9304 ///
9305 /// HexagonV62 intrinsics
9306 ///
9307
9308 //
9309 // Hexagon_LLiLLiLLi_Intrinsic<string GCCIntSuffix>
9310 // tag : M6_vabsdiffb
9311 class Hexagon_LLiLLiLLi_Intrinsic<string GCCIntSuffix>
9312  : Hexagon_Intrinsic<GCCIntSuffix,
9313                           [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],
9314                           [IntrNoMem]>;
9315
9316 //
9317 // Hexagon_LLii_Intrinsic<string GCCIntSuffix>
9318 // tag : S6_vsplatrbp
9319 class Hexagon_LLii_Intrinsic<string GCCIntSuffix>
9320  : Hexagon_Intrinsic<GCCIntSuffix,
9321                           [llvm_i64_ty], [llvm_i32_ty],
9322                           [IntrNoMem]>;
9323
9324 //
9325 // Hexagon_V62_v512v512i_Intrinsic<string GCCIntSuffix>
9326 // tag : V6_vlsrb
9327 class Hexagon_V62_v512v512i_Intrinsic<string GCCIntSuffix>
9328  : Hexagon_Intrinsic<GCCIntSuffix,
9329                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
9330                           [IntrNoMem]>;
9331
9332 //
9333 // Hexagon_V62_v1024v1024i_Intrinsic<string GCCIntSuffix>
9334 // tag : V6_vlsrb_128B
9335 class Hexagon_V62_v1024v1024i_Intrinsic<string GCCIntSuffix>
9336  : Hexagon_Intrinsic<GCCIntSuffix,
9337                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
9338                           [IntrNoMem]>;
9339
9340 //
9341 // Hexagon_V62_v512v512v512i_Intrinsic<string GCCIntSuffix>
9342 // tag : V6_vasrwuhrndsat
9343 class Hexagon_V62_v512v512v512i_Intrinsic<string GCCIntSuffix>
9344  : Hexagon_Intrinsic<GCCIntSuffix,
9345                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
9346                           [IntrNoMem]>;
9347
9348 //
9349 // Hexagon_V62_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
9350 // tag : V6_vasrwuhrndsat_128B
9351 class Hexagon_V62_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
9352  : Hexagon_Intrinsic<GCCIntSuffix,
9353                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
9354                           [IntrNoMem]>;
9355
9356 //
9357 // Hexagon_V62_v512v512v512_Intrinsic<string GCCIntSuffix>
9358 // tag : V6_vrounduwuh
9359 class Hexagon_V62_v512v512v512_Intrinsic<string GCCIntSuffix>
9360  : Hexagon_Intrinsic<GCCIntSuffix,
9361                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
9362                           [IntrNoMem]>;
9363
9364 //
9365 // Hexagon_V62_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
9366 // tag : V6_vrounduwuh_128B
9367 class Hexagon_V62_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
9368  : Hexagon_Intrinsic<GCCIntSuffix,
9369                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
9370                           [IntrNoMem]>;
9371
9372 //
9373 // Hexagon_V62_v2048v2048v2048_Intrinsic<string GCCIntSuffix>
9374 // tag : V6_vadduwsat_dv_128B
9375 class Hexagon_V62_v2048v2048v2048_Intrinsic<string GCCIntSuffix>
9376  : Hexagon_Intrinsic<GCCIntSuffix,
9377                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
9378                           [IntrNoMem]>;
9379
9380 //
9381 // Hexagon_V62_v1024v1024v512v512_Intrinsic<string GCCIntSuffix>
9382 // tag : V6_vaddhw_acc
9383 class Hexagon_V62_v1024v1024v512v512_Intrinsic<string GCCIntSuffix>
9384  : Hexagon_Intrinsic<GCCIntSuffix,
9385                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
9386                           [IntrNoMem]>;
9387
9388 //
9389 // Hexagon_V62_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix>
9390 // tag : V6_vaddhw_acc_128B
9391 class Hexagon_V62_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix>
9392  : Hexagon_Intrinsic<GCCIntSuffix,
9393                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
9394                           [IntrNoMem]>;
9395
9396 //
9397 // Hexagon_V62_v1024v512v512_Intrinsic<string GCCIntSuffix>
9398 // tag : V6_vmpyewuh_64
9399 class Hexagon_V62_v1024v512v512_Intrinsic<string GCCIntSuffix>
9400  : Hexagon_Intrinsic<GCCIntSuffix,
9401                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
9402                           [IntrNoMem]>;
9403
9404 //
9405 // Hexagon_V62_v2048v1024v1024_Intrinsic<string GCCIntSuffix>
9406 // tag : V6_vmpyewuh_64_128B
9407 class Hexagon_V62_v2048v1024v1024_Intrinsic<string GCCIntSuffix>
9408  : Hexagon_Intrinsic<GCCIntSuffix,
9409                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
9410                           [IntrNoMem]>;
9411
9412 //
9413 // Hexagon_V62_v2048v2048i_Intrinsic<string GCCIntSuffix>
9414 // tag : V6_vmpauhb_128B
9415 class Hexagon_V62_v2048v2048i_Intrinsic<string GCCIntSuffix>
9416  : Hexagon_Intrinsic<GCCIntSuffix,
9417                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
9418                           [IntrNoMem]>;
9419
9420 //
9421 // Hexagon_V62_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
9422 // tag : V6_vmpauhb_acc_128B
9423 class Hexagon_V62_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
9424  : Hexagon_Intrinsic<GCCIntSuffix,
9425                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
9426                           [IntrNoMem]>;
9427
9428 //
9429 // Hexagon_V62_v512v64ii_Intrinsic<string GCCIntSuffix>
9430 // tag : V6_vandnqrt
9431 class Hexagon_V62_v512v64ii_Intrinsic<string GCCIntSuffix>
9432  : Hexagon_Intrinsic<GCCIntSuffix,
9433                           [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],
9434                           [IntrNoMem]>;
9435
9436 //
9437 // Hexagon_V62_v1024v128ii_Intrinsic<string GCCIntSuffix>
9438 // tag : V6_vandnqrt_128B
9439 class Hexagon_V62_v1024v128ii_Intrinsic<string GCCIntSuffix>
9440  : Hexagon_Intrinsic<GCCIntSuffix,
9441                           [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],
9442                           [IntrNoMem]>;
9443
9444 //
9445 // Hexagon_V62_v512v512v64ii_Intrinsic<string GCCIntSuffix>
9446 // tag : V6_vandnqrt_acc
9447 class Hexagon_V62_v512v512v64ii_Intrinsic<string GCCIntSuffix>
9448  : Hexagon_Intrinsic<GCCIntSuffix,
9449                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],
9450                           [IntrNoMem]>;
9451
9452 //
9453 // Hexagon_V62_v1024v1024v128ii_Intrinsic<string GCCIntSuffix>
9454 // tag : V6_vandnqrt_acc_128B
9455 class Hexagon_V62_v1024v1024v128ii_Intrinsic<string GCCIntSuffix>
9456  : Hexagon_Intrinsic<GCCIntSuffix,
9457                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],
9458                           [IntrNoMem]>;
9459
9460 //
9461 // Hexagon_V62_v512v64iv512_Intrinsic<string GCCIntSuffix>
9462 // tag : V6_vandvqv
9463 class Hexagon_V62_v512v64iv512_Intrinsic<string GCCIntSuffix>
9464  : Hexagon_Intrinsic<GCCIntSuffix,
9465                           [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty],
9466                           [IntrNoMem]>;
9467
9468 //
9469 // Hexagon_V62_v1024v128iv1024_Intrinsic<string GCCIntSuffix>
9470 // tag : V6_vandvqv_128B
9471 class Hexagon_V62_v1024v128iv1024_Intrinsic<string GCCIntSuffix>
9472  : Hexagon_Intrinsic<GCCIntSuffix,
9473                           [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty],
9474                           [IntrNoMem]>;
9475
9476 //
9477 // Hexagon_V62_v64ii_Intrinsic<string GCCIntSuffix>
9478 // tag : V6_pred_scalar2v2
9479 class Hexagon_V62_v64ii_Intrinsic<string GCCIntSuffix>
9480  : Hexagon_Intrinsic<GCCIntSuffix,
9481                           [llvm_v512i1_ty], [llvm_i32_ty],
9482                           [IntrNoMem]>;
9483
9484 //
9485 // Hexagon_V62_v128ii_Intrinsic<string GCCIntSuffix>
9486 // tag : V6_pred_scalar2v2_128B
9487 class Hexagon_V62_v128ii_Intrinsic<string GCCIntSuffix>
9488  : Hexagon_Intrinsic<GCCIntSuffix,
9489                           [llvm_v1024i1_ty], [llvm_i32_ty],
9490                           [IntrNoMem]>;
9491
9492 //
9493 // Hexagon_V62_v64iv64iv64i_Intrinsic<string GCCIntSuffix>
9494 // tag : V6_shuffeqw
9495 class Hexagon_V62_v64iv64iv64i_Intrinsic<string GCCIntSuffix>
9496  : Hexagon_Intrinsic<GCCIntSuffix,
9497                           [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],
9498                           [IntrNoMem]>;
9499
9500 //
9501 // Hexagon_V62_v128iv128iv128i_Intrinsic<string GCCIntSuffix>
9502 // tag : V6_shuffeqw_128B
9503 class Hexagon_V62_v128iv128iv128i_Intrinsic<string GCCIntSuffix>
9504  : Hexagon_Intrinsic<GCCIntSuffix,
9505                           [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],
9506                           [IntrNoMem]>;
9507
9508 //
9509 // Hexagon_V62_v512i_Intrinsic<string GCCIntSuffix>
9510 // tag : V6_lvsplath
9511 class Hexagon_V62_v512i_Intrinsic<string GCCIntSuffix>
9512  : Hexagon_Intrinsic<GCCIntSuffix,
9513                           [llvm_v16i32_ty], [llvm_i32_ty],
9514                           [IntrNoMem]>;
9515
9516 //
9517 // Hexagon_V62_v1024i_Intrinsic<string GCCIntSuffix>
9518 // tag : V6_lvsplath_128B
9519 class Hexagon_V62_v1024i_Intrinsic<string GCCIntSuffix>
9520  : Hexagon_Intrinsic<GCCIntSuffix,
9521                           [llvm_v32i32_ty], [llvm_i32_ty],
9522                           [IntrNoMem]>;
9523
9524 //
9525 // Hexagon_V62_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
9526 // tag : V6_vlutvvb_oracci
9527 class Hexagon_V62_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
9528  : Hexagon_Intrinsic<GCCIntSuffix,
9529                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
9530                           [IntrNoMem]>;
9531
9532 //
9533 // Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
9534 // tag : V6_vlutvvb_oracci_128B
9535 class Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
9536  : Hexagon_Intrinsic<GCCIntSuffix,
9537                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
9538                           [IntrNoMem]>;
9539
9540 //
9541 // Hexagon_V62_v1024v512v512i_Intrinsic<string GCCIntSuffix>
9542 // tag : V6_vlutvwhi
9543 class Hexagon_V62_v1024v512v512i_Intrinsic<string GCCIntSuffix>
9544  : Hexagon_Intrinsic<GCCIntSuffix,
9545                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
9546                           [IntrNoMem]>;
9547
9548 //
9549 // Hexagon_V62_v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
9550 // tag : V6_vlutvwhi_128B
9551 class Hexagon_V62_v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
9552  : Hexagon_Intrinsic<GCCIntSuffix,
9553                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
9554                           [IntrNoMem]>;
9555
9556 //
9557 // Hexagon_V62_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix>
9558 // tag : V6_vlutvwh_oracci
9559 class Hexagon_V62_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix>
9560  : Hexagon_Intrinsic<GCCIntSuffix,
9561                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
9562                           [IntrNoMem]>;
9563
9564 //
9565 // Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
9566 // tag : V6_vlutvwh_oracci_128B
9567 class Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
9568  : Hexagon_Intrinsic<GCCIntSuffix,
9569                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
9570                           [IntrNoMem]>;
9571
9572 // Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix>
9573 // tag: V6_vaddcarry
9574 class Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix>
9575   : Hexagon_Intrinsic<GCCIntSuffix,
9576                           [llvm_v16i32_ty, llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
9577                           [IntrNoMem]>;
9578
9579 // Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix>
9580 // tag: V6_vaddcarry_128B
9581 class Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix>
9582   : Hexagon_Intrinsic<GCCIntSuffix,
9583                           [llvm_v32i32_ty, llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
9584                           [IntrNoMem]>;
9585
9586
9587 //
9588 // BUILTIN_INFO(HEXAGON.M6_vabsdiffb,DI_ftype_DIDI,2)
9589 // tag : M6_vabsdiffb
9590 def int_hexagon_M6_vabsdiffb :
9591 Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_M6_vabsdiffb">;
9592
9593 //
9594 // BUILTIN_INFO(HEXAGON.M6_vabsdiffub,DI_ftype_DIDI,2)
9595 // tag : M6_vabsdiffub
9596 def int_hexagon_M6_vabsdiffub :
9597 Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_M6_vabsdiffub">;
9598
9599 //
9600 // BUILTIN_INFO(HEXAGON.S6_vtrunehb_ppp,DI_ftype_DIDI,2)
9601 // tag : S6_vtrunehb_ppp
9602 def int_hexagon_S6_vtrunehb_ppp :
9603 Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">;
9604
9605 //
9606 // BUILTIN_INFO(HEXAGON.S6_vtrunohb_ppp,DI_ftype_DIDI,2)
9607 // tag : S6_vtrunohb_ppp
9608 def int_hexagon_S6_vtrunohb_ppp :
9609 Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">;
9610
9611 //
9612 // BUILTIN_INFO(HEXAGON.S6_vsplatrbp,DI_ftype_SI,1)
9613 // tag : S6_vsplatrbp
9614 def int_hexagon_S6_vsplatrbp :
9615 Hexagon_LLii_Intrinsic<"HEXAGON_S6_vsplatrbp">;
9616
9617 //
9618 // BUILTIN_INFO(HEXAGON.V6_vlsrb,VI_ftype_VISI,2)
9619 // tag : V6_vlsrb
9620 def int_hexagon_V6_vlsrb :
9621 Hexagon_V62_v512v512i_Intrinsic<"HEXAGON_V6_vlsrb">;
9622
9623 //
9624 // BUILTIN_INFO(HEXAGON.V6_vlsrb_128B,VI_ftype_VISI,2)
9625 // tag : V6_vlsrb_128B
9626 def int_hexagon_V6_vlsrb_128B :
9627 Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrb_128B">;
9628
9629 //
9630 // BUILTIN_INFO(HEXAGON.V6_vasrwuhrndsat,VI_ftype_VIVISI,3)
9631 // tag : V6_vasrwuhrndsat
9632 def int_hexagon_V6_vasrwuhrndsat :
9633 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">;
9634
9635 //
9636 // BUILTIN_INFO(HEXAGON.V6_vasrwuhrndsat_128B,VI_ftype_VIVISI,3)
9637 // tag : V6_vasrwuhrndsat_128B
9638 def int_hexagon_V6_vasrwuhrndsat_128B :
9639 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">;
9640
9641 //
9642 // BUILTIN_INFO(HEXAGON.V6_vasruwuhrndsat,VI_ftype_VIVISI,3)
9643 // tag : V6_vasruwuhrndsat
9644 def int_hexagon_V6_vasruwuhrndsat :
9645 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">;
9646
9647 //
9648 // BUILTIN_INFO(HEXAGON.V6_vasruwuhrndsat_128B,VI_ftype_VIVISI,3)
9649 // tag : V6_vasruwuhrndsat_128B
9650 def int_hexagon_V6_vasruwuhrndsat_128B :
9651 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">;
9652
9653 //
9654 // BUILTIN_INFO(HEXAGON.V6_vasrhbsat,VI_ftype_VIVISI,3)
9655 // tag : V6_vasrhbsat
9656 def int_hexagon_V6_vasrhbsat :
9657 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhbsat">;
9658
9659 //
9660 // BUILTIN_INFO(HEXAGON.V6_vasrhbsat_128B,VI_ftype_VIVISI,3)
9661 // tag : V6_vasrhbsat_128B
9662 def int_hexagon_V6_vasrhbsat_128B :
9663 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">;
9664
9665 //
9666 // BUILTIN_INFO(HEXAGON.V6_vrounduwuh,VI_ftype_VIVI,2)
9667 // tag : V6_vrounduwuh
9668 def int_hexagon_V6_vrounduwuh :
9669 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vrounduwuh">;
9670
9671 //
9672 // BUILTIN_INFO(HEXAGON.V6_vrounduwuh_128B,VI_ftype_VIVI,2)
9673 // tag : V6_vrounduwuh_128B
9674 def int_hexagon_V6_vrounduwuh_128B :
9675 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">;
9676
9677 //
9678 // BUILTIN_INFO(HEXAGON.V6_vrounduhub,VI_ftype_VIVI,2)
9679 // tag : V6_vrounduhub
9680 def int_hexagon_V6_vrounduhub :
9681 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vrounduhub">;
9682
9683 //
9684 // BUILTIN_INFO(HEXAGON.V6_vrounduhub_128B,VI_ftype_VIVI,2)
9685 // tag : V6_vrounduhub_128B
9686 def int_hexagon_V6_vrounduhub_128B :
9687 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrounduhub_128B">;
9688
9689 //
9690 // BUILTIN_INFO(HEXAGON.V6_vadduwsat,VI_ftype_VIVI,2)
9691 // tag : V6_vadduwsat
9692 def int_hexagon_V6_vadduwsat :
9693 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vadduwsat">;
9694
9695 //
9696 // BUILTIN_INFO(HEXAGON.V6_vadduwsat_128B,VI_ftype_VIVI,2)
9697 // tag : V6_vadduwsat_128B
9698 def int_hexagon_V6_vadduwsat_128B :
9699 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduwsat_128B">;
9700
9701 //
9702 // BUILTIN_INFO(HEXAGON.V6_vadduwsat_dv,VD_ftype_VDVD,2)
9703 // tag : V6_vadduwsat_dv
9704 def int_hexagon_V6_vadduwsat_dv :
9705 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduwsat_dv">;
9706
9707 //
9708 // BUILTIN_INFO(HEXAGON.V6_vadduwsat_dv_128B,VD_ftype_VDVD,2)
9709 // tag : V6_vadduwsat_dv_128B
9710 def int_hexagon_V6_vadduwsat_dv_128B :
9711 Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">;
9712
9713 //
9714 // BUILTIN_INFO(HEXAGON.V6_vsubuwsat,VI_ftype_VIVI,2)
9715 // tag : V6_vsubuwsat
9716 def int_hexagon_V6_vsubuwsat :
9717 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubuwsat">;
9718
9719 //
9720 // BUILTIN_INFO(HEXAGON.V6_vsubuwsat_128B,VI_ftype_VIVI,2)
9721 // tag : V6_vsubuwsat_128B
9722 def int_hexagon_V6_vsubuwsat_128B :
9723 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">;
9724
9725 //
9726 // BUILTIN_INFO(HEXAGON.V6_vsubuwsat_dv,VD_ftype_VDVD,2)
9727 // tag : V6_vsubuwsat_dv
9728 def int_hexagon_V6_vsubuwsat_dv :
9729 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">;
9730
9731 //
9732 // BUILTIN_INFO(HEXAGON.V6_vsubuwsat_dv_128B,VD_ftype_VDVD,2)
9733 // tag : V6_vsubuwsat_dv_128B
9734 def int_hexagon_V6_vsubuwsat_dv_128B :
9735 Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">;
9736
9737 //
9738 // BUILTIN_INFO(HEXAGON.V6_vaddbsat,VI_ftype_VIVI,2)
9739 // tag : V6_vaddbsat
9740 def int_hexagon_V6_vaddbsat :
9741 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddbsat">;
9742
9743 //
9744 // BUILTIN_INFO(HEXAGON.V6_vaddbsat_128B,VI_ftype_VIVI,2)
9745 // tag : V6_vaddbsat_128B
9746 def int_hexagon_V6_vaddbsat_128B :
9747 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddbsat_128B">;
9748
9749 //
9750 // BUILTIN_INFO(HEXAGON.V6_vaddbsat_dv,VD_ftype_VDVD,2)
9751 // tag : V6_vaddbsat_dv
9752 def int_hexagon_V6_vaddbsat_dv :
9753 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddbsat_dv">;
9754
9755 //
9756 // BUILTIN_INFO(HEXAGON.V6_vaddbsat_dv_128B,VD_ftype_VDVD,2)
9757 // tag : V6_vaddbsat_dv_128B
9758 def int_hexagon_V6_vaddbsat_dv_128B :
9759 Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">;
9760
9761 //
9762 // BUILTIN_INFO(HEXAGON.V6_vsubbsat,VI_ftype_VIVI,2)
9763 // tag : V6_vsubbsat
9764 def int_hexagon_V6_vsubbsat :
9765 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubbsat">;
9766
9767 //
9768 // BUILTIN_INFO(HEXAGON.V6_vsubbsat_128B,VI_ftype_VIVI,2)
9769 // tag : V6_vsubbsat_128B
9770 def int_hexagon_V6_vsubbsat_128B :
9771 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubbsat_128B">;
9772
9773 //
9774 // BUILTIN_INFO(HEXAGON.V6_vsubbsat_dv,VD_ftype_VDVD,2)
9775 // tag : V6_vsubbsat_dv
9776 def int_hexagon_V6_vsubbsat_dv :
9777 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubbsat_dv">;
9778
9779 //
9780 // BUILTIN_INFO(HEXAGON.V6_vsubbsat_dv_128B,VD_ftype_VDVD,2)
9781 // tag : V6_vsubbsat_dv_128B
9782 def int_hexagon_V6_vsubbsat_dv_128B :
9783 Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">;
9784
9785 //
9786 // BUILTIN_INFO(HEXAGON.V6_vaddububb_sat,VI_ftype_VIVI,2)
9787 // tag : V6_vaddububb_sat
9788 def int_hexagon_V6_vaddububb_sat :
9789 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddububb_sat">;
9790
9791 //
9792 // BUILTIN_INFO(HEXAGON.V6_vaddububb_sat_128B,VI_ftype_VIVI,2)
9793 // tag : V6_vaddububb_sat_128B
9794 def int_hexagon_V6_vaddububb_sat_128B :
9795 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">;
9796
9797 //
9798 // BUILTIN_INFO(HEXAGON.V6_vsubububb_sat,VI_ftype_VIVI,2)
9799 // tag : V6_vsubububb_sat
9800 def int_hexagon_V6_vsubububb_sat :
9801 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubububb_sat">;
9802
9803 //
9804 // BUILTIN_INFO(HEXAGON.V6_vsubububb_sat_128B,VI_ftype_VIVI,2)
9805 // tag : V6_vsubububb_sat_128B
9806 def int_hexagon_V6_vsubububb_sat_128B :
9807 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">;
9808
9809 //
9810 // BUILTIN_INFO(HEXAGON.V6_vaddhw_acc,VD_ftype_VDVIVI,3)
9811 // tag : V6_vaddhw_acc
9812 def int_hexagon_V6_vaddhw_acc :
9813 Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vaddhw_acc">;
9814
9815 //
9816 // BUILTIN_INFO(HEXAGON.V6_vaddhw_acc_128B,VD_ftype_VDVIVI,3)
9817 // tag : V6_vaddhw_acc_128B
9818 def int_hexagon_V6_vaddhw_acc_128B :
9819 Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">;
9820
9821 //
9822 // BUILTIN_INFO(HEXAGON.V6_vadduhw_acc,VD_ftype_VDVIVI,3)
9823 // tag : V6_vadduhw_acc
9824 def int_hexagon_V6_vadduhw_acc :
9825 Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vadduhw_acc">;
9826
9827 //
9828 // BUILTIN_INFO(HEXAGON.V6_vadduhw_acc_128B,VD_ftype_VDVIVI,3)
9829 // tag : V6_vadduhw_acc_128B
9830 def int_hexagon_V6_vadduhw_acc_128B :
9831 Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">;
9832
9833 //
9834 // BUILTIN_INFO(HEXAGON.V6_vaddubh_acc,VD_ftype_VDVIVI,3)
9835 // tag : V6_vaddubh_acc
9836 def int_hexagon_V6_vaddubh_acc :
9837 Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vaddubh_acc">;
9838
9839 //
9840 // BUILTIN_INFO(HEXAGON.V6_vaddubh_acc_128B,VD_ftype_VDVIVI,3)
9841 // tag : V6_vaddubh_acc_128B
9842 def int_hexagon_V6_vaddubh_acc_128B :
9843 Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">;
9844
9845 //
9846 // BUILTIN_INFO(HEXAGON.V6_vmpyewuh_64,VD_ftype_VIVI,2)
9847 // tag : V6_vmpyewuh_64
9848 def int_hexagon_V6_vmpyewuh_64 :
9849 Hexagon_V62_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyewuh_64">;
9850
9851 //
9852 // BUILTIN_INFO(HEXAGON.V6_vmpyewuh_64_128B,VD_ftype_VIVI,2)
9853 // tag : V6_vmpyewuh_64_128B
9854 def int_hexagon_V6_vmpyewuh_64_128B :
9855 Hexagon_V62_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">;
9856
9857 //
9858 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_64_acc,VD_ftype_VDVIVI,3)
9859 // tag : V6_vmpyowh_64_acc
9860 def int_hexagon_V6_vmpyowh_64_acc :
9861 Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">;
9862
9863 //
9864 // BUILTIN_INFO(HEXAGON.V6_vmpyowh_64_acc_128B,VD_ftype_VDVIVI,3)
9865 // tag : V6_vmpyowh_64_acc_128B
9866 def int_hexagon_V6_vmpyowh_64_acc_128B :
9867 Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">;
9868
9869 //
9870 // BUILTIN_INFO(HEXAGON.V6_vmpauhb,VD_ftype_VDSI,2)
9871 // tag : V6_vmpauhb
9872 def int_hexagon_V6_vmpauhb :
9873 Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpauhb">;
9874
9875 //
9876 // BUILTIN_INFO(HEXAGON.V6_vmpauhb_128B,VD_ftype_VDSI,2)
9877 // tag : V6_vmpauhb_128B
9878 def int_hexagon_V6_vmpauhb_128B :
9879 Hexagon_V62_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpauhb_128B">;
9880
9881 //
9882 // BUILTIN_INFO(HEXAGON.V6_vmpauhb_acc,VD_ftype_VDVDSI,3)
9883 // tag : V6_vmpauhb_acc
9884 def int_hexagon_V6_vmpauhb_acc :
9885 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpauhb_acc">;
9886
9887 //
9888 // BUILTIN_INFO(HEXAGON.V6_vmpauhb_acc_128B,VD_ftype_VDVDSI,3)
9889 // tag : V6_vmpauhb_acc_128B
9890 def int_hexagon_V6_vmpauhb_acc_128B :
9891 Hexagon_V62_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">;
9892
9893 //
9894 // BUILTIN_INFO(HEXAGON.V6_vmpyiwub,VI_ftype_VISI,2)
9895 // tag : V6_vmpyiwub
9896 def int_hexagon_V6_vmpyiwub :
9897 Hexagon_V62_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwub">;
9898
9899 //
9900 // BUILTIN_INFO(HEXAGON.V6_vmpyiwub_128B,VI_ftype_VISI,2)
9901 // tag : V6_vmpyiwub_128B
9902 def int_hexagon_V6_vmpyiwub_128B :
9903 Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">;
9904
9905 //
9906 // BUILTIN_INFO(HEXAGON.V6_vmpyiwub_acc,VI_ftype_VIVISI,3)
9907 // tag : V6_vmpyiwub_acc
9908 def int_hexagon_V6_vmpyiwub_acc :
9909 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">;
9910
9911 //
9912 // BUILTIN_INFO(HEXAGON.V6_vmpyiwub_acc_128B,VI_ftype_VIVISI,3)
9913 // tag : V6_vmpyiwub_acc_128B
9914 def int_hexagon_V6_vmpyiwub_acc_128B :
9915 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">;
9916
9917 //
9918 // BUILTIN_INFO(HEXAGON.V6_vandnqrt,VI_ftype_QVSI,2)
9919 // tag : V6_vandnqrt
9920 def int_hexagon_V6_vandnqrt :
9921 Hexagon_V62_v512v64ii_Intrinsic<"HEXAGON_V6_vandnqrt">;
9922
9923 //
9924 // BUILTIN_INFO(HEXAGON.V6_vandnqrt_128B,VI_ftype_QVSI,2)
9925 // tag : V6_vandnqrt_128B
9926 def int_hexagon_V6_vandnqrt_128B :
9927 Hexagon_V62_v1024v128ii_Intrinsic<"HEXAGON_V6_vandnqrt_128B">;
9928
9929 //
9930 // BUILTIN_INFO(HEXAGON.V6_vandnqrt_acc,VI_ftype_VIQVSI,3)
9931 // tag : V6_vandnqrt_acc
9932 def int_hexagon_V6_vandnqrt_acc :
9933 Hexagon_V62_v512v512v64ii_Intrinsic<"HEXAGON_V6_vandnqrt_acc">;
9934
9935 //
9936 // BUILTIN_INFO(HEXAGON.V6_vandnqrt_acc_128B,VI_ftype_VIQVSI,3)
9937 // tag : V6_vandnqrt_acc_128B
9938 def int_hexagon_V6_vandnqrt_acc_128B :
9939 Hexagon_V62_v1024v1024v128ii_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">;
9940
9941 //
9942 // BUILTIN_INFO(HEXAGON.V6_vandvqv,VI_ftype_QVVI,2)
9943 // tag : V6_vandvqv
9944 def int_hexagon_V6_vandvqv :
9945 Hexagon_V62_v512v64iv512_Intrinsic<"HEXAGON_V6_vandvqv">;
9946
9947 //
9948 // BUILTIN_INFO(HEXAGON.V6_vandvqv_128B,VI_ftype_QVVI,2)
9949 // tag : V6_vandvqv_128B
9950 def int_hexagon_V6_vandvqv_128B :
9951 Hexagon_V62_v1024v128iv1024_Intrinsic<"HEXAGON_V6_vandvqv_128B">;
9952
9953 //
9954 // BUILTIN_INFO(HEXAGON.V6_vandvnqv,VI_ftype_QVVI,2)
9955 // tag : V6_vandvnqv
9956 def int_hexagon_V6_vandvnqv :
9957 Hexagon_V62_v512v64iv512_Intrinsic<"HEXAGON_V6_vandvnqv">;
9958
9959 //
9960 // BUILTIN_INFO(HEXAGON.V6_vandvnqv_128B,VI_ftype_QVVI,2)
9961 // tag : V6_vandvnqv_128B
9962 def int_hexagon_V6_vandvnqv_128B :
9963 Hexagon_V62_v1024v128iv1024_Intrinsic<"HEXAGON_V6_vandvnqv_128B">;
9964
9965 //
9966 // BUILTIN_INFO(HEXAGON.V6_pred_scalar2v2,QV_ftype_SI,1)
9967 // tag : V6_pred_scalar2v2
9968 def int_hexagon_V6_pred_scalar2v2 :
9969 Hexagon_V62_v64ii_Intrinsic<"HEXAGON_V6_pred_scalar2v2">;
9970
9971 //
9972 // BUILTIN_INFO(HEXAGON.V6_pred_scalar2v2_128B,QV_ftype_SI,1)
9973 // tag : V6_pred_scalar2v2_128B
9974 def int_hexagon_V6_pred_scalar2v2_128B :
9975 Hexagon_V62_v128ii_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">;
9976
9977 //
9978 // BUILTIN_INFO(HEXAGON.V6_shuffeqw,QV_ftype_QVQV,2)
9979 // tag : V6_shuffeqw
9980 def int_hexagon_V6_shuffeqw :
9981 Hexagon_V62_v64iv64iv64i_Intrinsic<"HEXAGON_V6_shuffeqw">;
9982
9983 //
9984 // BUILTIN_INFO(HEXAGON.V6_shuffeqw_128B,QV_ftype_QVQV,2)
9985 // tag : V6_shuffeqw_128B
9986 def int_hexagon_V6_shuffeqw_128B :
9987 Hexagon_V62_v128iv128iv128i_Intrinsic<"HEXAGON_V6_shuffeqw_128B">;
9988
9989 //
9990 // BUILTIN_INFO(HEXAGON.V6_shuffeqh,QV_ftype_QVQV,2)
9991 // tag : V6_shuffeqh
9992 def int_hexagon_V6_shuffeqh :
9993 Hexagon_V62_v64iv64iv64i_Intrinsic<"HEXAGON_V6_shuffeqh">;
9994
9995 //
9996 // BUILTIN_INFO(HEXAGON.V6_shuffeqh_128B,QV_ftype_QVQV,2)
9997 // tag : V6_shuffeqh_128B
9998 def int_hexagon_V6_shuffeqh_128B :
9999 Hexagon_V62_v128iv128iv128i_Intrinsic<"HEXAGON_V6_shuffeqh_128B">;
10000
10001 //
10002 // BUILTIN_INFO(HEXAGON.V6_vmaxb,VI_ftype_VIVI,2)
10003 // tag : V6_vmaxb
10004 def int_hexagon_V6_vmaxb :
10005 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxb">;
10006
10007 //
10008 // BUILTIN_INFO(HEXAGON.V6_vmaxb_128B,VI_ftype_VIVI,2)
10009 // tag : V6_vmaxb_128B
10010 def int_hexagon_V6_vmaxb_128B :
10011 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxb_128B">;
10012
10013 //
10014 // BUILTIN_INFO(HEXAGON.V6_vminb,VI_ftype_VIVI,2)
10015 // tag : V6_vminb
10016 def int_hexagon_V6_vminb :
10017 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vminb">;
10018
10019 //
10020 // BUILTIN_INFO(HEXAGON.V6_vminb_128B,VI_ftype_VIVI,2)
10021 // tag : V6_vminb_128B
10022 def int_hexagon_V6_vminb_128B :
10023 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminb_128B">;
10024
10025 //
10026 // BUILTIN_INFO(HEXAGON.V6_vsatuwuh,VI_ftype_VIVI,2)
10027 // tag : V6_vsatuwuh
10028 def int_hexagon_V6_vsatuwuh :
10029 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsatuwuh">;
10030
10031 //
10032 // BUILTIN_INFO(HEXAGON.V6_vsatuwuh_128B,VI_ftype_VIVI,2)
10033 // tag : V6_vsatuwuh_128B
10034 def int_hexagon_V6_vsatuwuh_128B :
10035 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">;
10036
10037 //
10038 // BUILTIN_INFO(HEXAGON.V6_lvsplath,VI_ftype_SI,1)
10039 // tag : V6_lvsplath
10040 def int_hexagon_V6_lvsplath :
10041 Hexagon_V62_v512i_Intrinsic<"HEXAGON_V6_lvsplath">;
10042
10043 //
10044 // BUILTIN_INFO(HEXAGON.V6_lvsplath_128B,VI_ftype_SI,1)
10045 // tag : V6_lvsplath_128B
10046 def int_hexagon_V6_lvsplath_128B :
10047 Hexagon_V62_v1024i_Intrinsic<"HEXAGON_V6_lvsplath_128B">;
10048
10049 //
10050 // BUILTIN_INFO(HEXAGON.V6_lvsplatb,VI_ftype_SI,1)
10051 // tag : V6_lvsplatb
10052 def int_hexagon_V6_lvsplatb :
10053 Hexagon_V62_v512i_Intrinsic<"HEXAGON_V6_lvsplatb">;
10054
10055 //
10056 // BUILTIN_INFO(HEXAGON.V6_lvsplatb_128B,VI_ftype_SI,1)
10057 // tag : V6_lvsplatb_128B
10058 def int_hexagon_V6_lvsplatb_128B :
10059 Hexagon_V62_v1024i_Intrinsic<"HEXAGON_V6_lvsplatb_128B">;
10060
10061 //
10062 // BUILTIN_INFO(HEXAGON.V6_vaddclbw,VI_ftype_VIVI,2)
10063 // tag : V6_vaddclbw
10064 def int_hexagon_V6_vaddclbw :
10065 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddclbw">;
10066
10067 //
10068 // BUILTIN_INFO(HEXAGON.V6_vaddclbw_128B,VI_ftype_VIVI,2)
10069 // tag : V6_vaddclbw_128B
10070 def int_hexagon_V6_vaddclbw_128B :
10071 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddclbw_128B">;
10072
10073 //
10074 // BUILTIN_INFO(HEXAGON.V6_vaddclbh,VI_ftype_VIVI,2)
10075 // tag : V6_vaddclbh
10076 def int_hexagon_V6_vaddclbh :
10077 Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddclbh">;
10078
10079 //
10080 // BUILTIN_INFO(HEXAGON.V6_vaddclbh_128B,VI_ftype_VIVI,2)
10081 // tag : V6_vaddclbh_128B
10082 def int_hexagon_V6_vaddclbh_128B :
10083 Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddclbh_128B">;
10084
10085 //
10086 // BUILTIN_INFO(HEXAGON.V6_vlutvvbi,VI_ftype_VIVISI,3)
10087 // tag : V6_vlutvvbi
10088 def int_hexagon_V6_vlutvvbi :
10089 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvbi">;
10090
10091 //
10092 // BUILTIN_INFO(HEXAGON.V6_vlutvvbi_128B,VI_ftype_VIVISI,3)
10093 // tag : V6_vlutvvbi_128B
10094 def int_hexagon_V6_vlutvvbi_128B :
10095 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvbi_128B">;
10096
10097 //
10098 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracci,VI_ftype_VIVIVISI,4)
10099 // tag : V6_vlutvvb_oracci
10100 def int_hexagon_V6_vlutvvb_oracci :
10101 Hexagon_V62_v512v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_oracci">;
10102
10103 //
10104 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracci_128B,VI_ftype_VIVIVISI,4)
10105 // tag : V6_vlutvvb_oracci_128B
10106 def int_hexagon_V6_vlutvvb_oracci_128B :
10107 Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B">;
10108
10109 //
10110 // BUILTIN_INFO(HEXAGON.V6_vlutvwhi,VD_ftype_VIVISI,3)
10111 // tag : V6_vlutvwhi
10112 def int_hexagon_V6_vlutvwhi :
10113 Hexagon_V62_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwhi">;
10114
10115 //
10116 // BUILTIN_INFO(HEXAGON.V6_vlutvwhi_128B,VD_ftype_VIVISI,3)
10117 // tag : V6_vlutvwhi_128B
10118 def int_hexagon_V6_vlutvwhi_128B :
10119 Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwhi_128B">;
10120
10121 //
10122 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracci,VD_ftype_VDVIVISI,4)
10123 // tag : V6_vlutvwh_oracci
10124 def int_hexagon_V6_vlutvwh_oracci :
10125 Hexagon_V62_v1024v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_oracci">;
10126
10127 //
10128 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracci_128B,VD_ftype_VDVIVISI,4)
10129 // tag : V6_vlutvwh_oracci_128B
10130 def int_hexagon_V6_vlutvwh_oracci_128B :
10131 Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B">;
10132
10133 //
10134 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_nm,VI_ftype_VIVISI,3)
10135 // tag : V6_vlutvvb_nm
10136 def int_hexagon_V6_vlutvvb_nm :
10137 Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_nm">;
10138
10139 //
10140 // BUILTIN_INFO(HEXAGON.V6_vlutvvb_nm_128B,VI_ftype_VIVISI,3)
10141 // tag : V6_vlutvvb_nm_128B
10142 def int_hexagon_V6_vlutvvb_nm_128B :
10143 Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">;
10144
10145 //
10146 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_nm,VD_ftype_VIVISI,3)
10147 // tag : V6_vlutvwh_nm
10148 def int_hexagon_V6_vlutvwh_nm :
10149 Hexagon_V62_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_nm">;
10150
10151 //
10152 // BUILTIN_INFO(HEXAGON.V6_vlutvwh_nm_128B,VD_ftype_VIVISI,3)
10153 // tag : V6_vlutvwh_nm_128B
10154 def int_hexagon_V6_vlutvwh_nm_128B :
10155 Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;
10156
10157 //
10158 // BUILTIN_INFO(HEXAGON.V6_vaddcarry,VI_ftype_VIVIQV,3)
10159 // tag: V6_vaddcarry
10160 def int_hexagon_V6_vaddcarry :
10161 Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vaddcarry">;
10162
10163 //
10164 // BUILTIN_INFO(HEXAGON.V6_vaddcarry_128B,VI_ftype_VIVIQV,3)
10165 // tag: V6_vaddcarry_128B
10166 def int_hexagon_V6_vaddcarry_128B :
10167 Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vaddcarry_128B">;
10168
10169 //
10170 // BUILTIN_INFO(HEXAGON.V6_vsubcarry,VI_ftype_VIVIQV,3)
10171 // tag: V6_vsubcarry
10172 def int_hexagon_V6_vsubcarry :
10173 Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vsubcarry">;
10174
10175 //
10176 // BUILTIN_INFO(HEXAGON.V6_vsubcarry_128B,VI_ftype_VIVIQV,3)
10177 // tag: V6_vsubcarry_128B
10178 def int_hexagon_V6_vsubcarry_128B :
10179 Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vsubcarry_128B">;
10180
10181
10182 ///
10183 /// HexagonV65 intrinsics
10184 ///
10185
10186 //
10187 // Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix>
10188 // tag : A6_vcmpbeq_notany
10189 class Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix>
10190  : Hexagon_Intrinsic<GCCIntSuffix,
10191                           [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
10192                           [IntrNoMem]>;
10193
10194 //
10195 // Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix>
10196 // tag : V6_vrmpyub_rtt
10197 class Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix>
10198  : Hexagon_Intrinsic<GCCIntSuffix,
10199                           [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
10200                           [IntrNoMem]>;
10201
10202 //
10203 // Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix>
10204 // tag : V6_vrmpyub_rtt_128B
10205 class Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix>
10206  : Hexagon_Intrinsic<GCCIntSuffix,
10207                           [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
10208                           [IntrNoMem]>;
10209
10210 //
10211 // Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix>
10212 // tag : V6_vrmpyub_rtt_acc
10213 class Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix>
10214  : Hexagon_Intrinsic<GCCIntSuffix,
10215                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
10216                           [IntrNoMem]>;
10217
10218 //
10219 // Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix>
10220 // tag : V6_vrmpyub_rtt_acc_128B
10221 class Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix>
10222  : Hexagon_Intrinsic<GCCIntSuffix,
10223                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
10224                           [IntrNoMem]>;
10225
10226 //
10227 // Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix>
10228 // tag : V6_vasruwuhsat
10229 class Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix>
10230  : Hexagon_Intrinsic<GCCIntSuffix,
10231                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
10232                           [IntrNoMem]>;
10233
10234 //
10235 // Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
10236 // tag : V6_vasruwuhsat_128B
10237 class Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
10238  : Hexagon_Intrinsic<GCCIntSuffix,
10239                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
10240                           [IntrNoMem]>;
10241
10242 //
10243 // Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix>
10244 // tag : V6_vavguw
10245 class Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix>
10246  : Hexagon_Intrinsic<GCCIntSuffix,
10247                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
10248                           [IntrNoMem]>;
10249
10250 //
10251 // Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
10252 // tag : V6_vavguw_128B
10253 class Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
10254  : Hexagon_Intrinsic<GCCIntSuffix,
10255                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
10256                           [IntrNoMem]>;
10257
10258 //
10259 // Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix>
10260 // tag : V6_vabsb
10261 class Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix>
10262  : Hexagon_Intrinsic<GCCIntSuffix,
10263                           [llvm_v16i32_ty], [llvm_v16i32_ty],
10264                           [IntrNoMem]>;
10265
10266 //
10267 // Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix>
10268 // tag : V6_vabsb_128B
10269 class Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix>
10270  : Hexagon_Intrinsic<GCCIntSuffix,
10271                           [llvm_v32i32_ty], [llvm_v32i32_ty],
10272                           [IntrNoMem]>;
10273
10274 //
10275 // Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix>
10276 // tag : V6_vmpabuu
10277 class Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix>
10278  : Hexagon_Intrinsic<GCCIntSuffix,
10279                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
10280                           [IntrNoMem]>;
10281
10282 //
10283 // Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix>
10284 // tag : V6_vmpabuu_128B
10285 class Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix>
10286  : Hexagon_Intrinsic<GCCIntSuffix,
10287                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
10288                           [IntrNoMem]>;
10289
10290 //
10291 // Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
10292 // tag : V6_vmpabuu_acc_128B
10293 class Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
10294  : Hexagon_Intrinsic<GCCIntSuffix,
10295                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
10296                           [IntrNoMem]>;
10297
10298 //
10299 // Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
10300 // tag : V6_vmpyh_acc
10301 class Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
10302  : Hexagon_Intrinsic<GCCIntSuffix,
10303                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
10304                           [IntrNoMem]>;
10305
10306 //
10307 // Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
10308 // tag : V6_vmpyh_acc_128B
10309 class Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
10310  : Hexagon_Intrinsic<GCCIntSuffix,
10311                           [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
10312                           [IntrNoMem]>;
10313
10314 //
10315 // Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix>
10316 // tag : V6_vmpahhsat
10317 class Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix>
10318  : Hexagon_Intrinsic<GCCIntSuffix,
10319                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],
10320                           [IntrNoMem]>;
10321
10322 //
10323 // Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix>
10324 // tag : V6_vmpahhsat_128B
10325 class Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix>
10326  : Hexagon_Intrinsic<GCCIntSuffix,
10327                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],
10328                           [IntrNoMem]>;
10329
10330 //
10331 // Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix>
10332 // tag : V6_vlut4
10333 class Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix>
10334  : Hexagon_Intrinsic<GCCIntSuffix,
10335                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
10336                           [IntrNoMem]>;
10337
10338 //
10339 // Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix>
10340 // tag : V6_vlut4_128B
10341 class Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix>
10342  : Hexagon_Intrinsic<GCCIntSuffix,
10343                           [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
10344                           [IntrNoMem]>;
10345
10346 //
10347 // Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix>
10348 // tag : V6_vmpyuhe
10349 class Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix>
10350  : Hexagon_Intrinsic<GCCIntSuffix,
10351                           [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
10352                           [IntrNoMem]>;
10353
10354 //
10355 // Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix>
10356 // tag : V6_vprefixqb
10357 class Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix>
10358  : Hexagon_Intrinsic<GCCIntSuffix,
10359                           [llvm_v16i32_ty], [llvm_v512i1_ty],
10360                           [IntrNoMem]>;
10361
10362 //
10363 // Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix>
10364 // tag : V6_vprefixqb_128B
10365 class Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix>
10366  : Hexagon_Intrinsic<GCCIntSuffix,
10367                           [llvm_v32i32_ty], [llvm_v1024i1_ty],
10368                           [IntrNoMem]>;
10369
10370 //
10371 // BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany,QI_ftype_DIDI,2)
10372 // tag : A6_vcmpbeq_notany
10373 def int_hexagon_A6_vcmpbeq_notany :
10374 Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;
10375
10376 //
10377 // BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany_128B,QI_ftype_DIDI,2)
10378 // tag : A6_vcmpbeq_notany_128B
10379 def int_hexagon_A6_vcmpbeq_notany_128B :
10380 Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany_128B">;
10381
10382 //
10383 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt,VD_ftype_VIDI,2)
10384 // tag : V6_vrmpyub_rtt
10385 def int_hexagon_V6_vrmpyub_rtt :
10386 Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;
10387
10388 //
10389 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_128B,VD_ftype_VIDI,2)
10390 // tag : V6_vrmpyub_rtt_128B
10391 def int_hexagon_V6_vrmpyub_rtt_128B :
10392 Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;
10393
10394 //
10395 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc,VD_ftype_VDVIDI,3)
10396 // tag : V6_vrmpyub_rtt_acc
10397 def int_hexagon_V6_vrmpyub_rtt_acc :
10398 Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;
10399
10400 //
10401 // BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc_128B,VD_ftype_VDVIDI,3)
10402 // tag : V6_vrmpyub_rtt_acc_128B
10403 def int_hexagon_V6_vrmpyub_rtt_acc_128B :
10404 Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;
10405
10406 //
10407 // BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt,VD_ftype_VIDI,2)
10408 // tag : V6_vrmpybub_rtt
10409 def int_hexagon_V6_vrmpybub_rtt :
10410 Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;
10411
10412 //
10413 // BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_128B,VD_ftype_VIDI,2)
10414 // tag : V6_vrmpybub_rtt_128B
10415 def int_hexagon_V6_vrmpybub_rtt_128B :
10416 Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;
10417
10418 //
10419 // BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc,VD_ftype_VDVIDI,3)
10420 // tag : V6_vrmpybub_rtt_acc
10421 def int_hexagon_V6_vrmpybub_rtt_acc :
10422 Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;
10423
10424 //
10425 // BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc_128B,VD_ftype_VDVIDI,3)
10426 // tag : V6_vrmpybub_rtt_acc_128B
10427 def int_hexagon_V6_vrmpybub_rtt_acc_128B :
10428 Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;
10429
10430 //
10431 // BUILTIN_INFO(HEXAGON.V6_vasruwuhsat,VI_ftype_VIVISI,3)
10432 // tag : V6_vasruwuhsat
10433 def int_hexagon_V6_vasruwuhsat :
10434 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhsat">;
10435
10436 //
10437 // BUILTIN_INFO(HEXAGON.V6_vasruwuhsat_128B,VI_ftype_VIVISI,3)
10438 // tag : V6_vasruwuhsat_128B
10439 def int_hexagon_V6_vasruwuhsat_128B :
10440 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;
10441
10442 //
10443 // BUILTIN_INFO(HEXAGON.V6_vasruhubsat,VI_ftype_VIVISI,3)
10444 // tag : V6_vasruhubsat
10445 def int_hexagon_V6_vasruhubsat :
10446 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubsat">;
10447
10448 //
10449 // BUILTIN_INFO(HEXAGON.V6_vasruhubsat_128B,VI_ftype_VIVISI,3)
10450 // tag : V6_vasruhubsat_128B
10451 def int_hexagon_V6_vasruhubsat_128B :
10452 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;
10453
10454 //
10455 // BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat,VI_ftype_VIVISI,3)
10456 // tag : V6_vasruhubrndsat
10457 def int_hexagon_V6_vasruhubrndsat :
10458 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;
10459
10460 //
10461 // BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat_128B,VI_ftype_VIVISI,3)
10462 // tag : V6_vasruhubrndsat_128B
10463 def int_hexagon_V6_vasruhubrndsat_128B :
10464 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;
10465
10466 //
10467 // BUILTIN_INFO(HEXAGON.V6_vaslh_acc,VI_ftype_VIVISI,3)
10468 // tag : V6_vaslh_acc
10469 def int_hexagon_V6_vaslh_acc :
10470 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslh_acc">;
10471
10472 //
10473 // BUILTIN_INFO(HEXAGON.V6_vaslh_acc_128B,VI_ftype_VIVISI,3)
10474 // tag : V6_vaslh_acc_128B
10475 def int_hexagon_V6_vaslh_acc_128B :
10476 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;
10477
10478 //
10479 // BUILTIN_INFO(HEXAGON.V6_vasrh_acc,VI_ftype_VIVISI,3)
10480 // tag : V6_vasrh_acc
10481 def int_hexagon_V6_vasrh_acc :
10482 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrh_acc">;
10483
10484 //
10485 // BUILTIN_INFO(HEXAGON.V6_vasrh_acc_128B,VI_ftype_VIVISI,3)
10486 // tag : V6_vasrh_acc_128B
10487 def int_hexagon_V6_vasrh_acc_128B :
10488 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;
10489
10490 //
10491 // BUILTIN_INFO(HEXAGON.V6_vavguw,VI_ftype_VIVI,2)
10492 // tag : V6_vavguw
10493 def int_hexagon_V6_vavguw :
10494 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguw">;
10495
10496 //
10497 // BUILTIN_INFO(HEXAGON.V6_vavguw_128B,VI_ftype_VIVI,2)
10498 // tag : V6_vavguw_128B
10499 def int_hexagon_V6_vavguw_128B :
10500 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguw_128B">;
10501
10502 //
10503 // BUILTIN_INFO(HEXAGON.V6_vavguwrnd,VI_ftype_VIVI,2)
10504 // tag : V6_vavguwrnd
10505 def int_hexagon_V6_vavguwrnd :
10506 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguwrnd">;
10507
10508 //
10509 // BUILTIN_INFO(HEXAGON.V6_vavguwrnd_128B,VI_ftype_VIVI,2)
10510 // tag : V6_vavguwrnd_128B
10511 def int_hexagon_V6_vavguwrnd_128B :
10512 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;
10513
10514 //
10515 // BUILTIN_INFO(HEXAGON.V6_vavgb,VI_ftype_VIVI,2)
10516 // tag : V6_vavgb
10517 def int_hexagon_V6_vavgb :
10518 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgb">;
10519
10520 //
10521 // BUILTIN_INFO(HEXAGON.V6_vavgb_128B,VI_ftype_VIVI,2)
10522 // tag : V6_vavgb_128B
10523 def int_hexagon_V6_vavgb_128B :
10524 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgb_128B">;
10525
10526 //
10527 // BUILTIN_INFO(HEXAGON.V6_vavgbrnd,VI_ftype_VIVI,2)
10528 // tag : V6_vavgbrnd
10529 def int_hexagon_V6_vavgbrnd :
10530 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgbrnd">;
10531
10532 //
10533 // BUILTIN_INFO(HEXAGON.V6_vavgbrnd_128B,VI_ftype_VIVI,2)
10534 // tag : V6_vavgbrnd_128B
10535 def int_hexagon_V6_vavgbrnd_128B :
10536 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;
10537
10538 //
10539 // BUILTIN_INFO(HEXAGON.V6_vnavgb,VI_ftype_VIVI,2)
10540 // tag : V6_vnavgb
10541 def int_hexagon_V6_vnavgb :
10542 Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgb">;
10543
10544 //
10545 // BUILTIN_INFO(HEXAGON.V6_vnavgb_128B,VI_ftype_VIVI,2)
10546 // tag : V6_vnavgb_128B
10547 def int_hexagon_V6_vnavgb_128B :
10548 Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgb_128B">;
10549
10550 //
10551 // BUILTIN_INFO(HEXAGON.V6_vabsb,VI_ftype_VI,1)
10552 // tag : V6_vabsb
10553 def int_hexagon_V6_vabsb :
10554 Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb">;
10555
10556 //
10557 // BUILTIN_INFO(HEXAGON.V6_vabsb_128B,VI_ftype_VI,1)
10558 // tag : V6_vabsb_128B
10559 def int_hexagon_V6_vabsb_128B :
10560 Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_128B">;
10561
10562 //
10563 // BUILTIN_INFO(HEXAGON.V6_vabsb_sat,VI_ftype_VI,1)
10564 // tag : V6_vabsb_sat
10565 def int_hexagon_V6_vabsb_sat :
10566 Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb_sat">;
10567
10568 //
10569 // BUILTIN_INFO(HEXAGON.V6_vabsb_sat_128B,VI_ftype_VI,1)
10570 // tag : V6_vabsb_sat_128B
10571 def int_hexagon_V6_vabsb_sat_128B :
10572 Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;
10573
10574 //
10575 // BUILTIN_INFO(HEXAGON.V6_vmpabuu,VD_ftype_VDSI,2)
10576 // tag : V6_vmpabuu
10577 def int_hexagon_V6_vmpabuu :
10578 Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu">;
10579
10580 //
10581 // BUILTIN_INFO(HEXAGON.V6_vmpabuu_128B,VD_ftype_VDSI,2)
10582 // tag : V6_vmpabuu_128B
10583 def int_hexagon_V6_vmpabuu_128B :
10584 Hexagon_V65_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;
10585
10586 //
10587 // BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc,VD_ftype_VDVDSI,3)
10588 // tag : V6_vmpabuu_acc
10589 def int_hexagon_V6_vmpabuu_acc :
10590 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;
10591
10592 //
10593 // BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc_128B,VD_ftype_VDVDSI,3)
10594 // tag : V6_vmpabuu_acc_128B
10595 def int_hexagon_V6_vmpabuu_acc_128B :
10596 Hexagon_V65_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;
10597
10598 //
10599 // BUILTIN_INFO(HEXAGON.V6_vmpyh_acc,VD_ftype_VDVISI,3)
10600 // tag : V6_vmpyh_acc
10601 def int_hexagon_V6_vmpyh_acc :
10602 Hexagon_V65_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh_acc">;
10603
10604 //
10605 // BUILTIN_INFO(HEXAGON.V6_vmpyh_acc_128B,VD_ftype_VDVISI,3)
10606 // tag : V6_vmpyh_acc_128B
10607 def int_hexagon_V6_vmpyh_acc_128B :
10608 Hexagon_V65_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;
10609
10610 //
10611 // BUILTIN_INFO(HEXAGON.V6_vmpahhsat,VI_ftype_VIVIDI,3)
10612 // tag : V6_vmpahhsat
10613 def int_hexagon_V6_vmpahhsat :
10614 Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpahhsat">;
10615
10616 //
10617 // BUILTIN_INFO(HEXAGON.V6_vmpahhsat_128B,VI_ftype_VIVIDI,3)
10618 // tag : V6_vmpahhsat_128B
10619 def int_hexagon_V6_vmpahhsat_128B :
10620 Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;
10621
10622 //
10623 // BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat,VI_ftype_VIVIDI,3)
10624 // tag : V6_vmpauhuhsat
10625 def int_hexagon_V6_vmpauhuhsat :
10626 Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;
10627
10628 //
10629 // BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat_128B,VI_ftype_VIVIDI,3)
10630 // tag : V6_vmpauhuhsat_128B
10631 def int_hexagon_V6_vmpauhuhsat_128B :
10632 Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;
10633
10634 //
10635 // BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat,VI_ftype_VIVIDI,3)
10636 // tag : V6_vmpsuhuhsat
10637 def int_hexagon_V6_vmpsuhuhsat :
10638 Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;
10639
10640 //
10641 // BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat_128B,VI_ftype_VIVIDI,3)
10642 // tag : V6_vmpsuhuhsat_128B
10643 def int_hexagon_V6_vmpsuhuhsat_128B :
10644 Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;
10645
10646 //
10647 // BUILTIN_INFO(HEXAGON.V6_vlut4,VI_ftype_VIDI,2)
10648 // tag : V6_vlut4
10649 def int_hexagon_V6_vlut4 :
10650 Hexagon_V65_v512v512LLi_Intrinsic<"HEXAGON_V6_vlut4">;
10651
10652 //
10653 // BUILTIN_INFO(HEXAGON.V6_vlut4_128B,VI_ftype_VIDI,2)
10654 // tag : V6_vlut4_128B
10655 def int_hexagon_V6_vlut4_128B :
10656 Hexagon_V65_v1024v1024LLi_Intrinsic<"HEXAGON_V6_vlut4_128B">;
10657
10658 //
10659 // BUILTIN_INFO(HEXAGON.V6_vmpyuhe,VI_ftype_VISI,2)
10660 // tag : V6_vmpyuhe
10661 def int_hexagon_V6_vmpyuhe :
10662 Hexagon_V65_v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe">;
10663
10664 //
10665 // BUILTIN_INFO(HEXAGON.V6_vmpyuhe_128B,VI_ftype_VISI,2)
10666 // tag : V6_vmpyuhe_128B
10667 def int_hexagon_V6_vmpyuhe_128B :
10668 Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;
10669
10670 //
10671 // BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc,VI_ftype_VIVISI,3)
10672 // tag : V6_vmpyuhe_acc
10673 def int_hexagon_V6_vmpyuhe_acc :
10674 Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;
10675
10676 //
10677 // BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc_128B,VI_ftype_VIVISI,3)
10678 // tag : V6_vmpyuhe_acc_128B
10679 def int_hexagon_V6_vmpyuhe_acc_128B :
10680 Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;
10681
10682 //
10683 // BUILTIN_INFO(HEXAGON.V6_vprefixqb,VI_ftype_QV,1)
10684 // tag : V6_vprefixqb
10685 def int_hexagon_V6_vprefixqb :
10686 Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqb">;
10687
10688 //
10689 // BUILTIN_INFO(HEXAGON.V6_vprefixqb_128B,VI_ftype_QV,1)
10690 // tag : V6_vprefixqb_128B
10691 def int_hexagon_V6_vprefixqb_128B :
10692 Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;
10693
10694 //
10695 // BUILTIN_INFO(HEXAGON.V6_vprefixqh,VI_ftype_QV,1)
10696 // tag : V6_vprefixqh
10697 def int_hexagon_V6_vprefixqh :
10698 Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqh">;
10699
10700 //
10701 // BUILTIN_INFO(HEXAGON.V6_vprefixqh_128B,VI_ftype_QV,1)
10702 // tag : V6_vprefixqh_128B
10703 def int_hexagon_V6_vprefixqh_128B :
10704 Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;
10705
10706 //
10707 // BUILTIN_INFO(HEXAGON.V6_vprefixqw,VI_ftype_QV,1)
10708 // tag : V6_vprefixqw
10709 def int_hexagon_V6_vprefixqw :
10710 Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqw">;
10711
10712 //
10713 // BUILTIN_INFO(HEXAGON.V6_vprefixqw_128B,VI_ftype_QV,1)
10714 // tag : V6_vprefixqw_128B
10715 def int_hexagon_V6_vprefixqw_128B :
10716 Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;
10717
10718
10719 // The scatter/gather ones below will not be generated from iset.py. Make sure
10720 // you don't overwrite these.
10721 class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix>
10722  : Hexagon_Intrinsic<GCCIntSuffix,
10723                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
10724                                llvm_v16i32_ty],
10725                           [IntrArgMemOnly]>;
10726
10727 class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix>
10728  : Hexagon_Intrinsic<GCCIntSuffix,
10729                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
10730                                llvm_v32i32_ty],
10731                           [IntrArgMemOnly]>;
10732
10733 class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix>
10734  : Hexagon_Intrinsic<GCCIntSuffix,
10735                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
10736                                llvm_v64i32_ty],
10737                           [IntrArgMemOnly]>;
10738
10739 class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix>
10740  : Hexagon_Intrinsic<GCCIntSuffix,
10741                           [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
10742                                llvm_i32_ty,llvm_v16i32_ty],
10743                           [IntrArgMemOnly]>;
10744
10745 class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix>
10746  : Hexagon_Intrinsic<GCCIntSuffix,
10747                           [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
10748                                llvm_i32_ty,llvm_v32i32_ty],
10749                           [IntrArgMemOnly]>;
10750
10751 class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix>
10752  : Hexagon_Intrinsic<GCCIntSuffix,
10753                           [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
10754                                llvm_i32_ty,llvm_v32i32_ty],
10755                           [IntrArgMemOnly]>;
10756
10757 class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix>
10758  : Hexagon_Intrinsic<GCCIntSuffix,
10759                           [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
10760                                llvm_i32_ty,llvm_v64i32_ty],
10761                           [IntrArgMemOnly]>;
10762
10763 def int_hexagon_V6_vgathermw :
10764 Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;
10765
10766 def int_hexagon_V6_vgathermw_128B :
10767 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;
10768
10769 def int_hexagon_V6_vgathermh :
10770 Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;
10771
10772 def int_hexagon_V6_vgathermh_128B :
10773 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;
10774
10775 def int_hexagon_V6_vgathermhw :
10776 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;
10777
10778 def int_hexagon_V6_vgathermhw_128B :
10779 Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;
10780
10781 def int_hexagon_V6_vgathermwq :
10782 Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;
10783
10784 def int_hexagon_V6_vgathermwq_128B :
10785 Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;
10786
10787 def int_hexagon_V6_vgathermhq :
10788 Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;
10789
10790 def int_hexagon_V6_vgathermhq_128B :
10791 Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;
10792
10793 def int_hexagon_V6_vgathermhwq :
10794 Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;
10795
10796 def int_hexagon_V6_vgathermhwq_128B :
10797 Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;
10798
10799 class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix>
10800  : Hexagon_Intrinsic<GCCIntSuffix,
10801                           [], [llvm_i32_ty,llvm_i32_ty,
10802                                            llvm_v16i32_ty,llvm_v16i32_ty],
10803                           [IntrWriteMem]>;
10804
10805 class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix>
10806  : Hexagon_Intrinsic<GCCIntSuffix,
10807                           [], [llvm_i32_ty,llvm_i32_ty,
10808                                            llvm_v32i32_ty,llvm_v32i32_ty],
10809                           [IntrWriteMem]>;
10810
10811 class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix>
10812  : Hexagon_Intrinsic<GCCIntSuffix,
10813                           [], [llvm_v512i1_ty,llvm_i32_ty,
10814                                            llvm_i32_ty,llvm_v16i32_ty,
10815                                            llvm_v16i32_ty],
10816                           [IntrWriteMem]>;
10817
10818 class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix>
10819  : Hexagon_Intrinsic<GCCIntSuffix,
10820                           [], [llvm_v1024i1_ty,llvm_i32_ty,
10821                                            llvm_i32_ty,llvm_v32i32_ty,
10822                                            llvm_v32i32_ty],
10823                           [IntrWriteMem]>;
10824
10825 class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix>
10826  : Hexagon_Intrinsic<GCCIntSuffix,
10827                           [], [llvm_i32_ty,llvm_i32_ty,
10828                                            llvm_v32i32_ty,llvm_v16i32_ty],
10829                           [IntrWriteMem]>;
10830
10831 class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix>
10832  : Hexagon_Intrinsic<GCCIntSuffix,
10833                           [], [llvm_i32_ty,llvm_i32_ty,
10834                                            llvm_v64i32_ty,llvm_v32i32_ty],
10835                           [IntrWriteMem]>;
10836
10837 class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix>
10838  : Hexagon_Intrinsic<GCCIntSuffix,
10839                           [], [llvm_v512i1_ty,llvm_i32_ty,
10840                                            llvm_i32_ty,llvm_v32i32_ty,
10841                                            llvm_v16i32_ty],
10842                           [IntrWriteMem]>;
10843
10844 class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix>
10845  : Hexagon_Intrinsic<GCCIntSuffix,
10846                           [], [llvm_v1024i1_ty,llvm_i32_ty,
10847                                            llvm_i32_ty,llvm_v64i32_ty,
10848                                            llvm_v32i32_ty],
10849                           [IntrWriteMem]>;
10850
10851 class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix>
10852  : Hexagon_Intrinsic<GCCIntSuffix,
10853                           [llvm_v64i32_ty], [],
10854                           [IntrNoMem]>;
10855
10856 //
10857 // BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)
10858 // tag : V6_vscattermw
10859 def int_hexagon_V6_vscattermw :
10860 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;
10861
10862 //
10863 // BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)
10864 // tag : V6_vscattermw_128B
10865 def int_hexagon_V6_vscattermw_128B :
10866 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;
10867
10868 //
10869 // BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)
10870 // tag : V6_vscattermh
10871 def int_hexagon_V6_vscattermh :
10872 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;
10873
10874 //
10875 // BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)
10876 // tag : V6_vscattermh_128B
10877 def int_hexagon_V6_vscattermh_128B :
10878 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;
10879
10880 //
10881 // BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)
10882 // tag : V6_vscattermw_add
10883 def int_hexagon_V6_vscattermw_add :
10884 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;
10885
10886 //
10887 // BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)
10888 // tag : V6_vscattermw_add_128B
10889 def int_hexagon_V6_vscattermw_add_128B :
10890 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;
10891
10892 //
10893 // BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)
10894 // tag : V6_vscattermh_add
10895 def int_hexagon_V6_vscattermh_add :
10896 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;
10897
10898 //
10899 // BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)
10900 // tag : V6_vscattermh_add_128B
10901 def int_hexagon_V6_vscattermh_add_128B :
10902 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;
10903
10904 //
10905 // BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)
10906 // tag : V6_vscattermwq
10907 def int_hexagon_V6_vscattermwq :
10908 Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;
10909
10910 //
10911 // BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)
10912 // tag : V6_vscattermwq_128B
10913 def int_hexagon_V6_vscattermwq_128B :
10914 Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;
10915
10916 //
10917 // BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)
10918 // tag : V6_vscattermhq
10919 def int_hexagon_V6_vscattermhq :
10920 Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;
10921
10922 //
10923 // BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)
10924 // tag : V6_vscattermhq_128B
10925 def int_hexagon_V6_vscattermhq_128B :
10926 Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;
10927
10928 //
10929 // BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)
10930 // tag : V6_vscattermhw
10931 def int_hexagon_V6_vscattermhw :
10932 Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;
10933
10934 //
10935 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)
10936 // tag : V6_vscattermhw_128B
10937 def int_hexagon_V6_vscattermhw_128B :
10938 Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;
10939
10940 //
10941 // BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)
10942 // tag : V6_vscattermhwq
10943 def int_hexagon_V6_vscattermhwq :
10944 Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;
10945
10946 //
10947 // BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)
10948 // tag : V6_vscattermhwq_128B
10949 def int_hexagon_V6_vscattermhwq_128B :
10950 Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;
10951
10952 //
10953 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)
10954 // tag : V6_vscattermhw_add
10955 def int_hexagon_V6_vscattermhw_add :
10956 Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;
10957
10958 //
10959 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)
10960 // tag : V6_vscattermhw_add_128B
10961 def int_hexagon_V6_vscattermhw_add_128B :
10962 Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;
10963
10964 //
10965 // BUILTIN_INFO(HEXAGON.V6_vdd0,VD_ftype_,0)
10966 // tag : V6_vdd0
10967 def int_hexagon_V6_vdd0 :
10968 Hexagon_v1024_Intrinsic<"HEXAGON_V6_vdd0">;
10969
10970 //
10971 // BUILTIN_INFO(HEXAGON.V6_vdd0_128B,VD_ftype_,0)
10972 // tag : V6_vdd0_128B
10973 def int_hexagon_V6_vdd0_128B :
10974 Hexagon_V65_v2048_Intrinsic<"HEXAGON_V6_vdd0_128B">;