1 //===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCInstrAnalysis class which the MCTargetDescs can
11 // derive from to give additional information to MC.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRANALYSIS_H
16 #define LLVM_MC_MCINSTRANALYSIS_H
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCInstrInfo.h"
27 class MCInstrAnalysis {
31 const MCInstrInfo *Info;
34 MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}
35 virtual ~MCInstrAnalysis() = default;
37 virtual bool isBranch(const MCInst &Inst) const {
38 return Info->get(Inst.getOpcode()).isBranch();
41 virtual bool isConditionalBranch(const MCInst &Inst) const {
42 return Info->get(Inst.getOpcode()).isConditionalBranch();
45 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
46 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
49 virtual bool isIndirectBranch(const MCInst &Inst) const {
50 return Info->get(Inst.getOpcode()).isIndirectBranch();
53 virtual bool isCall(const MCInst &Inst) const {
54 return Info->get(Inst.getOpcode()).isCall();
57 virtual bool isReturn(const MCInst &Inst) const {
58 return Info->get(Inst.getOpcode()).isReturn();
61 virtual bool isTerminator(const MCInst &Inst) const {
62 return Info->get(Inst.getOpcode()).isTerminator();
65 /// Returns true if at least one of the register writes performed by
66 /// \param Inst implicitly clears the upper portion of all super-registers.
68 /// Example: on X86-64, a write to EAX implicitly clears the upper half of
69 /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit
70 /// instruction implicitly clears the upper portion of the correspondent
73 /// This method also updates an APInt which is used as mask of register
74 /// writes. There is one bit for every explicit/implicit write performed by
75 /// the instruction. If a write implicitly clears its super-registers, then
76 /// the corresponding bit is set (vic. the corresponding bit is cleared).
78 /// The first bits in the APint are related to explicit writes. The remaining
79 /// bits are related to implicit writes. The sequence of writes follows the
80 /// machine operand sequence. For implicit writes, the sequence is defined by
83 /// The assumption is that the bit-width of the APInt is correctly set by
84 /// the caller. The default implementation conservatively assumes that none of
85 /// the writes clears the upper portion of a super-register.
86 virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
90 /// Returns true if \param Inst is a dependency breaking instruction for the
93 /// The value computed by a dependency breaking instruction is not dependent
94 /// on the inputs. An example of dependency breaking instruction on X86 is
96 /// TODO: In future, we could implement an alternative approach where this
97 /// method returns `true` if the input instruction is not dependent on
98 /// some/all of its input operands. An APInt mask could then be used to
99 /// identify independent operands.
100 virtual bool isDependencyBreaking(const MCSubtargetInfo &STI,
101 const MCInst &Inst) const;
103 /// Given a branch instruction try to get the address the branch
104 /// targets. Return true on success, and the address in Target.
106 evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
107 uint64_t &Target) const;
110 } // end namespace llvm
112 #endif // LLVM_MC_MCINSTRANALYSIS_H