1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/Support/DataTypes.h"
24 class MCSubtargetInfo;
27 //===----------------------------------------------------------------------===//
28 // Machine Operand Flags and Description
29 //===----------------------------------------------------------------------===//
32 // Operand constraints
33 enum OperandConstraint {
34 TIED_TO = 0, // Must be allocated the same register as.
35 EARLY_CLOBBER // Operand is an early clobber register operand
38 /// \brief These are flags set on operands, but should be considered
39 /// private, all access should go through the MCOperandInfo accessors.
40 /// See the accessors for a description of what these are.
41 enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef };
43 /// \brief Operands are tagged with one of the values of this enum.
46 OPERAND_IMMEDIATE = 1,
51 OPERAND_FIRST_GENERIC = 6,
52 OPERAND_GENERIC_0 = 6,
53 OPERAND_GENERIC_1 = 7,
54 OPERAND_GENERIC_2 = 8,
55 OPERAND_GENERIC_3 = 9,
56 OPERAND_GENERIC_4 = 10,
57 OPERAND_GENERIC_5 = 11,
58 OPERAND_LAST_GENERIC = 11,
60 OPERAND_FIRST_TARGET = 12,
63 enum GenericOperandType {
68 /// \brief This holds information about one operand of a machine instruction,
69 /// indicating the register class for register operands, etc.
72 /// \brief This specifies the register class enumeration of the operand
73 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
74 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
75 /// get a dynamic register class.
78 /// \brief These are flags from the MCOI::OperandFlags enum.
81 /// \brief Information about the type of the operand.
83 /// \brief The lower 16 bits are used to specify which constraints are set.
84 /// The higher 16 bits are used to specify the value of constraints (4 bits
88 /// \brief Set if this operand is a pointer value and it requires a callback
89 /// to look up its register class.
90 bool isLookupPtrRegClass() const {
91 return Flags & (1 << MCOI::LookupPtrRegClass);
94 /// \brief Set if this is one of the operands that made up of the predicate
95 /// operand that controls an isPredicable() instruction.
96 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
98 /// \brief Set if this operand is a optional def.
99 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
101 bool isGenericType() const {
102 return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
103 OperandType <= MCOI::OPERAND_LAST_GENERIC;
106 unsigned getGenericTypeIndex() const {
107 assert(isGenericType() && "non-generic types don't have an index");
108 return OperandType - MCOI::OPERAND_FIRST_GENERIC;
112 //===----------------------------------------------------------------------===//
113 // Machine Instruction Flags and Description
114 //===----------------------------------------------------------------------===//
117 /// \brief These should be considered private to the implementation of the
118 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
119 /// not use these directly. These all correspond to bitfields in the
120 /// MCInstrDesc::Flags field.
141 UnmodeledSideEffects,
158 /// \brief Describe properties that are true of each instruction in the target
159 /// description file. This captures information about side effects, register
160 /// use and many other things. There is one instance of this struct for each
161 /// target instruction class, and the MachineInstr class points to this struct
162 /// directly to describe itself.
165 unsigned short Opcode; // The opcode number
166 unsigned short NumOperands; // Num of args (may be more if variable_ops)
167 unsigned char NumDefs; // Num of args that are definitions
168 unsigned char Size; // Number of bytes in encoding.
169 unsigned short SchedClass; // enum identifying instr sched class
170 uint64_t Flags; // Flags identifying machine instr class
171 uint64_t TSFlags; // Target Specific Flag values
172 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
173 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
174 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
175 // Subtarget feature that this is deprecated on, if any
176 // -1 implies this is not deprecated by any single feature. It may still be
177 // deprecated due to a "complex" reason, below.
178 int64_t DeprecatedFeature;
180 // A complex method to determine is a certain is deprecated or not, and return
181 // the reason for deprecation.
182 bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
185 /// \brief Returns the value of the specific constraint if
186 /// it is set. Returns -1 if it is not set.
187 int getOperandConstraint(unsigned OpNum,
188 MCOI::OperandConstraint Constraint) const {
189 if (OpNum < NumOperands &&
190 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
191 unsigned Pos = 16 + Constraint * 4;
192 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
197 /// \brief Returns true if a certain instruction is deprecated and if so
198 /// returns the reason in \p Info.
199 bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
200 std::string &Info) const;
202 /// \brief Return the opcode number for this descriptor.
203 unsigned getOpcode() const { return Opcode; }
205 /// \brief Return the number of declared MachineOperands for this
206 /// MachineInstruction. Note that variadic (isVariadic() returns true)
207 /// instructions may have additional operands at the end of the list, and note
208 /// that the machine instruction may include implicit register def/uses as
210 unsigned getNumOperands() const { return NumOperands; }
212 /// \brief Return the number of MachineOperands that are register
213 /// definitions. Register definitions always occur at the start of the
214 /// machine operand list. This is the number of "outs" in the .td file,
215 /// and does not include implicit defs.
216 unsigned getNumDefs() const { return NumDefs; }
218 /// \brief Return flags of this instruction.
219 uint64_t getFlags() const { return Flags; }
221 /// \brief Return true if this instruction can have a variable number of
222 /// operands. In this case, the variable operands will be after the normal
223 /// operands but before the implicit definitions and uses (if any are
225 bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
227 /// \brief Set if this instruction has an optional definition, e.g.
228 /// ARM instructions which can set condition code if 's' bit is set.
229 bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
231 /// \brief Return true if this is a pseudo instruction that doesn't
232 /// correspond to a real machine instruction.
233 bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
235 /// \brief Return true if the instruction is a return.
236 bool isReturn() const { return Flags & (1ULL << MCID::Return); }
238 /// \brief Return true if the instruction is an add instruction.
239 bool isAdd() const { return Flags & (1ULL << MCID::Add); }
241 /// \brief Return true if the instruction is a call.
242 bool isCall() const { return Flags & (1ULL << MCID::Call); }
244 /// \brief Returns true if the specified instruction stops control flow
245 /// from executing the instruction immediately following it. Examples include
246 /// unconditional branches and return instructions.
247 bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
249 /// \brief Returns true if this instruction part of the terminator for
250 /// a basic block. Typically this is things like return and branch
253 /// Various passes use this to insert code into the bottom of a basic block,
254 /// but before control flow occurs.
255 bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
257 /// \brief Returns true if this is a conditional, unconditional, or
258 /// indirect branch. Predicates below can be used to discriminate between
259 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
260 /// get more information.
261 bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
263 /// \brief Return true if this is an indirect branch, such as a
264 /// branch through a register.
265 bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
267 /// \brief Return true if this is a branch which may fall
268 /// through to the next instruction or may transfer control flow to some other
269 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
270 /// information about this branch.
271 bool isConditionalBranch() const {
272 return isBranch() & !isBarrier() & !isIndirectBranch();
275 /// \brief Return true if this is a branch which always
276 /// transfers control flow to some other block. The
277 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
278 /// about this branch.
279 bool isUnconditionalBranch() const {
280 return isBranch() & isBarrier() & !isIndirectBranch();
283 /// \brief Return true if this is a branch or an instruction which directly
284 /// writes to the program counter. Considered 'may' affect rather than
285 /// 'does' affect as things like predication are not taken into account.
286 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
288 /// \brief Return true if this instruction has a predicate operand
289 /// that controls execution. It may be set to 'always', or may be set to other
290 /// values. There are various methods in TargetInstrInfo that can be used to
291 /// control and modify the predicate in this instruction.
292 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
294 /// \brief Return true if this instruction is a comparison.
295 bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
297 /// \brief Return true if this instruction is a move immediate
298 /// (including conditional moves) instruction.
299 bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
301 /// \brief Return true if this instruction is a bitcast instruction.
302 bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
304 /// \brief Return true if this is a select instruction.
305 bool isSelect() const { return Flags & (1ULL << MCID::Select); }
307 /// \brief Return true if this instruction cannot be safely
308 /// duplicated. For example, if the instruction has a unique labels attached
309 /// to it, duplicating it would cause multiple definition errors.
310 bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
312 /// \brief Returns true if the specified instruction has a delay slot which
313 /// must be filled by the code generator.
314 bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
316 /// \brief Return true for instructions that can be folded as memory operands
317 /// in other instructions. The most common use for this is instructions that
318 /// are simple loads from memory that don't modify the loaded value in any
319 /// way, but it can also be used for instructions that can be expressed as
320 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
321 /// folded when it is beneficial. This should only be set on instructions
322 /// that return a value in their only virtual register definition.
323 bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
325 /// \brief Return true if this instruction behaves
326 /// the same way as the generic REG_SEQUENCE instructions.
328 /// dX VMOVDRR rY, rZ
330 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
332 /// Note that for the optimizers to be able to take advantage of
333 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
334 /// override accordingly.
335 bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
337 /// \brief Return true if this instruction behaves
338 /// the same way as the generic EXTRACT_SUBREG instructions.
340 /// rX, rY VMOVRRD dZ
341 /// is equivalent to two EXTRACT_SUBREG:
342 /// rX = EXTRACT_SUBREG dZ, ssub_0
343 /// rY = EXTRACT_SUBREG dZ, ssub_1
345 /// Note that for the optimizers to be able to take advantage of
346 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
347 /// override accordingly.
348 bool isExtractSubregLike() const {
349 return Flags & (1ULL << MCID::ExtractSubreg);
352 /// \brief Return true if this instruction behaves
353 /// the same way as the generic INSERT_SUBREG instructions.
355 /// dX = VSETLNi32 dY, rZ, Imm
356 /// is equivalent to a INSERT_SUBREG:
357 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
359 /// Note that for the optimizers to be able to take advantage of
360 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
361 /// override accordingly.
362 bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
365 /// \brief Return true if this instruction is convergent.
367 /// Convergent instructions may not be made control-dependent on any
368 /// additional values.
369 bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
371 //===--------------------------------------------------------------------===//
372 // Side Effect Analysis
373 //===--------------------------------------------------------------------===//
375 /// \brief Return true if this instruction could possibly read memory.
376 /// Instructions with this flag set are not necessarily simple load
377 /// instructions, they may load a value and modify it, for example.
378 bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
380 /// \brief Return true if this instruction could possibly modify memory.
381 /// Instructions with this flag set are not necessarily simple store
382 /// instructions, they may store a modified value based on their operands, or
383 /// may not actually modify anything, for example.
384 bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
386 /// \brief Return true if this instruction has side
387 /// effects that are not modeled by other flags. This does not return true
388 /// for instructions whose effects are captured by:
390 /// 1. Their operand list and implicit definition/use list. Register use/def
391 /// info is explicit for instructions.
392 /// 2. Memory accesses. Use mayLoad/mayStore.
393 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
395 /// Examples of side effects would be modifying 'invisible' machine state like
396 /// a control register, flushing a cache, modifying a register invisible to
398 bool hasUnmodeledSideEffects() const {
399 return Flags & (1ULL << MCID::UnmodeledSideEffects);
402 //===--------------------------------------------------------------------===//
403 // Flags that indicate whether an instruction can be modified by a method.
404 //===--------------------------------------------------------------------===//
406 /// \brief Return true if this may be a 2- or 3-address instruction (of the
407 /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
408 /// exchanged. If this flag is set, then the
409 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
412 /// Note that this flag may be set on instructions that are only commutable
413 /// sometimes. In these cases, the call to commuteInstruction will fail.
414 /// Also note that some instructions require non-trivial modification to
416 bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
418 /// \brief Return true if this is a 2-address instruction which can be changed
419 /// into a 3-address instruction if needed. Doing this transformation can be
420 /// profitable in the register allocator, because it means that the
421 /// instruction can use a 2-address form if possible, but degrade into a less
422 /// efficient form if the source and dest register cannot be assigned to the
423 /// same register. For example, this allows the x86 backend to turn a "shl
424 /// reg, 3" instruction into an LEA instruction, which is the same speed as
425 /// the shift but has bigger code size.
427 /// If this returns true, then the target must implement the
428 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
429 /// is allowed to fail if the transformation isn't valid for this specific
430 /// instruction (e.g. shl reg, 4 on x86).
432 bool isConvertibleTo3Addr() const {
433 return Flags & (1ULL << MCID::ConvertibleTo3Addr);
436 /// \brief Return true if this instruction requires custom insertion support
437 /// when the DAG scheduler is inserting it into a machine basic block. If
438 /// this is true for the instruction, it basically means that it is a pseudo
439 /// instruction used at SelectionDAG time that is expanded out into magic code
440 /// by the target when MachineInstrs are formed.
442 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
443 /// is used to insert this into the MachineBasicBlock.
444 bool usesCustomInsertionHook() const {
445 return Flags & (1ULL << MCID::UsesCustomInserter);
448 /// \brief Return true if this instruction requires *adjustment* after
449 /// instruction selection by calling a target hook. For example, this can be
450 /// used to fill in ARM 's' optional operand depending on whether the
451 /// conditional flag register is used.
452 bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
454 /// \brief Returns true if this instruction is a candidate for remat. This
455 /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
457 /// If this flag is set, the isReallyTriviallyReMaterializable()
458 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
459 /// the instruction is really rematable.
460 bool isRematerializable() const {
461 return Flags & (1ULL << MCID::Rematerializable);
464 /// \brief Returns true if this instruction has the same cost (or less) than a
465 /// move instruction. This is useful during certain types of optimizations
466 /// (e.g., remat during two-address conversion or machine licm) where we would
467 /// like to remat or hoist the instruction, but not if it costs more than
468 /// moving the instruction into the appropriate register. Note, we are not
469 /// marking copies from and to the same register class with this flag.
471 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
472 /// for different subtargets.
473 bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
475 /// \brief Returns true if this instruction source operands have special
476 /// register allocation requirements that are not captured by the operand
477 /// register classes. e.g. ARM::STRD's two source registers must be an even /
478 /// odd pair, ARM::STM registers have to be in ascending order. Post-register
479 /// allocation passes should not attempt to change allocations for sources of
480 /// instructions with this flag.
481 bool hasExtraSrcRegAllocReq() const {
482 return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
485 /// \brief Returns true if this instruction def operands have special register
486 /// allocation requirements that are not captured by the operand register
487 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
488 /// ARM::LDM registers have to be in ascending order. Post-register
489 /// allocation passes should not attempt to change allocations for definitions
490 /// of instructions with this flag.
491 bool hasExtraDefRegAllocReq() const {
492 return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
495 /// \brief Return a list of registers that are potentially read by any
496 /// instance of this machine instruction. For example, on X86, the "adc"
497 /// instruction adds two register operands and adds the carry bit in from the
498 /// flags register. In this case, the instruction is marked as implicitly
499 /// reading the flags. Likewise, the variable shift instruction on X86 is
500 /// marked as implicitly reading the 'CL' register, which it always does.
502 /// This method returns null if the instruction has no implicit uses.
503 const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
505 /// \brief Return the number of implicit uses this instruction has.
506 unsigned getNumImplicitUses() const {
510 for (; ImplicitUses[i]; ++i) /*empty*/
515 /// \brief Return a list of registers that are potentially written by any
516 /// instance of this machine instruction. For example, on X86, many
517 /// instructions implicitly set the flags register. In this case, they are
518 /// marked as setting the FLAGS. Likewise, many instructions always deposit
519 /// their result in a physical register. For example, the X86 divide
520 /// instruction always deposits the quotient and remainder in the EAX/EDX
521 /// registers. For that instruction, this will return a list containing the
522 /// EAX/EDX/EFLAGS registers.
524 /// This method returns null if the instruction has no implicit defs.
525 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
527 /// \brief Return the number of implicit defs this instruct has.
528 unsigned getNumImplicitDefs() const {
532 for (; ImplicitDefs[i]; ++i) /*empty*/
537 /// \brief Return true if this instruction implicitly
538 /// uses the specified physical register.
539 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
540 if (const MCPhysReg *ImpUses = ImplicitUses)
541 for (; *ImpUses; ++ImpUses)
547 /// \brief Return true if this instruction implicitly
548 /// defines the specified physical register.
549 bool hasImplicitDefOfPhysReg(unsigned Reg,
550 const MCRegisterInfo *MRI = nullptr) const;
552 /// \brief Return the scheduling class for this instruction. The
553 /// scheduling class is an index into the InstrItineraryData table. This
554 /// returns zero if there is no known scheduling information for the
556 unsigned getSchedClass() const { return SchedClass; }
558 /// \brief Return the number of bytes in the encoding of this instruction,
559 /// or zero if the encoding size cannot be known from the opcode.
560 unsigned getSize() const { return Size; }
562 /// \brief Find the index of the first operand in the
563 /// operand list that is used to represent the predicate. It returns -1 if
565 int findFirstPredOperandIdx() const {
566 if (isPredicable()) {
567 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
568 if (OpInfo[i].isPredicate())
576 /// \brief Return true if this instruction defines the specified physical
577 /// register, either explicitly or implicitly.
578 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
579 const MCRegisterInfo &RI) const;
582 } // end namespace llvm