1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes an abstract interface used to get information about a
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCREGISTERINFO_H
16 #define LLVM_MC_MCREGISTERINFO_H
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/iterator_range.h"
20 #include "llvm/MC/LaneBitmask.h"
27 /// An unsigned integer type large enough to represent all physical registers,
28 /// but not necessarily virtual registers.
29 using MCPhysReg = uint16_t;
31 /// MCRegisterClass - Base class of TargetRegisterClass.
32 class MCRegisterClass {
34 using iterator = const MCPhysReg*;
35 using const_iterator = const MCPhysReg*;
37 const iterator RegsBegin;
38 const uint8_t *const RegSet;
39 const uint32_t NameIdx;
40 const uint16_t RegsSize;
41 const uint16_t RegSetSize;
43 const int8_t CopyCost;
44 const bool Allocatable;
46 /// getID() - Return the register class ID number.
48 unsigned getID() const { return ID; }
50 /// begin/end - Return all of the registers in this class.
52 iterator begin() const { return RegsBegin; }
53 iterator end() const { return RegsBegin + RegsSize; }
55 /// getNumRegs - Return the number of registers in this class.
57 unsigned getNumRegs() const { return RegsSize; }
59 /// getRegister - Return the specified register in the class.
61 unsigned getRegister(unsigned i) const {
62 assert(i < getNumRegs() && "Register number out of range!");
66 /// contains - Return true if the specified register is included in this
67 /// register class. This does not include virtual registers.
68 bool contains(unsigned Reg) const {
69 unsigned InByte = Reg % 8;
70 unsigned Byte = Reg / 8;
71 if (Byte >= RegSetSize)
73 return (RegSet[Byte] & (1 << InByte)) != 0;
76 /// contains - Return true if both registers are in this class.
77 bool contains(unsigned Reg1, unsigned Reg2) const {
78 return contains(Reg1) && contains(Reg2);
81 /// getCopyCost - Return the cost of copying a value between two registers in
82 /// this class. A negative number means the register class is very expensive
83 /// to copy e.g. status flag register classes.
84 int getCopyCost() const { return CopyCost; }
86 /// isAllocatable - Return true if this register class may be used to create
87 /// virtual registers.
88 bool isAllocatable() const { return Allocatable; }
91 /// MCRegisterDesc - This record contains information about a particular
92 /// register. The SubRegs field is a zero terminated array of registers that
93 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
94 /// of AX. The SuperRegs field is a zero terminated array of registers that are
95 /// super-registers of the specific register, e.g. RAX, EAX, are
96 /// super-registers of AX.
98 struct MCRegisterDesc {
99 uint32_t Name; // Printable name for the reg (for debugging)
100 uint32_t SubRegs; // Sub-register set, described above
101 uint32_t SuperRegs; // Super-register set, described above
103 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
104 // sub-register in SubRegs.
105 uint32_t SubRegIndices;
107 // RegUnits - Points to the list of register units. The low 4 bits holds the
108 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
111 /// Index into list with lane mask sequences. The sequence contains a lanemask
112 /// for every register unit.
113 uint16_t RegUnitLaneMasks;
116 /// MCRegisterInfo base class - We assume that the target defines a static
117 /// array of MCRegisterDesc objects that represent all of the machine
118 /// registers that the target has. As such, we simply have to track a pointer
119 /// to this array so that we can turn register number into a register
122 /// Note this class is designed to be a base class of TargetRegisterInfo, which
123 /// is the interface used by codegen. However, specific targets *should never*
124 /// specialize this class. MCRegisterInfo should only contain getters to access
125 /// TableGen generated physical register data. It must not be extended with
128 class MCRegisterInfo {
130 using regclass_iterator = const MCRegisterClass *;
132 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
133 /// performed with a binary search.
134 struct DwarfLLVMRegPair {
138 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
141 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
142 /// index, -1 in any being invalid.
143 struct SubRegCoveredBits {
149 const MCRegisterDesc *Desc; // Pointer to the descriptor array
150 unsigned NumRegs; // Number of entries in the array
151 unsigned RAReg; // Return address register
152 unsigned PCReg; // Program counter register
153 const MCRegisterClass *Classes; // Pointer to the regclass array
154 unsigned NumClasses; // Number of entries in the array
155 unsigned NumRegUnits; // Number of regunits.
156 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
157 const MCPhysReg *DiffLists; // Pointer to the difflists array
158 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
159 // for register units.
160 const char *RegStrings; // Pointer to the string table.
161 const char *RegClassStrings; // Pointer to the class strings.
162 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
164 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
166 unsigned NumSubRegIndices; // Number of subreg indices.
167 const uint16_t *RegEncodingTable; // Pointer to array of register
170 unsigned L2DwarfRegsSize;
171 unsigned EHL2DwarfRegsSize;
172 unsigned Dwarf2LRegsSize;
173 unsigned EHDwarf2LRegsSize;
174 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
175 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
176 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
177 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
178 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
179 DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping
182 /// DiffListIterator - Base iterator class that can traverse the
183 /// differentially encoded register and regunit lists in DiffLists.
184 /// Don't use this class directly, use one of the specialized sub-classes
186 class DiffListIterator {
188 const MCPhysReg *List = nullptr;
191 /// Create an invalid iterator. Call init() to point to something useful.
192 DiffListIterator() = default;
194 /// init - Point the iterator to InitVal, decoding subsequent values from
195 /// DiffList. The iterator will initially point to InitVal, sub-classes are
196 /// responsible for skipping the seed value if it is not part of the list.
197 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
202 /// advance - Move to the next list position, return the applied
203 /// differential. This function does not detect the end of the list, that
204 /// is the caller's responsibility (by checking for a 0 return value).
206 assert(isValid() && "Cannot move off the end of the list.");
207 MCPhysReg D = *List++;
213 /// isValid - returns true if this iterator is not yet at the end.
214 bool isValid() const { return List; }
216 /// Dereference the iterator to get the value at the current position.
217 unsigned operator*() const { return Val; }
219 /// Pre-increment to move to the next position.
221 // The end of the list is encoded as a 0 differential.
227 // These iterators are allowed to sub-class DiffListIterator and access
228 // internal list pointers.
229 friend class MCSubRegIterator;
230 friend class MCSubRegIndexIterator;
231 friend class MCSuperRegIterator;
232 friend class MCRegUnitIterator;
233 friend class MCRegUnitMaskIterator;
234 friend class MCRegUnitRootIterator;
236 /// Initialize MCRegisterInfo, called by TableGen
237 /// auto-generated routines. *DO NOT USE*.
238 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
240 const MCRegisterClass *C, unsigned NC,
241 const MCPhysReg (*RURoots)[2],
244 const LaneBitmask *RUMS,
246 const char *ClassStrings,
247 const uint16_t *SubIndices,
249 const SubRegCoveredBits *SubIdxRanges,
250 const uint16_t *RET) {
257 RegUnitMaskSequences = RUMS;
258 RegStrings = Strings;
259 RegClassStrings = ClassStrings;
261 RegUnitRoots = RURoots;
263 SubRegIndices = SubIndices;
264 NumSubRegIndices = NumIndices;
265 SubRegIdxRanges = SubIdxRanges;
266 RegEncodingTable = RET;
268 // Initialize DWARF register mapping variables
269 EHL2DwarfRegs = nullptr;
270 EHL2DwarfRegsSize = 0;
271 L2DwarfRegs = nullptr;
273 EHDwarf2LRegs = nullptr;
274 EHDwarf2LRegsSize = 0;
275 Dwarf2LRegs = nullptr;
279 /// Used to initialize LLVM register to Dwarf
280 /// register number mapping. Called by TableGen auto-generated routines.
282 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
286 EHL2DwarfRegsSize = Size;
289 L2DwarfRegsSize = Size;
293 /// Used to initialize Dwarf register to LLVM
294 /// register number mapping. Called by TableGen auto-generated routines.
296 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
300 EHDwarf2LRegsSize = Size;
303 Dwarf2LRegsSize = Size;
307 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
308 /// number mapping. By default the SEH register number is just the same
309 /// as the LLVM register number.
310 /// FIXME: TableGen these numbers. Currently this requires target specific
311 /// initialization code.
312 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
313 L2SEHRegs[LLVMReg] = SEHReg;
316 void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
317 L2CVRegs[LLVMReg] = CVReg;
320 /// This method should return the register where the return
321 /// address can be found.
322 unsigned getRARegister() const {
326 /// Return the register which is the program counter.
327 unsigned getProgramCounter() const {
331 const MCRegisterDesc &operator[](unsigned RegNo) const {
332 assert(RegNo < NumRegs &&
333 "Attempting to access record for invalid register number!");
337 /// Provide a get method, equivalent to [], but more useful with a
338 /// pointer to this object.
339 const MCRegisterDesc &get(unsigned RegNo) const {
340 return operator[](RegNo);
343 /// Returns the physical register number of sub-register "Index"
344 /// for physical register RegNo. Return zero if the sub-register does not
346 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
348 /// Return a super-register of the specified register
349 /// Reg so its sub-register of index SubIdx is Reg.
350 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
351 const MCRegisterClass *RC) const;
353 /// For a given register pair, return the sub-register index
354 /// if the second register is a sub-register of the first. Return zero
356 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
358 /// Get the size of the bit range covered by a sub-register index.
359 /// If the index isn't continuous, return the sum of the sizes of its parts.
360 /// If the index is used to access subregisters of different sizes, return -1.
361 unsigned getSubRegIdxSize(unsigned Idx) const;
363 /// Get the offset of the bit range covered by a sub-register index.
364 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
365 /// access sub-registers at different offsets), return -1.
366 unsigned getSubRegIdxOffset(unsigned Idx) const;
368 /// Return the human-readable symbolic target-specific name for the
369 /// specified physical register.
370 const char *getName(unsigned RegNo) const {
371 return RegStrings + get(RegNo).Name;
374 /// Return the number of registers this target has (useful for
375 /// sizing arrays holding per register information)
376 unsigned getNumRegs() const {
380 /// Return the number of sub-register indices
381 /// understood by the target. Index 0 is reserved for the no-op sub-register,
382 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
383 unsigned getNumSubRegIndices() const {
384 return NumSubRegIndices;
387 /// Return the number of (native) register units in the
388 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
389 /// can be accessed through MCRegUnitIterator defined below.
390 unsigned getNumRegUnits() const {
394 /// Map a target register to an equivalent dwarf register
395 /// number. Returns -1 if there is no equivalent value. The second
396 /// parameter allows targets to use different numberings for EH info and
398 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
400 /// Map a dwarf register back to a target register.
401 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
403 /// Map a DWARF EH register back to a target register (same as
404 /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
405 /// rather than asserting that there must be one.
406 int getLLVMRegNumFromEH(unsigned RegNum) const;
408 /// Map a target EH register number to an equivalent DWARF register
410 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
412 /// Map a target register to an equivalent SEH register
413 /// number. Returns LLVM register number if there is no equivalent value.
414 int getSEHRegNum(unsigned RegNum) const;
416 /// Map a target register to an equivalent CodeView register
418 int getCodeViewRegNum(unsigned RegNum) const;
420 regclass_iterator regclass_begin() const { return Classes; }
421 regclass_iterator regclass_end() const { return Classes+NumClasses; }
422 iterator_range<regclass_iterator> regclasses() const {
423 return make_range(regclass_begin(), regclass_end());
426 unsigned getNumRegClasses() const {
427 return (unsigned)(regclass_end()-regclass_begin());
430 /// Returns the register class associated with the enumeration
431 /// value. See class MCOperandInfo.
432 const MCRegisterClass& getRegClass(unsigned i) const {
433 assert(i < getNumRegClasses() && "Register Class ID out of range");
437 const char *getRegClassName(const MCRegisterClass *Class) const {
438 return RegClassStrings + Class->NameIdx;
441 /// Returns the encoding for RegNo
442 uint16_t getEncodingValue(unsigned RegNo) const {
443 assert(RegNo < NumRegs &&
444 "Attempting to get encoding for invalid register number!");
445 return RegEncodingTable[RegNo];
448 /// Returns true if RegB is a sub-register of RegA.
449 bool isSubRegister(unsigned RegA, unsigned RegB) const {
450 return isSuperRegister(RegB, RegA);
453 /// Returns true if RegB is a super-register of RegA.
454 bool isSuperRegister(unsigned RegA, unsigned RegB) const;
456 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
457 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
458 return isSuperRegisterEq(RegB, RegA);
461 /// Returns true if RegB is a super-register of RegA or if
463 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
464 return RegA == RegB || isSuperRegister(RegA, RegB);
467 /// Returns true if RegB is a super-register or sub-register of RegA
468 /// or if RegB == RegA.
469 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
470 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
474 //===----------------------------------------------------------------------===//
475 // Register List Iterators
476 //===----------------------------------------------------------------------===//
478 // MCRegisterInfo provides lists of super-registers, sub-registers, and
479 // aliasing registers. Use these iterator classes to traverse the lists.
481 /// MCSubRegIterator enumerates all sub-registers of Reg.
482 /// If IncludeSelf is set, Reg itself is included in the list.
483 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
485 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
486 bool IncludeSelf = false) {
487 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
488 // Initially, the iterator points to Reg itself.
494 /// Iterator that enumerates the sub-registers of a Reg and the associated
495 /// sub-register indices.
496 class MCSubRegIndexIterator {
497 MCSubRegIterator SRIter;
498 const uint16_t *SRIndex;
501 /// Constructs an iterator that traverses subregisters and their
502 /// associated subregister indices.
503 MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
504 : SRIter(Reg, MCRI) {
505 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
508 /// Returns current sub-register.
509 unsigned getSubReg() const {
513 /// Returns sub-register index of the current sub-register.
514 unsigned getSubRegIndex() const {
518 /// Returns true if this iterator is not yet at the end.
519 bool isValid() const { return SRIter.isValid(); }
521 /// Moves to the next position.
528 /// MCSuperRegIterator enumerates all super-registers of Reg.
529 /// If IncludeSelf is set, Reg itself is included in the list.
530 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
532 MCSuperRegIterator() = default;
534 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
535 bool IncludeSelf = false) {
536 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
537 // Initially, the iterator points to Reg itself.
543 // Definition for isSuperRegister. Put it down here since it needs the
544 // iterator defined above in addition to the MCRegisterInfo class itself.
545 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
546 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
552 //===----------------------------------------------------------------------===//
554 //===----------------------------------------------------------------------===//
556 // Register units are used to compute register aliasing. Every register has at
557 // least one register unit, but it can have more. Two registers overlap if and
558 // only if they have a common register unit.
560 // A target with a complicated sub-register structure will typically have many
561 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
562 // the number of register units in the target.
564 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
565 // in ascending numerical order.
566 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
568 /// MCRegUnitIterator - Create an iterator that traverses the register units
570 MCRegUnitIterator() = default;
572 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
573 assert(Reg && "Null register has no regunits");
574 // Decode the RegUnits MCRegisterDesc field.
575 unsigned RU = MCRI->get(Reg).RegUnits;
576 unsigned Scale = RU & 15;
577 unsigned Offset = RU >> 4;
579 // Initialize the iterator to Reg * Scale, and the List pointer to
580 // DiffLists + Offset.
581 init(Reg * Scale, MCRI->DiffLists + Offset);
583 // That may not be a valid unit, we need to advance by one to get the real
584 // unit number. The first differential can be 0 which would normally
585 // terminate the list, but since we know every register has at least one
586 // unit, we can allow a 0 differential here.
591 /// MCRegUnitMaskIterator enumerates a list of register units and their
592 /// associated lane masks for Reg. The register units are in ascending
594 class MCRegUnitMaskIterator {
595 MCRegUnitIterator RUIter;
596 const LaneBitmask *MaskListIter;
599 MCRegUnitMaskIterator() = default;
601 /// Constructs an iterator that traverses the register units and their
602 /// associated LaneMasks in Reg.
603 MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
604 : RUIter(Reg, MCRI) {
605 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
606 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
609 /// Returns a (RegUnit, LaneMask) pair.
610 std::pair<unsigned,LaneBitmask> operator*() const {
611 return std::make_pair(*RUIter, *MaskListIter);
614 /// Returns true if this iterator is not yet at the end.
615 bool isValid() const { return RUIter.isValid(); }
617 /// Moves to the next position.
624 // Each register unit has one or two root registers. The complete set of
625 // registers containing a register unit is the union of the roots and their
626 // super-registers. All registers aliasing Unit can be visited like this:
628 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
629 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
633 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
634 class MCRegUnitRootIterator {
639 MCRegUnitRootIterator() = default;
641 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
642 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
643 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
644 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
647 /// Dereference to get the current root register.
648 unsigned operator*() const {
652 /// Check if the iterator is at the end of the list.
653 bool isValid() const {
657 /// Preincrement to move to the next root register.
659 assert(isValid() && "Cannot move off the end of the list.");
665 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
666 /// set, Reg itself is included in the list. This iterator does not guarantee
667 /// any ordering or that entries are unique.
668 class MCRegAliasIterator {
671 const MCRegisterInfo *MCRI;
674 MCRegUnitIterator RI;
675 MCRegUnitRootIterator RRI;
676 MCSuperRegIterator SI;
679 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
681 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
682 // Initialize the iterators.
683 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
684 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
685 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
686 if (!(!IncludeSelf && Reg == *SI))
693 bool isValid() const { return RI.isValid(); }
695 unsigned operator*() const {
696 assert(SI.isValid() && "Cannot dereference an invalid iterator.");
701 // Assuming SI is valid.
703 if (SI.isValid()) return;
707 SI = MCSuperRegIterator(*RRI, MCRI, true);
713 RRI = MCRegUnitRootIterator(*RI, MCRI);
714 SI = MCSuperRegIterator(*RRI, MCRI, true);
719 assert(isValid() && "Cannot move off the end of the list.");
721 while (!IncludeSelf && isValid() && *SI == Reg);
725 } // end namespace llvm
727 #endif // LLVM_MC_MCREGISTERINFO_H