1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/iterator_range.h"
21 #include "llvm/MC/LaneBitmask.h"
28 /// An unsigned integer type large enough to represent all physical registers,
29 /// but not necessarily virtual registers.
30 using MCPhysReg = uint16_t;
32 /// MCRegisterClass - Base class of TargetRegisterClass.
33 class MCRegisterClass {
35 using iterator = const MCPhysReg*;
36 using const_iterator = const MCPhysReg*;
38 const iterator RegsBegin;
39 const uint8_t *const RegSet;
40 const uint32_t NameIdx;
41 const uint16_t RegsSize;
42 const uint16_t RegSetSize;
44 const int8_t CopyCost;
45 const bool Allocatable;
47 /// getID() - Return the register class ID number.
49 unsigned getID() const { return ID; }
51 /// begin/end - Return all of the registers in this class.
53 iterator begin() const { return RegsBegin; }
54 iterator end() const { return RegsBegin + RegsSize; }
56 /// getNumRegs - Return the number of registers in this class.
58 unsigned getNumRegs() const { return RegsSize; }
60 /// getRegister - Return the specified register in the class.
62 unsigned getRegister(unsigned i) const {
63 assert(i < getNumRegs() && "Register number out of range!");
67 /// contains - Return true if the specified register is included in this
68 /// register class. This does not include virtual registers.
69 bool contains(unsigned Reg) const {
70 unsigned InByte = Reg % 8;
71 unsigned Byte = Reg / 8;
72 if (Byte >= RegSetSize)
74 return (RegSet[Byte] & (1 << InByte)) != 0;
77 /// contains - Return true if both registers are in this class.
78 bool contains(unsigned Reg1, unsigned Reg2) const {
79 return contains(Reg1) && contains(Reg2);
82 /// getCopyCost - Return the cost of copying a value between two registers in
83 /// this class. A negative number means the register class is very expensive
84 /// to copy e.g. status flag register classes.
85 int getCopyCost() const { return CopyCost; }
87 /// isAllocatable - Return true if this register class may be used to create
88 /// virtual registers.
89 bool isAllocatable() const { return Allocatable; }
92 /// MCRegisterDesc - This record contains information about a particular
93 /// register. The SubRegs field is a zero terminated array of registers that
94 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
95 /// of AX. The SuperRegs field is a zero terminated array of registers that are
96 /// super-registers of the specific register, e.g. RAX, EAX, are
97 /// super-registers of AX.
99 struct MCRegisterDesc {
100 uint32_t Name; // Printable name for the reg (for debugging)
101 uint32_t SubRegs; // Sub-register set, described above
102 uint32_t SuperRegs; // Super-register set, described above
104 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
105 // sub-register in SubRegs.
106 uint32_t SubRegIndices;
108 // RegUnits - Points to the list of register units. The low 4 bits holds the
109 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
112 /// Index into list with lane mask sequences. The sequence contains a lanemask
113 /// for every register unit.
114 uint16_t RegUnitLaneMasks;
117 /// MCRegisterInfo base class - We assume that the target defines a static
118 /// array of MCRegisterDesc objects that represent all of the machine
119 /// registers that the target has. As such, we simply have to track a pointer
120 /// to this array so that we can turn register number into a register
123 /// Note this class is designed to be a base class of TargetRegisterInfo, which
124 /// is the interface used by codegen. However, specific targets *should never*
125 /// specialize this class. MCRegisterInfo should only contain getters to access
126 /// TableGen generated physical register data. It must not be extended with
129 class MCRegisterInfo {
131 using regclass_iterator = const MCRegisterClass *;
133 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
134 /// performed with a binary search.
135 struct DwarfLLVMRegPair {
139 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
142 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
143 /// index, -1 in any being invalid.
144 struct SubRegCoveredBits {
150 const MCRegisterDesc *Desc; // Pointer to the descriptor array
151 unsigned NumRegs; // Number of entries in the array
152 unsigned RAReg; // Return address register
153 unsigned PCReg; // Program counter register
154 const MCRegisterClass *Classes; // Pointer to the regclass array
155 unsigned NumClasses; // Number of entries in the array
156 unsigned NumRegUnits; // Number of regunits.
157 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
158 const MCPhysReg *DiffLists; // Pointer to the difflists array
159 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
160 // for register units.
161 const char *RegStrings; // Pointer to the string table.
162 const char *RegClassStrings; // Pointer to the class strings.
163 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
165 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
167 unsigned NumSubRegIndices; // Number of subreg indices.
168 const uint16_t *RegEncodingTable; // Pointer to array of register
171 unsigned L2DwarfRegsSize;
172 unsigned EHL2DwarfRegsSize;
173 unsigned Dwarf2LRegsSize;
174 unsigned EHDwarf2LRegsSize;
175 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
176 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
177 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
178 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
179 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
180 DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping
183 /// DiffListIterator - Base iterator class that can traverse the
184 /// differentially encoded register and regunit lists in DiffLists.
185 /// Don't use this class directly, use one of the specialized sub-classes
187 class DiffListIterator {
189 const MCPhysReg *List = nullptr;
192 /// Create an invalid iterator. Call init() to point to something useful.
193 DiffListIterator() = default;
195 /// init - Point the iterator to InitVal, decoding subsequent values from
196 /// DiffList. The iterator will initially point to InitVal, sub-classes are
197 /// responsible for skipping the seed value if it is not part of the list.
198 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
203 /// advance - Move to the next list position, return the applied
204 /// differential. This function does not detect the end of the list, that
205 /// is the caller's responsibility (by checking for a 0 return value).
207 assert(isValid() && "Cannot move off the end of the list.");
208 MCPhysReg D = *List++;
214 /// isValid - returns true if this iterator is not yet at the end.
215 bool isValid() const { return List; }
217 /// Dereference the iterator to get the value at the current position.
218 unsigned operator*() const { return Val; }
220 /// Pre-increment to move to the next position.
222 // The end of the list is encoded as a 0 differential.
228 // These iterators are allowed to sub-class DiffListIterator and access
229 // internal list pointers.
230 friend class MCSubRegIterator;
231 friend class MCSubRegIndexIterator;
232 friend class MCSuperRegIterator;
233 friend class MCRegUnitIterator;
234 friend class MCRegUnitMaskIterator;
235 friend class MCRegUnitRootIterator;
237 /// Initialize MCRegisterInfo, called by TableGen
238 /// auto-generated routines. *DO NOT USE*.
239 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
241 const MCRegisterClass *C, unsigned NC,
242 const MCPhysReg (*RURoots)[2],
245 const LaneBitmask *RUMS,
247 const char *ClassStrings,
248 const uint16_t *SubIndices,
250 const SubRegCoveredBits *SubIdxRanges,
251 const uint16_t *RET) {
258 RegUnitMaskSequences = RUMS;
259 RegStrings = Strings;
260 RegClassStrings = ClassStrings;
262 RegUnitRoots = RURoots;
264 SubRegIndices = SubIndices;
265 NumSubRegIndices = NumIndices;
266 SubRegIdxRanges = SubIdxRanges;
267 RegEncodingTable = RET;
269 // Initialize DWARF register mapping variables
270 EHL2DwarfRegs = nullptr;
271 EHL2DwarfRegsSize = 0;
272 L2DwarfRegs = nullptr;
274 EHDwarf2LRegs = nullptr;
275 EHDwarf2LRegsSize = 0;
276 Dwarf2LRegs = nullptr;
280 /// Used to initialize LLVM register to Dwarf
281 /// register number mapping. Called by TableGen auto-generated routines.
283 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
287 EHL2DwarfRegsSize = Size;
290 L2DwarfRegsSize = Size;
294 /// Used to initialize Dwarf register to LLVM
295 /// register number mapping. Called by TableGen auto-generated routines.
297 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
301 EHDwarf2LRegsSize = Size;
304 Dwarf2LRegsSize = Size;
308 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
309 /// number mapping. By default the SEH register number is just the same
310 /// as the LLVM register number.
311 /// FIXME: TableGen these numbers. Currently this requires target specific
312 /// initialization code.
313 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
314 L2SEHRegs[LLVMReg] = SEHReg;
317 void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
318 L2CVRegs[LLVMReg] = CVReg;
321 /// This method should return the register where the return
322 /// address can be found.
323 unsigned getRARegister() const {
327 /// Return the register which is the program counter.
328 unsigned getProgramCounter() const {
332 const MCRegisterDesc &operator[](unsigned RegNo) const {
333 assert(RegNo < NumRegs &&
334 "Attempting to access record for invalid register number!");
338 /// Provide a get method, equivalent to [], but more useful with a
339 /// pointer to this object.
340 const MCRegisterDesc &get(unsigned RegNo) const {
341 return operator[](RegNo);
344 /// Returns the physical register number of sub-register "Index"
345 /// for physical register RegNo. Return zero if the sub-register does not
347 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
349 /// Return a super-register of the specified register
350 /// Reg so its sub-register of index SubIdx is Reg.
351 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
352 const MCRegisterClass *RC) const;
354 /// For a given register pair, return the sub-register index
355 /// if the second register is a sub-register of the first. Return zero
357 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
359 /// Get the size of the bit range covered by a sub-register index.
360 /// If the index isn't continuous, return the sum of the sizes of its parts.
361 /// If the index is used to access subregisters of different sizes, return -1.
362 unsigned getSubRegIdxSize(unsigned Idx) const;
364 /// Get the offset of the bit range covered by a sub-register index.
365 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
366 /// access sub-registers at different offsets), return -1.
367 unsigned getSubRegIdxOffset(unsigned Idx) const;
369 /// Return the human-readable symbolic target-specific name for the
370 /// specified physical register.
371 const char *getName(unsigned RegNo) const {
372 return RegStrings + get(RegNo).Name;
375 /// Return the number of registers this target has (useful for
376 /// sizing arrays holding per register information)
377 unsigned getNumRegs() const {
381 /// Return the number of sub-register indices
382 /// understood by the target. Index 0 is reserved for the no-op sub-register,
383 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
384 unsigned getNumSubRegIndices() const {
385 return NumSubRegIndices;
388 /// Return the number of (native) register units in the
389 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
390 /// can be accessed through MCRegUnitIterator defined below.
391 unsigned getNumRegUnits() const {
395 /// Map a target register to an equivalent dwarf register
396 /// number. Returns -1 if there is no equivalent value. The second
397 /// parameter allows targets to use different numberings for EH info and
399 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
401 /// Map a dwarf register back to a target register.
402 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
404 /// Map a DWARF EH register back to a target register (same as
405 /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
406 /// rather than asserting that there must be one.
407 int getLLVMRegNumFromEH(unsigned RegNum) const;
409 /// Map a target EH register number to an equivalent DWARF register
411 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
413 /// Map a target register to an equivalent SEH register
414 /// number. Returns LLVM register number if there is no equivalent value.
415 int getSEHRegNum(unsigned RegNum) const;
417 /// Map a target register to an equivalent CodeView register
419 int getCodeViewRegNum(unsigned RegNum) const;
421 regclass_iterator regclass_begin() const { return Classes; }
422 regclass_iterator regclass_end() const { return Classes+NumClasses; }
423 iterator_range<regclass_iterator> regclasses() const {
424 return make_range(regclass_begin(), regclass_end());
427 unsigned getNumRegClasses() const {
428 return (unsigned)(regclass_end()-regclass_begin());
431 /// Returns the register class associated with the enumeration
432 /// value. See class MCOperandInfo.
433 const MCRegisterClass& getRegClass(unsigned i) const {
434 assert(i < getNumRegClasses() && "Register Class ID out of range");
438 const char *getRegClassName(const MCRegisterClass *Class) const {
439 return RegClassStrings + Class->NameIdx;
442 /// Returns the encoding for RegNo
443 uint16_t getEncodingValue(unsigned RegNo) const {
444 assert(RegNo < NumRegs &&
445 "Attempting to get encoding for invalid register number!");
446 return RegEncodingTable[RegNo];
449 /// Returns true if RegB is a sub-register of RegA.
450 bool isSubRegister(unsigned RegA, unsigned RegB) const {
451 return isSuperRegister(RegB, RegA);
454 /// Returns true if RegB is a super-register of RegA.
455 bool isSuperRegister(unsigned RegA, unsigned RegB) const;
457 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
458 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
459 return isSuperRegisterEq(RegB, RegA);
462 /// Returns true if RegB is a super-register of RegA or if
464 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
465 return RegA == RegB || isSuperRegister(RegA, RegB);
468 /// Returns true if RegB is a super-register or sub-register of RegA
469 /// or if RegB == RegA.
470 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
471 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
475 //===----------------------------------------------------------------------===//
476 // Register List Iterators
477 //===----------------------------------------------------------------------===//
479 // MCRegisterInfo provides lists of super-registers, sub-registers, and
480 // aliasing registers. Use these iterator classes to traverse the lists.
482 /// MCSubRegIterator enumerates all sub-registers of Reg.
483 /// If IncludeSelf is set, Reg itself is included in the list.
484 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
486 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
487 bool IncludeSelf = false) {
488 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
489 // Initially, the iterator points to Reg itself.
495 /// Iterator that enumerates the sub-registers of a Reg and the associated
496 /// sub-register indices.
497 class MCSubRegIndexIterator {
498 MCSubRegIterator SRIter;
499 const uint16_t *SRIndex;
502 /// Constructs an iterator that traverses subregisters and their
503 /// associated subregister indices.
504 MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
505 : SRIter(Reg, MCRI) {
506 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
509 /// Returns current sub-register.
510 unsigned getSubReg() const {
514 /// Returns sub-register index of the current sub-register.
515 unsigned getSubRegIndex() const {
519 /// Returns true if this iterator is not yet at the end.
520 bool isValid() const { return SRIter.isValid(); }
522 /// Moves to the next position.
529 /// MCSuperRegIterator enumerates all super-registers of Reg.
530 /// If IncludeSelf is set, Reg itself is included in the list.
531 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
533 MCSuperRegIterator() = default;
535 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
536 bool IncludeSelf = false) {
537 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
538 // Initially, the iterator points to Reg itself.
544 // Definition for isSuperRegister. Put it down here since it needs the
545 // iterator defined above in addition to the MCRegisterInfo class itself.
546 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
547 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
553 //===----------------------------------------------------------------------===//
555 //===----------------------------------------------------------------------===//
557 // Register units are used to compute register aliasing. Every register has at
558 // least one register unit, but it can have more. Two registers overlap if and
559 // only if they have a common register unit.
561 // A target with a complicated sub-register structure will typically have many
562 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
563 // the number of register units in the target.
565 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
566 // in ascending numerical order.
567 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
569 /// MCRegUnitIterator - Create an iterator that traverses the register units
571 MCRegUnitIterator() = default;
573 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
574 assert(Reg && "Null register has no regunits");
575 // Decode the RegUnits MCRegisterDesc field.
576 unsigned RU = MCRI->get(Reg).RegUnits;
577 unsigned Scale = RU & 15;
578 unsigned Offset = RU >> 4;
580 // Initialize the iterator to Reg * Scale, and the List pointer to
581 // DiffLists + Offset.
582 init(Reg * Scale, MCRI->DiffLists + Offset);
584 // That may not be a valid unit, we need to advance by one to get the real
585 // unit number. The first differential can be 0 which would normally
586 // terminate the list, but since we know every register has at least one
587 // unit, we can allow a 0 differential here.
592 /// MCRegUnitMaskIterator enumerates a list of register units and their
593 /// associated lane masks for Reg. The register units are in ascending
595 class MCRegUnitMaskIterator {
596 MCRegUnitIterator RUIter;
597 const LaneBitmask *MaskListIter;
600 MCRegUnitMaskIterator() = default;
602 /// Constructs an iterator that traverses the register units and their
603 /// associated LaneMasks in Reg.
604 MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
605 : RUIter(Reg, MCRI) {
606 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
607 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
610 /// Returns a (RegUnit, LaneMask) pair.
611 std::pair<unsigned,LaneBitmask> operator*() const {
612 return std::make_pair(*RUIter, *MaskListIter);
615 /// Returns true if this iterator is not yet at the end.
616 bool isValid() const { return RUIter.isValid(); }
618 /// Moves to the next position.
625 // Each register unit has one or two root registers. The complete set of
626 // registers containing a register unit is the union of the roots and their
627 // super-registers. All registers aliasing Unit can be visited like this:
629 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
630 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
634 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
635 class MCRegUnitRootIterator {
640 MCRegUnitRootIterator() = default;
642 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
643 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
644 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
645 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
648 /// Dereference to get the current root register.
649 unsigned operator*() const {
653 /// Check if the iterator is at the end of the list.
654 bool isValid() const {
658 /// Preincrement to move to the next root register.
660 assert(isValid() && "Cannot move off the end of the list.");
666 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
667 /// set, Reg itself is included in the list. This iterator does not guarantee
668 /// any ordering or that entries are unique.
669 class MCRegAliasIterator {
672 const MCRegisterInfo *MCRI;
675 MCRegUnitIterator RI;
676 MCRegUnitRootIterator RRI;
677 MCSuperRegIterator SI;
680 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
682 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
683 // Initialize the iterators.
684 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
685 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
686 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
687 if (!(!IncludeSelf && Reg == *SI))
694 bool isValid() const { return RI.isValid(); }
696 unsigned operator*() const {
697 assert(SI.isValid() && "Cannot dereference an invalid iterator.");
702 // Assuming SI is valid.
704 if (SI.isValid()) return;
708 SI = MCSuperRegIterator(*RRI, MCRI, true);
714 RRI = MCRegUnitRootIterator(*RI, MCRI);
715 SI = MCSuperRegIterator(*RRI, MCRI, true);
720 assert(isValid() && "Cannot move off the end of the list.");
722 while (!IncludeSelf && isValid() && *SI == Reg);
726 } // end namespace llvm
728 #endif // LLVM_MC_MCREGISTERINFO_H