1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/MC/LaneBitmask.h"
21 #include "llvm/Support/ErrorHandling.h"
26 /// An unsigned integer type large enough to represent all physical registers,
27 /// but not necessarily virtual registers.
28 typedef uint16_t MCPhysReg;
30 /// MCRegisterClass - Base class of TargetRegisterClass.
31 class MCRegisterClass {
33 typedef const MCPhysReg* iterator;
34 typedef const MCPhysReg* const_iterator;
36 const iterator RegsBegin;
37 const uint8_t *const RegSet;
38 const uint32_t NameIdx;
39 const uint16_t RegsSize;
40 const uint16_t RegSetSize;
42 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
43 const int8_t CopyCost;
44 const bool Allocatable;
46 /// getID() - Return the register class ID number.
48 unsigned getID() const { return ID; }
50 /// begin/end - Return all of the registers in this class.
52 iterator begin() const { return RegsBegin; }
53 iterator end() const { return RegsBegin + RegsSize; }
55 /// getNumRegs - Return the number of registers in this class.
57 unsigned getNumRegs() const { return RegsSize; }
59 /// getRegister - Return the specified register in the class.
61 unsigned getRegister(unsigned i) const {
62 assert(i < getNumRegs() && "Register number out of range!");
66 /// contains - Return true if the specified register is included in this
67 /// register class. This does not include virtual registers.
68 bool contains(unsigned Reg) const {
69 unsigned InByte = Reg % 8;
70 unsigned Byte = Reg / 8;
71 if (Byte >= RegSetSize)
73 return (RegSet[Byte] & (1 << InByte)) != 0;
76 /// contains - Return true if both registers are in this class.
77 bool contains(unsigned Reg1, unsigned Reg2) const {
78 return contains(Reg1) && contains(Reg2);
81 /// getSize - Return the size of the register in bytes, which is also the size
82 /// of a stack slot allocated to hold a spilled copy of this register.
83 unsigned getSize() const { return RegSize; }
85 /// getAlignment - Return the minimum required alignment for a register of
87 unsigned getAlignment() const { return Alignment; }
89 /// getCopyCost - Return the cost of copying a value between two registers in
90 /// this class. A negative number means the register class is very expensive
91 /// to copy e.g. status flag register classes.
92 int getCopyCost() const { return CopyCost; }
94 /// isAllocatable - Return true if this register class may be used to create
95 /// virtual registers.
96 bool isAllocatable() const { return Allocatable; }
99 /// MCRegisterDesc - This record contains information about a particular
100 /// register. The SubRegs field is a zero terminated array of registers that
101 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
102 /// of AX. The SuperRegs field is a zero terminated array of registers that are
103 /// super-registers of the specific register, e.g. RAX, EAX, are
104 /// super-registers of AX.
106 struct MCRegisterDesc {
107 uint32_t Name; // Printable name for the reg (for debugging)
108 uint32_t SubRegs; // Sub-register set, described above
109 uint32_t SuperRegs; // Super-register set, described above
111 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
112 // sub-register in SubRegs.
113 uint32_t SubRegIndices;
115 // RegUnits - Points to the list of register units. The low 4 bits holds the
116 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
119 /// Index into list with lane mask sequences. The sequence contains a lanemask
120 /// for every register unit.
121 uint16_t RegUnitLaneMasks;
124 /// MCRegisterInfo base class - We assume that the target defines a static
125 /// array of MCRegisterDesc objects that represent all of the machine
126 /// registers that the target has. As such, we simply have to track a pointer
127 /// to this array so that we can turn register number into a register
130 /// Note this class is designed to be a base class of TargetRegisterInfo, which
131 /// is the interface used by codegen. However, specific targets *should never*
132 /// specialize this class. MCRegisterInfo should only contain getters to access
133 /// TableGen generated physical register data. It must not be extended with
136 class MCRegisterInfo {
138 typedef const MCRegisterClass *regclass_iterator;
140 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
141 /// performed with a binary search.
142 struct DwarfLLVMRegPair {
146 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
149 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
150 /// index, -1 in any being invalid.
151 struct SubRegCoveredBits {
156 const MCRegisterDesc *Desc; // Pointer to the descriptor array
157 unsigned NumRegs; // Number of entries in the array
158 unsigned RAReg; // Return address register
159 unsigned PCReg; // Program counter register
160 const MCRegisterClass *Classes; // Pointer to the regclass array
161 unsigned NumClasses; // Number of entries in the array
162 unsigned NumRegUnits; // Number of regunits.
163 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
164 const MCPhysReg *DiffLists; // Pointer to the difflists array
165 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
166 // for register units.
167 const char *RegStrings; // Pointer to the string table.
168 const char *RegClassStrings; // Pointer to the class strings.
169 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
171 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
173 unsigned NumSubRegIndices; // Number of subreg indices.
174 const uint16_t *RegEncodingTable; // Pointer to array of register
177 unsigned L2DwarfRegsSize;
178 unsigned EHL2DwarfRegsSize;
179 unsigned Dwarf2LRegsSize;
180 unsigned EHDwarf2LRegsSize;
181 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
182 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
183 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
184 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
185 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
186 DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping
189 /// DiffListIterator - Base iterator class that can traverse the
190 /// differentially encoded register and regunit lists in DiffLists.
191 /// Don't use this class directly, use one of the specialized sub-classes
193 class DiffListIterator {
195 const MCPhysReg *List;
198 /// Create an invalid iterator. Call init() to point to something useful.
199 DiffListIterator() : Val(0), List(nullptr) {}
201 /// init - Point the iterator to InitVal, decoding subsequent values from
202 /// DiffList. The iterator will initially point to InitVal, sub-classes are
203 /// responsible for skipping the seed value if it is not part of the list.
204 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
209 /// advance - Move to the next list position, return the applied
210 /// differential. This function does not detect the end of the list, that
211 /// is the caller's responsibility (by checking for a 0 return value).
213 assert(isValid() && "Cannot move off the end of the list.");
214 MCPhysReg D = *List++;
221 /// isValid - returns true if this iterator is not yet at the end.
222 bool isValid() const { return List; }
224 /// Dereference the iterator to get the value at the current position.
225 unsigned operator*() const { return Val; }
227 /// Pre-increment to move to the next position.
229 // The end of the list is encoded as a 0 differential.
235 // These iterators are allowed to sub-class DiffListIterator and access
236 // internal list pointers.
237 friend class MCSubRegIterator;
238 friend class MCSubRegIndexIterator;
239 friend class MCSuperRegIterator;
240 friend class MCRegUnitIterator;
241 friend class MCRegUnitMaskIterator;
242 friend class MCRegUnitRootIterator;
244 /// \brief Initialize MCRegisterInfo, called by TableGen
245 /// auto-generated routines. *DO NOT USE*.
246 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
248 const MCRegisterClass *C, unsigned NC,
249 const MCPhysReg (*RURoots)[2],
252 const LaneBitmask *RUMS,
254 const char *ClassStrings,
255 const uint16_t *SubIndices,
257 const SubRegCoveredBits *SubIdxRanges,
258 const uint16_t *RET) {
265 RegUnitMaskSequences = RUMS;
266 RegStrings = Strings;
267 RegClassStrings = ClassStrings;
269 RegUnitRoots = RURoots;
271 SubRegIndices = SubIndices;
272 NumSubRegIndices = NumIndices;
273 SubRegIdxRanges = SubIdxRanges;
274 RegEncodingTable = RET;
276 // Initialize DWARF register mapping variables
277 EHL2DwarfRegs = nullptr;
278 EHL2DwarfRegsSize = 0;
279 L2DwarfRegs = nullptr;
281 EHDwarf2LRegs = nullptr;
282 EHDwarf2LRegsSize = 0;
283 Dwarf2LRegs = nullptr;
287 /// \brief Used to initialize LLVM register to Dwarf
288 /// register number mapping. Called by TableGen auto-generated routines.
290 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
294 EHL2DwarfRegsSize = Size;
297 L2DwarfRegsSize = Size;
301 /// \brief Used to initialize Dwarf register to LLVM
302 /// register number mapping. Called by TableGen auto-generated routines.
304 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
308 EHDwarf2LRegsSize = Size;
311 Dwarf2LRegsSize = Size;
315 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
316 /// number mapping. By default the SEH register number is just the same
317 /// as the LLVM register number.
318 /// FIXME: TableGen these numbers. Currently this requires target specific
319 /// initialization code.
320 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
321 L2SEHRegs[LLVMReg] = SEHReg;
324 void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
325 L2CVRegs[LLVMReg] = CVReg;
328 /// \brief This method should return the register where the return
329 /// address can be found.
330 unsigned getRARegister() const {
334 /// Return the register which is the program counter.
335 unsigned getProgramCounter() const {
339 const MCRegisterDesc &operator[](unsigned RegNo) const {
340 assert(RegNo < NumRegs &&
341 "Attempting to access record for invalid register number!");
345 /// \brief Provide a get method, equivalent to [], but more useful with a
346 /// pointer to this object.
347 const MCRegisterDesc &get(unsigned RegNo) const {
348 return operator[](RegNo);
351 /// \brief Returns the physical register number of sub-register "Index"
352 /// for physical register RegNo. Return zero if the sub-register does not
354 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
356 /// \brief Return a super-register of the specified register
357 /// Reg so its sub-register of index SubIdx is Reg.
358 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
359 const MCRegisterClass *RC) const;
361 /// \brief For a given register pair, return the sub-register index
362 /// if the second register is a sub-register of the first. Return zero
364 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
366 /// \brief Get the size of the bit range covered by a sub-register index.
367 /// If the index isn't continuous, return the sum of the sizes of its parts.
368 /// If the index is used to access subregisters of different sizes, return -1.
369 unsigned getSubRegIdxSize(unsigned Idx) const;
371 /// \brief Get the offset of the bit range covered by a sub-register index.
372 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
373 /// access sub-registers at different offsets), return -1.
374 unsigned getSubRegIdxOffset(unsigned Idx) const;
376 /// \brief Return the human-readable symbolic target-specific name for the
377 /// specified physical register.
378 const char *getName(unsigned RegNo) const {
379 return RegStrings + get(RegNo).Name;
382 /// \brief Return the number of registers this target has (useful for
383 /// sizing arrays holding per register information)
384 unsigned getNumRegs() const {
388 /// \brief Return the number of sub-register indices
389 /// understood by the target. Index 0 is reserved for the no-op sub-register,
390 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
391 unsigned getNumSubRegIndices() const {
392 return NumSubRegIndices;
395 /// \brief Return the number of (native) register units in the
396 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
397 /// can be accessed through MCRegUnitIterator defined below.
398 unsigned getNumRegUnits() const {
402 /// \brief Map a target register to an equivalent dwarf register
403 /// number. Returns -1 if there is no equivalent value. The second
404 /// parameter allows targets to use different numberings for EH info and
406 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
408 /// \brief Map a dwarf register back to a target register.
409 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
411 /// \brief Map a target register to an equivalent SEH register
412 /// number. Returns LLVM register number if there is no equivalent value.
413 int getSEHRegNum(unsigned RegNum) const;
415 /// \brief Map a target register to an equivalent CodeView register
417 int getCodeViewRegNum(unsigned RegNum) const;
419 regclass_iterator regclass_begin() const { return Classes; }
420 regclass_iterator regclass_end() const { return Classes+NumClasses; }
422 unsigned getNumRegClasses() const {
423 return (unsigned)(regclass_end()-regclass_begin());
426 /// \brief Returns the register class associated with the enumeration
427 /// value. See class MCOperandInfo.
428 const MCRegisterClass& getRegClass(unsigned i) const {
429 assert(i < getNumRegClasses() && "Register Class ID out of range");
433 const char *getRegClassName(const MCRegisterClass *Class) const {
434 return RegClassStrings + Class->NameIdx;
437 /// \brief Returns the encoding for RegNo
438 uint16_t getEncodingValue(unsigned RegNo) const {
439 assert(RegNo < NumRegs &&
440 "Attempting to get encoding for invalid register number!");
441 return RegEncodingTable[RegNo];
444 /// \brief Returns true if RegB is a sub-register of RegA.
445 bool isSubRegister(unsigned RegA, unsigned RegB) const {
446 return isSuperRegister(RegB, RegA);
449 /// \brief Returns true if RegB is a super-register of RegA.
450 bool isSuperRegister(unsigned RegA, unsigned RegB) const;
452 /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA.
453 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
454 return isSuperRegisterEq(RegB, RegA);
457 /// \brief Returns true if RegB is a super-register of RegA or if
459 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
460 return RegA == RegB || isSuperRegister(RegA, RegB);
463 /// \brief Returns true if RegB is a super-register or sub-register of RegA
464 /// or if RegB == RegA.
465 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
466 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
470 //===----------------------------------------------------------------------===//
471 // Register List Iterators
472 //===----------------------------------------------------------------------===//
474 // MCRegisterInfo provides lists of super-registers, sub-registers, and
475 // aliasing registers. Use these iterator classes to traverse the lists.
477 /// MCSubRegIterator enumerates all sub-registers of Reg.
478 /// If IncludeSelf is set, Reg itself is included in the list.
479 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
481 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
482 bool IncludeSelf = false) {
483 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
484 // Initially, the iterator points to Reg itself.
490 /// Iterator that enumerates the sub-registers of a Reg and the associated
491 /// sub-register indices.
492 class MCSubRegIndexIterator {
493 MCSubRegIterator SRIter;
494 const uint16_t *SRIndex;
496 /// Constructs an iterator that traverses subregisters and their
497 /// associated subregister indices.
498 MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
499 : SRIter(Reg, MCRI) {
500 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
503 /// Returns current sub-register.
504 unsigned getSubReg() const {
507 /// Returns sub-register index of the current sub-register.
508 unsigned getSubRegIndex() const {
512 /// Returns true if this iterator is not yet at the end.
513 bool isValid() const { return SRIter.isValid(); }
515 /// Moves to the next position.
522 /// MCSuperRegIterator enumerates all super-registers of Reg.
523 /// If IncludeSelf is set, Reg itself is included in the list.
524 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
526 MCSuperRegIterator() {}
527 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
528 bool IncludeSelf = false) {
529 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
530 // Initially, the iterator points to Reg itself.
536 // Definition for isSuperRegister. Put it down here since it needs the
537 // iterator defined above in addition to the MCRegisterInfo class itself.
538 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
539 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
545 //===----------------------------------------------------------------------===//
547 //===----------------------------------------------------------------------===//
549 // Register units are used to compute register aliasing. Every register has at
550 // least one register unit, but it can have more. Two registers overlap if and
551 // only if they have a common register unit.
553 // A target with a complicated sub-register structure will typically have many
554 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
555 // the number of register units in the target.
557 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
558 // in ascending numerical order.
559 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
561 /// MCRegUnitIterator - Create an iterator that traverses the register units
563 MCRegUnitIterator() {}
564 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
565 assert(Reg && "Null register has no regunits");
566 // Decode the RegUnits MCRegisterDesc field.
567 unsigned RU = MCRI->get(Reg).RegUnits;
568 unsigned Scale = RU & 15;
569 unsigned Offset = RU >> 4;
571 // Initialize the iterator to Reg * Scale, and the List pointer to
572 // DiffLists + Offset.
573 init(Reg * Scale, MCRI->DiffLists + Offset);
575 // That may not be a valid unit, we need to advance by one to get the real
576 // unit number. The first differential can be 0 which would normally
577 // terminate the list, but since we know every register has at least one
578 // unit, we can allow a 0 differential here.
583 /// MCRegUnitMaskIterator enumerates a list of register units and their
584 /// associated lane masks for Reg. The register units are in ascending
586 class MCRegUnitMaskIterator {
587 MCRegUnitIterator RUIter;
588 const LaneBitmask *MaskListIter;
590 MCRegUnitMaskIterator() {}
591 /// Constructs an iterator that traverses the register units and their
592 /// associated LaneMasks in Reg.
593 MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
594 : RUIter(Reg, MCRI) {
595 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
596 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
599 /// Returns a (RegUnit, LaneMask) pair.
600 std::pair<unsigned,LaneBitmask> operator*() const {
601 return std::make_pair(*RUIter, *MaskListIter);
604 /// Returns true if this iterator is not yet at the end.
605 bool isValid() const { return RUIter.isValid(); }
607 /// Moves to the next position.
614 // Each register unit has one or two root registers. The complete set of
615 // registers containing a register unit is the union of the roots and their
616 // super-registers. All registers aliasing Unit can be visited like this:
618 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
619 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
623 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
624 class MCRegUnitRootIterator {
628 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
629 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
630 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
631 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
632 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
635 /// \brief Dereference to get the current root register.
636 unsigned operator*() const {
640 /// \brief Check if the iterator is at the end of the list.
641 bool isValid() const {
645 /// \brief Preincrement to move to the next root register.
647 assert(isValid() && "Cannot move off the end of the list.");
653 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
654 /// set, Reg itself is included in the list. This iterator does not guarantee
655 /// any ordering or that entries are unique.
656 class MCRegAliasIterator {
659 const MCRegisterInfo *MCRI;
662 MCRegUnitIterator RI;
663 MCRegUnitRootIterator RRI;
664 MCSuperRegIterator SI;
666 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
668 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
670 // Initialize the iterators.
671 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
672 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
673 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
674 if (!(!IncludeSelf && Reg == *SI))
681 bool isValid() const { return RI.isValid(); }
683 unsigned operator*() const {
684 assert (SI.isValid() && "Cannot dereference an invalid iterator.");
689 // Assuming SI is valid.
691 if (SI.isValid()) return;
695 SI = MCSuperRegIterator(*RRI, MCRI, true);
701 RRI = MCRegUnitRootIterator(*RI, MCRI);
702 SI = MCSuperRegIterator(*RRI, MCRI, true);
707 assert(isValid() && "Cannot move off the end of the list.");
709 while (!IncludeSelf && isValid() && *SI == Reg);
713 } // End llvm namespace