1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// An unsigned integer type large enough to represent all physical registers,
26 /// but not necessarily virtual registers.
27 typedef uint16_t MCPhysReg;
29 /// MCRegisterClass - Base class of TargetRegisterClass.
30 class MCRegisterClass {
32 typedef const MCPhysReg* iterator;
33 typedef const MCPhysReg* const_iterator;
35 const iterator RegsBegin;
36 const uint8_t *const RegSet;
37 const uint32_t NameIdx;
38 const uint16_t RegsSize;
39 const uint16_t RegSetSize;
41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
42 const int8_t CopyCost;
43 const bool Allocatable;
45 /// getID() - Return the register class ID number.
47 unsigned getID() const { return ID; }
49 /// begin/end - Return all of the registers in this class.
51 iterator begin() const { return RegsBegin; }
52 iterator end() const { return RegsBegin + RegsSize; }
54 /// getNumRegs - Return the number of registers in this class.
56 unsigned getNumRegs() const { return RegsSize; }
58 /// getRegister - Return the specified register in the class.
60 unsigned getRegister(unsigned i) const {
61 assert(i < getNumRegs() && "Register number out of range!");
65 /// contains - Return true if the specified register is included in this
66 /// register class. This does not include virtual registers.
67 bool contains(unsigned Reg) const {
68 unsigned InByte = Reg % 8;
69 unsigned Byte = Reg / 8;
70 if (Byte >= RegSetSize)
72 return (RegSet[Byte] & (1 << InByte)) != 0;
75 /// contains - Return true if both registers are in this class.
76 bool contains(unsigned Reg1, unsigned Reg2) const {
77 return contains(Reg1) && contains(Reg2);
80 /// getSize - Return the size of the register in bytes, which is also the size
81 /// of a stack slot allocated to hold a spilled copy of this register.
82 unsigned getSize() const { return RegSize; }
84 /// getAlignment - Return the minimum required alignment for a register of
86 unsigned getAlignment() const { return Alignment; }
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost; }
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable; }
98 /// MCRegisterDesc - This record contains information about a particular
99 /// register. The SubRegs field is a zero terminated array of registers that
100 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
101 /// of AX. The SuperRegs field is a zero terminated array of registers that are
102 /// super-registers of the specific register, e.g. RAX, EAX, are
103 /// super-registers of AX.
105 struct MCRegisterDesc {
106 uint32_t Name; // Printable name for the reg (for debugging)
107 uint32_t SubRegs; // Sub-register set, described above
108 uint32_t SuperRegs; // Super-register set, described above
110 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
111 // sub-register in SubRegs.
112 uint32_t SubRegIndices;
114 // RegUnits - Points to the list of register units. The low 4 bits holds the
115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
118 /// Index into list with lane mask sequences. The sequence contains a lanemask
119 /// for every register unit.
120 uint16_t RegUnitLaneMasks;
123 /// MCRegisterInfo base class - We assume that the target defines a static
124 /// array of MCRegisterDesc objects that represent all of the machine
125 /// registers that the target has. As such, we simply have to track a pointer
126 /// to this array so that we can turn register number into a register
129 /// Note this class is designed to be a base class of TargetRegisterInfo, which
130 /// is the interface used by codegen. However, specific targets *should never*
131 /// specialize this class. MCRegisterInfo should only contain getters to access
132 /// TableGen generated physical register data. It must not be extended with
135 class MCRegisterInfo {
137 typedef const MCRegisterClass *regclass_iterator;
139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140 /// performed with a binary search.
141 struct DwarfLLVMRegPair {
145 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
148 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
149 /// index, -1 in any being invalid.
150 struct SubRegCoveredBits {
155 const MCRegisterDesc *Desc; // Pointer to the descriptor array
156 unsigned NumRegs; // Number of entries in the array
157 unsigned RAReg; // Return address register
158 unsigned PCReg; // Program counter register
159 const MCRegisterClass *Classes; // Pointer to the regclass array
160 unsigned NumClasses; // Number of entries in the array
161 unsigned NumRegUnits; // Number of regunits.
162 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
163 const MCPhysReg *DiffLists; // Pointer to the difflists array
164 const unsigned *RegUnitMaskSequences; // Pointer to lane mask sequences
165 // for register units.
166 const char *RegStrings; // Pointer to the string table.
167 const char *RegClassStrings; // Pointer to the class strings.
168 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
170 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
172 unsigned NumSubRegIndices; // Number of subreg indices.
173 const uint16_t *RegEncodingTable; // Pointer to array of register
176 unsigned L2DwarfRegsSize;
177 unsigned EHL2DwarfRegsSize;
178 unsigned Dwarf2LRegsSize;
179 unsigned EHDwarf2LRegsSize;
180 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
181 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
182 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
183 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
184 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
185 DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping
188 /// DiffListIterator - Base iterator class that can traverse the
189 /// differentially encoded register and regunit lists in DiffLists.
190 /// Don't use this class directly, use one of the specialized sub-classes
192 class DiffListIterator {
194 const MCPhysReg *List;
197 /// Create an invalid iterator. Call init() to point to something useful.
198 DiffListIterator() : Val(0), List(nullptr) {}
200 /// init - Point the iterator to InitVal, decoding subsequent values from
201 /// DiffList. The iterator will initially point to InitVal, sub-classes are
202 /// responsible for skipping the seed value if it is not part of the list.
203 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
208 /// advance - Move to the next list position, return the applied
209 /// differential. This function does not detect the end of the list, that
210 /// is the caller's responsibility (by checking for a 0 return value).
212 assert(isValid() && "Cannot move off the end of the list.");
213 MCPhysReg D = *List++;
220 /// isValid - returns true if this iterator is not yet at the end.
221 bool isValid() const { return List; }
223 /// Dereference the iterator to get the value at the current position.
224 unsigned operator*() const { return Val; }
226 /// Pre-increment to move to the next position.
228 // The end of the list is encoded as a 0 differential.
234 // These iterators are allowed to sub-class DiffListIterator and access
235 // internal list pointers.
236 friend class MCSubRegIterator;
237 friend class MCSubRegIndexIterator;
238 friend class MCSuperRegIterator;
239 friend class MCRegUnitIterator;
240 friend class MCRegUnitMaskIterator;
241 friend class MCRegUnitRootIterator;
243 /// \brief Initialize MCRegisterInfo, called by TableGen
244 /// auto-generated routines. *DO NOT USE*.
245 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
247 const MCRegisterClass *C, unsigned NC,
248 const MCPhysReg (*RURoots)[2],
251 const unsigned *RUMS,
253 const char *ClassStrings,
254 const uint16_t *SubIndices,
256 const SubRegCoveredBits *SubIdxRanges,
257 const uint16_t *RET) {
264 RegUnitMaskSequences = RUMS;
265 RegStrings = Strings;
266 RegClassStrings = ClassStrings;
268 RegUnitRoots = RURoots;
270 SubRegIndices = SubIndices;
271 NumSubRegIndices = NumIndices;
272 SubRegIdxRanges = SubIdxRanges;
273 RegEncodingTable = RET;
276 /// \brief Used to initialize LLVM register to Dwarf
277 /// register number mapping. Called by TableGen auto-generated routines.
279 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
283 EHL2DwarfRegsSize = Size;
286 L2DwarfRegsSize = Size;
290 /// \brief Used to initialize Dwarf register to LLVM
291 /// register number mapping. Called by TableGen auto-generated routines.
293 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
297 EHDwarf2LRegsSize = Size;
300 Dwarf2LRegsSize = Size;
304 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
305 /// number mapping. By default the SEH register number is just the same
306 /// as the LLVM register number.
307 /// FIXME: TableGen these numbers. Currently this requires target specific
308 /// initialization code.
309 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
310 L2SEHRegs[LLVMReg] = SEHReg;
313 void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
314 L2CVRegs[LLVMReg] = CVReg;
317 /// \brief This method should return the register where the return
318 /// address can be found.
319 unsigned getRARegister() const {
323 /// Return the register which is the program counter.
324 unsigned getProgramCounter() const {
328 const MCRegisterDesc &operator[](unsigned RegNo) const {
329 assert(RegNo < NumRegs &&
330 "Attempting to access record for invalid register number!");
334 /// \brief Provide a get method, equivalent to [], but more useful with a
335 /// pointer to this object.
336 const MCRegisterDesc &get(unsigned RegNo) const {
337 return operator[](RegNo);
340 /// \brief Returns the physical register number of sub-register "Index"
341 /// for physical register RegNo. Return zero if the sub-register does not
343 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
345 /// \brief Return a super-register of the specified register
346 /// Reg so its sub-register of index SubIdx is Reg.
347 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
348 const MCRegisterClass *RC) const;
350 /// \brief For a given register pair, return the sub-register index
351 /// if the second register is a sub-register of the first. Return zero
353 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
355 /// \brief Get the size of the bit range covered by a sub-register index.
356 /// If the index isn't continuous, return the sum of the sizes of its parts.
357 /// If the index is used to access subregisters of different sizes, return -1.
358 unsigned getSubRegIdxSize(unsigned Idx) const;
360 /// \brief Get the offset of the bit range covered by a sub-register index.
361 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
362 /// access sub-registers at different offsets), return -1.
363 unsigned getSubRegIdxOffset(unsigned Idx) const;
365 /// \brief Return the human-readable symbolic target-specific name for the
366 /// specified physical register.
367 const char *getName(unsigned RegNo) const {
368 return RegStrings + get(RegNo).Name;
371 /// \brief Return the number of registers this target has (useful for
372 /// sizing arrays holding per register information)
373 unsigned getNumRegs() const {
377 /// \brief Return the number of sub-register indices
378 /// understood by the target. Index 0 is reserved for the no-op sub-register,
379 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
380 unsigned getNumSubRegIndices() const {
381 return NumSubRegIndices;
384 /// \brief Return the number of (native) register units in the
385 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
386 /// can be accessed through MCRegUnitIterator defined below.
387 unsigned getNumRegUnits() const {
391 /// \brief Map a target register to an equivalent dwarf register
392 /// number. Returns -1 if there is no equivalent value. The second
393 /// parameter allows targets to use different numberings for EH info and
395 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
397 /// \brief Map a dwarf register back to a target register.
398 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
400 /// \brief Map a target register to an equivalent SEH register
401 /// number. Returns LLVM register number if there is no equivalent value.
402 int getSEHRegNum(unsigned RegNum) const;
404 /// \brief Map a target register to an equivalent CodeView register
406 int getCodeViewRegNum(unsigned RegNum) const;
408 regclass_iterator regclass_begin() const { return Classes; }
409 regclass_iterator regclass_end() const { return Classes+NumClasses; }
411 unsigned getNumRegClasses() const {
412 return (unsigned)(regclass_end()-regclass_begin());
415 /// \brief Returns the register class associated with the enumeration
416 /// value. See class MCOperandInfo.
417 const MCRegisterClass& getRegClass(unsigned i) const {
418 assert(i < getNumRegClasses() && "Register Class ID out of range");
422 const char *getRegClassName(const MCRegisterClass *Class) const {
423 return RegClassStrings + Class->NameIdx;
426 /// \brief Returns the encoding for RegNo
427 uint16_t getEncodingValue(unsigned RegNo) const {
428 assert(RegNo < NumRegs &&
429 "Attempting to get encoding for invalid register number!");
430 return RegEncodingTable[RegNo];
433 /// \brief Returns true if RegB is a sub-register of RegA.
434 bool isSubRegister(unsigned RegA, unsigned RegB) const {
435 return isSuperRegister(RegB, RegA);
438 /// \brief Returns true if RegB is a super-register of RegA.
439 bool isSuperRegister(unsigned RegA, unsigned RegB) const;
441 /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA.
442 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
443 return isSuperRegisterEq(RegB, RegA);
446 /// \brief Returns true if RegB is a super-register of RegA or if
448 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
449 return RegA == RegB || isSuperRegister(RegA, RegB);
452 /// \brief Returns true if RegB is a super-register or sub-register of RegA
453 /// or if RegB == RegA.
454 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
455 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
459 //===----------------------------------------------------------------------===//
460 // Register List Iterators
461 //===----------------------------------------------------------------------===//
463 // MCRegisterInfo provides lists of super-registers, sub-registers, and
464 // aliasing registers. Use these iterator classes to traverse the lists.
466 /// MCSubRegIterator enumerates all sub-registers of Reg.
467 /// If IncludeSelf is set, Reg itself is included in the list.
468 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
470 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
471 bool IncludeSelf = false) {
472 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
473 // Initially, the iterator points to Reg itself.
479 /// Iterator that enumerates the sub-registers of a Reg and the associated
480 /// sub-register indices.
481 class MCSubRegIndexIterator {
482 MCSubRegIterator SRIter;
483 const uint16_t *SRIndex;
485 /// Constructs an iterator that traverses subregisters and their
486 /// associated subregister indices.
487 MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
488 : SRIter(Reg, MCRI) {
489 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
492 /// Returns current sub-register.
493 unsigned getSubReg() const {
496 /// Returns sub-register index of the current sub-register.
497 unsigned getSubRegIndex() const {
501 /// Returns true if this iterator is not yet at the end.
502 bool isValid() const { return SRIter.isValid(); }
504 /// Moves to the next position.
511 /// MCSuperRegIterator enumerates all super-registers of Reg.
512 /// If IncludeSelf is set, Reg itself is included in the list.
513 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
515 MCSuperRegIterator() {}
516 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
517 bool IncludeSelf = false) {
518 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
519 // Initially, the iterator points to Reg itself.
525 // Definition for isSuperRegister. Put it down here since it needs the
526 // iterator defined above in addition to the MCRegisterInfo class itself.
527 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
528 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
534 //===----------------------------------------------------------------------===//
536 //===----------------------------------------------------------------------===//
538 // Register units are used to compute register aliasing. Every register has at
539 // least one register unit, but it can have more. Two registers overlap if and
540 // only if they have a common register unit.
542 // A target with a complicated sub-register structure will typically have many
543 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
544 // the number of register units in the target.
546 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
547 // in ascending numerical order.
548 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
550 /// MCRegUnitIterator - Create an iterator that traverses the register units
552 MCRegUnitIterator() {}
553 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
554 assert(Reg && "Null register has no regunits");
555 // Decode the RegUnits MCRegisterDesc field.
556 unsigned RU = MCRI->get(Reg).RegUnits;
557 unsigned Scale = RU & 15;
558 unsigned Offset = RU >> 4;
560 // Initialize the iterator to Reg * Scale, and the List pointer to
561 // DiffLists + Offset.
562 init(Reg * Scale, MCRI->DiffLists + Offset);
564 // That may not be a valid unit, we need to advance by one to get the real
565 // unit number. The first differential can be 0 which would normally
566 // terminate the list, but since we know every register has at least one
567 // unit, we can allow a 0 differential here.
572 /// MCRegUnitIterator enumerates a list of register units and their associated
573 /// lane masks for Reg. The register units are in ascending numerical order.
574 class MCRegUnitMaskIterator {
575 MCRegUnitIterator RUIter;
576 const unsigned *MaskListIter;
578 MCRegUnitMaskIterator() {}
579 /// Constructs an iterator that traverses the register units and their
580 /// associated LaneMasks in Reg.
581 MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
582 : RUIter(Reg, MCRI) {
583 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
584 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
587 /// Returns a (RegUnit, LaneMask) pair.
588 std::pair<unsigned,unsigned> operator*() const {
589 return std::make_pair(*RUIter, *MaskListIter);
592 /// Returns true if this iterator is not yet at the end.
593 bool isValid() const { return RUIter.isValid(); }
595 /// Moves to the next position.
602 // Each register unit has one or two root registers. The complete set of
603 // registers containing a register unit is the union of the roots and their
604 // super-registers. All registers aliasing Unit can be visited like this:
606 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
607 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
611 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
612 class MCRegUnitRootIterator {
616 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
617 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
618 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
619 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
620 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
623 /// \brief Dereference to get the current root register.
624 unsigned operator*() const {
628 /// \brief Check if the iterator is at the end of the list.
629 bool isValid() const {
633 /// \brief Preincrement to move to the next root register.
635 assert(isValid() && "Cannot move off the end of the list.");
641 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
642 /// set, Reg itself is included in the list. This iterator does not guarantee
643 /// any ordering or that entries are unique.
644 class MCRegAliasIterator {
647 const MCRegisterInfo *MCRI;
650 MCRegUnitIterator RI;
651 MCRegUnitRootIterator RRI;
652 MCSuperRegIterator SI;
654 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
656 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
658 // Initialize the iterators.
659 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
660 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
661 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
662 if (!(!IncludeSelf && Reg == *SI))
669 bool isValid() const { return RI.isValid(); }
671 unsigned operator*() const {
672 assert (SI.isValid() && "Cannot dereference an invalid iterator.");
677 // Assuming SI is valid.
679 if (SI.isValid()) return;
683 SI = MCSuperRegIterator(*RRI, MCRI, true);
689 RRI = MCRegUnitRootIterator(*RI, MCRI);
690 SI = MCSuperRegIterator(*RRI, MCRI, true);
695 assert(isValid() && "Cannot move off the end of the list.");
697 while (!IncludeSelf && isValid() && *SI == Reg);
701 } // End llvm namespace