1 //===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target independent instruction opcodes.
12 //===----------------------------------------------------------------------===//
14 // NOTE: NO INCLUDE GUARD DESIRED!
16 /// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value.
18 #ifndef HANDLE_TARGET_OPCODE
19 #define HANDLE_TARGET_OPCODE(OPC, NUM)
22 /// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode.
24 #ifndef HANDLE_TARGET_OPCODE_MARKER
25 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
28 /// Every instruction defined here must also appear in Target.td.
30 HANDLE_TARGET_OPCODE(PHI)
31 HANDLE_TARGET_OPCODE(INLINEASM)
32 HANDLE_TARGET_OPCODE(CFI_INSTRUCTION)
33 HANDLE_TARGET_OPCODE(EH_LABEL)
34 HANDLE_TARGET_OPCODE(GC_LABEL)
35 HANDLE_TARGET_OPCODE(ANNOTATION_LABEL)
37 /// KILL - This instruction is a noop that is used only to adjust the
38 /// liveness of registers. This can be useful when dealing with
40 HANDLE_TARGET_OPCODE(KILL)
42 /// EXTRACT_SUBREG - This instruction takes two operands: a register
43 /// that has subregisters, and a subregister index. It returns the
44 /// extracted subregister value. This is commonly used to implement
45 /// truncation operations on target architectures which support it.
46 HANDLE_TARGET_OPCODE(EXTRACT_SUBREG)
48 /// INSERT_SUBREG - This instruction takes three operands: a register that
49 /// has subregisters, a register providing an insert value, and a
50 /// subregister index. It returns the value of the first register with the
51 /// value of the second register inserted. The first register is often
52 /// defined by an IMPLICIT_DEF, because it is commonly used to implement
53 /// anyext operations on target architectures which support it.
54 HANDLE_TARGET_OPCODE(INSERT_SUBREG)
56 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
57 HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
59 /// SUBREG_TO_REG - Assert the value of bits in a super register.
60 /// The result of this instruction is the value of the second operand inserted
61 /// into the subregister specified by the third operand. All other bits are
62 /// assumed to be equal to the bits in the immediate integer constant in the
63 /// first operand. This instruction just communicates information; No code
64 /// should be generated.
65 /// This is typically used after an instruction where the write to a subregister
66 /// implicitly cleared the bits in the super registers.
67 HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
69 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
70 /// register-to-register copy into a specific register class. This is only
71 /// used between instruction selection and MachineInstr creation, before
72 /// virtual registers have been created for all the instructions, and it's
73 /// only needed in cases where the register classes implied by the
74 /// instructions are insufficient. It is emitted as a COPY MachineInstr.
75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS)
77 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
78 HANDLE_TARGET_OPCODE(DBG_VALUE)
80 /// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic
81 HANDLE_TARGET_OPCODE(DBG_LABEL)
83 /// REG_SEQUENCE - This variadic instruction is used to form a register that
84 /// represents a consecutive sequence of sub-registers. It's used as a
85 /// register coalescing / allocation aid and must be eliminated before code
87 // In SDNode form, the first operand encodes the register class created by
88 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
89 // pair. Once it has been lowered to a MachineInstr, the regclass operand
90 // is no longer present.
91 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
92 /// After register coalescing references of v1024 should be replace with
93 /// v1027:3, v1025 with v1027:4, etc.
94 HANDLE_TARGET_OPCODE(REG_SEQUENCE)
96 /// COPY - Target-independent register copy. This instruction can also be
97 /// used to copy between subregisters of virtual registers.
98 HANDLE_TARGET_OPCODE(COPY)
100 /// BUNDLE - This instruction represents an instruction bundle. Instructions
101 /// which immediately follow a BUNDLE instruction which are marked with
102 /// 'InsideBundle' flag are inside the bundle.
103 HANDLE_TARGET_OPCODE(BUNDLE)
105 /// Lifetime markers.
106 HANDLE_TARGET_OPCODE(LIFETIME_START)
107 HANDLE_TARGET_OPCODE(LIFETIME_END)
109 /// A Stackmap instruction captures the location of live variables at its
110 /// position in the instruction stream. It is followed by a shadow of bytes
111 /// that must lie within the function and not contain another stackmap.
112 HANDLE_TARGET_OPCODE(STACKMAP)
114 /// FEntry all - This is a marker instruction which gets translated into a raw fentry call.
115 HANDLE_TARGET_OPCODE(FENTRY_CALL)
117 /// Patchable call instruction - this instruction represents a call to a
118 /// constant address, followed by a series of NOPs. It is intended to
119 /// support optimizations for dynamic languages (such as javascript) that
120 /// rewrite calls to runtimes with more efficient code sequences.
121 /// This also implies a stack map.
122 HANDLE_TARGET_OPCODE(PATCHPOINT)
124 /// This pseudo-instruction loads the stack guard value. Targets which need
125 /// to prevent the stack guard value or address from being spilled to the
126 /// stack should override TargetLowering::emitLoadStackGuardNode and
127 /// additionally expand this pseudo after register allocation.
128 HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD)
130 /// Call instruction with associated vm state for deoptimization and list
131 /// of live pointers for relocation by the garbage collector. It is
132 /// intended to support garbage collection with fully precise relocating
133 /// collectors and deoptimizations in either the callee or caller.
134 HANDLE_TARGET_OPCODE(STATEPOINT)
136 /// Instruction that records the offset of a local stack allocation passed to
137 /// llvm.localescape. It has two arguments: the symbol for the label and the
138 /// frame index of the local stack allocation.
139 HANDLE_TARGET_OPCODE(LOCAL_ESCAPE)
141 /// Wraps a machine instruction which can fault, bundled with associated
142 /// information on how to handle such a fault.
143 /// For example loading instruction that may page fault, bundled with associated
144 /// information on how to handle such a page fault. It is intended to support
145 /// "zero cost" null checks in managed languages by allowing LLVM to fold
146 /// comparisons into existing memory operations.
147 HANDLE_TARGET_OPCODE(FAULTING_OP)
149 /// Wraps a machine instruction to add patchability constraints. An
150 /// instruction wrapped in PATCHABLE_OP has to either have a minimum
151 /// size or be preceded with a nop of that size. The first operand is
152 /// an immediate denoting the minimum size of the instruction, the
153 /// second operand is an immediate denoting the opcode of the original
154 /// instruction. The rest of the operands are the operands of the
155 /// original instruction.
156 HANDLE_TARGET_OPCODE(PATCHABLE_OP)
158 /// This is a marker instruction which gets translated into a nop sled, useful
159 /// for inserting instrumentation instructions at runtime.
160 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER)
162 /// Wraps a return instruction and its operands to enable adding nop sleds
163 /// either before or after the return. The nop sleds are useful for inserting
164 /// instrumentation instructions at runtime.
165 /// The patch here replaces the return instruction.
166 HANDLE_TARGET_OPCODE(PATCHABLE_RET)
168 /// This is a marker instruction which gets translated into a nop sled, useful
169 /// for inserting instrumentation instructions at runtime.
170 /// The patch here prepends the return instruction.
171 /// The same thing as in x86_64 is not possible for ARM because it has multiple
172 /// return instructions. Furthermore, CPU allows parametrized and even
173 /// conditional return instructions. In the current ARM implementation we are
174 /// making use of the fact that currently LLVM doesn't seem to generate
175 /// conditional return instructions.
176 /// On ARM, the same instruction can be used for popping multiple registers
177 /// from the stack and returning (it just pops pc register too), and LLVM
178 /// generates it sometimes. So we can't insert the sled between this stack
179 /// adjustment and the return without splitting the original instruction into 2
180 /// instructions. So on ARM, rather than jumping into the exit trampoline, we
181 /// call it, it does the tracing, preserves the stack and returns.
182 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT)
184 /// Wraps a tail call instruction and its operands to enable adding nop sleds
185 /// either before or after the tail exit. We use this as a disambiguation from
186 /// PATCHABLE_RET which specifically only works for return instructions.
187 HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL)
189 /// Wraps a logging call and its arguments with nop sleds. At runtime, this can
190 /// be patched to insert instrumentation instructions.
191 HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL)
193 /// Wraps a typed logging call and its argument with nop sleds. At runtime, this
194 /// can be patched to insert instrumentation instructions.
195 HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL)
197 HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
199 /// The following generic opcodes are not supposed to appear after ISel.
200 /// This is something we might want to relax, but for now, this is convenient
201 /// to produce diagnostics.
203 /// Generic ADD instruction. This is an integer add.
204 HANDLE_TARGET_OPCODE(G_ADD)
205 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
207 /// Generic SUB instruction. This is an integer sub.
208 HANDLE_TARGET_OPCODE(G_SUB)
210 // Generic multiply instruction.
211 HANDLE_TARGET_OPCODE(G_MUL)
213 // Generic signed division instruction.
214 HANDLE_TARGET_OPCODE(G_SDIV)
216 // Generic unsigned division instruction.
217 HANDLE_TARGET_OPCODE(G_UDIV)
219 // Generic signed remainder instruction.
220 HANDLE_TARGET_OPCODE(G_SREM)
222 // Generic unsigned remainder instruction.
223 HANDLE_TARGET_OPCODE(G_UREM)
225 /// Generic bitwise and instruction.
226 HANDLE_TARGET_OPCODE(G_AND)
228 /// Generic bitwise or instruction.
229 HANDLE_TARGET_OPCODE(G_OR)
231 /// Generic bitwise exclusive-or instruction.
232 HANDLE_TARGET_OPCODE(G_XOR)
235 HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
237 /// Generic PHI instruction with types.
238 HANDLE_TARGET_OPCODE(G_PHI)
240 /// Generic instruction to materialize the address of an alloca or other
241 /// stack-based object.
242 HANDLE_TARGET_OPCODE(G_FRAME_INDEX)
244 /// Generic reference to global value.
245 HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE)
247 /// Generic instruction to extract blocks of bits from the register given
248 /// (typically a sub-register COPY after instruction selection).
249 HANDLE_TARGET_OPCODE(G_EXTRACT)
251 HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES)
253 /// Generic instruction to insert blocks of bits from the registers given into
255 HANDLE_TARGET_OPCODE(G_INSERT)
257 /// Generic instruction to paste a variable number of components together into a
259 HANDLE_TARGET_OPCODE(G_MERGE_VALUES)
261 /// Generic pointer to int conversion.
262 HANDLE_TARGET_OPCODE(G_PTRTOINT)
264 /// Generic int to pointer conversion.
265 HANDLE_TARGET_OPCODE(G_INTTOPTR)
267 /// Generic bitcast. The source and destination types must be different, or a
268 /// COPY is the relevant instruction.
269 HANDLE_TARGET_OPCODE(G_BITCAST)
271 /// Generic load (including anyext load)
272 HANDLE_TARGET_OPCODE(G_LOAD)
274 /// Generic signext load
275 HANDLE_TARGET_OPCODE(G_SEXTLOAD)
277 /// Generic zeroext load
278 HANDLE_TARGET_OPCODE(G_ZEXTLOAD)
281 HANDLE_TARGET_OPCODE(G_STORE)
283 /// Generic atomic cmpxchg with internal success check.
284 HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS)
286 /// Generic atomic cmpxchg.
287 HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG)
289 /// Generic atomicrmw.
290 HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG)
291 HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD)
292 HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB)
293 HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND)
294 HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND)
295 HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR)
296 HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR)
297 HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX)
298 HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN)
299 HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX)
300 HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN)
302 /// Generic conditional branch instruction.
303 HANDLE_TARGET_OPCODE(G_BRCOND)
305 /// Generic indirect branch instruction.
306 HANDLE_TARGET_OPCODE(G_BRINDIRECT)
308 /// Generic intrinsic use (without side effects).
309 HANDLE_TARGET_OPCODE(G_INTRINSIC)
311 /// Generic intrinsic use (with side effects).
312 HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS)
314 /// Generic extension allowing rubbish in high bits.
315 HANDLE_TARGET_OPCODE(G_ANYEXT)
317 /// Generic instruction to discard the high bits of a register. This differs
318 /// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate
319 /// each element individually, G_EXTRACT will typically discard the high
320 /// elements of the vector.
321 HANDLE_TARGET_OPCODE(G_TRUNC)
323 /// Generic integer constant.
324 HANDLE_TARGET_OPCODE(G_CONSTANT)
326 /// Generic floating constant.
327 HANDLE_TARGET_OPCODE(G_FCONSTANT)
329 /// Generic va_start instruction. Stores to its one pointer operand.
330 HANDLE_TARGET_OPCODE(G_VASTART)
332 /// Generic va_start instruction. Stores to its one pointer operand.
333 HANDLE_TARGET_OPCODE(G_VAARG)
335 // Generic sign extend
336 HANDLE_TARGET_OPCODE(G_SEXT)
338 // Generic zero extend
339 HANDLE_TARGET_OPCODE(G_ZEXT)
341 // Generic left-shift
342 HANDLE_TARGET_OPCODE(G_SHL)
344 // Generic logical right-shift
345 HANDLE_TARGET_OPCODE(G_LSHR)
347 // Generic arithmetic right-shift
348 HANDLE_TARGET_OPCODE(G_ASHR)
350 /// Generic integer-base comparison, also applicable to vectors of integers.
351 HANDLE_TARGET_OPCODE(G_ICMP)
353 /// Generic floating-point comparison, also applicable to vectors.
354 HANDLE_TARGET_OPCODE(G_FCMP)
357 HANDLE_TARGET_OPCODE(G_SELECT)
359 /// Generic unsigned add instruction, consuming the normal operands plus a carry
360 /// flag, and similarly producing the result and a carry flag.
361 HANDLE_TARGET_OPCODE(G_UADDE)
363 /// Generic unsigned subtract instruction, consuming the normal operands plus a
364 /// carry flag, and similarly producing the result and a carry flag.
365 HANDLE_TARGET_OPCODE(G_USUBE)
367 /// Generic signed add instruction, producing the result and a signed overflow
369 HANDLE_TARGET_OPCODE(G_SADDO)
371 /// Generic signed subtract instruction, producing the result and a signed
373 HANDLE_TARGET_OPCODE(G_SSUBO)
375 /// Generic unsigned multiply instruction, producing the result and a signed
377 HANDLE_TARGET_OPCODE(G_UMULO)
379 /// Generic signed multiply instruction, producing the result and a signed
381 HANDLE_TARGET_OPCODE(G_SMULO)
383 // Multiply two numbers at twice the incoming bit width (unsigned) and return
384 // the high half of the result.
385 HANDLE_TARGET_OPCODE(G_UMULH)
387 // Multiply two numbers at twice the incoming bit width (signed) and return
388 // the high half of the result.
389 HANDLE_TARGET_OPCODE(G_SMULH)
391 /// Generic FP addition.
392 HANDLE_TARGET_OPCODE(G_FADD)
394 /// Generic FP subtraction.
395 HANDLE_TARGET_OPCODE(G_FSUB)
397 /// Generic FP multiplication.
398 HANDLE_TARGET_OPCODE(G_FMUL)
400 /// Generic FMA multiplication. Behaves like llvm fma intrinsic
401 HANDLE_TARGET_OPCODE(G_FMA)
403 /// Generic FP division.
404 HANDLE_TARGET_OPCODE(G_FDIV)
406 /// Generic FP remainder.
407 HANDLE_TARGET_OPCODE(G_FREM)
409 /// Generic FP exponentiation.
410 HANDLE_TARGET_OPCODE(G_FPOW)
412 /// Generic base-e exponential of a value.
413 HANDLE_TARGET_OPCODE(G_FEXP)
415 /// Generic base-2 exponential of a value.
416 HANDLE_TARGET_OPCODE(G_FEXP2)
418 /// Floating point base-e logarithm of a value.
419 HANDLE_TARGET_OPCODE(G_FLOG)
421 /// Floating point base-2 logarithm of a value.
422 HANDLE_TARGET_OPCODE(G_FLOG2)
424 /// Generic FP negation.
425 HANDLE_TARGET_OPCODE(G_FNEG)
427 /// Generic FP extension.
428 HANDLE_TARGET_OPCODE(G_FPEXT)
430 /// Generic float to signed-int conversion
431 HANDLE_TARGET_OPCODE(G_FPTRUNC)
433 /// Generic float to signed-int conversion
434 HANDLE_TARGET_OPCODE(G_FPTOSI)
436 /// Generic float to unsigned-int conversion
437 HANDLE_TARGET_OPCODE(G_FPTOUI)
439 /// Generic signed-int to float conversion
440 HANDLE_TARGET_OPCODE(G_SITOFP)
442 /// Generic unsigned-int to float conversion
443 HANDLE_TARGET_OPCODE(G_UITOFP)
445 /// Generic FP absolute value.
446 HANDLE_TARGET_OPCODE(G_FABS)
448 /// Generic pointer offset
449 HANDLE_TARGET_OPCODE(G_GEP)
451 /// Clear the specified number of low bits in a pointer. This rounds the value
452 /// *down* to the given alignment.
453 HANDLE_TARGET_OPCODE(G_PTR_MASK)
455 /// Generic BRANCH instruction. This is an unconditional branch.
456 HANDLE_TARGET_OPCODE(G_BR)
458 /// Generic insertelement.
459 HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
461 /// Generic extractelement.
462 HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
464 /// Generic shufflevector.
465 HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
467 /// Generic byte swap.
468 HANDLE_TARGET_OPCODE(G_BSWAP)
470 /// Generic AddressSpaceCast.
471 HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST)
473 /// Generic block address
474 HANDLE_TARGET_OPCODE(G_BLOCK_ADDR)
476 // TODO: Add more generic opcodes as we move along.
478 /// Marker for the end of the generic opcode.
479 /// This is used to check if an opcode is in the range of the
481 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_BLOCK_ADDR)
483 /// BUILTIN_OP_END - This must be the last enum value in this list.
484 /// The target-specific post-isel opcode values start here.
485 HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END)