1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/IR/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 class HwMode<string FS> {
25 // A string representing subtarget features that turn on this HW mode.
26 // For example, "+feat1,-feat2" will indicate that the mode is active
27 // when "feat1" is enabled and "feat2" is disabled at the same time.
28 // Any other features are not checked.
29 // When multiple modes are used, they should be mutually exclusive,
30 // otherwise the results are unpredictable.
34 // A special mode recognized by tablegen. This mode is considered active
35 // when no other mode is active. For targets that do not use specific hw
36 // modes, this is the only mode.
37 def DefaultMode : HwMode<"">;
39 // A class used to associate objects with HW modes. It is only intended to
40 // be used as a base class, where the derived class should contain a member
41 // "Objects", which is a list of the same length as the list of modes.
42 // The n-th element on the Objects list will be associated with the n-th
43 // element on the Modes list.
44 class HwModeSelect<list<HwMode> Ms> {
45 list<HwMode> Modes = Ms;
48 // A common class that implements a counterpart of ValueType, which is
49 // dependent on a HW mode. This class inherits from ValueType itself,
50 // which makes it possible to use objects of this class where ValueType
51 // objects could be used. This is specifically applicable to selection
53 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
54 : HwModeSelect<Ms>, ValueType<0, 0> {
55 // The length of this list must be the same as the length of Ms.
56 list<ValueType> Objects = Ts;
59 // A class representing the register size, spill size and spill alignment
60 // in bits of a register.
61 class RegInfo<int RS, int SS, int SA> {
62 int RegSize = RS; // Register size in bits.
63 int SpillSize = SS; // Spill slot size in bits.
64 int SpillAlignment = SA; // Spill slot alignment in bits.
67 // The register size/alignment information, parameterized by a HW mode.
68 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
70 // The length of this list must be the same as the length of Ms.
71 list<RegInfo> Objects = Ts;
74 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
75 class SubRegIndex<int size, int offset = 0> {
76 string Namespace = "";
78 // Size - Size (in bits) of the sub-registers represented by this index.
81 // Offset - Offset of the first bit that is part of this sub-register index.
82 // Set it to -1 if the same index is used to represent sub-registers that can
83 // be at different offsets (for example when using an index to access an
84 // element in a register tuple).
87 // ComposedOf - A list of two SubRegIndex instances, [A, B].
88 // This indicates that this SubRegIndex is the result of composing A and B.
89 // See ComposedSubRegIndex.
90 list<SubRegIndex> ComposedOf = [];
92 // CoveringSubRegIndices - A list of two or more sub-register indexes that
93 // cover this sub-register.
95 // This field should normally be left blank as TableGen can infer it.
97 // TableGen automatically detects sub-registers that straddle the registers
98 // in the SubRegs field of a Register definition. For example:
100 // Q0 = dsub_0 -> D0, dsub_1 -> D1
101 // Q1 = dsub_0 -> D2, dsub_1 -> D3
102 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
103 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
105 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
106 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
107 // CoveringSubRegIndices = [dsub_1, dsub_2].
108 list<SubRegIndex> CoveringSubRegIndices = [];
111 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
112 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
113 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
114 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
115 !if(!eq(B.Offset, -1), -1,
116 !add(A.Offset, B.Offset)))> {
118 let ComposedOf = [A, B];
121 // RegAltNameIndex - The alternate name set to use for register operands of
122 // this register class when printing.
123 class RegAltNameIndex {
124 string Namespace = "";
126 def NoRegAltName : RegAltNameIndex;
128 // Register - You should define one instance of this class for each register
129 // in the target machine. String n will become the "name" of the register.
130 class Register<string n, list<string> altNames = []> {
131 string Namespace = "";
133 list<string> AltNames = altNames;
135 // Aliases - A list of registers that this register overlaps with. A read or
136 // modification of this register can potentially read or modify the aliased
138 list<Register> Aliases = [];
140 // SubRegs - A list of registers that are parts of this register. Note these
141 // are "immediate" sub-registers and the registers within the list do not
142 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
144 list<Register> SubRegs = [];
146 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
147 // to address it. Sub-sub-register indices are automatically inherited from
149 list<SubRegIndex> SubRegIndices = [];
151 // RegAltNameIndices - The alternate name indices which are valid for this
153 list<RegAltNameIndex> RegAltNameIndices = [];
155 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
156 // These values can be determined by locating the <target>.h file in the
157 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
158 // order of these names correspond to the enumeration used by gcc. A value of
159 // -1 indicates that the gcc number is undefined and -2 that register number
160 // is invalid for this mode/flavour.
161 list<int> DwarfNumbers = [];
163 // CostPerUse - Additional cost of instructions using this register compared
164 // to other registers in its class. The register allocator will try to
165 // minimize the number of instructions using a register with a CostPerUse.
166 // This is used by the x86-64 and ARM Thumb targets where some registers
167 // require larger instruction encodings.
170 // CoveredBySubRegs - When this bit is set, the value of this register is
171 // completely determined by the value of its sub-registers. For example, the
172 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
173 // covered by its sub-register AX.
174 bit CoveredBySubRegs = 0;
176 // HWEncoding - The target specific hardware encoding for this register.
177 bits<16> HWEncoding = 0;
180 // RegisterWithSubRegs - This can be used to define instances of Register which
181 // need to specify sub-registers.
182 // List "subregs" specifies which registers are sub-registers to this one. This
183 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
184 // This allows the code generator to be careful not to put two values with
185 // overlapping live ranges into registers which alias.
186 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
187 let SubRegs = subregs;
190 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
191 // of Operand's that are legal as type qualifiers in DAG patterns. This should
192 // only ever be used for defining multiclasses that are polymorphic over both
193 // RegisterClass's and other Operand's.
195 string OperandNamespace = "MCOI";
196 string DecoderMethod = "";
199 // RegisterClass - Now that all of the registers are defined, and aliases
200 // between registers are defined, specify which registers belong to which
201 // register classes. This also defines the default allocation order of
202 // registers by register allocators.
204 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
205 dag regList, RegAltNameIndex idx = NoRegAltName>
207 string Namespace = namespace;
209 // The register size/alignment information, parameterized by a HW mode.
210 RegInfoByHwMode RegInfos;
212 // RegType - Specify the list ValueType of the registers in this register
213 // class. Note that all registers in a register class must have the same
214 // ValueTypes. This is a list because some targets permit storing different
215 // types in same register, for example vector values with 128-bit total size,
216 // but different count/size of items, like SSE on x86.
218 list<ValueType> RegTypes = regTypes;
220 // Size - Specify the spill size in bits of the registers. A default value of
221 // zero lets tablgen pick an appropriate size.
224 // Alignment - Specify the alignment required of the registers when they are
225 // stored or loaded to memory.
227 int Alignment = alignment;
229 // CopyCost - This value is used to specify the cost of copying a value
230 // between two registers in this register class. The default value is one
231 // meaning it takes a single instruction to perform the copying. A negative
232 // value means copying is extremely expensive or impossible.
235 // MemberList - Specify which registers are in this class. If the
236 // allocation_order_* method are not specified, this also defines the order of
237 // allocation used by the register allocator.
239 dag MemberList = regList;
241 // AltNameIndex - The alternate register name to use when printing operands
242 // of this register class. Every register in the register class must have
243 // a valid alternate name for the given index.
244 RegAltNameIndex altNameIndex = idx;
246 // isAllocatable - Specify that the register class can be used for virtual
247 // registers and register allocation. Some register classes are only used to
248 // model instruction operand constraints, and should have isAllocatable = 0.
249 bit isAllocatable = 1;
251 // AltOrders - List of alternative allocation orders. The default order is
252 // MemberList itself, and that is good enough for most targets since the
253 // register allocators automatically remove reserved registers and move
254 // callee-saved registers to the end.
255 list<dag> AltOrders = [];
257 // AltOrderSelect - The body of a function that selects the allocation order
258 // to use in a given machine function. The code will be inserted in a
259 // function like this:
261 // static inline unsigned f(const MachineFunction &MF) { ... }
263 // The function should return 0 to select the default order defined by
264 // MemberList, 1 to select the first AltOrders entry and so on.
265 code AltOrderSelect = [{}];
267 // Specify allocation priority for register allocators using a greedy
268 // heuristic. Classes with higher priority values are assigned first. This is
269 // useful as it is sometimes beneficial to assign registers to highly
270 // constrained classes first. The value has to be in the range [0,63].
271 int AllocationPriority = 0;
273 // The diagnostic type to present when referencing this operand in a match
274 // failure error message. If this is empty, the default Match_InvalidOperand
275 // diagnostic type will be used. If this is "<name>", a Match_<name> enum
276 // value will be generated and used for this operand type. The target
277 // assembly parser is responsible for converting this into a user-facing
278 // diagnostic message.
279 string DiagnosticType = "";
281 // A diagnostic message to emit when an invalid value is provided for this
282 // register class when it is being used an an assembly operand. If this is
283 // non-empty, an anonymous diagnostic type enum value will be generated, and
284 // the assembly matcher will provide a function to map from diagnostic types
285 // to message strings.
286 string DiagnosticString = "";
289 // The memberList in a RegisterClass is a dag of set operations. TableGen
290 // evaluates these set operations and expand them into register lists. These
291 // are the most common operation, see test/TableGen/SetTheory.td for more
292 // examples of what is possible:
294 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
295 // register class, or a sub-expression. This is also the way to simply list
298 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
300 // (and GPR, CSR) - Set intersection. All registers from the first set that are
301 // also in the second set.
303 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
304 // numbered registers. Takes an optional 4th operand which is a stride to use
305 // when generating the sequence.
307 // (shl GPR, 4) - Remove the first N elements.
309 // (trunc GPR, 4) - Truncate after the first N elements.
311 // (rotl GPR, 1) - Rotate N places to the left.
313 // (rotr GPR, 1) - Rotate N places to the right.
315 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
317 // (interleave A, B, ...) - Interleave the elements from each argument list.
319 // All of these operators work on ordered sets, not lists. That means
320 // duplicates are removed from sub-expressions.
322 // Set operators. The rest is defined in TargetSelectionDAG.td.
327 // RegisterTuples - Automatically generate super-registers by forming tuples of
328 // sub-registers. This is useful for modeling register sequence constraints
329 // with pseudo-registers that are larger than the architectural registers.
331 // The sub-register lists are zipped together:
333 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
335 // Generates the same registers as:
337 // let SubRegIndices = [sube, subo] in {
338 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
339 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
342 // The generated pseudo-registers inherit super-classes and fields from their
343 // first sub-register. Most fields from the Register class are inferred, and
344 // the AsmName and Dwarf numbers are cleared.
346 // RegisterTuples instances can be used in other set operations to form
347 // register classes and so on. This is the only way of using the generated
349 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
350 // SubRegs - N lists of registers to be zipped up. Super-registers are
351 // synthesized from the first element of each SubRegs list, the second
352 // element and so on.
353 list<dag> SubRegs = Regs;
355 // SubRegIndices - N SubRegIndex instances. This provides the names of the
356 // sub-registers in the synthesized super-registers.
357 list<SubRegIndex> SubRegIndices = Indices;
361 //===----------------------------------------------------------------------===//
362 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
363 // to the register numbering used by gcc and gdb. These values are used by a
364 // debug information writer to describe where values may be located during
366 class DwarfRegNum<list<int> Numbers> {
367 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
368 // These values can be determined by locating the <target>.h file in the
369 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
370 // order of these names correspond to the enumeration used by gcc. A value of
371 // -1 indicates that the gcc number is undefined and -2 that register number
372 // is invalid for this mode/flavour.
373 list<int> DwarfNumbers = Numbers;
376 // DwarfRegAlias - This class declares that a given register uses the same dwarf
377 // numbers as another one. This is useful for making it clear that the two
378 // registers do have the same number. It also lets us build a mapping
379 // from dwarf register number to llvm register.
380 class DwarfRegAlias<Register reg> {
381 Register DwarfAlias = reg;
384 //===----------------------------------------------------------------------===//
385 // Pull in the common support for scheduling
387 include "llvm/Target/TargetSchedule.td"
389 class Predicate; // Forward def
391 //===----------------------------------------------------------------------===//
392 // Instruction set description - These classes correspond to the C++ classes in
393 // the Target/TargetInstrInfo.h file.
396 string Namespace = "";
398 dag OutOperandList; // An dag containing the MI def operand list.
399 dag InOperandList; // An dag containing the MI use operand list.
400 string AsmString = ""; // The .s format to print the instruction with.
402 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
403 // otherwise, uninitialized.
406 // The follow state will eventually be inferred automatically from the
407 // instruction pattern.
409 list<Register> Uses = []; // Default to using no non-operand registers
410 list<Register> Defs = []; // Default to modifying no non-operand registers
412 // Predicates - List of predicates which will be turned into isel matching
414 list<Predicate> Predicates = [];
416 // Size - Size of encoded instruction, or zero if the size cannot be determined
420 // DecoderNamespace - The "namespace" in which this instruction exists, on
421 // targets like ARM which multiple ISA namespaces exist.
422 string DecoderNamespace = "";
424 // Code size, for instruction selection.
425 // FIXME: What does this actually mean?
428 // Added complexity passed onto matching pattern.
429 int AddedComplexity = 0;
431 // These bits capture information about the high-level semantics of the
433 bit isReturn = 0; // Is this instruction a return instruction?
434 bit isBranch = 0; // Is this instruction a branch instruction?
435 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
436 bit isCompare = 0; // Is this instruction a comparison instruction?
437 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
438 bit isBitcast = 0; // Is this instruction a bitcast instruction?
439 bit isSelect = 0; // Is this instruction a select instruction?
440 bit isBarrier = 0; // Can control flow fall through this instruction?
441 bit isCall = 0; // Is this instruction a call instruction?
442 bit isAdd = 0; // Is this instruction an add instruction?
443 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
444 bit mayLoad = ?; // Is it possible for this inst to read memory?
445 bit mayStore = ?; // Is it possible for this inst to write memory?
446 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
447 bit isCommutable = 0; // Is this 3 operand instruction commutable?
448 bit isTerminator = 0; // Is this part of the terminator for a basic block?
449 bit isReMaterializable = 0; // Is this instruction re-materializable?
450 bit isPredicable = 0; // Is this instruction predicable?
451 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
452 bit usesCustomInserter = 0; // Pseudo instr needing special help.
453 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
454 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
455 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
456 bit isConvergent = 0; // Is this instruction convergent?
457 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
458 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
459 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
460 bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
461 // If so, make sure to override
462 // TargetInstrInfo::getRegSequenceLikeInputs.
463 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
464 // If so, won't have encoding information for
465 // the [MC]CodeEmitter stuff.
466 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
467 // If so, make sure to override
468 // TargetInstrInfo::getExtractSubregLikeInputs.
469 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
470 // If so, make sure to override
471 // TargetInstrInfo::getInsertSubregLikeInputs.
473 // Does the instruction have side effects that are not captured by any
474 // operands of the instruction or other flags?
475 bit hasSideEffects = ?;
477 // Is this instruction a "real" instruction (with a distinct machine
478 // encoding), or is it a pseudo instruction used for codegen modeling
480 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
481 // instructions can (and often do) still have encoding information
482 // associated with them. Once we've migrated all of them over to true
483 // pseudo-instructions that are lowered to real instructions prior to
484 // the printer/emitter, we can remove this attribute and just use isPseudo.
486 // The intended use is:
487 // isPseudo: Does not have encoding information and should be expanded,
488 // at the latest, during lowering to MCInst.
490 // isCodeGenOnly: Does have encoding information and can go through to the
491 // CodeEmitter unchanged, but duplicates a canonical instruction
492 // definition's encoding and should be ignored when constructing the
493 // assembler match tables.
494 bit isCodeGenOnly = 0;
496 // Is this instruction a pseudo instruction for use by the assembler parser.
497 bit isAsmParserOnly = 0;
499 // This instruction is not expected to be queried for scheduling latencies
500 // and therefore needs no scheduling information even for a complete
502 bit hasNoSchedulingInfo = 0;
504 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
506 // Scheduling information from TargetSchedule.td.
507 list<SchedReadWrite> SchedRW;
509 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
511 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
512 /// be encoded into the output machineinstr.
513 string DisableEncoding = "";
515 string PostEncoderMethod = "";
516 string DecoderMethod = "";
518 // Is the instruction decoder method able to completely determine if the
519 // given instruction is valid or not. If the TableGen definition of the
520 // instruction specifies bitpattern A??B where A and B are static bits, the
521 // hasCompleteDecoder flag says whether the decoder method fully handles the
522 // ?? space, i.e. if it is a final arbiter for the instruction validity.
523 // If not then the decoder attempts to continue decoding when the decoder
526 // This allows to handle situations where the encoding is not fully
527 // orthogonal. Example:
528 // * InstA with bitpattern 0b0000????,
529 // * InstB with bitpattern 0b000000?? but the associated decoder method
530 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
532 // The decoder tries to decode a bitpattern that matches both InstA and
533 // InstB bitpatterns first as InstB (because it is the most specific
534 // encoding). In the default case (hasCompleteDecoder = 1), when
535 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
536 // hasCompleteDecoder = 0 in InstB, the decoder is informed that
537 // DecodeInstB() is not able to determine if all possible values of ?? are
538 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
539 // decode the bitpattern as InstA too.
540 bit hasCompleteDecoder = 1;
542 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
543 bits<64> TSFlags = 0;
545 ///@name Assembler Parser Support
548 string AsmMatchConverter = "";
550 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
551 /// two-operand matcher inst-alias for a three operand instruction.
552 /// For example, the arm instruction "add r3, r3, r5" can be written
553 /// as "add r3, r5". The constraint is of the same form as a tied-operand
554 /// constraint. For example, "$Rn = $Rd".
555 string TwoOperandAliasConstraint = "";
557 /// Assembler variant name to use for this instruction. If specified then
558 /// instruction will be presented only in MatchTable for this variant. If
559 /// not specified then assembler variants will be determined based on
561 string AsmVariantName = "";
565 /// UseNamedOperandTable - If set, the operand indices of this instruction
566 /// can be queried via the getNamedOperandIdx() function which is generated
568 bit UseNamedOperandTable = 0;
571 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
572 /// Which instruction it expands to and how the operands map from the
574 class PseudoInstExpansion<dag Result> {
575 dag ResultInst = Result; // The instruction to generate.
579 /// Predicates - These are extra conditionals which are turned into instruction
580 /// selector matching code. Currently each predicate is just a string.
581 class Predicate<string cond> {
582 string CondString = cond;
584 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
585 /// matcher, this is true. Targets should set this by inheriting their
586 /// feature from the AssemblerPredicate class in addition to Predicate.
587 bit AssemblerMatcherPredicate = 0;
589 /// AssemblerCondString - Name of the subtarget feature being tested used
590 /// as alternative condition string used for assembler matcher.
591 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
592 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
593 /// It can also list multiple features separated by ",".
594 /// e.g. "ModeThumb,FeatureThumb2" is translated to
595 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
596 string AssemblerCondString = "";
598 /// PredicateName - User-level name to use for the predicate. Mainly for use
599 /// in diagnostics such as missing feature errors in the asm matcher.
600 string PredicateName = "";
602 /// Setting this to '1' indicates that the predicate must be recomputed on
603 /// every function change. Most predicates can leave this at '0'.
605 /// Ignored by SelectionDAG, it always recomputes the predicate on every use.
606 bit RecomputePerFunction = 0;
609 /// NoHonorSignDependentRounding - This predicate is true if support for
610 /// sign-dependent-rounding is not enabled.
611 def NoHonorSignDependentRounding
612 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
614 class Requires<list<Predicate> preds> {
615 list<Predicate> Predicates = preds;
618 /// ops definition - This is just a simple marker used to identify the operand
619 /// list for an instruction. outs and ins are identical both syntactically and
620 /// semantically; they are used to define def operands and use operands to
621 /// improve readibility. This should be used like this:
622 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
627 /// variable_ops definition - Mark this instruction as taking a variable number
632 /// PointerLikeRegClass - Values that are designed to have pointer width are
633 /// derived from this. TableGen treats the register class as having a symbolic
634 /// type that it doesn't know, and resolves the actual regclass to use by using
635 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
636 class PointerLikeRegClass<int Kind> {
637 int RegClassKind = Kind;
641 /// ptr_rc definition - Mark this operand as being a pointer value whose
642 /// register class is resolved dynamically via a callback to TargetInstrInfo.
643 /// FIXME: We should probably change this to a class which contain a list of
644 /// flags. But currently we have but one flag.
645 def ptr_rc : PointerLikeRegClass<0>;
647 /// unknown definition - Mark this operand as being of unknown type, causing
648 /// it to be resolved by inference in the context it is used.
650 def unknown : unknown_class;
652 /// AsmOperandClass - Representation for the kinds of operands which the target
653 /// specific parser can create and the assembly matcher may need to distinguish.
655 /// Operand classes are used to define the order in which instructions are
656 /// matched, to ensure that the instruction which gets matched for any
657 /// particular list of operands is deterministic.
659 /// The target specific parser must be able to classify a parsed operand into a
660 /// unique class which does not partially overlap with any other classes. It can
661 /// match a subset of some other class, in which case the super class field
662 /// should be defined.
663 class AsmOperandClass {
664 /// The name to use for this class, which should be usable as an enum value.
667 /// The super classes of this operand.
668 list<AsmOperandClass> SuperClasses = [];
670 /// The name of the method on the target specific operand to call to test
671 /// whether the operand is an instance of this class. If not set, this will
672 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
673 /// signature should be:
674 /// bool isFoo() const;
675 string PredicateMethod = ?;
677 /// The name of the method on the target specific operand to call to add the
678 /// target specific operand to an MCInst. If not set, this will default to
679 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
680 /// signature should be:
681 /// void addFooOperands(MCInst &Inst, unsigned N) const;
682 string RenderMethod = ?;
684 /// The name of the method on the target specific operand to call to custom
685 /// handle the operand parsing. This is useful when the operands do not relate
686 /// to immediates or registers and are very instruction specific (as flags to
687 /// set in a processor register, coprocessor number, ...).
688 string ParserMethod = ?;
690 // The diagnostic type to present when referencing this operand in a
691 // match failure error message. By default, use a generic "invalid operand"
692 // diagnostic. The target AsmParser maps these codes to text.
693 string DiagnosticType = "";
695 /// A diagnostic message to emit when an invalid value is provided for this
697 string DiagnosticString = "";
699 /// Set to 1 if this operand is optional and not always required. Typically,
700 /// the AsmParser will emit an error when it finishes parsing an
701 /// instruction if it hasn't matched all the operands yet. However, this
702 /// error will be suppressed if all of the remaining unmatched operands are
703 /// marked as IsOptional.
705 /// Optional arguments must be at the end of the operand list.
708 /// The name of the method on the target specific asm parser that returns the
709 /// default operand for this optional operand. This method is only used if
710 /// IsOptional == 1. If not set, this will default to "defaultFooOperands",
711 /// where Foo is the AsmOperandClass name. The method signature should be:
712 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const;
713 string DefaultMethod = ?;
716 def ImmAsmOperand : AsmOperandClass {
720 /// Operand Types - These provide the built-in operand types that may be used
721 /// by a target. Targets can optionally provide their own operand types as
722 /// needed, though this should not be needed for RISC targets.
723 class Operand<ValueType ty> : DAGOperand {
725 string PrintMethod = "printOperand";
726 string EncoderMethod = "";
727 bit hasCompleteDecoder = 1;
728 string OperandType = "OPERAND_UNKNOWN";
729 dag MIOperandInfo = (ops);
731 // MCOperandPredicate - Optionally, a code fragment operating on
732 // const MCOperand &MCOp, and returning a bool, to indicate if
733 // the value of MCOp is valid for the specific subclass of Operand
734 code MCOperandPredicate;
736 // ParserMatchClass - The "match class" that operands of this type fit
737 // in. Match classes are used to define the order in which instructions are
738 // match, to ensure that which instructions gets matched is deterministic.
740 // The target specific parser must be able to classify an parsed operand into
741 // a unique class, which does not partially overlap with any other classes. It
742 // can match a subset of some other class, in which case the AsmOperandClass
743 // should declare the other operand as one of its super classes.
744 AsmOperandClass ParserMatchClass = ImmAsmOperand;
747 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
749 // RegClass - The register class of the operand.
750 RegisterClass RegClass = regclass;
751 // PrintMethod - The target method to call to print register operands of
752 // this type. The method normally will just use an alt-name index to look
753 // up the name to print. Default to the generic printOperand().
754 string PrintMethod = pm;
756 // EncoderMethod - The target method name to call to encode this register
758 string EncoderMethod = "";
760 // ParserMatchClass - The "match class" that operands of this type fit
761 // in. Match classes are used to define the order in which instructions are
762 // match, to ensure that which instructions gets matched is deterministic.
764 // The target specific parser must be able to classify an parsed operand into
765 // a unique class, which does not partially overlap with any other classes. It
766 // can match a subset of some other class, in which case the AsmOperandClass
767 // should declare the other operand as one of its super classes.
768 AsmOperandClass ParserMatchClass;
770 string OperandType = "OPERAND_REGISTER";
772 // When referenced in the result of a CodeGen pattern, GlobalISel will
773 // normally copy the matched operand to the result. When this is set, it will
774 // emit a special copy that will replace zero-immediates with the specified
776 Register GIZeroRegister = ?;
779 let OperandType = "OPERAND_IMMEDIATE" in {
780 def i1imm : Operand<i1>;
781 def i8imm : Operand<i8>;
782 def i16imm : Operand<i16>;
783 def i32imm : Operand<i32>;
784 def i64imm : Operand<i64>;
786 def f32imm : Operand<f32>;
787 def f64imm : Operand<f64>;
790 // Register operands for generic instructions don't have an MVT, but do have
791 // constraints linking the operands (e.g. all operands of a G_ADD must
792 // have the same LLT).
793 class TypedOperand<string Ty> : Operand<untyped> {
794 let OperandType = Ty;
798 def type0 : TypedOperand<"OPERAND_GENERIC_0">;
799 def type1 : TypedOperand<"OPERAND_GENERIC_1">;
800 def type2 : TypedOperand<"OPERAND_GENERIC_2">;
801 def type3 : TypedOperand<"OPERAND_GENERIC_3">;
802 def type4 : TypedOperand<"OPERAND_GENERIC_4">;
803 def type5 : TypedOperand<"OPERAND_GENERIC_5">;
805 let IsPointer = 1 in {
806 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">;
807 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">;
808 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">;
809 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">;
810 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">;
811 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">;
814 /// zero_reg definition - Special node to stand for the zero register.
818 /// All operands which the MC layer classifies as predicates should inherit from
819 /// this class in some manner. This is already handled for the most commonly
820 /// used PredicateOperand, but may be useful in other circumstances.
823 /// OperandWithDefaultOps - This Operand class can be used as the parent class
824 /// for an Operand that needs to be initialized with a default value if
825 /// no value is supplied in a pattern. This class can be used to simplify the
826 /// pattern definitions for instructions that have target specific flags
827 /// encoded as immediate operands.
828 class OperandWithDefaultOps<ValueType ty, dag defaultops>
830 dag DefaultOps = defaultops;
833 /// PredicateOperand - This can be used to define a predicate operand for an
834 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
835 /// AlwaysVal specifies the value of this predicate when set to "always
837 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
838 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
839 let MIOperandInfo = OpTypes;
842 /// OptionalDefOperand - This is used to define a optional definition operand
843 /// for an instruction. DefaultOps is the register the operand represents if
844 /// none is supplied, e.g. zero_reg.
845 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
846 : OperandWithDefaultOps<ty, defaultops> {
847 let MIOperandInfo = OpTypes;
851 // InstrInfo - This class should only be instantiated once to provide parameters
852 // which are global to the target machine.
855 // Target can specify its instructions in either big or little-endian formats.
856 // For instance, while both Sparc and PowerPC are big-endian platforms, the
857 // Sparc manual specifies its instructions in the format [31..0] (big), while
858 // PowerPC specifies them using the format [0..31] (little).
859 bit isLittleEndianEncoding = 0;
861 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
862 // by default, and TableGen will infer their value from the instruction
863 // pattern when possible.
865 // Normally, TableGen will issue an error it it can't infer the value of a
866 // property that hasn't been set explicitly. When guessInstructionProperties
867 // is set, it will guess a safe value instead.
869 // This option is a temporary migration help. It will go away.
870 bit guessInstructionProperties = 1;
872 // TableGen's instruction encoder generator has support for matching operands
873 // to bit-field variables both by name and by position. While matching by
874 // name is preferred, this is currently not possible for complex operands,
875 // and some targets still reply on the positional encoding rules. When
876 // generating a decoder for such targets, the positional encoding rules must
877 // be used by the decoder generator as well.
879 // This option is temporary; it will go away once the TableGen decoder
880 // generator has better support for complex operands and targets have
881 // migrated away from using positionally encoded operands.
882 bit decodePositionallyEncodedOperands = 0;
884 // When set, this indicates that there will be no overlap between those
885 // operands that are matched by ordering (positional operands) and those
888 // This option is temporary; it will go away once the TableGen decoder
889 // generator has better support for complex operands and targets have
890 // migrated away from using positionally encoded operands.
891 bit noNamedPositionallyEncodedOperands = 0;
894 // Standard Pseudo Instructions.
895 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
896 // Only these instructions are allowed in the TargetOpcode namespace.
897 // Ensure mayLoad and mayStore have a default value, so as not to break
898 // targets that set guessInstructionProperties=0. Any local definition of
899 // mayLoad/mayStore takes precedence over these default values.
900 class StandardPseudoInstruction : Instruction {
903 let isCodeGenOnly = 1;
905 let hasNoSchedulingInfo = 1;
906 let Namespace = "TargetOpcode";
908 def PHI : StandardPseudoInstruction {
909 let OutOperandList = (outs unknown:$dst);
910 let InOperandList = (ins variable_ops);
911 let AsmString = "PHINODE";
912 let hasSideEffects = 0;
914 def INLINEASM : StandardPseudoInstruction {
915 let OutOperandList = (outs);
916 let InOperandList = (ins variable_ops);
918 let hasSideEffects = 0; // Note side effect is encoded in an operand.
920 def CFI_INSTRUCTION : StandardPseudoInstruction {
921 let OutOperandList = (outs);
922 let InOperandList = (ins i32imm:$id);
925 let hasSideEffects = 0;
926 let isNotDuplicable = 1;
928 def EH_LABEL : StandardPseudoInstruction {
929 let OutOperandList = (outs);
930 let InOperandList = (ins i32imm:$id);
933 let hasSideEffects = 0;
934 let isNotDuplicable = 1;
936 def GC_LABEL : StandardPseudoInstruction {
937 let OutOperandList = (outs);
938 let InOperandList = (ins i32imm:$id);
941 let hasSideEffects = 0;
942 let isNotDuplicable = 1;
944 def ANNOTATION_LABEL : StandardPseudoInstruction {
945 let OutOperandList = (outs);
946 let InOperandList = (ins i32imm:$id);
949 let hasSideEffects = 0;
950 let isNotDuplicable = 1;
952 def KILL : StandardPseudoInstruction {
953 let OutOperandList = (outs);
954 let InOperandList = (ins variable_ops);
956 let hasSideEffects = 0;
958 def EXTRACT_SUBREG : StandardPseudoInstruction {
959 let OutOperandList = (outs unknown:$dst);
960 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
962 let hasSideEffects = 0;
964 def INSERT_SUBREG : StandardPseudoInstruction {
965 let OutOperandList = (outs unknown:$dst);
966 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
968 let hasSideEffects = 0;
969 let Constraints = "$supersrc = $dst";
971 def IMPLICIT_DEF : StandardPseudoInstruction {
972 let OutOperandList = (outs unknown:$dst);
973 let InOperandList = (ins);
975 let hasSideEffects = 0;
976 let isReMaterializable = 1;
977 let isAsCheapAsAMove = 1;
979 def SUBREG_TO_REG : StandardPseudoInstruction {
980 let OutOperandList = (outs unknown:$dst);
981 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
983 let hasSideEffects = 0;
985 def COPY_TO_REGCLASS : StandardPseudoInstruction {
986 let OutOperandList = (outs unknown:$dst);
987 let InOperandList = (ins unknown:$src, i32imm:$regclass);
989 let hasSideEffects = 0;
990 let isAsCheapAsAMove = 1;
992 def DBG_VALUE : StandardPseudoInstruction {
993 let OutOperandList = (outs);
994 let InOperandList = (ins variable_ops);
995 let AsmString = "DBG_VALUE";
996 let hasSideEffects = 0;
998 def REG_SEQUENCE : StandardPseudoInstruction {
999 let OutOperandList = (outs unknown:$dst);
1000 let InOperandList = (ins unknown:$supersrc, variable_ops);
1002 let hasSideEffects = 0;
1003 let isAsCheapAsAMove = 1;
1005 def COPY : StandardPseudoInstruction {
1006 let OutOperandList = (outs unknown:$dst);
1007 let InOperandList = (ins unknown:$src);
1009 let hasSideEffects = 0;
1010 let isAsCheapAsAMove = 1;
1011 let hasNoSchedulingInfo = 0;
1013 def BUNDLE : StandardPseudoInstruction {
1014 let OutOperandList = (outs);
1015 let InOperandList = (ins variable_ops);
1016 let AsmString = "BUNDLE";
1017 let hasSideEffects = 1;
1019 def LIFETIME_START : StandardPseudoInstruction {
1020 let OutOperandList = (outs);
1021 let InOperandList = (ins i32imm:$id);
1022 let AsmString = "LIFETIME_START";
1023 let hasSideEffects = 0;
1025 def LIFETIME_END : StandardPseudoInstruction {
1026 let OutOperandList = (outs);
1027 let InOperandList = (ins i32imm:$id);
1028 let AsmString = "LIFETIME_END";
1029 let hasSideEffects = 0;
1031 def STACKMAP : StandardPseudoInstruction {
1032 let OutOperandList = (outs);
1033 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
1034 let hasSideEffects = 1;
1037 let usesCustomInserter = 1;
1039 def PATCHPOINT : StandardPseudoInstruction {
1040 let OutOperandList = (outs unknown:$dst);
1041 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
1042 i32imm:$nargs, i32imm:$cc, variable_ops);
1043 let hasSideEffects = 1;
1046 let usesCustomInserter = 1;
1048 def STATEPOINT : StandardPseudoInstruction {
1049 let OutOperandList = (outs);
1050 let InOperandList = (ins variable_ops);
1051 let usesCustomInserter = 1;
1054 let hasSideEffects = 1;
1057 def LOAD_STACK_GUARD : StandardPseudoInstruction {
1058 let OutOperandList = (outs ptr_rc:$dst);
1059 let InOperandList = (ins);
1061 bit isReMaterializable = 1;
1062 let hasSideEffects = 0;
1065 def LOCAL_ESCAPE : StandardPseudoInstruction {
1066 // This instruction is really just a label. It has to be part of the chain so
1067 // that it doesn't get dropped from the DAG, but it produces nothing and has
1069 let OutOperandList = (outs);
1070 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
1071 let hasSideEffects = 0;
1074 def FAULTING_OP : StandardPseudoInstruction {
1075 let OutOperandList = (outs unknown:$dst);
1076 let InOperandList = (ins variable_ops);
1077 let usesCustomInserter = 1;
1078 let hasSideEffects = 1;
1081 let isTerminator = 1;
1084 def PATCHABLE_OP : StandardPseudoInstruction {
1085 let OutOperandList = (outs unknown:$dst);
1086 let InOperandList = (ins variable_ops);
1087 let usesCustomInserter = 1;
1090 let hasSideEffects = 1;
1092 def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction {
1093 let OutOperandList = (outs);
1094 let InOperandList = (ins);
1095 let AsmString = "# XRay Function Enter.";
1096 let usesCustomInserter = 1;
1097 let hasSideEffects = 0;
1099 def PATCHABLE_RET : StandardPseudoInstruction {
1100 let OutOperandList = (outs unknown:$dst);
1101 let InOperandList = (ins variable_ops);
1102 let AsmString = "# XRay Function Patchable RET.";
1103 let usesCustomInserter = 1;
1104 let hasSideEffects = 1;
1105 let isTerminator = 1;
1108 def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction {
1109 let OutOperandList = (outs);
1110 let InOperandList = (ins);
1111 let AsmString = "# XRay Function Exit.";
1112 let usesCustomInserter = 1;
1113 let hasSideEffects = 0; // FIXME: is this correct?
1114 let isReturn = 0; // Original return instruction will follow
1116 def PATCHABLE_TAIL_CALL : StandardPseudoInstruction {
1117 let OutOperandList = (outs unknown:$dst);
1118 let InOperandList = (ins variable_ops);
1119 let AsmString = "# XRay Tail Call Exit.";
1120 let usesCustomInserter = 1;
1121 let hasSideEffects = 1;
1124 def PATCHABLE_EVENT_CALL : StandardPseudoInstruction {
1125 let OutOperandList = (outs);
1126 let InOperandList = (ins ptr_rc:$event, i8imm:$size);
1127 let AsmString = "# XRay Custom Event Log.";
1128 let usesCustomInserter = 1;
1132 let hasSideEffects = 1;
1134 def FENTRY_CALL : StandardPseudoInstruction {
1135 let OutOperandList = (outs unknown:$dst);
1136 let InOperandList = (ins variable_ops);
1137 let AsmString = "# FEntry call";
1138 let usesCustomInserter = 1;
1141 let hasSideEffects = 1;
1144 // Generic opcodes used in GlobalISel.
1145 include "llvm/Target/GenericOpcodes.td"
1147 //===----------------------------------------------------------------------===//
1148 // AsmParser - This class can be implemented by targets that wish to implement
1151 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
1152 // syntax on X86 for example).
1155 // AsmParserClassName - This specifies the suffix to use for the asmparser
1156 // class. Generated AsmParser classes are always prefixed with the target
1158 string AsmParserClassName = "AsmParser";
1160 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
1161 // function of the AsmParser class to call on every matched instruction.
1162 // This can be used to perform target specific instruction post-processing.
1163 string AsmParserInstCleanup = "";
1165 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
1166 // written register name matcher
1167 bit ShouldEmitMatchRegisterName = 1;
1169 // Set to true if the target needs a generated 'alternative register name'
1172 // This generates a function which can be used to lookup registers from
1173 // their aliases. This function will fail when called on targets where
1174 // several registers share the same alias (i.e. not a 1:1 mapping).
1175 bit ShouldEmitMatchRegisterAltName = 0;
1177 // Set to true if MatchRegisterName and MatchRegisterAltName functions
1178 // should be generated even if there are duplicate register names. The
1179 // target is responsible for coercing aliased registers as necessary
1180 // (e.g. in validateTargetOperandClass), and there are no guarantees about
1181 // which numeric register identifier will be returned in the case of
1182 // multiple matches.
1183 bit AllowDuplicateRegisterNames = 0;
1185 // HasMnemonicFirst - Set to false if target instructions don't always
1186 // start with a mnemonic as the first token.
1187 bit HasMnemonicFirst = 1;
1189 // ReportMultipleNearMisses -
1190 // When 0, the assembly matcher reports an error for one encoding or operand
1191 // that did not match the parsed instruction.
1192 // When 1, the assmebly matcher returns a list of encodings that were close
1193 // to matching the parsed instruction, so to allow more detailed error
1195 bit ReportMultipleNearMisses = 0;
1197 def DefaultAsmParser : AsmParser;
1199 //===----------------------------------------------------------------------===//
1200 // AsmParserVariant - Subtargets can have multiple different assembly parsers
1201 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
1202 // implemented by targets to describe such variants.
1204 class AsmParserVariant {
1205 // Variant - AsmParsers can be of multiple different variants. Variants are
1206 // used to support targets that need to parser multiple formats for the
1207 // assembly language.
1210 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
1213 // CommentDelimiter - If given, the delimiter string used to recognize
1214 // comments which are hard coded in the .td assembler strings for individual
1216 string CommentDelimiter = "";
1218 // RegisterPrefix - If given, the token prefix which indicates a register
1219 // token. This is used by the matcher to automatically recognize hard coded
1220 // register tokens as constrained registers, instead of tokens, for the
1221 // purposes of matching.
1222 string RegisterPrefix = "";
1224 // TokenizingCharacters - Characters that are standalone tokens
1225 string TokenizingCharacters = "[]*!";
1227 // SeparatorCharacters - Characters that are not tokens
1228 string SeparatorCharacters = " \t,";
1230 // BreakCharacters - Characters that start new identifiers
1231 string BreakCharacters = "";
1233 def DefaultAsmParserVariant : AsmParserVariant;
1235 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
1236 /// matches instructions and aliases.
1237 class AssemblerPredicate<string cond, string name = ""> {
1238 bit AssemblerMatcherPredicate = 1;
1239 string AssemblerCondString = cond;
1240 string PredicateName = name;
1243 /// TokenAlias - This class allows targets to define assembler token
1244 /// operand aliases. That is, a token literal operand which is equivalent
1245 /// to another, canonical, token literal. For example, ARM allows:
1246 /// vmov.u32 s4, #0 -> vmov.i32, #0
1247 /// 'u32' is a more specific designator for the 32-bit integer type specifier
1248 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
1249 /// def : TokenAlias<".u32", ".i32">;
1251 /// This works by marking the match class of 'From' as a subclass of the
1252 /// match class of 'To'.
1253 class TokenAlias<string From, string To> {
1254 string FromToken = From;
1255 string ToToken = To;
1258 /// MnemonicAlias - This class allows targets to define assembler mnemonic
1259 /// aliases. This should be used when all forms of one mnemonic are accepted
1260 /// with a different mnemonic. For example, X86 allows:
1261 /// sal %al, 1 -> shl %al, 1
1262 /// sal %ax, %cl -> shl %ax, %cl
1263 /// sal %eax, %cl -> shl %eax, %cl
1264 /// etc. Though "sal" is accepted with many forms, all of them are directly
1265 /// translated to a shl, so it can be handled with (in the case of X86, it
1266 /// actually has one for each suffix as well):
1267 /// def : MnemonicAlias<"sal", "shl">;
1269 /// Mnemonic aliases are mapped before any other translation in the match phase,
1270 /// and do allow Requires predicates, e.g.:
1272 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1273 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1275 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
1277 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
1279 /// If no variant (e.g., "att" or "intel") is specified then the alias is
1280 /// applied unconditionally.
1281 class MnemonicAlias<string From, string To, string VariantName = ""> {
1282 string FromMnemonic = From;
1283 string ToMnemonic = To;
1284 string AsmVariantName = VariantName;
1286 // Predicates - Predicates that must be true for this remapping to happen.
1287 list<Predicate> Predicates = [];
1290 /// InstAlias - This defines an alternate assembly syntax that is allowed to
1291 /// match an instruction that has a different (more canonical) assembly
1293 class InstAlias<string Asm, dag Result, int Emit = 1> {
1294 string AsmString = Asm; // The .s format to match the instruction with.
1295 dag ResultInst = Result; // The MCInst to generate.
1297 // This determines which order the InstPrinter detects aliases for
1298 // printing. A larger value makes the alias more likely to be
1299 // emitted. The Instruction's own definition is notionally 0.5, so 0
1300 // disables printing and 1 enables it if there are no conflicting aliases.
1301 int EmitPriority = Emit;
1303 // Predicates - Predicates that must be true for this to match.
1304 list<Predicate> Predicates = [];
1306 // If the instruction specified in Result has defined an AsmMatchConverter
1307 // then setting this to 1 will cause the alias to use the AsmMatchConverter
1308 // function when converting the OperandVector into an MCInst instead of the
1309 // function that is generated by the dag Result.
1310 // Setting this to 0 will cause the alias to ignore the Result instruction's
1311 // defined AsmMatchConverter and instead use the function generated by the
1313 bit UseInstAsmMatchConverter = 1;
1315 // Assembler variant name to use for this alias. If not specified then
1316 // assembler variants will be determined based on AsmString
1317 string AsmVariantName = "";
1320 //===----------------------------------------------------------------------===//
1321 // AsmWriter - This class can be implemented by targets that need to customize
1322 // the format of the .s file writer.
1324 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1325 // on X86 for example).
1328 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
1329 // class. Generated AsmWriter classes are always prefixed with the target
1331 string AsmWriterClassName = "InstPrinter";
1333 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to
1334 // the various print methods.
1335 // FIXME: Remove after all ports are updated.
1336 int PassSubtarget = 0;
1338 // Variant - AsmWriters can be of multiple different variants. Variants are
1339 // used to support targets that need to emit assembly code in ways that are
1340 // mostly the same for different targets, but have minor differences in
1341 // syntax. If the asmstring contains {|} characters in them, this integer
1342 // will specify which alternative to use. For example "{x|y|z}" with Variant
1343 // == 1, will expand to "y".
1346 def DefaultAsmWriter : AsmWriter;
1349 //===----------------------------------------------------------------------===//
1350 // Target - This class contains the "global" target information
1353 // InstructionSet - Instruction set description for this target.
1354 InstrInfo InstructionSet;
1356 // AssemblyParsers - The AsmParser instances available for this target.
1357 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
1359 /// AssemblyParserVariants - The AsmParserVariant instances available for
1361 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
1363 // AssemblyWriters - The AsmWriter instances available for this target.
1364 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
1367 //===----------------------------------------------------------------------===//
1368 // SubtargetFeature - A characteristic of the chip set.
1370 class SubtargetFeature<string n, string a, string v, string d,
1371 list<SubtargetFeature> i = []> {
1372 // Name - Feature name. Used by command line (-mattr=) to determine the
1373 // appropriate target chip.
1377 // Attribute - Attribute to be set by feature.
1379 string Attribute = a;
1381 // Value - Value the attribute to be set to by feature.
1385 // Desc - Feature description. Used by command line (-mattr=) to display help
1390 // Implies - Features that this feature implies are present. If one of those
1391 // features isn't set, then this one shouldn't be set either.
1393 list<SubtargetFeature> Implies = i;
1396 /// Specifies a Subtarget feature that this instruction is deprecated on.
1397 class Deprecated<SubtargetFeature dep> {
1398 SubtargetFeature DeprecatedFeatureMask = dep;
1401 /// A custom predicate used to determine if an instruction is
1402 /// deprecated or not.
1403 class ComplexDeprecationPredicate<string dep> {
1404 string ComplexDeprecationPredicate = dep;
1407 //===----------------------------------------------------------------------===//
1408 // Processor chip sets - These values represent each of the chip sets supported
1409 // by the scheduler. Each Processor definition requires corresponding
1410 // instruction itineraries.
1412 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1413 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1414 // appropriate target chip.
1418 // SchedModel - The machine model for scheduling and instruction cost.
1420 SchedMachineModel SchedModel = NoSchedModel;
1422 // ProcItin - The scheduling information for the target processor.
1424 ProcessorItineraries ProcItin = pi;
1426 // Features - list of
1427 list<SubtargetFeature> Features = f;
1430 // ProcessorModel allows subtargets to specify the more general
1431 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1432 // gradually move to this newer form.
1434 // Although this class always passes NoItineraries to the Processor
1435 // class, the SchedMachineModel may still define valid Itineraries.
1436 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1437 : Processor<n, NoItineraries, f> {
1441 //===----------------------------------------------------------------------===//
1442 // InstrMapping - This class is used to create mapping tables to relate
1443 // instructions with each other based on the values specified in RowFields,
1444 // ColFields, KeyCol and ValueCols.
1446 class InstrMapping {
1447 // FilterClass - Used to limit search space only to the instructions that
1448 // define the relationship modeled by this InstrMapping record.
1451 // RowFields - List of fields/attributes that should be same for all the
1452 // instructions in a row of the relation table. Think of this as a set of
1453 // properties shared by all the instructions related by this relationship
1454 // model and is used to categorize instructions into subgroups. For instance,
1455 // if we want to define a relation that maps 'Add' instruction to its
1456 // predicated forms, we can define RowFields like this:
1458 // let RowFields = BaseOp
1459 // All add instruction predicated/non-predicated will have to set their BaseOp
1460 // to the same value.
1462 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1463 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1464 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1465 list<string> RowFields = [];
1467 // List of fields/attributes that are same for all the instructions
1468 // in a column of the relation table.
1469 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1470 // based on the 'predSense' values. All the instruction in a specific
1471 // column have the same value and it is fixed for the column according
1472 // to the values set in 'ValueCols'.
1473 list<string> ColFields = [];
1475 // Values for the fields/attributes listed in 'ColFields'.
1476 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1477 // that models this relation) should be non-predicated.
1478 // In the example above, 'Add' is the key instruction.
1479 list<string> KeyCol = [];
1481 // List of values for the fields/attributes listed in 'ColFields', one for
1482 // each column in the relation table.
1484 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1485 // table. First column requires all the instructions to have predSense
1486 // set to 'true' and second column requires it to be 'false'.
1487 list<list<string> > ValueCols = [];
1490 //===----------------------------------------------------------------------===//
1491 // Pull in the common support for calling conventions.
1493 include "llvm/Target/TargetCallingConv.td"
1495 //===----------------------------------------------------------------------===//
1496 // Pull in the common support for DAG isel generation.
1498 include "llvm/Target/TargetSelectionDAG.td"
1500 //===----------------------------------------------------------------------===//
1501 // Pull in the common support for Global ISel register bank info generation.
1503 include "llvm/Target/GlobalISel/RegisterBank.td"
1505 //===----------------------------------------------------------------------===//
1506 // Pull in the common support for DAG isel generation.
1508 include "llvm/Target/GlobalISel/Target.td"
1510 //===----------------------------------------------------------------------===//
1511 // Pull in the common support for the Global ISel DAG-based selector generation.
1513 include "llvm/Target/GlobalISel/SelectionDAGCompat.td"