1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/IR/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 class HwMode<string FS> {
25 // A string representing subtarget features that turn on this HW mode.
26 // For example, "+feat1,-feat2" will indicate that the mode is active
27 // when "feat1" is enabled and "feat2" is disabled at the same time.
28 // Any other features are not checked.
29 // When multiple modes are used, they should be mutually exclusive,
30 // otherwise the results are unpredictable.
34 // A special mode recognized by tablegen. This mode is considered active
35 // when no other mode is active. For targets that do not use specific hw
36 // modes, this is the only mode.
37 def DefaultMode : HwMode<"">;
39 // A class used to associate objects with HW modes. It is only intended to
40 // be used as a base class, where the derived class should contain a member
41 // "Objects", which is a list of the same length as the list of modes.
42 // The n-th element on the Objects list will be associated with the n-th
43 // element on the Modes list.
44 class HwModeSelect<list<HwMode> Ms> {
45 list<HwMode> Modes = Ms;
48 // A common class that implements a counterpart of ValueType, which is
49 // dependent on a HW mode. This class inherits from ValueType itself,
50 // which makes it possible to use objects of this class where ValueType
51 // objects could be used. This is specifically applicable to selection
53 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
54 : HwModeSelect<Ms>, ValueType<0, 0> {
55 // The length of this list must be the same as the length of Ms.
56 list<ValueType> Objects = Ts;
59 // A class representing the register size, spill size and spill alignment
60 // in bits of a register.
61 class RegInfo<int RS, int SS, int SA> {
62 int RegSize = RS; // Register size in bits.
63 int SpillSize = SS; // Spill slot size in bits.
64 int SpillAlignment = SA; // Spill slot alignment in bits.
67 // The register size/alignment information, parameterized by a HW mode.
68 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
70 // The length of this list must be the same as the length of Ms.
71 list<RegInfo> Objects = Ts;
74 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
75 class SubRegIndex<int size, int offset = 0> {
76 string Namespace = "";
78 // Size - Size (in bits) of the sub-registers represented by this index.
81 // Offset - Offset of the first bit that is part of this sub-register index.
82 // Set it to -1 if the same index is used to represent sub-registers that can
83 // be at different offsets (for example when using an index to access an
84 // element in a register tuple).
87 // ComposedOf - A list of two SubRegIndex instances, [A, B].
88 // This indicates that this SubRegIndex is the result of composing A and B.
89 // See ComposedSubRegIndex.
90 list<SubRegIndex> ComposedOf = [];
92 // CoveringSubRegIndices - A list of two or more sub-register indexes that
93 // cover this sub-register.
95 // This field should normally be left blank as TableGen can infer it.
97 // TableGen automatically detects sub-registers that straddle the registers
98 // in the SubRegs field of a Register definition. For example:
100 // Q0 = dsub_0 -> D0, dsub_1 -> D1
101 // Q1 = dsub_0 -> D2, dsub_1 -> D3
102 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
103 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
105 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
106 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
107 // CoveringSubRegIndices = [dsub_1, dsub_2].
108 list<SubRegIndex> CoveringSubRegIndices = [];
111 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
112 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
113 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
114 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
115 !if(!eq(B.Offset, -1), -1,
116 !add(A.Offset, B.Offset)))> {
118 let ComposedOf = [A, B];
121 // RegAltNameIndex - The alternate name set to use for register operands of
122 // this register class when printing.
123 class RegAltNameIndex {
124 string Namespace = "";
126 def NoRegAltName : RegAltNameIndex;
128 // Register - You should define one instance of this class for each register
129 // in the target machine. String n will become the "name" of the register.
130 class Register<string n, list<string> altNames = []> {
131 string Namespace = "";
133 list<string> AltNames = altNames;
135 // Aliases - A list of registers that this register overlaps with. A read or
136 // modification of this register can potentially read or modify the aliased
138 list<Register> Aliases = [];
140 // SubRegs - A list of registers that are parts of this register. Note these
141 // are "immediate" sub-registers and the registers within the list do not
142 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
144 list<Register> SubRegs = [];
146 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
147 // to address it. Sub-sub-register indices are automatically inherited from
149 list<SubRegIndex> SubRegIndices = [];
151 // RegAltNameIndices - The alternate name indices which are valid for this
153 list<RegAltNameIndex> RegAltNameIndices = [];
155 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
156 // These values can be determined by locating the <target>.h file in the
157 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
158 // order of these names correspond to the enumeration used by gcc. A value of
159 // -1 indicates that the gcc number is undefined and -2 that register number
160 // is invalid for this mode/flavour.
161 list<int> DwarfNumbers = [];
163 // CostPerUse - Additional cost of instructions using this register compared
164 // to other registers in its class. The register allocator will try to
165 // minimize the number of instructions using a register with a CostPerUse.
166 // This is used by the x86-64 and ARM Thumb targets where some registers
167 // require larger instruction encodings.
170 // CoveredBySubRegs - When this bit is set, the value of this register is
171 // completely determined by the value of its sub-registers. For example, the
172 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
173 // covered by its sub-register AX.
174 bit CoveredBySubRegs = 0;
176 // HWEncoding - The target specific hardware encoding for this register.
177 bits<16> HWEncoding = 0;
179 bit isArtificial = 0;
182 // RegisterWithSubRegs - This can be used to define instances of Register which
183 // need to specify sub-registers.
184 // List "subregs" specifies which registers are sub-registers to this one. This
185 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
186 // This allows the code generator to be careful not to put two values with
187 // overlapping live ranges into registers which alias.
188 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
189 let SubRegs = subregs;
192 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
193 // of Operand's that are legal as type qualifiers in DAG patterns. This should
194 // only ever be used for defining multiclasses that are polymorphic over both
195 // RegisterClass's and other Operand's.
197 string OperandNamespace = "MCOI";
198 string DecoderMethod = "";
201 // RegisterClass - Now that all of the registers are defined, and aliases
202 // between registers are defined, specify which registers belong to which
203 // register classes. This also defines the default allocation order of
204 // registers by register allocators.
206 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
207 dag regList, RegAltNameIndex idx = NoRegAltName>
209 string Namespace = namespace;
211 // The register size/alignment information, parameterized by a HW mode.
212 RegInfoByHwMode RegInfos;
214 // RegType - Specify the list ValueType of the registers in this register
215 // class. Note that all registers in a register class must have the same
216 // ValueTypes. This is a list because some targets permit storing different
217 // types in same register, for example vector values with 128-bit total size,
218 // but different count/size of items, like SSE on x86.
220 list<ValueType> RegTypes = regTypes;
222 // Size - Specify the spill size in bits of the registers. A default value of
223 // zero lets tablgen pick an appropriate size.
226 // Alignment - Specify the alignment required of the registers when they are
227 // stored or loaded to memory.
229 int Alignment = alignment;
231 // CopyCost - This value is used to specify the cost of copying a value
232 // between two registers in this register class. The default value is one
233 // meaning it takes a single instruction to perform the copying. A negative
234 // value means copying is extremely expensive or impossible.
237 // MemberList - Specify which registers are in this class. If the
238 // allocation_order_* method are not specified, this also defines the order of
239 // allocation used by the register allocator.
241 dag MemberList = regList;
243 // AltNameIndex - The alternate register name to use when printing operands
244 // of this register class. Every register in the register class must have
245 // a valid alternate name for the given index.
246 RegAltNameIndex altNameIndex = idx;
248 // isAllocatable - Specify that the register class can be used for virtual
249 // registers and register allocation. Some register classes are only used to
250 // model instruction operand constraints, and should have isAllocatable = 0.
251 bit isAllocatable = 1;
253 // AltOrders - List of alternative allocation orders. The default order is
254 // MemberList itself, and that is good enough for most targets since the
255 // register allocators automatically remove reserved registers and move
256 // callee-saved registers to the end.
257 list<dag> AltOrders = [];
259 // AltOrderSelect - The body of a function that selects the allocation order
260 // to use in a given machine function. The code will be inserted in a
261 // function like this:
263 // static inline unsigned f(const MachineFunction &MF) { ... }
265 // The function should return 0 to select the default order defined by
266 // MemberList, 1 to select the first AltOrders entry and so on.
267 code AltOrderSelect = [{}];
269 // Specify allocation priority for register allocators using a greedy
270 // heuristic. Classes with higher priority values are assigned first. This is
271 // useful as it is sometimes beneficial to assign registers to highly
272 // constrained classes first. The value has to be in the range [0,63].
273 int AllocationPriority = 0;
275 // The diagnostic type to present when referencing this operand in a match
276 // failure error message. If this is empty, the default Match_InvalidOperand
277 // diagnostic type will be used. If this is "<name>", a Match_<name> enum
278 // value will be generated and used for this operand type. The target
279 // assembly parser is responsible for converting this into a user-facing
280 // diagnostic message.
281 string DiagnosticType = "";
283 // A diagnostic message to emit when an invalid value is provided for this
284 // register class when it is being used an an assembly operand. If this is
285 // non-empty, an anonymous diagnostic type enum value will be generated, and
286 // the assembly matcher will provide a function to map from diagnostic types
287 // to message strings.
288 string DiagnosticString = "";
291 // The memberList in a RegisterClass is a dag of set operations. TableGen
292 // evaluates these set operations and expand them into register lists. These
293 // are the most common operation, see test/TableGen/SetTheory.td for more
294 // examples of what is possible:
296 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
297 // register class, or a sub-expression. This is also the way to simply list
300 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
302 // (and GPR, CSR) - Set intersection. All registers from the first set that are
303 // also in the second set.
305 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
306 // numbered registers. Takes an optional 4th operand which is a stride to use
307 // when generating the sequence.
309 // (shl GPR, 4) - Remove the first N elements.
311 // (trunc GPR, 4) - Truncate after the first N elements.
313 // (rotl GPR, 1) - Rotate N places to the left.
315 // (rotr GPR, 1) - Rotate N places to the right.
317 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
319 // (interleave A, B, ...) - Interleave the elements from each argument list.
321 // All of these operators work on ordered sets, not lists. That means
322 // duplicates are removed from sub-expressions.
324 // Set operators. The rest is defined in TargetSelectionDAG.td.
329 // RegisterTuples - Automatically generate super-registers by forming tuples of
330 // sub-registers. This is useful for modeling register sequence constraints
331 // with pseudo-registers that are larger than the architectural registers.
333 // The sub-register lists are zipped together:
335 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
337 // Generates the same registers as:
339 // let SubRegIndices = [sube, subo] in {
340 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
341 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
344 // The generated pseudo-registers inherit super-classes and fields from their
345 // first sub-register. Most fields from the Register class are inferred, and
346 // the AsmName and Dwarf numbers are cleared.
348 // RegisterTuples instances can be used in other set operations to form
349 // register classes and so on. This is the only way of using the generated
351 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
352 // SubRegs - N lists of registers to be zipped up. Super-registers are
353 // synthesized from the first element of each SubRegs list, the second
354 // element and so on.
355 list<dag> SubRegs = Regs;
357 // SubRegIndices - N SubRegIndex instances. This provides the names of the
358 // sub-registers in the synthesized super-registers.
359 list<SubRegIndex> SubRegIndices = Indices;
363 //===----------------------------------------------------------------------===//
364 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
365 // to the register numbering used by gcc and gdb. These values are used by a
366 // debug information writer to describe where values may be located during
368 class DwarfRegNum<list<int> Numbers> {
369 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
370 // These values can be determined by locating the <target>.h file in the
371 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
372 // order of these names correspond to the enumeration used by gcc. A value of
373 // -1 indicates that the gcc number is undefined and -2 that register number
374 // is invalid for this mode/flavour.
375 list<int> DwarfNumbers = Numbers;
378 // DwarfRegAlias - This class declares that a given register uses the same dwarf
379 // numbers as another one. This is useful for making it clear that the two
380 // registers do have the same number. It also lets us build a mapping
381 // from dwarf register number to llvm register.
382 class DwarfRegAlias<Register reg> {
383 Register DwarfAlias = reg;
386 //===----------------------------------------------------------------------===//
387 // Pull in the common support for MCPredicate (portable scheduling predicates).
389 include "llvm/Target/TargetInstrPredicate.td"
391 //===----------------------------------------------------------------------===//
392 // Pull in the common support for scheduling
394 include "llvm/Target/TargetSchedule.td"
396 class Predicate; // Forward def
398 //===----------------------------------------------------------------------===//
399 // Instruction set description - These classes correspond to the C++ classes in
400 // the Target/TargetInstrInfo.h file.
403 string Namespace = "";
405 dag OutOperandList; // An dag containing the MI def operand list.
406 dag InOperandList; // An dag containing the MI use operand list.
407 string AsmString = ""; // The .s format to print the instruction with.
409 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
410 // otherwise, uninitialized.
413 // The follow state will eventually be inferred automatically from the
414 // instruction pattern.
416 list<Register> Uses = []; // Default to using no non-operand registers
417 list<Register> Defs = []; // Default to modifying no non-operand registers
419 // Predicates - List of predicates which will be turned into isel matching
421 list<Predicate> Predicates = [];
423 // Size - Size of encoded instruction, or zero if the size cannot be determined
427 // DecoderNamespace - The "namespace" in which this instruction exists, on
428 // targets like ARM which multiple ISA namespaces exist.
429 string DecoderNamespace = "";
431 // Code size, for instruction selection.
432 // FIXME: What does this actually mean?
435 // Added complexity passed onto matching pattern.
436 int AddedComplexity = 0;
438 // These bits capture information about the high-level semantics of the
440 bit isReturn = 0; // Is this instruction a return instruction?
441 bit isBranch = 0; // Is this instruction a branch instruction?
442 bit isEHScopeReturn = 0; // Does this instruction end an EH scope?
443 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
444 bit isCompare = 0; // Is this instruction a comparison instruction?
445 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
446 bit isMoveReg = 0; // Is this instruction a move register instruction?
447 bit isBitcast = 0; // Is this instruction a bitcast instruction?
448 bit isSelect = 0; // Is this instruction a select instruction?
449 bit isBarrier = 0; // Can control flow fall through this instruction?
450 bit isCall = 0; // Is this instruction a call instruction?
451 bit isAdd = 0; // Is this instruction an add instruction?
452 bit isTrap = 0; // Is this instruction a trap instruction?
453 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
454 bit mayLoad = ?; // Is it possible for this inst to read memory?
455 bit mayStore = ?; // Is it possible for this inst to write memory?
456 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
457 bit isCommutable = 0; // Is this 3 operand instruction commutable?
458 bit isTerminator = 0; // Is this part of the terminator for a basic block?
459 bit isReMaterializable = 0; // Is this instruction re-materializable?
460 bit isPredicable = 0; // Is this instruction predicable?
461 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
462 bit usesCustomInserter = 0; // Pseudo instr needing special help.
463 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
464 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
465 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
466 bit isConvergent = 0; // Is this instruction convergent?
467 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
468 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
469 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
470 bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
471 // If so, make sure to override
472 // TargetInstrInfo::getRegSequenceLikeInputs.
473 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
474 // If so, won't have encoding information for
475 // the [MC]CodeEmitter stuff.
476 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
477 // If so, make sure to override
478 // TargetInstrInfo::getExtractSubregLikeInputs.
479 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
480 // If so, make sure to override
481 // TargetInstrInfo::getInsertSubregLikeInputs.
482 bit variadicOpsAreDefs = 0; // Are variadic operands definitions?
484 // Does the instruction have side effects that are not captured by any
485 // operands of the instruction or other flags?
486 bit hasSideEffects = ?;
488 // Is this instruction a "real" instruction (with a distinct machine
489 // encoding), or is it a pseudo instruction used for codegen modeling
491 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
492 // instructions can (and often do) still have encoding information
493 // associated with them. Once we've migrated all of them over to true
494 // pseudo-instructions that are lowered to real instructions prior to
495 // the printer/emitter, we can remove this attribute and just use isPseudo.
497 // The intended use is:
498 // isPseudo: Does not have encoding information and should be expanded,
499 // at the latest, during lowering to MCInst.
501 // isCodeGenOnly: Does have encoding information and can go through to the
502 // CodeEmitter unchanged, but duplicates a canonical instruction
503 // definition's encoding and should be ignored when constructing the
504 // assembler match tables.
505 bit isCodeGenOnly = 0;
507 // Is this instruction a pseudo instruction for use by the assembler parser.
508 bit isAsmParserOnly = 0;
510 // This instruction is not expected to be queried for scheduling latencies
511 // and therefore needs no scheduling information even for a complete
513 bit hasNoSchedulingInfo = 0;
515 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
517 // Scheduling information from TargetSchedule.td.
518 list<SchedReadWrite> SchedRW;
520 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
522 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
523 /// be encoded into the output machineinstr.
524 string DisableEncoding = "";
526 string PostEncoderMethod = "";
527 string DecoderMethod = "";
529 // Is the instruction decoder method able to completely determine if the
530 // given instruction is valid or not. If the TableGen definition of the
531 // instruction specifies bitpattern A??B where A and B are static bits, the
532 // hasCompleteDecoder flag says whether the decoder method fully handles the
533 // ?? space, i.e. if it is a final arbiter for the instruction validity.
534 // If not then the decoder attempts to continue decoding when the decoder
537 // This allows to handle situations where the encoding is not fully
538 // orthogonal. Example:
539 // * InstA with bitpattern 0b0000????,
540 // * InstB with bitpattern 0b000000?? but the associated decoder method
541 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
543 // The decoder tries to decode a bitpattern that matches both InstA and
544 // InstB bitpatterns first as InstB (because it is the most specific
545 // encoding). In the default case (hasCompleteDecoder = 1), when
546 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
547 // hasCompleteDecoder = 0 in InstB, the decoder is informed that
548 // DecodeInstB() is not able to determine if all possible values of ?? are
549 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
550 // decode the bitpattern as InstA too.
551 bit hasCompleteDecoder = 1;
553 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
554 bits<64> TSFlags = 0;
556 ///@name Assembler Parser Support
559 string AsmMatchConverter = "";
561 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
562 /// two-operand matcher inst-alias for a three operand instruction.
563 /// For example, the arm instruction "add r3, r3, r5" can be written
564 /// as "add r3, r5". The constraint is of the same form as a tied-operand
565 /// constraint. For example, "$Rn = $Rd".
566 string TwoOperandAliasConstraint = "";
568 /// Assembler variant name to use for this instruction. If specified then
569 /// instruction will be presented only in MatchTable for this variant. If
570 /// not specified then assembler variants will be determined based on
572 string AsmVariantName = "";
576 /// UseNamedOperandTable - If set, the operand indices of this instruction
577 /// can be queried via the getNamedOperandIdx() function which is generated
579 bit UseNamedOperandTable = 0;
581 /// Should FastISel ignore this instruction. For certain ISAs, they have
582 /// instructions which map to the same ISD Opcode, value type operands and
583 /// instruction selection predicates. FastISel cannot handle such cases, but
584 /// SelectionDAG can.
585 bit FastISelShouldIgnore = 0;
588 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
589 /// Which instruction it expands to and how the operands map from the
591 class PseudoInstExpansion<dag Result> {
592 dag ResultInst = Result; // The instruction to generate.
596 /// Predicates - These are extra conditionals which are turned into instruction
597 /// selector matching code. Currently each predicate is just a string.
598 class Predicate<string cond> {
599 string CondString = cond;
601 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
602 /// matcher, this is true. Targets should set this by inheriting their
603 /// feature from the AssemblerPredicate class in addition to Predicate.
604 bit AssemblerMatcherPredicate = 0;
606 /// AssemblerCondString - Name of the subtarget feature being tested used
607 /// as alternative condition string used for assembler matcher.
608 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
609 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
610 /// It can also list multiple features separated by ",".
611 /// e.g. "ModeThumb,FeatureThumb2" is translated to
612 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
613 string AssemblerCondString = "";
615 /// PredicateName - User-level name to use for the predicate. Mainly for use
616 /// in diagnostics such as missing feature errors in the asm matcher.
617 string PredicateName = "";
619 /// Setting this to '1' indicates that the predicate must be recomputed on
620 /// every function change. Most predicates can leave this at '0'.
622 /// Ignored by SelectionDAG, it always recomputes the predicate on every use.
623 bit RecomputePerFunction = 0;
626 /// NoHonorSignDependentRounding - This predicate is true if support for
627 /// sign-dependent-rounding is not enabled.
628 def NoHonorSignDependentRounding
629 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
631 class Requires<list<Predicate> preds> {
632 list<Predicate> Predicates = preds;
635 /// ops definition - This is just a simple marker used to identify the operand
636 /// list for an instruction. outs and ins are identical both syntactically and
637 /// semantically; they are used to define def operands and use operands to
638 /// improve readibility. This should be used like this:
639 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
644 /// variable_ops definition - Mark this instruction as taking a variable number
649 /// PointerLikeRegClass - Values that are designed to have pointer width are
650 /// derived from this. TableGen treats the register class as having a symbolic
651 /// type that it doesn't know, and resolves the actual regclass to use by using
652 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
653 class PointerLikeRegClass<int Kind> {
654 int RegClassKind = Kind;
658 /// ptr_rc definition - Mark this operand as being a pointer value whose
659 /// register class is resolved dynamically via a callback to TargetInstrInfo.
660 /// FIXME: We should probably change this to a class which contain a list of
661 /// flags. But currently we have but one flag.
662 def ptr_rc : PointerLikeRegClass<0>;
664 /// unknown definition - Mark this operand as being of unknown type, causing
665 /// it to be resolved by inference in the context it is used.
667 def unknown : unknown_class;
669 /// AsmOperandClass - Representation for the kinds of operands which the target
670 /// specific parser can create and the assembly matcher may need to distinguish.
672 /// Operand classes are used to define the order in which instructions are
673 /// matched, to ensure that the instruction which gets matched for any
674 /// particular list of operands is deterministic.
676 /// The target specific parser must be able to classify a parsed operand into a
677 /// unique class which does not partially overlap with any other classes. It can
678 /// match a subset of some other class, in which case the super class field
679 /// should be defined.
680 class AsmOperandClass {
681 /// The name to use for this class, which should be usable as an enum value.
684 /// The super classes of this operand.
685 list<AsmOperandClass> SuperClasses = [];
687 /// The name of the method on the target specific operand to call to test
688 /// whether the operand is an instance of this class. If not set, this will
689 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
690 /// signature should be:
691 /// bool isFoo() const;
692 string PredicateMethod = ?;
694 /// The name of the method on the target specific operand to call to add the
695 /// target specific operand to an MCInst. If not set, this will default to
696 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
697 /// signature should be:
698 /// void addFooOperands(MCInst &Inst, unsigned N) const;
699 string RenderMethod = ?;
701 /// The name of the method on the target specific operand to call to custom
702 /// handle the operand parsing. This is useful when the operands do not relate
703 /// to immediates or registers and are very instruction specific (as flags to
704 /// set in a processor register, coprocessor number, ...).
705 string ParserMethod = ?;
707 // The diagnostic type to present when referencing this operand in a
708 // match failure error message. By default, use a generic "invalid operand"
709 // diagnostic. The target AsmParser maps these codes to text.
710 string DiagnosticType = "";
712 /// A diagnostic message to emit when an invalid value is provided for this
714 string DiagnosticString = "";
716 /// Set to 1 if this operand is optional and not always required. Typically,
717 /// the AsmParser will emit an error when it finishes parsing an
718 /// instruction if it hasn't matched all the operands yet. However, this
719 /// error will be suppressed if all of the remaining unmatched operands are
720 /// marked as IsOptional.
722 /// Optional arguments must be at the end of the operand list.
725 /// The name of the method on the target specific asm parser that returns the
726 /// default operand for this optional operand. This method is only used if
727 /// IsOptional == 1. If not set, this will default to "defaultFooOperands",
728 /// where Foo is the AsmOperandClass name. The method signature should be:
729 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const;
730 string DefaultMethod = ?;
733 def ImmAsmOperand : AsmOperandClass {
737 /// Operand Types - These provide the built-in operand types that may be used
738 /// by a target. Targets can optionally provide their own operand types as
739 /// needed, though this should not be needed for RISC targets.
740 class Operand<ValueType ty> : DAGOperand {
742 string PrintMethod = "printOperand";
743 string EncoderMethod = "";
744 bit hasCompleteDecoder = 1;
745 string OperandType = "OPERAND_UNKNOWN";
746 dag MIOperandInfo = (ops);
748 // MCOperandPredicate - Optionally, a code fragment operating on
749 // const MCOperand &MCOp, and returning a bool, to indicate if
750 // the value of MCOp is valid for the specific subclass of Operand
751 code MCOperandPredicate;
753 // ParserMatchClass - The "match class" that operands of this type fit
754 // in. Match classes are used to define the order in which instructions are
755 // match, to ensure that which instructions gets matched is deterministic.
757 // The target specific parser must be able to classify an parsed operand into
758 // a unique class, which does not partially overlap with any other classes. It
759 // can match a subset of some other class, in which case the AsmOperandClass
760 // should declare the other operand as one of its super classes.
761 AsmOperandClass ParserMatchClass = ImmAsmOperand;
764 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
766 // RegClass - The register class of the operand.
767 RegisterClass RegClass = regclass;
768 // PrintMethod - The target method to call to print register operands of
769 // this type. The method normally will just use an alt-name index to look
770 // up the name to print. Default to the generic printOperand().
771 string PrintMethod = pm;
773 // EncoderMethod - The target method name to call to encode this register
775 string EncoderMethod = "";
777 // ParserMatchClass - The "match class" that operands of this type fit
778 // in. Match classes are used to define the order in which instructions are
779 // match, to ensure that which instructions gets matched is deterministic.
781 // The target specific parser must be able to classify an parsed operand into
782 // a unique class, which does not partially overlap with any other classes. It
783 // can match a subset of some other class, in which case the AsmOperandClass
784 // should declare the other operand as one of its super classes.
785 AsmOperandClass ParserMatchClass;
787 string OperandType = "OPERAND_REGISTER";
789 // When referenced in the result of a CodeGen pattern, GlobalISel will
790 // normally copy the matched operand to the result. When this is set, it will
791 // emit a special copy that will replace zero-immediates with the specified
793 Register GIZeroRegister = ?;
796 let OperandType = "OPERAND_IMMEDIATE" in {
797 def i1imm : Operand<i1>;
798 def i8imm : Operand<i8>;
799 def i16imm : Operand<i16>;
800 def i32imm : Operand<i32>;
801 def i64imm : Operand<i64>;
803 def f32imm : Operand<f32>;
804 def f64imm : Operand<f64>;
807 // Register operands for generic instructions don't have an MVT, but do have
808 // constraints linking the operands (e.g. all operands of a G_ADD must
809 // have the same LLT).
810 class TypedOperand<string Ty> : Operand<untyped> {
811 let OperandType = Ty;
815 def type0 : TypedOperand<"OPERAND_GENERIC_0">;
816 def type1 : TypedOperand<"OPERAND_GENERIC_1">;
817 def type2 : TypedOperand<"OPERAND_GENERIC_2">;
818 def type3 : TypedOperand<"OPERAND_GENERIC_3">;
819 def type4 : TypedOperand<"OPERAND_GENERIC_4">;
820 def type5 : TypedOperand<"OPERAND_GENERIC_5">;
822 let IsPointer = 1 in {
823 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">;
824 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">;
825 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">;
826 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">;
827 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">;
828 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">;
831 /// zero_reg definition - Special node to stand for the zero register.
835 /// All operands which the MC layer classifies as predicates should inherit from
836 /// this class in some manner. This is already handled for the most commonly
837 /// used PredicateOperand, but may be useful in other circumstances.
840 /// OperandWithDefaultOps - This Operand class can be used as the parent class
841 /// for an Operand that needs to be initialized with a default value if
842 /// no value is supplied in a pattern. This class can be used to simplify the
843 /// pattern definitions for instructions that have target specific flags
844 /// encoded as immediate operands.
845 class OperandWithDefaultOps<ValueType ty, dag defaultops>
847 dag DefaultOps = defaultops;
850 /// PredicateOperand - This can be used to define a predicate operand for an
851 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
852 /// AlwaysVal specifies the value of this predicate when set to "always
854 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
855 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
856 let MIOperandInfo = OpTypes;
859 /// OptionalDefOperand - This is used to define a optional definition operand
860 /// for an instruction. DefaultOps is the register the operand represents if
861 /// none is supplied, e.g. zero_reg.
862 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
863 : OperandWithDefaultOps<ty, defaultops> {
864 let MIOperandInfo = OpTypes;
868 // InstrInfo - This class should only be instantiated once to provide parameters
869 // which are global to the target machine.
872 // Target can specify its instructions in either big or little-endian formats.
873 // For instance, while both Sparc and PowerPC are big-endian platforms, the
874 // Sparc manual specifies its instructions in the format [31..0] (big), while
875 // PowerPC specifies them using the format [0..31] (little).
876 bit isLittleEndianEncoding = 0;
878 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
879 // by default, and TableGen will infer their value from the instruction
880 // pattern when possible.
882 // Normally, TableGen will issue an error it it can't infer the value of a
883 // property that hasn't been set explicitly. When guessInstructionProperties
884 // is set, it will guess a safe value instead.
886 // This option is a temporary migration help. It will go away.
887 bit guessInstructionProperties = 1;
889 // TableGen's instruction encoder generator has support for matching operands
890 // to bit-field variables both by name and by position. While matching by
891 // name is preferred, this is currently not possible for complex operands,
892 // and some targets still reply on the positional encoding rules. When
893 // generating a decoder for such targets, the positional encoding rules must
894 // be used by the decoder generator as well.
896 // This option is temporary; it will go away once the TableGen decoder
897 // generator has better support for complex operands and targets have
898 // migrated away from using positionally encoded operands.
899 bit decodePositionallyEncodedOperands = 0;
901 // When set, this indicates that there will be no overlap between those
902 // operands that are matched by ordering (positional operands) and those
905 // This option is temporary; it will go away once the TableGen decoder
906 // generator has better support for complex operands and targets have
907 // migrated away from using positionally encoded operands.
908 bit noNamedPositionallyEncodedOperands = 0;
911 // Standard Pseudo Instructions.
912 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
913 // Only these instructions are allowed in the TargetOpcode namespace.
914 // Ensure mayLoad and mayStore have a default value, so as not to break
915 // targets that set guessInstructionProperties=0. Any local definition of
916 // mayLoad/mayStore takes precedence over these default values.
917 class StandardPseudoInstruction : Instruction {
920 let isCodeGenOnly = 1;
922 let hasNoSchedulingInfo = 1;
923 let Namespace = "TargetOpcode";
925 def PHI : StandardPseudoInstruction {
926 let OutOperandList = (outs unknown:$dst);
927 let InOperandList = (ins variable_ops);
928 let AsmString = "PHINODE";
929 let hasSideEffects = 0;
931 def INLINEASM : StandardPseudoInstruction {
932 let OutOperandList = (outs);
933 let InOperandList = (ins variable_ops);
935 let hasSideEffects = 0; // Note side effect is encoded in an operand.
937 def CFI_INSTRUCTION : StandardPseudoInstruction {
938 let OutOperandList = (outs);
939 let InOperandList = (ins i32imm:$id);
942 let hasSideEffects = 0;
943 let isNotDuplicable = 1;
945 def EH_LABEL : StandardPseudoInstruction {
946 let OutOperandList = (outs);
947 let InOperandList = (ins i32imm:$id);
950 let hasSideEffects = 0;
951 let isNotDuplicable = 1;
953 def GC_LABEL : StandardPseudoInstruction {
954 let OutOperandList = (outs);
955 let InOperandList = (ins i32imm:$id);
958 let hasSideEffects = 0;
959 let isNotDuplicable = 1;
961 def ANNOTATION_LABEL : StandardPseudoInstruction {
962 let OutOperandList = (outs);
963 let InOperandList = (ins i32imm:$id);
966 let hasSideEffects = 0;
967 let isNotDuplicable = 1;
969 def KILL : StandardPseudoInstruction {
970 let OutOperandList = (outs);
971 let InOperandList = (ins variable_ops);
973 let hasSideEffects = 0;
975 def EXTRACT_SUBREG : StandardPseudoInstruction {
976 let OutOperandList = (outs unknown:$dst);
977 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
979 let hasSideEffects = 0;
981 def INSERT_SUBREG : StandardPseudoInstruction {
982 let OutOperandList = (outs unknown:$dst);
983 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
985 let hasSideEffects = 0;
986 let Constraints = "$supersrc = $dst";
988 def IMPLICIT_DEF : StandardPseudoInstruction {
989 let OutOperandList = (outs unknown:$dst);
990 let InOperandList = (ins);
992 let hasSideEffects = 0;
993 let isReMaterializable = 1;
994 let isAsCheapAsAMove = 1;
996 def SUBREG_TO_REG : StandardPseudoInstruction {
997 let OutOperandList = (outs unknown:$dst);
998 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
1000 let hasSideEffects = 0;
1002 def COPY_TO_REGCLASS : StandardPseudoInstruction {
1003 let OutOperandList = (outs unknown:$dst);
1004 let InOperandList = (ins unknown:$src, i32imm:$regclass);
1006 let hasSideEffects = 0;
1007 let isAsCheapAsAMove = 1;
1009 def DBG_VALUE : StandardPseudoInstruction {
1010 let OutOperandList = (outs);
1011 let InOperandList = (ins variable_ops);
1012 let AsmString = "DBG_VALUE";
1013 let hasSideEffects = 0;
1015 def DBG_LABEL : StandardPseudoInstruction {
1016 let OutOperandList = (outs);
1017 let InOperandList = (ins unknown:$label);
1018 let AsmString = "DBG_LABEL";
1019 let hasSideEffects = 0;
1021 def REG_SEQUENCE : StandardPseudoInstruction {
1022 let OutOperandList = (outs unknown:$dst);
1023 let InOperandList = (ins unknown:$supersrc, variable_ops);
1025 let hasSideEffects = 0;
1026 let isAsCheapAsAMove = 1;
1028 def COPY : StandardPseudoInstruction {
1029 let OutOperandList = (outs unknown:$dst);
1030 let InOperandList = (ins unknown:$src);
1032 let hasSideEffects = 0;
1033 let isAsCheapAsAMove = 1;
1034 let hasNoSchedulingInfo = 0;
1036 def BUNDLE : StandardPseudoInstruction {
1037 let OutOperandList = (outs);
1038 let InOperandList = (ins variable_ops);
1039 let AsmString = "BUNDLE";
1040 let hasSideEffects = 1;
1042 def LIFETIME_START : StandardPseudoInstruction {
1043 let OutOperandList = (outs);
1044 let InOperandList = (ins i32imm:$id);
1045 let AsmString = "LIFETIME_START";
1046 let hasSideEffects = 0;
1048 def LIFETIME_END : StandardPseudoInstruction {
1049 let OutOperandList = (outs);
1050 let InOperandList = (ins i32imm:$id);
1051 let AsmString = "LIFETIME_END";
1052 let hasSideEffects = 0;
1054 def STACKMAP : StandardPseudoInstruction {
1055 let OutOperandList = (outs);
1056 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
1057 let hasSideEffects = 1;
1060 let usesCustomInserter = 1;
1062 def PATCHPOINT : StandardPseudoInstruction {
1063 let OutOperandList = (outs unknown:$dst);
1064 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
1065 i32imm:$nargs, i32imm:$cc, variable_ops);
1066 let hasSideEffects = 1;
1069 let usesCustomInserter = 1;
1071 def STATEPOINT : StandardPseudoInstruction {
1072 let OutOperandList = (outs);
1073 let InOperandList = (ins variable_ops);
1074 let usesCustomInserter = 1;
1077 let hasSideEffects = 1;
1080 def LOAD_STACK_GUARD : StandardPseudoInstruction {
1081 let OutOperandList = (outs ptr_rc:$dst);
1082 let InOperandList = (ins);
1084 bit isReMaterializable = 1;
1085 let hasSideEffects = 0;
1088 def LOCAL_ESCAPE : StandardPseudoInstruction {
1089 // This instruction is really just a label. It has to be part of the chain so
1090 // that it doesn't get dropped from the DAG, but it produces nothing and has
1092 let OutOperandList = (outs);
1093 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
1094 let hasSideEffects = 0;
1097 def FAULTING_OP : StandardPseudoInstruction {
1098 let OutOperandList = (outs unknown:$dst);
1099 let InOperandList = (ins variable_ops);
1100 let usesCustomInserter = 1;
1101 let hasSideEffects = 1;
1104 let isTerminator = 1;
1107 def PATCHABLE_OP : StandardPseudoInstruction {
1108 let OutOperandList = (outs);
1109 let InOperandList = (ins variable_ops);
1110 let usesCustomInserter = 1;
1113 let hasSideEffects = 1;
1115 def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction {
1116 let OutOperandList = (outs);
1117 let InOperandList = (ins);
1118 let AsmString = "# XRay Function Enter.";
1119 let usesCustomInserter = 1;
1120 let hasSideEffects = 0;
1122 def PATCHABLE_RET : StandardPseudoInstruction {
1123 let OutOperandList = (outs);
1124 let InOperandList = (ins variable_ops);
1125 let AsmString = "# XRay Function Patchable RET.";
1126 let usesCustomInserter = 1;
1127 let hasSideEffects = 1;
1128 let isTerminator = 1;
1131 def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction {
1132 let OutOperandList = (outs);
1133 let InOperandList = (ins);
1134 let AsmString = "# XRay Function Exit.";
1135 let usesCustomInserter = 1;
1136 let hasSideEffects = 0; // FIXME: is this correct?
1137 let isReturn = 0; // Original return instruction will follow
1139 def PATCHABLE_TAIL_CALL : StandardPseudoInstruction {
1140 let OutOperandList = (outs);
1141 let InOperandList = (ins variable_ops);
1142 let AsmString = "# XRay Tail Call Exit.";
1143 let usesCustomInserter = 1;
1144 let hasSideEffects = 1;
1147 def PATCHABLE_EVENT_CALL : StandardPseudoInstruction {
1148 let OutOperandList = (outs);
1149 let InOperandList = (ins ptr_rc:$event, i8imm:$size);
1150 let AsmString = "# XRay Custom Event Log.";
1151 let usesCustomInserter = 1;
1155 let hasSideEffects = 1;
1157 def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction {
1158 let OutOperandList = (outs);
1159 let InOperandList = (ins i16imm:$type, ptr_rc:$event, i32imm:$size);
1160 let AsmString = "# XRay Typed Event Log.";
1161 let usesCustomInserter = 1;
1165 let hasSideEffects = 1;
1167 def FENTRY_CALL : StandardPseudoInstruction {
1168 let OutOperandList = (outs);
1169 let InOperandList = (ins);
1170 let AsmString = "# FEntry call";
1171 let usesCustomInserter = 1;
1174 let hasSideEffects = 1;
1176 def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
1177 let OutOperandList = (outs unknown:$dst);
1178 let InOperandList = (ins variable_ops);
1180 let hasSideEffects = 1;
1183 // Generic opcodes used in GlobalISel.
1184 include "llvm/Target/GenericOpcodes.td"
1186 //===----------------------------------------------------------------------===//
1187 // AsmParser - This class can be implemented by targets that wish to implement
1190 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
1191 // syntax on X86 for example).
1194 // AsmParserClassName - This specifies the suffix to use for the asmparser
1195 // class. Generated AsmParser classes are always prefixed with the target
1197 string AsmParserClassName = "AsmParser";
1199 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
1200 // function of the AsmParser class to call on every matched instruction.
1201 // This can be used to perform target specific instruction post-processing.
1202 string AsmParserInstCleanup = "";
1204 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
1205 // written register name matcher
1206 bit ShouldEmitMatchRegisterName = 1;
1208 // Set to true if the target needs a generated 'alternative register name'
1211 // This generates a function which can be used to lookup registers from
1212 // their aliases. This function will fail when called on targets where
1213 // several registers share the same alias (i.e. not a 1:1 mapping).
1214 bit ShouldEmitMatchRegisterAltName = 0;
1216 // Set to true if MatchRegisterName and MatchRegisterAltName functions
1217 // should be generated even if there are duplicate register names. The
1218 // target is responsible for coercing aliased registers as necessary
1219 // (e.g. in validateTargetOperandClass), and there are no guarantees about
1220 // which numeric register identifier will be returned in the case of
1221 // multiple matches.
1222 bit AllowDuplicateRegisterNames = 0;
1224 // HasMnemonicFirst - Set to false if target instructions don't always
1225 // start with a mnemonic as the first token.
1226 bit HasMnemonicFirst = 1;
1228 // ReportMultipleNearMisses -
1229 // When 0, the assembly matcher reports an error for one encoding or operand
1230 // that did not match the parsed instruction.
1231 // When 1, the assmebly matcher returns a list of encodings that were close
1232 // to matching the parsed instruction, so to allow more detailed error
1234 bit ReportMultipleNearMisses = 0;
1236 def DefaultAsmParser : AsmParser;
1238 //===----------------------------------------------------------------------===//
1239 // AsmParserVariant - Subtargets can have multiple different assembly parsers
1240 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
1241 // implemented by targets to describe such variants.
1243 class AsmParserVariant {
1244 // Variant - AsmParsers can be of multiple different variants. Variants are
1245 // used to support targets that need to parser multiple formats for the
1246 // assembly language.
1249 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
1252 // CommentDelimiter - If given, the delimiter string used to recognize
1253 // comments which are hard coded in the .td assembler strings for individual
1255 string CommentDelimiter = "";
1257 // RegisterPrefix - If given, the token prefix which indicates a register
1258 // token. This is used by the matcher to automatically recognize hard coded
1259 // register tokens as constrained registers, instead of tokens, for the
1260 // purposes of matching.
1261 string RegisterPrefix = "";
1263 // TokenizingCharacters - Characters that are standalone tokens
1264 string TokenizingCharacters = "[]*!";
1266 // SeparatorCharacters - Characters that are not tokens
1267 string SeparatorCharacters = " \t,";
1269 // BreakCharacters - Characters that start new identifiers
1270 string BreakCharacters = "";
1272 def DefaultAsmParserVariant : AsmParserVariant;
1274 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
1275 /// matches instructions and aliases.
1276 class AssemblerPredicate<string cond, string name = ""> {
1277 bit AssemblerMatcherPredicate = 1;
1278 string AssemblerCondString = cond;
1279 string PredicateName = name;
1282 /// TokenAlias - This class allows targets to define assembler token
1283 /// operand aliases. That is, a token literal operand which is equivalent
1284 /// to another, canonical, token literal. For example, ARM allows:
1285 /// vmov.u32 s4, #0 -> vmov.i32, #0
1286 /// 'u32' is a more specific designator for the 32-bit integer type specifier
1287 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
1288 /// def : TokenAlias<".u32", ".i32">;
1290 /// This works by marking the match class of 'From' as a subclass of the
1291 /// match class of 'To'.
1292 class TokenAlias<string From, string To> {
1293 string FromToken = From;
1294 string ToToken = To;
1297 /// MnemonicAlias - This class allows targets to define assembler mnemonic
1298 /// aliases. This should be used when all forms of one mnemonic are accepted
1299 /// with a different mnemonic. For example, X86 allows:
1300 /// sal %al, 1 -> shl %al, 1
1301 /// sal %ax, %cl -> shl %ax, %cl
1302 /// sal %eax, %cl -> shl %eax, %cl
1303 /// etc. Though "sal" is accepted with many forms, all of them are directly
1304 /// translated to a shl, so it can be handled with (in the case of X86, it
1305 /// actually has one for each suffix as well):
1306 /// def : MnemonicAlias<"sal", "shl">;
1308 /// Mnemonic aliases are mapped before any other translation in the match phase,
1309 /// and do allow Requires predicates, e.g.:
1311 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1312 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1314 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
1316 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
1318 /// If no variant (e.g., "att" or "intel") is specified then the alias is
1319 /// applied unconditionally.
1320 class MnemonicAlias<string From, string To, string VariantName = ""> {
1321 string FromMnemonic = From;
1322 string ToMnemonic = To;
1323 string AsmVariantName = VariantName;
1325 // Predicates - Predicates that must be true for this remapping to happen.
1326 list<Predicate> Predicates = [];
1329 /// InstAlias - This defines an alternate assembly syntax that is allowed to
1330 /// match an instruction that has a different (more canonical) assembly
1332 class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> {
1333 string AsmString = Asm; // The .s format to match the instruction with.
1334 dag ResultInst = Result; // The MCInst to generate.
1336 // This determines which order the InstPrinter detects aliases for
1337 // printing. A larger value makes the alias more likely to be
1338 // emitted. The Instruction's own definition is notionally 0.5, so 0
1339 // disables printing and 1 enables it if there are no conflicting aliases.
1340 int EmitPriority = Emit;
1342 // Predicates - Predicates that must be true for this to match.
1343 list<Predicate> Predicates = [];
1345 // If the instruction specified in Result has defined an AsmMatchConverter
1346 // then setting this to 1 will cause the alias to use the AsmMatchConverter
1347 // function when converting the OperandVector into an MCInst instead of the
1348 // function that is generated by the dag Result.
1349 // Setting this to 0 will cause the alias to ignore the Result instruction's
1350 // defined AsmMatchConverter and instead use the function generated by the
1352 bit UseInstAsmMatchConverter = 1;
1354 // Assembler variant name to use for this alias. If not specified then
1355 // assembler variants will be determined based on AsmString
1356 string AsmVariantName = VariantName;
1359 //===----------------------------------------------------------------------===//
1360 // AsmWriter - This class can be implemented by targets that need to customize
1361 // the format of the .s file writer.
1363 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1364 // on X86 for example).
1367 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
1368 // class. Generated AsmWriter classes are always prefixed with the target
1370 string AsmWriterClassName = "InstPrinter";
1372 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to
1373 // the various print methods.
1374 // FIXME: Remove after all ports are updated.
1375 int PassSubtarget = 0;
1377 // Variant - AsmWriters can be of multiple different variants. Variants are
1378 // used to support targets that need to emit assembly code in ways that are
1379 // mostly the same for different targets, but have minor differences in
1380 // syntax. If the asmstring contains {|} characters in them, this integer
1381 // will specify which alternative to use. For example "{x|y|z}" with Variant
1382 // == 1, will expand to "y".
1385 def DefaultAsmWriter : AsmWriter;
1388 //===----------------------------------------------------------------------===//
1389 // Target - This class contains the "global" target information
1392 // InstructionSet - Instruction set description for this target.
1393 InstrInfo InstructionSet;
1395 // AssemblyParsers - The AsmParser instances available for this target.
1396 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
1398 /// AssemblyParserVariants - The AsmParserVariant instances available for
1400 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
1402 // AssemblyWriters - The AsmWriter instances available for this target.
1403 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
1405 // AllowRegisterRenaming - Controls whether this target allows
1406 // post-register-allocation renaming of registers. This is done by
1407 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
1408 // for all opcodes if this flag is set to 0.
1409 int AllowRegisterRenaming = 0;
1412 //===----------------------------------------------------------------------===//
1413 // SubtargetFeature - A characteristic of the chip set.
1415 class SubtargetFeature<string n, string a, string v, string d,
1416 list<SubtargetFeature> i = []> {
1417 // Name - Feature name. Used by command line (-mattr=) to determine the
1418 // appropriate target chip.
1422 // Attribute - Attribute to be set by feature.
1424 string Attribute = a;
1426 // Value - Value the attribute to be set to by feature.
1430 // Desc - Feature description. Used by command line (-mattr=) to display help
1435 // Implies - Features that this feature implies are present. If one of those
1436 // features isn't set, then this one shouldn't be set either.
1438 list<SubtargetFeature> Implies = i;
1441 /// Specifies a Subtarget feature that this instruction is deprecated on.
1442 class Deprecated<SubtargetFeature dep> {
1443 SubtargetFeature DeprecatedFeatureMask = dep;
1446 /// A custom predicate used to determine if an instruction is
1447 /// deprecated or not.
1448 class ComplexDeprecationPredicate<string dep> {
1449 string ComplexDeprecationPredicate = dep;
1452 //===----------------------------------------------------------------------===//
1453 // Processor chip sets - These values represent each of the chip sets supported
1454 // by the scheduler. Each Processor definition requires corresponding
1455 // instruction itineraries.
1457 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1458 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1459 // appropriate target chip.
1463 // SchedModel - The machine model for scheduling and instruction cost.
1465 SchedMachineModel SchedModel = NoSchedModel;
1467 // ProcItin - The scheduling information for the target processor.
1469 ProcessorItineraries ProcItin = pi;
1471 // Features - list of
1472 list<SubtargetFeature> Features = f;
1475 // ProcessorModel allows subtargets to specify the more general
1476 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1477 // gradually move to this newer form.
1479 // Although this class always passes NoItineraries to the Processor
1480 // class, the SchedMachineModel may still define valid Itineraries.
1481 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1482 : Processor<n, NoItineraries, f> {
1486 //===----------------------------------------------------------------------===//
1487 // InstrMapping - This class is used to create mapping tables to relate
1488 // instructions with each other based on the values specified in RowFields,
1489 // ColFields, KeyCol and ValueCols.
1491 class InstrMapping {
1492 // FilterClass - Used to limit search space only to the instructions that
1493 // define the relationship modeled by this InstrMapping record.
1496 // RowFields - List of fields/attributes that should be same for all the
1497 // instructions in a row of the relation table. Think of this as a set of
1498 // properties shared by all the instructions related by this relationship
1499 // model and is used to categorize instructions into subgroups. For instance,
1500 // if we want to define a relation that maps 'Add' instruction to its
1501 // predicated forms, we can define RowFields like this:
1503 // let RowFields = BaseOp
1504 // All add instruction predicated/non-predicated will have to set their BaseOp
1505 // to the same value.
1507 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1508 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1509 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1510 list<string> RowFields = [];
1512 // List of fields/attributes that are same for all the instructions
1513 // in a column of the relation table.
1514 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1515 // based on the 'predSense' values. All the instruction in a specific
1516 // column have the same value and it is fixed for the column according
1517 // to the values set in 'ValueCols'.
1518 list<string> ColFields = [];
1520 // Values for the fields/attributes listed in 'ColFields'.
1521 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1522 // that models this relation) should be non-predicated.
1523 // In the example above, 'Add' is the key instruction.
1524 list<string> KeyCol = [];
1526 // List of values for the fields/attributes listed in 'ColFields', one for
1527 // each column in the relation table.
1529 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1530 // table. First column requires all the instructions to have predSense
1531 // set to 'true' and second column requires it to be 'false'.
1532 list<list<string> > ValueCols = [];
1535 //===----------------------------------------------------------------------===//
1536 // Pull in the common support for calling conventions.
1538 include "llvm/Target/TargetCallingConv.td"
1540 //===----------------------------------------------------------------------===//
1541 // Pull in the common support for DAG isel generation.
1543 include "llvm/Target/TargetSelectionDAG.td"
1545 //===----------------------------------------------------------------------===//
1546 // Pull in the common support for Global ISel register bank info generation.
1548 include "llvm/Target/GlobalISel/RegisterBank.td"
1550 //===----------------------------------------------------------------------===//
1551 // Pull in the common support for DAG isel generation.
1553 include "llvm/Target/GlobalISel/Target.td"
1555 //===----------------------------------------------------------------------===//
1556 // Pull in the common support for the Global ISel DAG-based selector generation.
1558 include "llvm/Target/GlobalISel/SelectionDAGCompat.td"
1560 //===----------------------------------------------------------------------===//
1561 // Pull in the common support for Pfm Counters generation.
1563 include "llvm/Target/TargetPfmCounters.td"