1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineLoopInfo.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/Support/BranchProbability.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 class InstrItineraryData;
32 class MachineMemOperand;
33 class MachineRegisterInfo;
37 class MCSymbolRefExpr;
39 class ScheduleHazardRecognizer;
42 class TargetRegisterClass;
43 class TargetRegisterInfo;
44 class TargetSubtargetInfo;
45 class TargetSchedModel;
48 template<class T> class SmallVectorImpl;
50 //---------------------------------------------------------------------------
52 /// TargetInstrInfo - Interface to description of machine instruction set
54 class TargetInstrInfo : public MCInstrInfo {
55 TargetInstrInfo(const TargetInstrInfo &) = delete;
56 void operator=(const TargetInstrInfo &) = delete;
58 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
59 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
60 : CallFrameSetupOpcode(CFSetupOpcode),
61 CallFrameDestroyOpcode(CFDestroyOpcode),
62 CatchRetOpcode(CatchRetOpcode),
63 ReturnOpcode(ReturnOpcode) {}
65 virtual ~TargetInstrInfo();
67 static bool isGenericOpcode(unsigned Opc) {
68 return Opc <= TargetOpcode::GENERIC_OP_END;
71 /// Given a machine instruction descriptor, returns the register
72 /// class constraint for OpNum, or NULL.
73 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
75 const TargetRegisterInfo *TRI,
76 const MachineFunction &MF) const;
78 /// Return true if the instruction is trivially rematerializable, meaning it
79 /// has no side effects and requires no operands that aren't always available.
80 /// This means the only allowed uses are constants and unallocatable physical
81 /// registers so that the instructions result is independent of the place
83 bool isTriviallyReMaterializable(const MachineInstr &MI,
84 AliasAnalysis *AA = nullptr) const {
85 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
86 (MI.getDesc().isRematerializable() &&
87 (isReallyTriviallyReMaterializable(MI, AA) ||
88 isReallyTriviallyReMaterializableGeneric(MI, AA)));
92 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
93 /// set, this hook lets the target specify whether the instruction is actually
94 /// trivially rematerializable, taking into consideration its operands. This
95 /// predicate must return false if the instruction has any side effects other
96 /// than producing a value, or if it requres any address registers that are
97 /// not always available.
98 /// Requirements must be check as stated in isTriviallyReMaterializable() .
99 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
100 AliasAnalysis *AA) const {
104 /// This method commutes the operands of the given machine instruction MI.
105 /// The operands to be commuted are specified by their indices OpIdx1 and
108 /// If a target has any instructions that are commutable but require
109 /// converting to different instructions or making non-trivial changes
110 /// to commute them, this method can be overloaded to do that.
111 /// The default implementation simply swaps the commutable operands.
113 /// If NewMI is false, MI is modified in place and returned; otherwise, a
114 /// new machine instruction is created and returned.
116 /// Do not call this method for a non-commutable instruction.
117 /// Even though the instruction is commutable, the method may still
118 /// fail to commute the operands, null pointer is returned in such cases.
119 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
121 unsigned OpIdx2) const;
123 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
124 /// operand indices to (ResultIdx1, ResultIdx2).
125 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
126 /// predefined to some indices or be undefined (designated by the special
127 /// value 'CommuteAnyOperandIndex').
128 /// The predefined result indices cannot be re-defined.
129 /// The function returns true iff after the result pair redefinition
130 /// the fixed result pair is equal to or equivalent to the source pair of
131 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
132 /// the pairs (x,y) and (y,x) are equivalent.
133 static bool fixCommutedOpIndices(unsigned &ResultIdx1,
134 unsigned &ResultIdx2,
135 unsigned CommutableOpIdx1,
136 unsigned CommutableOpIdx2);
139 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
140 /// set and the target hook isReallyTriviallyReMaterializable returns false,
141 /// this function does target-independent tests to determine if the
142 /// instruction is really trivially rematerializable.
143 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
144 AliasAnalysis *AA) const;
147 /// These methods return the opcode of the frame setup/destroy instructions
148 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
149 /// order to abstract away the difference between operating with a frame
150 /// pointer and operating without, through the use of these two instructions.
152 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
153 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
155 /// Returns true if the argument is a frame pseudo instruction.
156 bool isFrameInstr(const MachineInstr &I) const {
157 return I.getOpcode() == getCallFrameSetupOpcode() ||
158 I.getOpcode() == getCallFrameDestroyOpcode();
161 /// Returns true if the argument is a frame setup pseudo instruction.
162 bool isFrameSetup(const MachineInstr &I) const {
163 return I.getOpcode() == getCallFrameSetupOpcode();
166 /// Returns size of the frame associated with the given frame instruction.
167 /// For frame setup instruction this is frame that is set up space set up
168 /// after the instruction. For frame destroy instruction this is the frame
169 /// freed by the caller.
170 /// Note, in some cases a call frame (or a part of it) may be prepared prior
171 /// to the frame setup instruction. It occurs in the calls that involve
172 /// inalloca arguments. This function reports only the size of the frame part
173 /// that is set up between the frame setup and destroy pseudo instructions.
174 int64_t getFrameSize(const MachineInstr &I) const {
175 assert(isFrameInstr(I));
176 assert(I.getOperand(0).getImm() >= 0);
177 return I.getOperand(0).getImm();
180 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
181 unsigned getReturnOpcode() const { return ReturnOpcode; }
183 /// Returns the actual stack pointer adjustment made by an instruction
184 /// as part of a call sequence. By default, only call frame setup/destroy
185 /// instructions adjust the stack, but targets may want to override this
186 /// to enable more fine-grained adjustment, or adjust by a different value.
187 virtual int getSPAdjust(const MachineInstr &MI) const;
189 /// Return true if the instruction is a "coalescable" extension instruction.
190 /// That is, it's like a copy where it's legal for the source to overlap the
191 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
192 /// expected the pre-extension value is available as a subreg of the result
193 /// register. This also returns the sub-register index in SubIdx.
194 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
195 unsigned &SrcReg, unsigned &DstReg,
196 unsigned &SubIdx) const {
200 /// If the specified machine instruction is a direct
201 /// load from a stack slot, return the virtual or physical register number of
202 /// the destination along with the FrameIndex of the loaded stack slot. If
203 /// not, return 0. This predicate must return 0 if the instruction has
204 /// any side effects other than loading from the stack slot.
205 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
206 int &FrameIndex) const {
210 /// Check for post-frame ptr elimination stack locations as well.
211 /// This uses a heuristic so it isn't reliable for correctness.
212 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
213 int &FrameIndex) const {
217 /// If the specified machine instruction has a load from a stack slot,
218 /// return true along with the FrameIndex of the loaded stack slot and the
219 /// machine mem operand containing the reference.
220 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
221 /// any instructions that loads from the stack. This is just a hint, as some
222 /// cases may be missed.
223 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
224 const MachineMemOperand *&MMO,
225 int &FrameIndex) const;
227 /// If the specified machine instruction is a direct
228 /// store to a stack slot, return the virtual or physical register number of
229 /// the source reg along with the FrameIndex of the loaded stack slot. If
230 /// not, return 0. This predicate must return 0 if the instruction has
231 /// any side effects other than storing to the stack slot.
232 virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
233 int &FrameIndex) const {
237 /// Check for post-frame ptr elimination stack locations as well.
238 /// This uses a heuristic, so it isn't reliable for correctness.
239 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
240 int &FrameIndex) const {
244 /// If the specified machine instruction has a store to a stack slot,
245 /// return true along with the FrameIndex of the loaded stack slot and the
246 /// machine mem operand containing the reference.
247 /// If not, return false. Unlike isStoreToStackSlot,
248 /// this returns true for any instructions that stores to the
249 /// stack. This is just a hint, as some cases may be missed.
250 virtual bool hasStoreToStackSlot(const MachineInstr &MI,
251 const MachineMemOperand *&MMO,
252 int &FrameIndex) const;
254 /// Return true if the specified machine instruction
255 /// is a copy of one stack slot to another and has no other effect.
256 /// Provide the identity of the two frame indices.
257 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
258 int &SrcFrameIndex) const {
262 /// Compute the size in bytes and offset within a stack slot of a spilled
263 /// register or subregister.
265 /// \param [out] Size in bytes of the spilled value.
266 /// \param [out] Offset in bytes within the stack slot.
267 /// \returns true if both Size and Offset are successfully computed.
269 /// Not all subregisters have computable spill slots. For example,
270 /// subregisters registers may not be byte-sized, and a pair of discontiguous
271 /// subregisters has no single offset.
273 /// Targets with nontrivial bigendian implementations may need to override
274 /// this, particularly to support spilled vector registers.
275 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
276 unsigned &Size, unsigned &Offset,
277 const MachineFunction &MF) const;
279 /// Returns the size in bytes of the specified MachineInstr, or ~0U
280 /// when this function is not implemented by a target.
281 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
285 /// Return true if the instruction is as cheap as a move instruction.
287 /// Targets for different archs need to override this, and different
288 /// micro-architectures can also be finely tuned inside.
289 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
290 return MI.isAsCheapAsAMove();
293 /// Return true if the instruction should be sunk by MachineSink.
295 /// MachineSink determines on its own whether the instruction is safe to sink;
296 /// this gives the target a hook to override the default behavior with regards
297 /// to which instructions should be sunk.
298 virtual bool shouldSink(const MachineInstr &MI) const {
302 /// Re-issue the specified 'original' instruction at the
303 /// specific location targeting a new destination register.
304 /// The register in Orig->getOperand(0).getReg() will be substituted by
305 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
307 virtual void reMaterialize(MachineBasicBlock &MBB,
308 MachineBasicBlock::iterator MI, unsigned DestReg,
309 unsigned SubIdx, const MachineInstr &Orig,
310 const TargetRegisterInfo &TRI) const;
312 /// Create a duplicate of the Orig instruction in MF. This is like
313 /// MachineFunction::CloneMachineInstr(), but the target may update operands
314 /// that are required to be unique.
316 /// The instruction must be duplicable as indicated by isNotDuplicable().
317 virtual MachineInstr *duplicate(MachineInstr &Orig,
318 MachineFunction &MF) const;
320 /// This method must be implemented by targets that
321 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
322 /// may be able to convert a two-address instruction into one or more true
323 /// three-address instructions on demand. This allows the X86 target (for
324 /// example) to convert ADD and SHL instructions into LEA instructions if they
325 /// would require register copies due to two-addressness.
327 /// This method returns a null pointer if the transformation cannot be
328 /// performed, otherwise it returns the last new instruction.
330 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
332 LiveVariables *LV) const {
336 // This constant can be used as an input value of operand index passed to
337 // the method findCommutedOpIndices() to tell the method that the
338 // corresponding operand index is not pre-defined and that the method
339 // can pick any commutable operand.
340 static const unsigned CommuteAnyOperandIndex = ~0U;
342 /// This method commutes the operands of the given machine instruction MI.
344 /// The operands to be commuted are specified by their indices OpIdx1 and
345 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
346 /// 'CommuteAnyOperandIndex', which means that the method is free to choose
347 /// any arbitrarily chosen commutable operand. If both arguments are set to
348 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
349 /// operands; then commutes them if such operands could be found.
351 /// If NewMI is false, MI is modified in place and returned; otherwise, a
352 /// new machine instruction is created and returned.
354 /// Do not call this method for a non-commutable instruction or
355 /// for non-commuable operands.
356 /// Even though the instruction is commutable, the method may still
357 /// fail to commute the operands, null pointer is returned in such cases.
359 commuteInstruction(MachineInstr &MI, bool NewMI = false,
360 unsigned OpIdx1 = CommuteAnyOperandIndex,
361 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
363 /// Returns true iff the routine could find two commutable operands in the
364 /// given machine instruction.
365 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
366 /// If any of the INPUT values is set to the special value
367 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
368 /// operand, then returns its index in the corresponding argument.
369 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
370 /// looks for 2 commutable operands.
371 /// If INPUT values refer to some operands of MI, then the method simply
372 /// returns true if the corresponding operands are commutable and returns
375 /// For example, calling this method this way:
376 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
377 /// findCommutedOpIndices(MI, Op1, Op2);
378 /// can be interpreted as a query asking to find an operand that would be
379 /// commutable with the operand#1.
380 virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
381 unsigned &SrcOpIdx2) const;
383 /// A pair composed of a register and a sub-register index.
384 /// Used to give some type checking when modeling Reg:SubReg.
385 struct RegSubRegPair {
388 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
389 : Reg(Reg), SubReg(SubReg) {}
391 /// A pair composed of a pair of a register and a sub-register index,
392 /// and another sub-register index.
393 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
394 struct RegSubRegPairAndIdx : RegSubRegPair {
396 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
398 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
401 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
403 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
404 /// the list is modeled as <Reg:SubReg, SubIdx>.
405 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
407 /// - vreg1:sub1, sub0
408 /// - vreg2<:0>, sub1
410 /// \returns true if it is possible to build such an input sequence
411 /// with the pair \p MI, \p DefIdx. False otherwise.
413 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
415 /// \note The generic implementation does not provide any support for
416 /// MI.isRegSequenceLike(). In other words, one has to override
417 /// getRegSequenceLikeInputs for target specific instructions.
419 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
420 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
422 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
424 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
425 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
426 /// - vreg1:sub1, sub0
428 /// \returns true if it is possible to build such an input sequence
429 /// with the pair \p MI, \p DefIdx. False otherwise.
431 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
433 /// \note The generic implementation does not provide any support for
434 /// MI.isExtractSubregLike(). In other words, one has to override
435 /// getExtractSubregLikeInputs for target specific instructions.
437 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
438 RegSubRegPairAndIdx &InputReg) const;
440 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
442 /// \p [out] BaseReg and \p [out] InsertedReg contain
443 /// the equivalent inputs of INSERT_SUBREG.
444 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
445 /// - BaseReg: vreg0:sub0
446 /// - InsertedReg: vreg1:sub1, sub3
448 /// \returns true if it is possible to build such an input sequence
449 /// with the pair \p MI, \p DefIdx. False otherwise.
451 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
453 /// \note The generic implementation does not provide any support for
454 /// MI.isInsertSubregLike(). In other words, one has to override
455 /// getInsertSubregLikeInputs for target specific instructions.
457 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
458 RegSubRegPair &BaseReg,
459 RegSubRegPairAndIdx &InsertedReg) const;
462 /// Return true if two machine instructions would produce identical values.
463 /// By default, this is only true when the two instructions
464 /// are deemed identical except for defs. If this function is called when the
465 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
466 /// aggressive checks.
467 virtual bool produceSameValue(const MachineInstr &MI0,
468 const MachineInstr &MI1,
469 const MachineRegisterInfo *MRI = nullptr) const;
471 /// \returns true if a branch from an instruction with opcode \p BranchOpc
472 /// bytes is capable of jumping to a position \p BrOffset bytes away.
473 virtual bool isBranchOffsetInRange(unsigned BranchOpc,
474 int64_t BrOffset) const {
475 llvm_unreachable("target did not implement");
478 /// \returns The block that branch instruction \p MI jumps to.
479 virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
480 llvm_unreachable("target did not implement");
483 /// Insert an unconditional indirect branch at the end of \p MBB to \p
484 /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
485 /// the offset of the position to insert the new branch.
487 /// \returns The number of bytes added to the block.
488 virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
489 MachineBasicBlock &NewDestBB,
491 int64_t BrOffset = 0,
492 RegScavenger *RS = nullptr) const {
493 llvm_unreachable("target did not implement");
496 /// Analyze the branching code at the end of MBB, returning
497 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
498 /// implemented for a target). Upon success, this returns false and returns
499 /// with the following information in various cases:
501 /// 1. If this block ends with no branches (it just falls through to its succ)
502 /// just return false, leaving TBB/FBB null.
503 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
504 /// the destination block.
505 /// 3. If this block ends with a conditional branch and it falls through to a
506 /// successor block, it sets TBB to be the branch destination block and a
507 /// list of operands that evaluate the condition. These operands can be
508 /// passed to other TargetInstrInfo methods to create new branches.
509 /// 4. If this block ends with a conditional branch followed by an
510 /// unconditional branch, it returns the 'true' destination in TBB, the
511 /// 'false' destination in FBB, and a list of operands that evaluate the
512 /// condition. These operands can be passed to other TargetInstrInfo
513 /// methods to create new branches.
515 /// Note that removeBranch and insertBranch must be implemented to support
516 /// cases where this method returns success.
518 /// If AllowModify is true, then this routine is allowed to modify the basic
519 /// block (e.g. delete instructions after the unconditional branch).
521 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
522 /// before calling this function.
523 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
524 MachineBasicBlock *&FBB,
525 SmallVectorImpl<MachineOperand> &Cond,
526 bool AllowModify = false) const {
530 /// Represents a predicate at the MachineFunction level. The control flow a
531 /// MachineBranchPredicate represents is:
533 /// Reg <def>= LHS `Predicate` RHS == ConditionDef
534 /// if Reg then goto TrueDest else goto FalseDest
536 struct MachineBranchPredicate {
537 enum ComparePredicate {
538 PRED_EQ, // True if two values are equal
539 PRED_NE, // True if two values are not equal
540 PRED_INVALID // Sentinel value
543 ComparePredicate Predicate;
546 MachineBasicBlock *TrueDest;
547 MachineBasicBlock *FalseDest;
548 MachineInstr *ConditionDef;
550 /// SingleUseCondition is true if ConditionDef is dead except for the
551 /// branch(es) at the end of the basic block.
553 bool SingleUseCondition;
555 explicit MachineBranchPredicate()
556 : Predicate(PRED_INVALID), LHS(MachineOperand::CreateImm(0)),
557 RHS(MachineOperand::CreateImm(0)), TrueDest(nullptr),
558 FalseDest(nullptr), ConditionDef(nullptr), SingleUseCondition(false) {
562 /// Analyze the branching code at the end of MBB and parse it into the
563 /// MachineBranchPredicate structure if possible. Returns false on success
564 /// and true on failure.
566 /// If AllowModify is true, then this routine is allowed to modify the basic
567 /// block (e.g. delete instructions after the unconditional branch).
569 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
570 MachineBranchPredicate &MBP,
571 bool AllowModify = false) const {
575 /// Remove the branching code at the end of the specific MBB.
576 /// This is only invoked in cases where AnalyzeBranch returns success. It
577 /// returns the number of instructions that were removed.
578 /// If \p BytesRemoved is non-null, report the change in code size from the
579 /// removed instructions.
580 virtual unsigned removeBranch(MachineBasicBlock &MBB,
581 int *BytesRemoved = nullptr) const {
582 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
585 /// Insert branch code into the end of the specified MachineBasicBlock. The
586 /// operands to this method are the same as those returned by AnalyzeBranch.
587 /// This is only invoked in cases where AnalyzeBranch returns success. It
588 /// returns the number of instructions inserted. If \p BytesAdded is non-null,
589 /// report the change in code size from the added instructions.
591 /// It is also invoked by tail merging to add unconditional branches in
592 /// cases where AnalyzeBranch doesn't apply because there was no original
593 /// branch to analyze. At least this much must be implemented, else tail
594 /// merging needs to be disabled.
596 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
597 /// before calling this function.
598 virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
599 MachineBasicBlock *FBB,
600 ArrayRef<MachineOperand> Cond,
602 int *BytesAdded = nullptr) const {
603 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
606 unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
607 MachineBasicBlock *DestBB,
609 int *BytesAdded = nullptr) const {
610 return insertBranch(MBB, DestBB, nullptr,
611 ArrayRef<MachineOperand>(), DL, BytesAdded);
614 /// Analyze the loop code, return true if it cannot be understoo. Upon
615 /// success, this function returns false and returns information about the
616 /// induction variable and compare instruction used at the end.
617 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
618 MachineInstr *&CmpInst) const {
622 /// Generate code to reduce the loop iteration by one and check if the loop is
623 /// finished. Return the value/register of the the new loop count. We need
624 /// this function when peeling off one or more iterations of a loop. This
625 /// function assumes the nth iteration is peeled first.
626 virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
627 MachineInstr *IndVar, MachineInstr &Cmp,
628 SmallVectorImpl<MachineOperand> &Cond,
629 SmallVectorImpl<MachineInstr *> &PrevInsts,
630 unsigned Iter, unsigned MaxIter) const {
631 llvm_unreachable("Target didn't implement ReduceLoopCount");
634 /// Delete the instruction OldInst and everything after it, replacing it with
635 /// an unconditional branch to NewDest. This is used by the tail merging pass.
636 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
637 MachineBasicBlock *NewDest) const;
639 /// Return true if it's legal to split the given basic
640 /// block at the specified instruction (i.e. instruction would be the start
641 /// of a new basic block).
642 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
643 MachineBasicBlock::iterator MBBI) const {
647 /// Return true if it's profitable to predicate
648 /// instructions with accumulated instruction latency of "NumCycles"
649 /// of the specified basic block, where the probability of the instructions
650 /// being executed is given by Probability, and Confidence is a measure
651 /// of our confidence that it will be properly predicted.
653 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
654 unsigned ExtraPredCycles,
655 BranchProbability Probability) const {
659 /// Second variant of isProfitableToIfCvt. This one
660 /// checks for the case where two basic blocks from true and false path
661 /// of a if-then-else (diamond) are predicated on mutally exclusive
662 /// predicates, where the probability of the true path being taken is given
663 /// by Probability, and Confidence is a measure of our confidence that it
664 /// will be properly predicted.
666 isProfitableToIfCvt(MachineBasicBlock &TMBB,
667 unsigned NumTCycles, unsigned ExtraTCycles,
668 MachineBasicBlock &FMBB,
669 unsigned NumFCycles, unsigned ExtraFCycles,
670 BranchProbability Probability) const {
674 /// Return true if it's profitable for if-converter to duplicate instructions
675 /// of specified accumulated instruction latencies in the specified MBB to
676 /// enable if-conversion.
677 /// The probability of the instructions being executed is given by
678 /// Probability, and Confidence is a measure of our confidence that it
679 /// will be properly predicted.
681 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
682 BranchProbability Probability) const {
686 /// Return true if it's profitable to unpredicate
687 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
688 /// exclusive predicates.
696 /// This may be profitable is conditional instructions are always executed.
697 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
698 MachineBasicBlock &FMBB) const {
702 /// Return true if it is possible to insert a select
703 /// instruction that chooses between TrueReg and FalseReg based on the
704 /// condition code in Cond.
706 /// When successful, also return the latency in cycles from TrueReg,
707 /// FalseReg, and Cond to the destination register. In most cases, a select
708 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
710 /// Some x86 implementations have 2-cycle cmov instructions.
712 /// @param MBB Block where select instruction would be inserted.
713 /// @param Cond Condition returned by AnalyzeBranch.
714 /// @param TrueReg Virtual register to select when Cond is true.
715 /// @param FalseReg Virtual register to select when Cond is false.
716 /// @param CondCycles Latency from Cond+Branch to select output.
717 /// @param TrueCycles Latency from TrueReg to select output.
718 /// @param FalseCycles Latency from FalseReg to select output.
719 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
720 ArrayRef<MachineOperand> Cond,
721 unsigned TrueReg, unsigned FalseReg,
723 int &TrueCycles, int &FalseCycles) const {
727 /// Insert a select instruction into MBB before I that will copy TrueReg to
728 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
730 /// This function can only be called after canInsertSelect() returned true.
731 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
732 /// that the same flags or registers required by Cond are available at the
735 /// @param MBB Block where select instruction should be inserted.
736 /// @param I Insertion point.
737 /// @param DL Source location for debugging.
738 /// @param DstReg Virtual register to be defined by select instruction.
739 /// @param Cond Condition as computed by AnalyzeBranch.
740 /// @param TrueReg Virtual register to copy when Cond is true.
741 /// @param FalseReg Virtual register to copy when Cons is false.
742 virtual void insertSelect(MachineBasicBlock &MBB,
743 MachineBasicBlock::iterator I, const DebugLoc &DL,
744 unsigned DstReg, ArrayRef<MachineOperand> Cond,
745 unsigned TrueReg, unsigned FalseReg) const {
746 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
749 /// Analyze the given select instruction, returning true if
750 /// it cannot be understood. It is assumed that MI->isSelect() is true.
752 /// When successful, return the controlling condition and the operands that
753 /// determine the true and false result values.
755 /// Result = SELECT Cond, TrueOp, FalseOp
757 /// Some targets can optimize select instructions, for example by predicating
758 /// the instruction defining one of the operands. Such targets should set
761 /// @param MI Select instruction to analyze.
762 /// @param Cond Condition controlling the select.
763 /// @param TrueOp Operand number of the value selected when Cond is true.
764 /// @param FalseOp Operand number of the value selected when Cond is false.
765 /// @param Optimizable Returned as true if MI is optimizable.
766 /// @returns False on success.
767 virtual bool analyzeSelect(const MachineInstr &MI,
768 SmallVectorImpl<MachineOperand> &Cond,
769 unsigned &TrueOp, unsigned &FalseOp,
770 bool &Optimizable) const {
771 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
775 /// Given a select instruction that was understood by
776 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
777 /// merging it with one of its operands. Returns NULL on failure.
779 /// When successful, returns the new select instruction. The client is
780 /// responsible for deleting MI.
782 /// If both sides of the select can be optimized, PreferFalse is used to pick
785 /// @param MI Optimizable select instruction.
786 /// @param NewMIs Set that record all MIs in the basic block up to \p
787 /// MI. Has to be updated with any newly created MI or deleted ones.
788 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
789 /// @returns Optimized instruction or NULL.
790 virtual MachineInstr *optimizeSelect(MachineInstr &MI,
791 SmallPtrSetImpl<MachineInstr *> &NewMIs,
792 bool PreferFalse = false) const {
793 // This function must be implemented if Optimizable is ever set.
794 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
797 /// Emit instructions to copy a pair of physical registers.
799 /// This function should support copies within any legal register class as
800 /// well as any cross-class copies created during instruction selection.
802 /// The source and destination registers may overlap, which may require a
803 /// careful implementation when multiple copy instructions are required for
804 /// large registers. See for example the ARM target.
805 virtual void copyPhysReg(MachineBasicBlock &MBB,
806 MachineBasicBlock::iterator MI, const DebugLoc &DL,
807 unsigned DestReg, unsigned SrcReg,
808 bool KillSrc) const {
809 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
812 /// Store the specified register of the given register class to the specified
813 /// stack frame index. The store instruction is to be added to the given
814 /// machine basic block before the specified machine instruction. If isKill
815 /// is true, the register operand is the last use and must be marked kill.
816 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
817 MachineBasicBlock::iterator MI,
818 unsigned SrcReg, bool isKill, int FrameIndex,
819 const TargetRegisterClass *RC,
820 const TargetRegisterInfo *TRI) const {
821 llvm_unreachable("Target didn't implement "
822 "TargetInstrInfo::storeRegToStackSlot!");
825 /// Load the specified register of the given register class from the specified
826 /// stack frame index. The load instruction is to be added to the given
827 /// machine basic block before the specified machine instruction.
828 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
829 MachineBasicBlock::iterator MI,
830 unsigned DestReg, int FrameIndex,
831 const TargetRegisterClass *RC,
832 const TargetRegisterInfo *TRI) const {
833 llvm_unreachable("Target didn't implement "
834 "TargetInstrInfo::loadRegFromStackSlot!");
837 /// This function is called for all pseudo instructions
838 /// that remain after register allocation. Many pseudo instructions are
839 /// created to help register allocation. This is the place to convert them
840 /// into real instructions. The target can edit MI in place, or it can insert
841 /// new instructions and erase MI. The function should return true if
842 /// anything was changed.
843 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
845 /// Check whether the target can fold a load that feeds a subreg operand
846 /// (or a subreg operand that feeds a store).
847 /// For example, X86 may want to return true if it can fold
848 /// movl (%esp), %eax
853 /// Ideally, we'd like the target implementation of foldMemoryOperand() to
854 /// reject subregs - but since this behavior used to be enforced in the
855 /// target-independent code, moving this responsibility to the targets
856 /// has the potential of causing nasty silent breakage in out-of-tree targets.
857 virtual bool isSubregFoldable() const { return false; }
859 /// Attempt to fold a load or store of the specified stack
860 /// slot into the specified machine instruction for the specified operand(s).
861 /// If this is possible, a new instruction is returned with the specified
862 /// operand folded, otherwise NULL is returned.
863 /// The new instruction is inserted before MI, and the client is responsible
864 /// for removing the old instruction.
865 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
867 LiveIntervals *LIS = nullptr) const;
869 /// Same as the previous version except it allows folding of any load and
870 /// store from / to any address, not just from a specific stack slot.
871 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
872 MachineInstr &LoadMI,
873 LiveIntervals *LIS = nullptr) const;
875 /// Return true when there is potentially a faster code sequence
876 /// for an instruction chain ending in \p Root. All potential patterns are
877 /// returned in the \p Pattern vector. Pattern should be sorted in priority
878 /// order since the pattern evaluator stops checking as soon as it finds a
880 /// \param Root - Instruction that could be combined with one of its operands
881 /// \param Patterns - Vector of possible combination patterns
882 virtual bool getMachineCombinerPatterns(
884 SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
886 /// Return true when a code sequence can improve throughput. It
887 /// should be called only for instructions in loops.
888 /// \param Pattern - combiner pattern
889 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
891 /// Return true if the input \P Inst is part of a chain of dependent ops
892 /// that are suitable for reassociation, otherwise return false.
893 /// If the instruction's operands must be commuted to have a previous
894 /// instruction of the same type define the first source operand, \P Commuted
895 /// will be set to true.
896 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
898 /// Return true when \P Inst is both associative and commutative.
899 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
903 /// Return true when \P Inst has reassociable operands in the same \P MBB.
904 virtual bool hasReassociableOperands(const MachineInstr &Inst,
905 const MachineBasicBlock *MBB) const;
907 /// Return true when \P Inst has reassociable sibling.
908 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
910 /// When getMachineCombinerPatterns() finds patterns, this function generates
911 /// the instructions that could replace the original code sequence. The client
912 /// has to decide whether the actual replacement is beneficial or not.
913 /// \param Root - Instruction that could be combined with one of its operands
914 /// \param Pattern - Combination pattern for Root
915 /// \param InsInstrs - Vector of new instructions that implement P
916 /// \param DelInstrs - Old instructions, including Root, that could be
917 /// replaced by InsInstr
918 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
919 /// InsInstr that defines it
920 virtual void genAlternativeCodeSequence(
921 MachineInstr &Root, MachineCombinerPattern Pattern,
922 SmallVectorImpl<MachineInstr *> &InsInstrs,
923 SmallVectorImpl<MachineInstr *> &DelInstrs,
924 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
926 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
927 /// reduce critical path length.
928 void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
929 MachineCombinerPattern Pattern,
930 SmallVectorImpl<MachineInstr *> &InsInstrs,
931 SmallVectorImpl<MachineInstr *> &DelInstrs,
932 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
934 /// This is an architecture-specific helper function of reassociateOps.
935 /// Set special operand attributes for new instructions after reassociation.
936 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
937 MachineInstr &NewMI1,
938 MachineInstr &NewMI2) const {
941 /// Return true when a target supports MachineCombiner.
942 virtual bool useMachineCombiner() const { return false; }
945 /// Target-dependent implementation for foldMemoryOperand.
946 /// Target-independent code in foldMemoryOperand will
947 /// take care of adding a MachineMemOperand to the newly created instruction.
948 /// The instruction and any auxiliary instructions necessary will be inserted
950 virtual MachineInstr *
951 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
952 ArrayRef<unsigned> Ops,
953 MachineBasicBlock::iterator InsertPt, int FrameIndex,
954 LiveIntervals *LIS = nullptr) const {
958 /// Target-dependent implementation for foldMemoryOperand.
959 /// Target-independent code in foldMemoryOperand will
960 /// take care of adding a MachineMemOperand to the newly created instruction.
961 /// The instruction and any auxiliary instructions necessary will be inserted
963 virtual MachineInstr *foldMemoryOperandImpl(
964 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
965 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
966 LiveIntervals *LIS = nullptr) const {
970 /// \brief Target-dependent implementation of getRegSequenceInputs.
972 /// \returns true if it is possible to build the equivalent
973 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
975 /// \pre MI.isRegSequenceLike().
977 /// \see TargetInstrInfo::getRegSequenceInputs.
978 virtual bool getRegSequenceLikeInputs(
979 const MachineInstr &MI, unsigned DefIdx,
980 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
984 /// \brief Target-dependent implementation of getExtractSubregInputs.
986 /// \returns true if it is possible to build the equivalent
987 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
989 /// \pre MI.isExtractSubregLike().
991 /// \see TargetInstrInfo::getExtractSubregInputs.
992 virtual bool getExtractSubregLikeInputs(
993 const MachineInstr &MI, unsigned DefIdx,
994 RegSubRegPairAndIdx &InputReg) const {
998 /// \brief Target-dependent implementation of getInsertSubregInputs.
1000 /// \returns true if it is possible to build the equivalent
1001 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1003 /// \pre MI.isInsertSubregLike().
1005 /// \see TargetInstrInfo::getInsertSubregInputs.
1007 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1008 RegSubRegPair &BaseReg,
1009 RegSubRegPairAndIdx &InsertedReg) const {
1014 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1015 /// a store or a load and a store into two or more instruction. If this is
1016 /// possible, returns true as well as the new instructions by reference.
1018 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1019 bool UnfoldLoad, bool UnfoldStore,
1020 SmallVectorImpl<MachineInstr *> &NewMIs) const {
1024 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1025 SmallVectorImpl<SDNode*> &NewNodes) const {
1029 /// Returns the opcode of the would be new
1030 /// instruction after load / store are unfolded from an instruction of the
1031 /// specified opcode. It returns zero if the specified unfolding is not
1032 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1033 /// index of the operand which will hold the register holding the loaded
1035 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
1036 bool UnfoldLoad, bool UnfoldStore,
1037 unsigned *LoadRegIndex = nullptr) const {
1041 /// This is used by the pre-regalloc scheduler to determine if two loads are
1042 /// loading from the same base address. It should only return true if the base
1043 /// pointers are the same and the only differences between the two addresses
1044 /// are the offset. It also returns the offsets by reference.
1045 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1046 int64_t &Offset1, int64_t &Offset2) const {
1050 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1051 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1052 /// On some targets if two loads are loading from
1053 /// addresses in the same cache line, it's better if they are scheduled
1054 /// together. This function takes two integers that represent the load offsets
1055 /// from the common base address. It returns true if it decides it's desirable
1056 /// to schedule the two loads together. "NumLoads" is the number of loads that
1057 /// have already been scheduled after Load1.
1058 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1059 int64_t Offset1, int64_t Offset2,
1060 unsigned NumLoads) const {
1064 /// Get the base register and byte offset of an instruction that reads/writes
1066 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1068 const TargetRegisterInfo *TRI) const {
1072 /// Return true if the instruction contains a base register and offset. If
1073 /// true, the function also sets the operand position in the instruction
1074 /// for the base register and offset.
1075 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1077 unsigned &OffsetPos) const {
1081 /// If the instruction is an increment of a constant value, return the amount.
1082 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1086 /// Returns true if the two given memory operations should be scheduled
1087 /// adjacent. Note that you have to add:
1088 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1090 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1091 /// to TargetPassConfig::createMachineScheduler() to have an effect.
1092 virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt,
1093 MachineInstr &SecondLdSt,
1094 unsigned NumLoads) const {
1095 llvm_unreachable("target did not implement shouldClusterMemOps()");
1098 /// Reverses the branch condition of the specified condition list,
1099 /// returning false on success and true if it cannot be reversed.
1101 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1105 /// Insert a noop into the instruction stream at the specified point.
1106 virtual void insertNoop(MachineBasicBlock &MBB,
1107 MachineBasicBlock::iterator MI) const;
1110 /// Return the noop instruction to use for a noop.
1111 virtual void getNoop(MCInst &NopInst) const;
1113 /// Return true for post-incremented instructions.
1114 virtual bool isPostIncrement(const MachineInstr &MI) const {
1118 /// Returns true if the instruction is already predicated.
1119 virtual bool isPredicated(const MachineInstr &MI) const {
1123 /// Returns true if the instruction is a
1124 /// terminator instruction that has not been predicated.
1125 virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1127 /// Returns true if MI is an unconditional tail call.
1128 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1132 /// Returns true if the tail call can be made conditional on BranchCond.
1134 canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
1135 const MachineInstr &TailCall) const {
1139 /// Replace the conditional branch in MBB with a conditional tail call.
1140 virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1141 SmallVectorImpl<MachineOperand> &Cond,
1142 const MachineInstr &TailCall) const {
1143 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1146 /// Convert the instruction into a predicated instruction.
1147 /// It returns true if the operation was successful.
1148 virtual bool PredicateInstruction(MachineInstr &MI,
1149 ArrayRef<MachineOperand> Pred) const;
1151 /// Returns true if the first specified predicate
1152 /// subsumes the second, e.g. GE subsumes GT.
1154 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1155 ArrayRef<MachineOperand> Pred2) const {
1159 /// If the specified instruction defines any predicate
1160 /// or condition code register(s) used for predication, returns true as well
1161 /// as the definition predicate(s) by reference.
1162 virtual bool DefinesPredicate(MachineInstr &MI,
1163 std::vector<MachineOperand> &Pred) const {
1167 /// Return true if the specified instruction can be predicated.
1168 /// By default, this returns true for every instruction with a
1169 /// PredicateOperand.
1170 virtual bool isPredicable(const MachineInstr &MI) const {
1171 return MI.getDesc().isPredicable();
1174 /// Return true if it's safe to move a machine
1175 /// instruction that defines the specified register class.
1176 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1180 /// Test if the given instruction should be considered a scheduling boundary.
1181 /// This primarily includes labels and terminators.
1182 virtual bool isSchedulingBoundary(const MachineInstr &MI,
1183 const MachineBasicBlock *MBB,
1184 const MachineFunction &MF) const;
1186 /// Measure the specified inline asm to determine an approximation of its
1188 virtual unsigned getInlineAsmLength(const char *Str,
1189 const MCAsmInfo &MAI) const;
1191 /// Allocate and return a hazard recognizer to use for this target when
1192 /// scheduling the machine instructions before register allocation.
1193 virtual ScheduleHazardRecognizer*
1194 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1195 const ScheduleDAG *DAG) const;
1197 /// Allocate and return a hazard recognizer to use for this target when
1198 /// scheduling the machine instructions before register allocation.
1199 virtual ScheduleHazardRecognizer*
1200 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
1201 const ScheduleDAG *DAG) const;
1203 /// Allocate and return a hazard recognizer to use for this target when
1204 /// scheduling the machine instructions after register allocation.
1205 virtual ScheduleHazardRecognizer*
1206 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
1207 const ScheduleDAG *DAG) const;
1209 /// Allocate and return a hazard recognizer to use for by non-scheduling
1211 virtual ScheduleHazardRecognizer*
1212 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1216 /// Provide a global flag for disabling the PreRA hazard recognizer that
1217 /// targets may choose to honor.
1218 bool usePreRAHazardRecognizer() const;
1220 /// For a comparison instruction, return the source registers
1221 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1222 /// compares against in CmpValue. Return true if the comparison instruction
1223 /// can be analyzed.
1224 virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1225 unsigned &SrcReg2, int &Mask, int &Value) const {
1229 /// See if the comparison instruction can be converted
1230 /// into something more efficient. E.g., on ARM most instructions can set the
1231 /// flags register, obviating the need for a separate CMP.
1232 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1233 unsigned SrcReg2, int Mask, int Value,
1234 const MachineRegisterInfo *MRI) const {
1237 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1239 /// Try to remove the load by folding it to a register operand at the use.
1240 /// We fold the load instructions if and only if the
1241 /// def and use are in the same BB. We only look at one load and see
1242 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1243 /// defined by the load we are trying to fold. DefMI returns the machine
1244 /// instruction that defines FoldAsLoadDefReg, and the function returns
1245 /// the machine instruction generated due to folding.
1246 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1247 const MachineRegisterInfo *MRI,
1248 unsigned &FoldAsLoadDefReg,
1249 MachineInstr *&DefMI) const {
1253 /// 'Reg' is known to be defined by a move immediate instruction,
1254 /// try to fold the immediate into the use instruction.
1255 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1256 /// then the caller may assume that DefMI has been erased from its parent
1257 /// block. The caller may assume that it will not be erased by this
1258 /// function otherwise.
1259 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1260 unsigned Reg, MachineRegisterInfo *MRI) const {
1264 /// Return the number of u-operations the given machine
1265 /// instruction will be decoded to on the target cpu. The itinerary's
1266 /// IssueWidth is the number of microops that can be dispatched each
1267 /// cycle. An instruction with zero microops takes no dispatch resources.
1268 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1269 const MachineInstr &MI) const;
1271 /// Return true for pseudo instructions that don't consume any
1272 /// machine resources in their current form. These are common cases that the
1273 /// scheduler should consider free, rather than conservatively handling them
1274 /// as instructions with no itinerary.
1275 bool isZeroCost(unsigned Opcode) const {
1276 return Opcode <= TargetOpcode::COPY;
1279 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1280 SDNode *DefNode, unsigned DefIdx,
1281 SDNode *UseNode, unsigned UseIdx) const;
1283 /// Compute and return the use operand latency of a given pair of def and use.
1284 /// In most cases, the static scheduling itinerary was enough to determine the
1285 /// operand latency. But it may not be possible for instructions with variable
1286 /// number of defs / uses.
1288 /// This is a raw interface to the itinerary that may be directly overridden
1289 /// by a target. Use computeOperandLatency to get the best estimate of
1291 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1292 const MachineInstr &DefMI, unsigned DefIdx,
1293 const MachineInstr &UseMI,
1294 unsigned UseIdx) const;
1296 /// Compute the instruction latency of a given instruction.
1297 /// If the instruction has higher cost when predicated, it's returned via
1299 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1300 const MachineInstr &MI,
1301 unsigned *PredCost = nullptr) const;
1303 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1305 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1306 SDNode *Node) const;
1308 /// Return the default expected latency for a def based on its opcode.
1309 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1310 const MachineInstr &DefMI) const;
1312 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1313 const MachineInstr &DefMI) const;
1315 /// Return true if this opcode has high latency to its result.
1316 virtual bool isHighLatencyDef(int opc) const { return false; }
1318 /// Compute operand latency between a def of 'Reg'
1319 /// and a use in the current loop. Return true if the target considered
1320 /// it 'high'. This is used by optimization passes such as machine LICM to
1321 /// determine whether it makes sense to hoist an instruction out even in a
1322 /// high register pressure situation.
1323 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1324 const MachineRegisterInfo *MRI,
1325 const MachineInstr &DefMI, unsigned DefIdx,
1326 const MachineInstr &UseMI,
1327 unsigned UseIdx) const {
1331 /// Compute operand latency of a def of 'Reg'. Return true
1332 /// if the target considered it 'low'.
1333 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1334 const MachineInstr &DefMI,
1335 unsigned DefIdx) const;
1337 /// Perform target-specific instruction verification.
1338 virtual bool verifyInstruction(const MachineInstr &MI,
1339 StringRef &ErrInfo) const {
1343 /// Return the current execution domain and bit mask of
1344 /// possible domains for instruction.
1346 /// Some micro-architectures have multiple execution domains, and multiple
1347 /// opcodes that perform the same operation in different domains. For
1348 /// example, the x86 architecture provides the por, orps, and orpd
1349 /// instructions that all do the same thing. There is a latency penalty if a
1350 /// register is written in one domain and read in another.
1352 /// This function returns a pair (domain, mask) containing the execution
1353 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1354 /// function can be used to change the opcode to one of the domains in the
1355 /// bit mask. Instructions whose execution domain can't be changed should
1356 /// return a 0 mask.
1358 /// The execution domain numbers don't have any special meaning except domain
1359 /// 0 is used for instructions that are not associated with any interesting
1360 /// execution domain.
1362 virtual std::pair<uint16_t, uint16_t>
1363 getExecutionDomain(const MachineInstr &MI) const {
1364 return std::make_pair(0, 0);
1367 /// Change the opcode of MI to execute in Domain.
1369 /// The bit (1 << Domain) must be set in the mask returned from
1370 /// getExecutionDomain(MI).
1371 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1373 /// Returns the preferred minimum clearance
1374 /// before an instruction with an unwanted partial register update.
1376 /// Some instructions only write part of a register, and implicitly need to
1377 /// read the other parts of the register. This may cause unwanted stalls
1378 /// preventing otherwise unrelated instructions from executing in parallel in
1379 /// an out-of-order CPU.
1381 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1382 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1383 /// the instruction needs to wait for the old value of the register to become
1386 /// addps %xmm1, %xmm0
1387 /// movaps %xmm0, (%rax)
1388 /// cvtsi2ss %rbx, %xmm0
1390 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1391 /// instruction before it can issue, even though the high bits of %xmm0
1392 /// probably aren't needed.
1394 /// This hook returns the preferred clearance before MI, measured in
1395 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1396 /// instructions before MI. It should only return a positive value for
1397 /// unwanted dependencies. If the old bits of the defined register have
1398 /// useful values, or if MI is determined to otherwise read the dependency,
1399 /// the hook should return 0.
1401 /// The unwanted dependency may be handled by:
1403 /// 1. Allocating the same register for an MI def and use. That makes the
1404 /// unwanted dependency identical to a required dependency.
1406 /// 2. Allocating a register for the def that has no defs in the previous N
1409 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1410 /// allows the target to insert a dependency breaking instruction.
1413 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1414 const TargetRegisterInfo *TRI) const {
1415 // The default implementation returns 0 for no partial register dependency.
1419 /// \brief Return the minimum clearance before an instruction that reads an
1420 /// unused register.
1422 /// For example, AVX instructions may copy part of a register operand into
1423 /// the unused high bits of the destination register.
1425 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1427 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1428 /// false dependence on any previous write to %xmm0.
1430 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1431 /// does not take an operand index. Instead sets \p OpNum to the index of the
1432 /// unused register.
1433 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1434 const TargetRegisterInfo *TRI) const {
1435 // The default implementation returns 0 for no undef register dependency.
1439 /// Insert a dependency-breaking instruction
1440 /// before MI to eliminate an unwanted dependency on OpNum.
1442 /// If it wasn't possible to avoid a def in the last N instructions before MI
1443 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1444 /// unwanted dependency.
1446 /// On x86, an xorps instruction can be used as a dependency breaker:
1448 /// addps %xmm1, %xmm0
1449 /// movaps %xmm0, (%rax)
1450 /// xorps %xmm0, %xmm0
1451 /// cvtsi2ss %rbx, %xmm0
1453 /// An <imp-kill> operand should be added to MI if an instruction was
1454 /// inserted. This ties the instructions together in the post-ra scheduler.
1456 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1457 const TargetRegisterInfo *TRI) const {}
1459 /// Create machine specific model for scheduling.
1460 virtual DFAPacketizer *
1461 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1465 /// Sometimes, it is possible for the target
1466 /// to tell, even without aliasing information, that two MIs access different
1467 /// memory addresses. This function returns true if two MIs access different
1468 /// memory addresses and false otherwise.
1470 /// Assumes any physical registers used to compute addresses have the same
1471 /// value for both instructions. (This is the most useful assumption for
1472 /// post-RA scheduling.)
1474 /// See also MachineInstr::mayAlias, which is implemented on top of this
1477 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1478 AliasAnalysis *AA = nullptr) const {
1479 assert((MIa.mayLoad() || MIa.mayStore()) &&
1480 "MIa must load from or modify a memory location");
1481 assert((MIb.mayLoad() || MIb.mayStore()) &&
1482 "MIb must load from or modify a memory location");
1486 /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1487 /// which is a heuristic used for CSE'ing phys reg defs.
1488 virtual unsigned getMachineCSELookAheadLimit () const {
1489 // The default lookahead is small to prevent unprofitable quadratic
1494 /// Return an array that contains the ids of the target indices (used for the
1495 /// TargetIndex machine operand) and their names.
1497 /// MIR Serialization is able to serialize only the target indices that are
1498 /// defined by this method.
1499 virtual ArrayRef<std::pair<int, const char *>>
1500 getSerializableTargetIndices() const {
1504 /// Decompose the machine operand's target flags into two values - the direct
1505 /// target flag value and any of bit flags that are applied.
1506 virtual std::pair<unsigned, unsigned>
1507 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1508 return std::make_pair(0u, 0u);
1511 /// Return an array that contains the direct target flag values and their
1514 /// MIR Serialization is able to serialize only the target flags that are
1515 /// defined by this method.
1516 virtual ArrayRef<std::pair<unsigned, const char *>>
1517 getSerializableDirectMachineOperandTargetFlags() const {
1521 /// Return an array that contains the bitmask target flag values and their
1524 /// MIR Serialization is able to serialize only the target flags that are
1525 /// defined by this method.
1526 virtual ArrayRef<std::pair<unsigned, const char *>>
1527 getSerializableBitmaskMachineOperandTargetFlags() const {
1531 /// Determines whether \p Inst is a tail call instruction. Override this
1532 /// method on targets that do not properly set MCID::Return and MCID::Call on
1533 /// tail call instructions."
1534 virtual bool isTailCall(const MachineInstr &Inst) const {
1535 return Inst.isReturn() && Inst.isCall();
1538 /// True if the instruction is bound to the top of its basic block and no
1539 /// other instructions shall be inserted before it. This can be implemented
1540 /// to prevent register allocator to insert spills before such instructions.
1541 virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1545 /// \brief Return how many instructions would be saved by outlining a
1546 /// sequence containing \p SequenceSize instructions that appears
1547 /// \p Occurrences times in a module.
1548 virtual unsigned getOutliningBenefit(size_t SequenceSize, size_t Occurrences,
1549 bool CanBeTailCall) const {
1551 "Target didn't implement TargetInstrInfo::getOutliningBenefit!");
1554 /// Represents how an instruction should be mapped by the outliner.
1555 /// \p Legal instructions are those which are safe to outline.
1556 /// \p Illegal instructions are those which cannot be outlined.
1557 /// \p Invisible instructions are instructions which can be outlined, but
1558 /// shouldn't actually impact the outlining result.
1559 enum MachineOutlinerInstrType {Legal, Illegal, Invisible};
1561 /// Returns how or if \p MI should be outlined.
1562 virtual MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const {
1564 "Target didn't implement TargetInstrInfo::getOutliningType!");
1567 /// Insert a custom epilogue for outlined functions.
1568 /// This may be empty, in which case no epilogue or return statement will be
1570 virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB,
1571 MachineFunction &MF,
1572 bool IsTailCall) const {
1574 "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!");
1577 /// Insert a call to an outlined function into the program.
1578 /// Returns an iterator to the spot where we inserted the call. This must be
1579 /// implemented by the target.
1580 virtual MachineBasicBlock::iterator
1581 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
1582 MachineBasicBlock::iterator &It, MachineFunction &MF,
1583 bool IsTailCall) const {
1585 "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1588 /// Insert a custom prologue for outlined functions.
1589 /// This may be empty, in which case no prologue will be emitted.
1590 virtual void insertOutlinerPrologue(MachineBasicBlock &MBB,
1591 MachineFunction &MF,
1592 bool IsTailCall) const {
1594 "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!");
1597 /// Return true if the function can safely be outlined from.
1598 /// By default, this means that the function has no red zone.
1599 virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF) const {
1600 llvm_unreachable("Target didn't implement "
1601 "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1605 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1606 unsigned CatchRetOpcode;
1607 unsigned ReturnOpcode;
1610 /// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1612 struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
1613 typedef DenseMapInfo<unsigned> RegInfo;
1615 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1616 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1617 RegInfo::getEmptyKey());
1619 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1620 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1621 RegInfo::getTombstoneKey());
1623 /// \brief Reuse getHashValue implementation from
1624 /// std::pair<unsigned, unsigned>.
1625 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1626 std::pair<unsigned, unsigned> PairVal =
1627 std::make_pair(Val.Reg, Val.SubReg);
1628 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1630 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1631 const TargetInstrInfo::RegSubRegPair &RHS) {
1632 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1633 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1637 } // end namespace llvm
1639 #endif // LLVM_TARGET_TARGETINSTRINFO_H