1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/BranchProbability.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 class InstrItineraryData;
31 class MachineMemOperand;
32 class MachineRegisterInfo;
36 class MCSymbolRefExpr;
38 class ScheduleHazardRecognizer;
41 class TargetRegisterClass;
42 class TargetRegisterInfo;
43 class TargetSubtargetInfo;
44 class TargetSchedModel;
47 template<class T> class SmallVectorImpl;
49 //---------------------------------------------------------------------------
51 /// TargetInstrInfo - Interface to description of machine instruction set
53 class TargetInstrInfo : public MCInstrInfo {
54 TargetInstrInfo(const TargetInstrInfo &) = delete;
55 void operator=(const TargetInstrInfo &) = delete;
57 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
58 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
59 : CallFrameSetupOpcode(CFSetupOpcode),
60 CallFrameDestroyOpcode(CFDestroyOpcode),
61 CatchRetOpcode(CatchRetOpcode),
62 ReturnOpcode(ReturnOpcode) {}
64 virtual ~TargetInstrInfo();
66 static bool isGenericOpcode(unsigned Opc) {
67 return Opc <= TargetOpcode::GENERIC_OP_END;
70 /// Given a machine instruction descriptor, returns the register
71 /// class constraint for OpNum, or NULL.
72 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
74 const TargetRegisterInfo *TRI,
75 const MachineFunction &MF) const;
77 /// Return true if the instruction is trivially rematerializable, meaning it
78 /// has no side effects and requires no operands that aren't always available.
79 /// This means the only allowed uses are constants and unallocatable physical
80 /// registers so that the instructions result is independent of the place
82 bool isTriviallyReMaterializable(const MachineInstr &MI,
83 AliasAnalysis *AA = nullptr) const {
84 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
85 (MI.getDesc().isRematerializable() &&
86 (isReallyTriviallyReMaterializable(MI, AA) ||
87 isReallyTriviallyReMaterializableGeneric(MI, AA)));
91 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
92 /// set, this hook lets the target specify whether the instruction is actually
93 /// trivially rematerializable, taking into consideration its operands. This
94 /// predicate must return false if the instruction has any side effects other
95 /// than producing a value, or if it requres any address registers that are
96 /// not always available.
97 /// Requirements must be check as stated in isTriviallyReMaterializable() .
98 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
99 AliasAnalysis *AA) const {
103 /// This method commutes the operands of the given machine instruction MI.
104 /// The operands to be commuted are specified by their indices OpIdx1 and
107 /// If a target has any instructions that are commutable but require
108 /// converting to different instructions or making non-trivial changes
109 /// to commute them, this method can be overloaded to do that.
110 /// The default implementation simply swaps the commutable operands.
112 /// If NewMI is false, MI is modified in place and returned; otherwise, a
113 /// new machine instruction is created and returned.
115 /// Do not call this method for a non-commutable instruction.
116 /// Even though the instruction is commutable, the method may still
117 /// fail to commute the operands, null pointer is returned in such cases.
118 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
120 unsigned OpIdx2) const;
122 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
123 /// operand indices to (ResultIdx1, ResultIdx2).
124 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
125 /// predefined to some indices or be undefined (designated by the special
126 /// value 'CommuteAnyOperandIndex').
127 /// The predefined result indices cannot be re-defined.
128 /// The function returns true iff after the result pair redefinition
129 /// the fixed result pair is equal to or equivalent to the source pair of
130 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
131 /// the pairs (x,y) and (y,x) are equivalent.
132 static bool fixCommutedOpIndices(unsigned &ResultIdx1,
133 unsigned &ResultIdx2,
134 unsigned CommutableOpIdx1,
135 unsigned CommutableOpIdx2);
138 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
139 /// set and the target hook isReallyTriviallyReMaterializable returns false,
140 /// this function does target-independent tests to determine if the
141 /// instruction is really trivially rematerializable.
142 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
143 AliasAnalysis *AA) const;
146 /// These methods return the opcode of the frame setup/destroy instructions
147 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
148 /// order to abstract away the difference between operating with a frame
149 /// pointer and operating without, through the use of these two instructions.
151 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
152 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
154 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
155 unsigned getReturnOpcode() const { return ReturnOpcode; }
157 /// Returns the actual stack pointer adjustment made by an instruction
158 /// as part of a call sequence. By default, only call frame setup/destroy
159 /// instructions adjust the stack, but targets may want to override this
160 /// to enable more fine-grained adjustment, or adjust by a different value.
161 virtual int getSPAdjust(const MachineInstr &MI) const;
163 /// Return true if the instruction is a "coalescable" extension instruction.
164 /// That is, it's like a copy where it's legal for the source to overlap the
165 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
166 /// expected the pre-extension value is available as a subreg of the result
167 /// register. This also returns the sub-register index in SubIdx.
168 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
169 unsigned &SrcReg, unsigned &DstReg,
170 unsigned &SubIdx) const {
174 /// If the specified machine instruction is a direct
175 /// load from a stack slot, return the virtual or physical register number of
176 /// the destination along with the FrameIndex of the loaded stack slot. If
177 /// not, return 0. This predicate must return 0 if the instruction has
178 /// any side effects other than loading from the stack slot.
179 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
180 int &FrameIndex) const {
184 /// Check for post-frame ptr elimination stack locations as well.
185 /// This uses a heuristic so it isn't reliable for correctness.
186 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
187 int &FrameIndex) const {
191 /// If the specified machine instruction has a load from a stack slot,
192 /// return true along with the FrameIndex of the loaded stack slot and the
193 /// machine mem operand containing the reference.
194 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
195 /// any instructions that loads from the stack. This is just a hint, as some
196 /// cases may be missed.
197 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
198 const MachineMemOperand *&MMO,
199 int &FrameIndex) const;
201 /// If the specified machine instruction is a direct
202 /// store to a stack slot, return the virtual or physical register number of
203 /// the source reg along with the FrameIndex of the loaded stack slot. If
204 /// not, return 0. This predicate must return 0 if the instruction has
205 /// any side effects other than storing to the stack slot.
206 virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
207 int &FrameIndex) const {
211 /// Check for post-frame ptr elimination stack locations as well.
212 /// This uses a heuristic, so it isn't reliable for correctness.
213 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
214 int &FrameIndex) const {
218 /// If the specified machine instruction has a store to a stack slot,
219 /// return true along with the FrameIndex of the loaded stack slot and the
220 /// machine mem operand containing the reference.
221 /// If not, return false. Unlike isStoreToStackSlot,
222 /// this returns true for any instructions that stores to the
223 /// stack. This is just a hint, as some cases may be missed.
224 virtual bool hasStoreToStackSlot(const MachineInstr &MI,
225 const MachineMemOperand *&MMO,
226 int &FrameIndex) const;
228 /// Return true if the specified machine instruction
229 /// is a copy of one stack slot to another and has no other effect.
230 /// Provide the identity of the two frame indices.
231 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
232 int &SrcFrameIndex) const {
236 /// Compute the size in bytes and offset within a stack slot of a spilled
237 /// register or subregister.
239 /// \param [out] Size in bytes of the spilled value.
240 /// \param [out] Offset in bytes within the stack slot.
241 /// \returns true if both Size and Offset are successfully computed.
243 /// Not all subregisters have computable spill slots. For example,
244 /// subregisters registers may not be byte-sized, and a pair of discontiguous
245 /// subregisters has no single offset.
247 /// Targets with nontrivial bigendian implementations may need to override
248 /// this, particularly to support spilled vector registers.
249 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
250 unsigned &Size, unsigned &Offset,
251 const MachineFunction &MF) const;
253 /// Return true if the instruction is as cheap as a move instruction.
255 /// Targets for different archs need to override this, and different
256 /// micro-architectures can also be finely tuned inside.
257 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
258 return MI.isAsCheapAsAMove();
261 /// Return true if the instruction should be sunk by MachineSink.
263 /// MachineSink determines on its own whether the instruction is safe to sink;
264 /// this gives the target a hook to override the default behavior with regards
265 /// to which instructions should be sunk.
266 /// The default behavior is to not sink insert_subreg, subreg_to_reg, and
267 /// reg_sequence. These are meant to be close to the source to make it easier
269 virtual bool shouldSink(const MachineInstr &MI) const {
270 return !MI.isInsertSubreg() && !MI.isSubregToReg() && !MI.isRegSequence();
273 /// Re-issue the specified 'original' instruction at the
274 /// specific location targeting a new destination register.
275 /// The register in Orig->getOperand(0).getReg() will be substituted by
276 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
278 virtual void reMaterialize(MachineBasicBlock &MBB,
279 MachineBasicBlock::iterator MI, unsigned DestReg,
280 unsigned SubIdx, const MachineInstr &Orig,
281 const TargetRegisterInfo &TRI) const;
283 /// Create a duplicate of the Orig instruction in MF. This is like
284 /// MachineFunction::CloneMachineInstr(), but the target may update operands
285 /// that are required to be unique.
287 /// The instruction must be duplicable as indicated by isNotDuplicable().
288 virtual MachineInstr *duplicate(MachineInstr &Orig,
289 MachineFunction &MF) const;
291 /// This method must be implemented by targets that
292 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
293 /// may be able to convert a two-address instruction into one or more true
294 /// three-address instructions on demand. This allows the X86 target (for
295 /// example) to convert ADD and SHL instructions into LEA instructions if they
296 /// would require register copies due to two-addressness.
298 /// This method returns a null pointer if the transformation cannot be
299 /// performed, otherwise it returns the last new instruction.
301 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
303 LiveVariables *LV) const {
307 // This constant can be used as an input value of operand index passed to
308 // the method findCommutedOpIndices() to tell the method that the
309 // corresponding operand index is not pre-defined and that the method
310 // can pick any commutable operand.
311 static const unsigned CommuteAnyOperandIndex = ~0U;
313 /// This method commutes the operands of the given machine instruction MI.
315 /// The operands to be commuted are specified by their indices OpIdx1 and
316 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
317 /// 'CommuteAnyOperandIndex', which means that the method is free to choose
318 /// any arbitrarily chosen commutable operand. If both arguments are set to
319 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
320 /// operands; then commutes them if such operands could be found.
322 /// If NewMI is false, MI is modified in place and returned; otherwise, a
323 /// new machine instruction is created and returned.
325 /// Do not call this method for a non-commutable instruction or
326 /// for non-commuable operands.
327 /// Even though the instruction is commutable, the method may still
328 /// fail to commute the operands, null pointer is returned in such cases.
330 commuteInstruction(MachineInstr &MI, bool NewMI = false,
331 unsigned OpIdx1 = CommuteAnyOperandIndex,
332 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
334 /// Returns true iff the routine could find two commutable operands in the
335 /// given machine instruction.
336 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
337 /// If any of the INPUT values is set to the special value
338 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
339 /// operand, then returns its index in the corresponding argument.
340 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
341 /// looks for 2 commutable operands.
342 /// If INPUT values refer to some operands of MI, then the method simply
343 /// returns true if the corresponding operands are commutable and returns
346 /// For example, calling this method this way:
347 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
348 /// findCommutedOpIndices(MI, Op1, Op2);
349 /// can be interpreted as a query asking to find an operand that would be
350 /// commutable with the operand#1.
351 virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
352 unsigned &SrcOpIdx2) const;
354 /// A pair composed of a register and a sub-register index.
355 /// Used to give some type checking when modeling Reg:SubReg.
356 struct RegSubRegPair {
359 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
360 : Reg(Reg), SubReg(SubReg) {}
362 /// A pair composed of a pair of a register and a sub-register index,
363 /// and another sub-register index.
364 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
365 struct RegSubRegPairAndIdx : RegSubRegPair {
367 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
369 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
372 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
374 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
375 /// the list is modeled as <Reg:SubReg, SubIdx>.
376 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
378 /// - vreg1:sub1, sub0
379 /// - vreg2<:0>, sub1
381 /// \returns true if it is possible to build such an input sequence
382 /// with the pair \p MI, \p DefIdx. False otherwise.
384 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
386 /// \note The generic implementation does not provide any support for
387 /// MI.isRegSequenceLike(). In other words, one has to override
388 /// getRegSequenceLikeInputs for target specific instructions.
390 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
391 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
393 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
395 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
396 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
397 /// - vreg1:sub1, sub0
399 /// \returns true if it is possible to build such an input sequence
400 /// with the pair \p MI, \p DefIdx. False otherwise.
402 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
404 /// \note The generic implementation does not provide any support for
405 /// MI.isExtractSubregLike(). In other words, one has to override
406 /// getExtractSubregLikeInputs for target specific instructions.
408 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
409 RegSubRegPairAndIdx &InputReg) const;
411 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
413 /// \p [out] BaseReg and \p [out] InsertedReg contain
414 /// the equivalent inputs of INSERT_SUBREG.
415 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
416 /// - BaseReg: vreg0:sub0
417 /// - InsertedReg: vreg1:sub1, sub3
419 /// \returns true if it is possible to build such an input sequence
420 /// with the pair \p MI, \p DefIdx. False otherwise.
422 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
424 /// \note The generic implementation does not provide any support for
425 /// MI.isInsertSubregLike(). In other words, one has to override
426 /// getInsertSubregLikeInputs for target specific instructions.
428 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
429 RegSubRegPair &BaseReg,
430 RegSubRegPairAndIdx &InsertedReg) const;
433 /// Return true if two machine instructions would produce identical values.
434 /// By default, this is only true when the two instructions
435 /// are deemed identical except for defs. If this function is called when the
436 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
437 /// aggressive checks.
438 virtual bool produceSameValue(const MachineInstr &MI0,
439 const MachineInstr &MI1,
440 const MachineRegisterInfo *MRI = nullptr) const;
442 /// Analyze the branching code at the end of MBB, returning
443 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
444 /// implemented for a target). Upon success, this returns false and returns
445 /// with the following information in various cases:
447 /// 1. If this block ends with no branches (it just falls through to its succ)
448 /// just return false, leaving TBB/FBB null.
449 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
450 /// the destination block.
451 /// 3. If this block ends with a conditional branch and it falls through to a
452 /// successor block, it sets TBB to be the branch destination block and a
453 /// list of operands that evaluate the condition. These operands can be
454 /// passed to other TargetInstrInfo methods to create new branches.
455 /// 4. If this block ends with a conditional branch followed by an
456 /// unconditional branch, it returns the 'true' destination in TBB, the
457 /// 'false' destination in FBB, and a list of operands that evaluate the
458 /// condition. These operands can be passed to other TargetInstrInfo
459 /// methods to create new branches.
461 /// Note that RemoveBranch and InsertBranch must be implemented to support
462 /// cases where this method returns success.
464 /// If AllowModify is true, then this routine is allowed to modify the basic
465 /// block (e.g. delete instructions after the unconditional branch).
467 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
468 /// before calling this function.
469 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
470 MachineBasicBlock *&FBB,
471 SmallVectorImpl<MachineOperand> &Cond,
472 bool AllowModify = false) const {
476 /// Represents a predicate at the MachineFunction level. The control flow a
477 /// MachineBranchPredicate represents is:
479 /// Reg <def>= LHS `Predicate` RHS == ConditionDef
480 /// if Reg then goto TrueDest else goto FalseDest
482 struct MachineBranchPredicate {
483 enum ComparePredicate {
484 PRED_EQ, // True if two values are equal
485 PRED_NE, // True if two values are not equal
486 PRED_INVALID // Sentinel value
489 ComparePredicate Predicate;
492 MachineBasicBlock *TrueDest;
493 MachineBasicBlock *FalseDest;
494 MachineInstr *ConditionDef;
496 /// SingleUseCondition is true if ConditionDef is dead except for the
497 /// branch(es) at the end of the basic block.
499 bool SingleUseCondition;
501 explicit MachineBranchPredicate()
502 : Predicate(PRED_INVALID), LHS(MachineOperand::CreateImm(0)),
503 RHS(MachineOperand::CreateImm(0)), TrueDest(nullptr),
504 FalseDest(nullptr), ConditionDef(nullptr), SingleUseCondition(false) {
508 /// Analyze the branching code at the end of MBB and parse it into the
509 /// MachineBranchPredicate structure if possible. Returns false on success
510 /// and true on failure.
512 /// If AllowModify is true, then this routine is allowed to modify the basic
513 /// block (e.g. delete instructions after the unconditional branch).
515 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
516 MachineBranchPredicate &MBP,
517 bool AllowModify = false) const {
521 /// Remove the branching code at the end of the specific MBB.
522 /// This is only invoked in cases where AnalyzeBranch returns success. It
523 /// returns the number of instructions that were removed.
524 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
525 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
528 /// Insert branch code into the end of the specified MachineBasicBlock.
529 /// The operands to this method are the same as those
530 /// returned by AnalyzeBranch. This is only invoked in cases where
531 /// AnalyzeBranch returns success. It returns the number of instructions
534 /// It is also invoked by tail merging to add unconditional branches in
535 /// cases where AnalyzeBranch doesn't apply because there was no original
536 /// branch to analyze. At least this much must be implemented, else tail
537 /// merging needs to be disabled.
539 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
540 /// before calling this function.
541 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
542 MachineBasicBlock *FBB,
543 ArrayRef<MachineOperand> Cond,
544 const DebugLoc &DL) const {
545 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
548 /// Delete the instruction OldInst and everything after it, replacing it with
549 /// an unconditional branch to NewDest. This is used by the tail merging pass.
550 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
551 MachineBasicBlock *NewDest) const;
553 /// Get an instruction that performs an unconditional branch to the given
556 getUnconditionalBranch(MCInst &MI,
557 const MCSymbolRefExpr *BranchTarget) const {
558 llvm_unreachable("Target didn't implement "
559 "TargetInstrInfo::getUnconditionalBranch!");
562 /// Get a machine trap instruction.
563 virtual void getTrap(MCInst &MI) const {
564 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!");
567 /// Get a number of bytes that suffices to hold
568 /// either the instruction returned by getUnconditionalBranch or the
569 /// instruction returned by getTrap. This only makes sense because
570 /// getUnconditionalBranch returns a single, specific instruction. This
571 /// information is needed by the jumptable construction code, since it must
572 /// decide how many bytes to use for a jumptable entry so it can generate the
575 /// Note that if the jumptable instruction requires alignment, then that
576 /// alignment should be factored into this required bound so that the
577 /// resulting bound gives the right alignment for the instruction.
578 virtual unsigned getJumpInstrTableEntryBound() const {
579 // This method gets called by LLVMTargetMachine always, so it can't fail
580 // just because there happens to be no implementation for this target.
581 // Any code that tries to use a jumptable annotation without defining
582 // getUnconditionalBranch on the appropriate Target will fail anyway, and
583 // the value returned here won't matter in that case.
587 /// Return true if it's legal to split the given basic
588 /// block at the specified instruction (i.e. instruction would be the start
589 /// of a new basic block).
590 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
591 MachineBasicBlock::iterator MBBI) const {
595 /// Return true if it's profitable to predicate
596 /// instructions with accumulated instruction latency of "NumCycles"
597 /// of the specified basic block, where the probability of the instructions
598 /// being executed is given by Probability, and Confidence is a measure
599 /// of our confidence that it will be properly predicted.
601 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
602 unsigned ExtraPredCycles,
603 BranchProbability Probability) const {
607 /// Second variant of isProfitableToIfCvt. This one
608 /// checks for the case where two basic blocks from true and false path
609 /// of a if-then-else (diamond) are predicated on mutally exclusive
610 /// predicates, where the probability of the true path being taken is given
611 /// by Probability, and Confidence is a measure of our confidence that it
612 /// will be properly predicted.
614 isProfitableToIfCvt(MachineBasicBlock &TMBB,
615 unsigned NumTCycles, unsigned ExtraTCycles,
616 MachineBasicBlock &FMBB,
617 unsigned NumFCycles, unsigned ExtraFCycles,
618 BranchProbability Probability) const {
622 /// Return true if it's profitable for if-converter to duplicate instructions
623 /// of specified accumulated instruction latencies in the specified MBB to
624 /// enable if-conversion.
625 /// The probability of the instructions being executed is given by
626 /// Probability, and Confidence is a measure of our confidence that it
627 /// will be properly predicted.
629 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
630 BranchProbability Probability) const {
634 /// Return true if it's profitable to unpredicate
635 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
636 /// exclusive predicates.
644 /// This may be profitable is conditional instructions are always executed.
645 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
646 MachineBasicBlock &FMBB) const {
650 /// Return true if it is possible to insert a select
651 /// instruction that chooses between TrueReg and FalseReg based on the
652 /// condition code in Cond.
654 /// When successful, also return the latency in cycles from TrueReg,
655 /// FalseReg, and Cond to the destination register. In most cases, a select
656 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
658 /// Some x86 implementations have 2-cycle cmov instructions.
660 /// @param MBB Block where select instruction would be inserted.
661 /// @param Cond Condition returned by AnalyzeBranch.
662 /// @param TrueReg Virtual register to select when Cond is true.
663 /// @param FalseReg Virtual register to select when Cond is false.
664 /// @param CondCycles Latency from Cond+Branch to select output.
665 /// @param TrueCycles Latency from TrueReg to select output.
666 /// @param FalseCycles Latency from FalseReg to select output.
667 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
668 ArrayRef<MachineOperand> Cond,
669 unsigned TrueReg, unsigned FalseReg,
671 int &TrueCycles, int &FalseCycles) const {
675 /// Insert a select instruction into MBB before I that will copy TrueReg to
676 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
678 /// This function can only be called after canInsertSelect() returned true.
679 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
680 /// that the same flags or registers required by Cond are available at the
683 /// @param MBB Block where select instruction should be inserted.
684 /// @param I Insertion point.
685 /// @param DL Source location for debugging.
686 /// @param DstReg Virtual register to be defined by select instruction.
687 /// @param Cond Condition as computed by AnalyzeBranch.
688 /// @param TrueReg Virtual register to copy when Cond is true.
689 /// @param FalseReg Virtual register to copy when Cons is false.
690 virtual void insertSelect(MachineBasicBlock &MBB,
691 MachineBasicBlock::iterator I, const DebugLoc &DL,
692 unsigned DstReg, ArrayRef<MachineOperand> Cond,
693 unsigned TrueReg, unsigned FalseReg) const {
694 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
697 /// Analyze the given select instruction, returning true if
698 /// it cannot be understood. It is assumed that MI->isSelect() is true.
700 /// When successful, return the controlling condition and the operands that
701 /// determine the true and false result values.
703 /// Result = SELECT Cond, TrueOp, FalseOp
705 /// Some targets can optimize select instructions, for example by predicating
706 /// the instruction defining one of the operands. Such targets should set
709 /// @param MI Select instruction to analyze.
710 /// @param Cond Condition controlling the select.
711 /// @param TrueOp Operand number of the value selected when Cond is true.
712 /// @param FalseOp Operand number of the value selected when Cond is false.
713 /// @param Optimizable Returned as true if MI is optimizable.
714 /// @returns False on success.
715 virtual bool analyzeSelect(const MachineInstr &MI,
716 SmallVectorImpl<MachineOperand> &Cond,
717 unsigned &TrueOp, unsigned &FalseOp,
718 bool &Optimizable) const {
719 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
723 /// Given a select instruction that was understood by
724 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
725 /// merging it with one of its operands. Returns NULL on failure.
727 /// When successful, returns the new select instruction. The client is
728 /// responsible for deleting MI.
730 /// If both sides of the select can be optimized, PreferFalse is used to pick
733 /// @param MI Optimizable select instruction.
734 /// @param NewMIs Set that record all MIs in the basic block up to \p
735 /// MI. Has to be updated with any newly created MI or deleted ones.
736 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
737 /// @returns Optimized instruction or NULL.
738 virtual MachineInstr *optimizeSelect(MachineInstr &MI,
739 SmallPtrSetImpl<MachineInstr *> &NewMIs,
740 bool PreferFalse = false) const {
741 // This function must be implemented if Optimizable is ever set.
742 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
745 /// Emit instructions to copy a pair of physical registers.
747 /// This function should support copies within any legal register class as
748 /// well as any cross-class copies created during instruction selection.
750 /// The source and destination registers may overlap, which may require a
751 /// careful implementation when multiple copy instructions are required for
752 /// large registers. See for example the ARM target.
753 virtual void copyPhysReg(MachineBasicBlock &MBB,
754 MachineBasicBlock::iterator MI, const DebugLoc &DL,
755 unsigned DestReg, unsigned SrcReg,
756 bool KillSrc) const {
757 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
760 /// Store the specified register of the given register class to the specified
761 /// stack frame index. The store instruction is to be added to the given
762 /// machine basic block before the specified machine instruction. If isKill
763 /// is true, the register operand is the last use and must be marked kill.
764 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
765 MachineBasicBlock::iterator MI,
766 unsigned SrcReg, bool isKill, int FrameIndex,
767 const TargetRegisterClass *RC,
768 const TargetRegisterInfo *TRI) const {
769 llvm_unreachable("Target didn't implement "
770 "TargetInstrInfo::storeRegToStackSlot!");
773 /// Load the specified register of the given register class from the specified
774 /// stack frame index. The load instruction is to be added to the given
775 /// machine basic block before the specified machine instruction.
776 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
777 MachineBasicBlock::iterator MI,
778 unsigned DestReg, int FrameIndex,
779 const TargetRegisterClass *RC,
780 const TargetRegisterInfo *TRI) const {
781 llvm_unreachable("Target didn't implement "
782 "TargetInstrInfo::loadRegFromStackSlot!");
785 /// This function is called for all pseudo instructions
786 /// that remain after register allocation. Many pseudo instructions are
787 /// created to help register allocation. This is the place to convert them
788 /// into real instructions. The target can edit MI in place, or it can insert
789 /// new instructions and erase MI. The function should return true if
790 /// anything was changed.
791 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
793 /// Attempt to fold a load or store of the specified stack
794 /// slot into the specified machine instruction for the specified operand(s).
795 /// If this is possible, a new instruction is returned with the specified
796 /// operand folded, otherwise NULL is returned.
797 /// The new instruction is inserted before MI, and the client is responsible
798 /// for removing the old instruction.
799 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
801 LiveIntervals *LIS = nullptr) const;
803 /// Same as the previous version except it allows folding of any load and
804 /// store from / to any address, not just from a specific stack slot.
805 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
806 MachineInstr &LoadMI,
807 LiveIntervals *LIS = nullptr) const;
809 /// Return true when there is potentially a faster code sequence
810 /// for an instruction chain ending in \p Root. All potential patterns are
811 /// returned in the \p Pattern vector. Pattern should be sorted in priority
812 /// order since the pattern evaluator stops checking as soon as it finds a
814 /// \param Root - Instruction that could be combined with one of its operands
815 /// \param Patterns - Vector of possible combination patterns
816 virtual bool getMachineCombinerPatterns(
818 SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
820 /// Return true when a code sequence can improve throughput. It
821 /// should be called only for instructions in loops.
822 /// \param Pattern - combiner pattern
823 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
825 /// Return true if the input \P Inst is part of a chain of dependent ops
826 /// that are suitable for reassociation, otherwise return false.
827 /// If the instruction's operands must be commuted to have a previous
828 /// instruction of the same type define the first source operand, \P Commuted
829 /// will be set to true.
830 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
832 /// Return true when \P Inst is both associative and commutative.
833 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
837 /// Return true when \P Inst has reassociable operands in the same \P MBB.
838 virtual bool hasReassociableOperands(const MachineInstr &Inst,
839 const MachineBasicBlock *MBB) const;
841 /// Return true when \P Inst has reassociable sibling.
842 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
844 /// When getMachineCombinerPatterns() finds patterns, this function generates
845 /// the instructions that could replace the original code sequence. The client
846 /// has to decide whether the actual replacement is beneficial or not.
847 /// \param Root - Instruction that could be combined with one of its operands
848 /// \param Pattern - Combination pattern for Root
849 /// \param InsInstrs - Vector of new instructions that implement P
850 /// \param DelInstrs - Old instructions, including Root, that could be
851 /// replaced by InsInstr
852 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
853 /// InsInstr that defines it
854 virtual void genAlternativeCodeSequence(
855 MachineInstr &Root, MachineCombinerPattern Pattern,
856 SmallVectorImpl<MachineInstr *> &InsInstrs,
857 SmallVectorImpl<MachineInstr *> &DelInstrs,
858 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
860 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
861 /// reduce critical path length.
862 void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
863 MachineCombinerPattern Pattern,
864 SmallVectorImpl<MachineInstr *> &InsInstrs,
865 SmallVectorImpl<MachineInstr *> &DelInstrs,
866 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
868 /// This is an architecture-specific helper function of reassociateOps.
869 /// Set special operand attributes for new instructions after reassociation.
870 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
871 MachineInstr &NewMI1,
872 MachineInstr &NewMI2) const {
875 /// Return true when a target supports MachineCombiner.
876 virtual bool useMachineCombiner() const { return false; }
879 /// Target-dependent implementation for foldMemoryOperand.
880 /// Target-independent code in foldMemoryOperand will
881 /// take care of adding a MachineMemOperand to the newly created instruction.
882 /// The instruction and any auxiliary instructions necessary will be inserted
884 virtual MachineInstr *
885 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
886 ArrayRef<unsigned> Ops,
887 MachineBasicBlock::iterator InsertPt, int FrameIndex,
888 LiveIntervals *LIS = nullptr) const {
892 /// Target-dependent implementation for foldMemoryOperand.
893 /// Target-independent code in foldMemoryOperand will
894 /// take care of adding a MachineMemOperand to the newly created instruction.
895 /// The instruction and any auxiliary instructions necessary will be inserted
897 virtual MachineInstr *foldMemoryOperandImpl(
898 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
899 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
900 LiveIntervals *LIS = nullptr) const {
904 /// \brief Target-dependent implementation of getRegSequenceInputs.
906 /// \returns true if it is possible to build the equivalent
907 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
909 /// \pre MI.isRegSequenceLike().
911 /// \see TargetInstrInfo::getRegSequenceInputs.
912 virtual bool getRegSequenceLikeInputs(
913 const MachineInstr &MI, unsigned DefIdx,
914 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
918 /// \brief Target-dependent implementation of getExtractSubregInputs.
920 /// \returns true if it is possible to build the equivalent
921 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
923 /// \pre MI.isExtractSubregLike().
925 /// \see TargetInstrInfo::getExtractSubregInputs.
926 virtual bool getExtractSubregLikeInputs(
927 const MachineInstr &MI, unsigned DefIdx,
928 RegSubRegPairAndIdx &InputReg) const {
932 /// \brief Target-dependent implementation of getInsertSubregInputs.
934 /// \returns true if it is possible to build the equivalent
935 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
937 /// \pre MI.isInsertSubregLike().
939 /// \see TargetInstrInfo::getInsertSubregInputs.
941 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
942 RegSubRegPair &BaseReg,
943 RegSubRegPairAndIdx &InsertedReg) const {
948 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
949 /// a store or a load and a store into two or more instruction. If this is
950 /// possible, returns true as well as the new instructions by reference.
952 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
953 bool UnfoldLoad, bool UnfoldStore,
954 SmallVectorImpl<MachineInstr *> &NewMIs) const {
958 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
959 SmallVectorImpl<SDNode*> &NewNodes) const {
963 /// Returns the opcode of the would be new
964 /// instruction after load / store are unfolded from an instruction of the
965 /// specified opcode. It returns zero if the specified unfolding is not
966 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
967 /// index of the operand which will hold the register holding the loaded
969 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
970 bool UnfoldLoad, bool UnfoldStore,
971 unsigned *LoadRegIndex = nullptr) const {
975 /// This is used by the pre-regalloc scheduler to determine if two loads are
976 /// loading from the same base address. It should only return true if the base
977 /// pointers are the same and the only differences between the two addresses
978 /// are the offset. It also returns the offsets by reference.
979 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
980 int64_t &Offset1, int64_t &Offset2) const {
984 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
985 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
986 /// On some targets if two loads are loading from
987 /// addresses in the same cache line, it's better if they are scheduled
988 /// together. This function takes two integers that represent the load offsets
989 /// from the common base address. It returns true if it decides it's desirable
990 /// to schedule the two loads together. "NumLoads" is the number of loads that
991 /// have already been scheduled after Load1.
992 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
993 int64_t Offset1, int64_t Offset2,
994 unsigned NumLoads) const {
998 /// Get the base register and byte offset of an instruction that reads/writes
1000 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1002 const TargetRegisterInfo *TRI) const {
1006 virtual bool enableClusterLoads() const { return false; }
1008 virtual bool enableClusterStores() const { return false; }
1010 virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt,
1011 MachineInstr &SecondLdSt,
1012 unsigned NumLoads) const {
1016 /// Can this target fuse the given instructions if they are scheduled
1018 virtual bool shouldScheduleAdjacent(MachineInstr &First,
1019 MachineInstr &Second) const {
1023 /// Reverses the branch condition of the specified condition list,
1024 /// returning false on success and true if it cannot be reversed.
1026 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1030 /// Insert a noop into the instruction stream at the specified point.
1031 virtual void insertNoop(MachineBasicBlock &MBB,
1032 MachineBasicBlock::iterator MI) const;
1035 /// Return the noop instruction to use for a noop.
1036 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
1039 /// Returns true if the instruction is already predicated.
1040 virtual bool isPredicated(const MachineInstr &MI) const {
1044 /// Returns true if the instruction is a
1045 /// terminator instruction that has not been predicated.
1046 virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1048 /// Convert the instruction into a predicated instruction.
1049 /// It returns true if the operation was successful.
1050 virtual bool PredicateInstruction(MachineInstr &MI,
1051 ArrayRef<MachineOperand> Pred) const;
1053 /// Returns true if the first specified predicate
1054 /// subsumes the second, e.g. GE subsumes GT.
1056 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1057 ArrayRef<MachineOperand> Pred2) const {
1061 /// If the specified instruction defines any predicate
1062 /// or condition code register(s) used for predication, returns true as well
1063 /// as the definition predicate(s) by reference.
1064 virtual bool DefinesPredicate(MachineInstr &MI,
1065 std::vector<MachineOperand> &Pred) const {
1069 /// Return true if the specified instruction can be predicated.
1070 /// By default, this returns true for every instruction with a
1071 /// PredicateOperand.
1072 virtual bool isPredicable(MachineInstr &MI) const {
1073 return MI.getDesc().isPredicable();
1076 /// Return true if it's safe to move a machine
1077 /// instruction that defines the specified register class.
1078 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1082 /// Test if the given instruction should be considered a scheduling boundary.
1083 /// This primarily includes labels and terminators.
1084 virtual bool isSchedulingBoundary(const MachineInstr &MI,
1085 const MachineBasicBlock *MBB,
1086 const MachineFunction &MF) const;
1088 /// Measure the specified inline asm to determine an approximation of its
1090 virtual unsigned getInlineAsmLength(const char *Str,
1091 const MCAsmInfo &MAI) const;
1093 /// Allocate and return a hazard recognizer to use for this target when
1094 /// scheduling the machine instructions before register allocation.
1095 virtual ScheduleHazardRecognizer*
1096 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1097 const ScheduleDAG *DAG) const;
1099 /// Allocate and return a hazard recognizer to use for this target when
1100 /// scheduling the machine instructions before register allocation.
1101 virtual ScheduleHazardRecognizer*
1102 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
1103 const ScheduleDAG *DAG) const;
1105 /// Allocate and return a hazard recognizer to use for this target when
1106 /// scheduling the machine instructions after register allocation.
1107 virtual ScheduleHazardRecognizer*
1108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
1109 const ScheduleDAG *DAG) const;
1111 /// Allocate and return a hazard recognizer to use for by non-scheduling
1113 virtual ScheduleHazardRecognizer*
1114 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1118 /// Provide a global flag for disabling the PreRA hazard recognizer that
1119 /// targets may choose to honor.
1120 bool usePreRAHazardRecognizer() const;
1122 /// For a comparison instruction, return the source registers
1123 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1124 /// compares against in CmpValue. Return true if the comparison instruction
1125 /// can be analyzed.
1126 virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1127 unsigned &SrcReg2, int &Mask, int &Value) const {
1131 /// See if the comparison instruction can be converted
1132 /// into something more efficient. E.g., on ARM most instructions can set the
1133 /// flags register, obviating the need for a separate CMP.
1134 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1135 unsigned SrcReg2, int Mask, int Value,
1136 const MachineRegisterInfo *MRI) const {
1139 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1141 /// Try to remove the load by folding it to a register operand at the use.
1142 /// We fold the load instructions if and only if the
1143 /// def and use are in the same BB. We only look at one load and see
1144 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1145 /// defined by the load we are trying to fold. DefMI returns the machine
1146 /// instruction that defines FoldAsLoadDefReg, and the function returns
1147 /// the machine instruction generated due to folding.
1148 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1149 const MachineRegisterInfo *MRI,
1150 unsigned &FoldAsLoadDefReg,
1151 MachineInstr *&DefMI) const {
1155 /// 'Reg' is known to be defined by a move immediate instruction,
1156 /// try to fold the immediate into the use instruction.
1157 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1158 /// then the caller may assume that DefMI has been erased from its parent
1159 /// block. The caller may assume that it will not be erased by this
1160 /// function otherwise.
1161 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1162 unsigned Reg, MachineRegisterInfo *MRI) const {
1166 /// Return the number of u-operations the given machine
1167 /// instruction will be decoded to on the target cpu. The itinerary's
1168 /// IssueWidth is the number of microops that can be dispatched each
1169 /// cycle. An instruction with zero microops takes no dispatch resources.
1170 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1171 const MachineInstr &MI) const;
1173 /// Return true for pseudo instructions that don't consume any
1174 /// machine resources in their current form. These are common cases that the
1175 /// scheduler should consider free, rather than conservatively handling them
1176 /// as instructions with no itinerary.
1177 bool isZeroCost(unsigned Opcode) const {
1178 return Opcode <= TargetOpcode::COPY;
1181 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1182 SDNode *DefNode, unsigned DefIdx,
1183 SDNode *UseNode, unsigned UseIdx) const;
1185 /// Compute and return the use operand latency of a given pair of def and use.
1186 /// In most cases, the static scheduling itinerary was enough to determine the
1187 /// operand latency. But it may not be possible for instructions with variable
1188 /// number of defs / uses.
1190 /// This is a raw interface to the itinerary that may be directly overridden
1191 /// by a target. Use computeOperandLatency to get the best estimate of
1193 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1194 const MachineInstr &DefMI, unsigned DefIdx,
1195 const MachineInstr &UseMI,
1196 unsigned UseIdx) const;
1198 /// Compute and return the latency of the given data dependent def and use
1199 /// when the operand indices are already known. UseMI may be \c nullptr for
1202 /// FindMin may be set to get the minimum vs. expected latency. Minimum
1203 /// latency is used for scheduling groups, while expected latency is for
1204 /// instruction cost and critical path.
1206 /// Depending on the subtarget's itinerary properties, this may or may not
1207 /// need to call getOperandLatency(). For most subtargets, we don't need
1208 /// DefIdx or UseIdx to compute min latency.
1209 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
1210 const MachineInstr &DefMI, unsigned DefIdx,
1211 const MachineInstr *UseMI,
1212 unsigned UseIdx) const;
1214 /// Compute the instruction latency of a given instruction.
1215 /// If the instruction has higher cost when predicated, it's returned via
1217 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1218 const MachineInstr &MI,
1219 unsigned *PredCost = nullptr) const;
1221 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1223 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1224 SDNode *Node) const;
1226 /// Return the default expected latency for a def based on its opcode.
1227 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1228 const MachineInstr &DefMI) const;
1230 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1231 const MachineInstr &DefMI) const;
1233 /// Return true if this opcode has high latency to its result.
1234 virtual bool isHighLatencyDef(int opc) const { return false; }
1236 /// Compute operand latency between a def of 'Reg'
1237 /// and a use in the current loop. Return true if the target considered
1238 /// it 'high'. This is used by optimization passes such as machine LICM to
1239 /// determine whether it makes sense to hoist an instruction out even in a
1240 /// high register pressure situation.
1241 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1242 const MachineRegisterInfo *MRI,
1243 const MachineInstr &DefMI, unsigned DefIdx,
1244 const MachineInstr &UseMI,
1245 unsigned UseIdx) const {
1249 /// Compute operand latency of a def of 'Reg'. Return true
1250 /// if the target considered it 'low'.
1251 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1252 const MachineInstr &DefMI,
1253 unsigned DefIdx) const;
1255 /// Perform target-specific instruction verification.
1256 virtual bool verifyInstruction(const MachineInstr &MI,
1257 StringRef &ErrInfo) const {
1261 /// Return the current execution domain and bit mask of
1262 /// possible domains for instruction.
1264 /// Some micro-architectures have multiple execution domains, and multiple
1265 /// opcodes that perform the same operation in different domains. For
1266 /// example, the x86 architecture provides the por, orps, and orpd
1267 /// instructions that all do the same thing. There is a latency penalty if a
1268 /// register is written in one domain and read in another.
1270 /// This function returns a pair (domain, mask) containing the execution
1271 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1272 /// function can be used to change the opcode to one of the domains in the
1273 /// bit mask. Instructions whose execution domain can't be changed should
1274 /// return a 0 mask.
1276 /// The execution domain numbers don't have any special meaning except domain
1277 /// 0 is used for instructions that are not associated with any interesting
1278 /// execution domain.
1280 virtual std::pair<uint16_t, uint16_t>
1281 getExecutionDomain(const MachineInstr &MI) const {
1282 return std::make_pair(0, 0);
1285 /// Change the opcode of MI to execute in Domain.
1287 /// The bit (1 << Domain) must be set in the mask returned from
1288 /// getExecutionDomain(MI).
1289 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1291 /// Returns the preferred minimum clearance
1292 /// before an instruction with an unwanted partial register update.
1294 /// Some instructions only write part of a register, and implicitly need to
1295 /// read the other parts of the register. This may cause unwanted stalls
1296 /// preventing otherwise unrelated instructions from executing in parallel in
1297 /// an out-of-order CPU.
1299 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1300 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1301 /// the instruction needs to wait for the old value of the register to become
1304 /// addps %xmm1, %xmm0
1305 /// movaps %xmm0, (%rax)
1306 /// cvtsi2ss %rbx, %xmm0
1308 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1309 /// instruction before it can issue, even though the high bits of %xmm0
1310 /// probably aren't needed.
1312 /// This hook returns the preferred clearance before MI, measured in
1313 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1314 /// instructions before MI. It should only return a positive value for
1315 /// unwanted dependencies. If the old bits of the defined register have
1316 /// useful values, or if MI is determined to otherwise read the dependency,
1317 /// the hook should return 0.
1319 /// The unwanted dependency may be handled by:
1321 /// 1. Allocating the same register for an MI def and use. That makes the
1322 /// unwanted dependency identical to a required dependency.
1324 /// 2. Allocating a register for the def that has no defs in the previous N
1327 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1328 /// allows the target to insert a dependency breaking instruction.
1331 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1332 const TargetRegisterInfo *TRI) const {
1333 // The default implementation returns 0 for no partial register dependency.
1337 /// \brief Return the minimum clearance before an instruction that reads an
1338 /// unused register.
1340 /// For example, AVX instructions may copy part of a register operand into
1341 /// the unused high bits of the destination register.
1343 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1345 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1346 /// false dependence on any previous write to %xmm0.
1348 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1349 /// does not take an operand index. Instead sets \p OpNum to the index of the
1350 /// unused register.
1351 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1352 const TargetRegisterInfo *TRI) const {
1353 // The default implementation returns 0 for no undef register dependency.
1357 /// Insert a dependency-breaking instruction
1358 /// before MI to eliminate an unwanted dependency on OpNum.
1360 /// If it wasn't possible to avoid a def in the last N instructions before MI
1361 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1362 /// unwanted dependency.
1364 /// On x86, an xorps instruction can be used as a dependency breaker:
1366 /// addps %xmm1, %xmm0
1367 /// movaps %xmm0, (%rax)
1368 /// xorps %xmm0, %xmm0
1369 /// cvtsi2ss %rbx, %xmm0
1371 /// An <imp-kill> operand should be added to MI if an instruction was
1372 /// inserted. This ties the instructions together in the post-ra scheduler.
1374 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1375 const TargetRegisterInfo *TRI) const {}
1377 /// Create machine specific model for scheduling.
1378 virtual DFAPacketizer *
1379 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1383 // Sometimes, it is possible for the target
1384 // to tell, even without aliasing information, that two MIs access different
1385 // memory addresses. This function returns true if two MIs access different
1386 // memory addresses and false otherwise.
1388 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1389 AliasAnalysis *AA = nullptr) const {
1390 assert((MIa.mayLoad() || MIa.mayStore()) &&
1391 "MIa must load from or modify a memory location");
1392 assert((MIb.mayLoad() || MIb.mayStore()) &&
1393 "MIb must load from or modify a memory location");
1397 /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1398 /// which is a heuristic used for CSE'ing phys reg defs.
1399 virtual unsigned getMachineCSELookAheadLimit () const {
1400 // The default lookahead is small to prevent unprofitable quadratic
1405 /// Return an array that contains the ids of the target indices (used for the
1406 /// TargetIndex machine operand) and their names.
1408 /// MIR Serialization is able to serialize only the target indices that are
1409 /// defined by this method.
1410 virtual ArrayRef<std::pair<int, const char *>>
1411 getSerializableTargetIndices() const {
1415 /// Decompose the machine operand's target flags into two values - the direct
1416 /// target flag value and any of bit flags that are applied.
1417 virtual std::pair<unsigned, unsigned>
1418 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1419 return std::make_pair(0u, 0u);
1422 /// Return an array that contains the direct target flag values and their
1425 /// MIR Serialization is able to serialize only the target flags that are
1426 /// defined by this method.
1427 virtual ArrayRef<std::pair<unsigned, const char *>>
1428 getSerializableDirectMachineOperandTargetFlags() const {
1432 /// Return an array that contains the bitmask target flag values and their
1435 /// MIR Serialization is able to serialize only the target flags that are
1436 /// defined by this method.
1437 virtual ArrayRef<std::pair<unsigned, const char *>>
1438 getSerializableBitmaskMachineOperandTargetFlags() const {
1443 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1444 unsigned CatchRetOpcode;
1445 unsigned ReturnOpcode;
1448 /// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1450 struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
1451 typedef DenseMapInfo<unsigned> RegInfo;
1453 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1454 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1455 RegInfo::getEmptyKey());
1457 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1458 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1459 RegInfo::getTombstoneKey());
1461 /// \brief Reuse getHashValue implementation from
1462 /// std::pair<unsigned, unsigned>.
1463 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1464 std::pair<unsigned, unsigned> PairVal =
1465 std::make_pair(Val.Reg, Val.SubReg);
1466 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1468 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1469 const TargetInstrInfo::RegSubRegPair &RHS) {
1470 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1471 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1475 } // end namespace llvm
1477 #endif // LLVM_TARGET_TARGETINSTRINFO_H