1 //===- llvm/Target/TargetInstrInfo.h - Instruction Info ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineCombinerPattern.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/Support/BranchProbability.h"
30 #include "llvm/Support/ErrorHandling.h"
40 class InstrItineraryData;
42 class MachineMemOperand;
43 class MachineRegisterInfo;
49 class ScheduleHazardRecognizer;
53 class TargetRegisterClass;
54 class TargetRegisterInfo;
55 class TargetSchedModel;
56 class TargetSubtargetInfo;
58 template<class T> class SmallVectorImpl;
60 //---------------------------------------------------------------------------
62 /// TargetInstrInfo - Interface to description of machine instruction set
64 class TargetInstrInfo : public MCInstrInfo {
66 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
67 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
68 : CallFrameSetupOpcode(CFSetupOpcode),
69 CallFrameDestroyOpcode(CFDestroyOpcode),
70 CatchRetOpcode(CatchRetOpcode),
71 ReturnOpcode(ReturnOpcode) {}
72 TargetInstrInfo(const TargetInstrInfo &) = delete;
73 TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
74 virtual ~TargetInstrInfo();
76 static bool isGenericOpcode(unsigned Opc) {
77 return Opc <= TargetOpcode::GENERIC_OP_END;
80 /// Given a machine instruction descriptor, returns the register
81 /// class constraint for OpNum, or NULL.
82 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
84 const TargetRegisterInfo *TRI,
85 const MachineFunction &MF) const;
87 /// Return true if the instruction is trivially rematerializable, meaning it
88 /// has no side effects and requires no operands that aren't always available.
89 /// This means the only allowed uses are constants and unallocatable physical
90 /// registers so that the instructions result is independent of the place
92 bool isTriviallyReMaterializable(const MachineInstr &MI,
93 AliasAnalysis *AA = nullptr) const {
94 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
95 (MI.getDesc().isRematerializable() &&
96 (isReallyTriviallyReMaterializable(MI, AA) ||
97 isReallyTriviallyReMaterializableGeneric(MI, AA)));
101 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
102 /// set, this hook lets the target specify whether the instruction is actually
103 /// trivially rematerializable, taking into consideration its operands. This
104 /// predicate must return false if the instruction has any side effects other
105 /// than producing a value, or if it requres any address registers that are
106 /// not always available.
107 /// Requirements must be check as stated in isTriviallyReMaterializable() .
108 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
109 AliasAnalysis *AA) const {
113 /// This method commutes the operands of the given machine instruction MI.
114 /// The operands to be commuted are specified by their indices OpIdx1 and
117 /// If a target has any instructions that are commutable but require
118 /// converting to different instructions or making non-trivial changes
119 /// to commute them, this method can be overloaded to do that.
120 /// The default implementation simply swaps the commutable operands.
122 /// If NewMI is false, MI is modified in place and returned; otherwise, a
123 /// new machine instruction is created and returned.
125 /// Do not call this method for a non-commutable instruction.
126 /// Even though the instruction is commutable, the method may still
127 /// fail to commute the operands, null pointer is returned in such cases.
128 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
130 unsigned OpIdx2) const;
132 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
133 /// operand indices to (ResultIdx1, ResultIdx2).
134 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
135 /// predefined to some indices or be undefined (designated by the special
136 /// value 'CommuteAnyOperandIndex').
137 /// The predefined result indices cannot be re-defined.
138 /// The function returns true iff after the result pair redefinition
139 /// the fixed result pair is equal to or equivalent to the source pair of
140 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
141 /// the pairs (x,y) and (y,x) are equivalent.
142 static bool fixCommutedOpIndices(unsigned &ResultIdx1,
143 unsigned &ResultIdx2,
144 unsigned CommutableOpIdx1,
145 unsigned CommutableOpIdx2);
148 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
149 /// set and the target hook isReallyTriviallyReMaterializable returns false,
150 /// this function does target-independent tests to determine if the
151 /// instruction is really trivially rematerializable.
152 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
153 AliasAnalysis *AA) const;
156 /// These methods return the opcode of the frame setup/destroy instructions
157 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
158 /// order to abstract away the difference between operating with a frame
159 /// pointer and operating without, through the use of these two instructions.
161 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
162 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
164 /// Returns true if the argument is a frame pseudo instruction.
165 bool isFrameInstr(const MachineInstr &I) const {
166 return I.getOpcode() == getCallFrameSetupOpcode() ||
167 I.getOpcode() == getCallFrameDestroyOpcode();
170 /// Returns true if the argument is a frame setup pseudo instruction.
171 bool isFrameSetup(const MachineInstr &I) const {
172 return I.getOpcode() == getCallFrameSetupOpcode();
175 /// Returns size of the frame associated with the given frame instruction.
176 /// For frame setup instruction this is frame that is set up space set up
177 /// after the instruction. For frame destroy instruction this is the frame
178 /// freed by the caller.
179 /// Note, in some cases a call frame (or a part of it) may be prepared prior
180 /// to the frame setup instruction. It occurs in the calls that involve
181 /// inalloca arguments. This function reports only the size of the frame part
182 /// that is set up between the frame setup and destroy pseudo instructions.
183 int64_t getFrameSize(const MachineInstr &I) const {
184 assert(isFrameInstr(I) && "Not a frame instruction");
185 assert(I.getOperand(0).getImm() >= 0);
186 return I.getOperand(0).getImm();
189 /// Returns the total frame size, which is made up of the space set up inside
190 /// the pair of frame start-stop instructions and the space that is set up
191 /// prior to the pair.
192 int64_t getFrameTotalSize(const MachineInstr &I) const {
193 if (isFrameSetup(I)) {
194 assert(I.getOperand(1).getImm() >= 0 && "Frame size must not be negative");
195 return getFrameSize(I) + I.getOperand(1).getImm();
197 return getFrameSize(I);
200 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
201 unsigned getReturnOpcode() const { return ReturnOpcode; }
203 /// Returns the actual stack pointer adjustment made by an instruction
204 /// as part of a call sequence. By default, only call frame setup/destroy
205 /// instructions adjust the stack, but targets may want to override this
206 /// to enable more fine-grained adjustment, or adjust by a different value.
207 virtual int getSPAdjust(const MachineInstr &MI) const;
209 /// Return true if the instruction is a "coalescable" extension instruction.
210 /// That is, it's like a copy where it's legal for the source to overlap the
211 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
212 /// expected the pre-extension value is available as a subreg of the result
213 /// register. This also returns the sub-register index in SubIdx.
214 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
215 unsigned &SrcReg, unsigned &DstReg,
216 unsigned &SubIdx) const {
220 /// If the specified machine instruction is a direct
221 /// load from a stack slot, return the virtual or physical register number of
222 /// the destination along with the FrameIndex of the loaded stack slot. If
223 /// not, return 0. This predicate must return 0 if the instruction has
224 /// any side effects other than loading from the stack slot.
225 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
226 int &FrameIndex) const {
230 /// Check for post-frame ptr elimination stack locations as well.
231 /// This uses a heuristic so it isn't reliable for correctness.
232 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
233 int &FrameIndex) const {
237 /// If the specified machine instruction has a load from a stack slot,
238 /// return true along with the FrameIndex of the loaded stack slot and the
239 /// machine mem operand containing the reference.
240 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
241 /// any instructions that loads from the stack. This is just a hint, as some
242 /// cases may be missed.
243 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
244 const MachineMemOperand *&MMO,
245 int &FrameIndex) const;
247 /// If the specified machine instruction is a direct
248 /// store to a stack slot, return the virtual or physical register number of
249 /// the source reg along with the FrameIndex of the loaded stack slot. If
250 /// not, return 0. This predicate must return 0 if the instruction has
251 /// any side effects other than storing to the stack slot.
252 virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
253 int &FrameIndex) const {
257 /// Check for post-frame ptr elimination stack locations as well.
258 /// This uses a heuristic, so it isn't reliable for correctness.
259 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
260 int &FrameIndex) const {
264 /// If the specified machine instruction has a store to a stack slot,
265 /// return true along with the FrameIndex of the loaded stack slot and the
266 /// machine mem operand containing the reference.
267 /// If not, return false. Unlike isStoreToStackSlot,
268 /// this returns true for any instructions that stores to the
269 /// stack. This is just a hint, as some cases may be missed.
270 virtual bool hasStoreToStackSlot(const MachineInstr &MI,
271 const MachineMemOperand *&MMO,
272 int &FrameIndex) const;
274 /// Return true if the specified machine instruction
275 /// is a copy of one stack slot to another and has no other effect.
276 /// Provide the identity of the two frame indices.
277 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
278 int &SrcFrameIndex) const {
282 /// Compute the size in bytes and offset within a stack slot of a spilled
283 /// register or subregister.
285 /// \param [out] Size in bytes of the spilled value.
286 /// \param [out] Offset in bytes within the stack slot.
287 /// \returns true if both Size and Offset are successfully computed.
289 /// Not all subregisters have computable spill slots. For example,
290 /// subregisters registers may not be byte-sized, and a pair of discontiguous
291 /// subregisters has no single offset.
293 /// Targets with nontrivial bigendian implementations may need to override
294 /// this, particularly to support spilled vector registers.
295 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
296 unsigned &Size, unsigned &Offset,
297 const MachineFunction &MF) const;
299 /// Returns the size in bytes of the specified MachineInstr, or ~0U
300 /// when this function is not implemented by a target.
301 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
305 /// Return true if the instruction is as cheap as a move instruction.
307 /// Targets for different archs need to override this, and different
308 /// micro-architectures can also be finely tuned inside.
309 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
310 return MI.isAsCheapAsAMove();
313 /// Return true if the instruction should be sunk by MachineSink.
315 /// MachineSink determines on its own whether the instruction is safe to sink;
316 /// this gives the target a hook to override the default behavior with regards
317 /// to which instructions should be sunk.
318 virtual bool shouldSink(const MachineInstr &MI) const {
322 /// Re-issue the specified 'original' instruction at the
323 /// specific location targeting a new destination register.
324 /// The register in Orig->getOperand(0).getReg() will be substituted by
325 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
327 virtual void reMaterialize(MachineBasicBlock &MBB,
328 MachineBasicBlock::iterator MI, unsigned DestReg,
329 unsigned SubIdx, const MachineInstr &Orig,
330 const TargetRegisterInfo &TRI) const;
332 /// Create a duplicate of the Orig instruction in MF. This is like
333 /// MachineFunction::CloneMachineInstr(), but the target may update operands
334 /// that are required to be unique.
336 /// The instruction must be duplicable as indicated by isNotDuplicable().
337 virtual MachineInstr *duplicate(MachineInstr &Orig,
338 MachineFunction &MF) const;
340 /// This method must be implemented by targets that
341 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
342 /// may be able to convert a two-address instruction into one or more true
343 /// three-address instructions on demand. This allows the X86 target (for
344 /// example) to convert ADD and SHL instructions into LEA instructions if they
345 /// would require register copies due to two-addressness.
347 /// This method returns a null pointer if the transformation cannot be
348 /// performed, otherwise it returns the last new instruction.
350 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
352 LiveVariables *LV) const {
356 // This constant can be used as an input value of operand index passed to
357 // the method findCommutedOpIndices() to tell the method that the
358 // corresponding operand index is not pre-defined and that the method
359 // can pick any commutable operand.
360 static const unsigned CommuteAnyOperandIndex = ~0U;
362 /// This method commutes the operands of the given machine instruction MI.
364 /// The operands to be commuted are specified by their indices OpIdx1 and
365 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
366 /// 'CommuteAnyOperandIndex', which means that the method is free to choose
367 /// any arbitrarily chosen commutable operand. If both arguments are set to
368 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
369 /// operands; then commutes them if such operands could be found.
371 /// If NewMI is false, MI is modified in place and returned; otherwise, a
372 /// new machine instruction is created and returned.
374 /// Do not call this method for a non-commutable instruction or
375 /// for non-commuable operands.
376 /// Even though the instruction is commutable, the method may still
377 /// fail to commute the operands, null pointer is returned in such cases.
379 commuteInstruction(MachineInstr &MI, bool NewMI = false,
380 unsigned OpIdx1 = CommuteAnyOperandIndex,
381 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
383 /// Returns true iff the routine could find two commutable operands in the
384 /// given machine instruction.
385 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
386 /// If any of the INPUT values is set to the special value
387 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
388 /// operand, then returns its index in the corresponding argument.
389 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
390 /// looks for 2 commutable operands.
391 /// If INPUT values refer to some operands of MI, then the method simply
392 /// returns true if the corresponding operands are commutable and returns
395 /// For example, calling this method this way:
396 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
397 /// findCommutedOpIndices(MI, Op1, Op2);
398 /// can be interpreted as a query asking to find an operand that would be
399 /// commutable with the operand#1.
400 virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
401 unsigned &SrcOpIdx2) const;
403 /// A pair composed of a register and a sub-register index.
404 /// Used to give some type checking when modeling Reg:SubReg.
405 struct RegSubRegPair {
409 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
410 : Reg(Reg), SubReg(SubReg) {}
413 /// A pair composed of a pair of a register and a sub-register index,
414 /// and another sub-register index.
415 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
416 struct RegSubRegPairAndIdx : RegSubRegPair {
419 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
421 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
424 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
426 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
427 /// the list is modeled as <Reg:SubReg, SubIdx>.
428 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
430 /// - vreg1:sub1, sub0
431 /// - vreg2<:0>, sub1
433 /// \returns true if it is possible to build such an input sequence
434 /// with the pair \p MI, \p DefIdx. False otherwise.
436 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
438 /// \note The generic implementation does not provide any support for
439 /// MI.isRegSequenceLike(). In other words, one has to override
440 /// getRegSequenceLikeInputs for target specific instructions.
442 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
443 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
445 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
447 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
448 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
449 /// - vreg1:sub1, sub0
451 /// \returns true if it is possible to build such an input sequence
452 /// with the pair \p MI, \p DefIdx. False otherwise.
454 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
456 /// \note The generic implementation does not provide any support for
457 /// MI.isExtractSubregLike(). In other words, one has to override
458 /// getExtractSubregLikeInputs for target specific instructions.
460 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
461 RegSubRegPairAndIdx &InputReg) const;
463 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
465 /// \p [out] BaseReg and \p [out] InsertedReg contain
466 /// the equivalent inputs of INSERT_SUBREG.
467 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
468 /// - BaseReg: vreg0:sub0
469 /// - InsertedReg: vreg1:sub1, sub3
471 /// \returns true if it is possible to build such an input sequence
472 /// with the pair \p MI, \p DefIdx. False otherwise.
474 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
476 /// \note The generic implementation does not provide any support for
477 /// MI.isInsertSubregLike(). In other words, one has to override
478 /// getInsertSubregLikeInputs for target specific instructions.
480 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
481 RegSubRegPair &BaseReg,
482 RegSubRegPairAndIdx &InsertedReg) const;
484 /// Return true if two machine instructions would produce identical values.
485 /// By default, this is only true when the two instructions
486 /// are deemed identical except for defs. If this function is called when the
487 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
488 /// aggressive checks.
489 virtual bool produceSameValue(const MachineInstr &MI0,
490 const MachineInstr &MI1,
491 const MachineRegisterInfo *MRI = nullptr) const;
493 /// \returns true if a branch from an instruction with opcode \p BranchOpc
494 /// bytes is capable of jumping to a position \p BrOffset bytes away.
495 virtual bool isBranchOffsetInRange(unsigned BranchOpc,
496 int64_t BrOffset) const {
497 llvm_unreachable("target did not implement");
500 /// \returns The block that branch instruction \p MI jumps to.
501 virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
502 llvm_unreachable("target did not implement");
505 /// Insert an unconditional indirect branch at the end of \p MBB to \p
506 /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
507 /// the offset of the position to insert the new branch.
509 /// \returns The number of bytes added to the block.
510 virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
511 MachineBasicBlock &NewDestBB,
513 int64_t BrOffset = 0,
514 RegScavenger *RS = nullptr) const {
515 llvm_unreachable("target did not implement");
518 /// Analyze the branching code at the end of MBB, returning
519 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
520 /// implemented for a target). Upon success, this returns false and returns
521 /// with the following information in various cases:
523 /// 1. If this block ends with no branches (it just falls through to its succ)
524 /// just return false, leaving TBB/FBB null.
525 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
526 /// the destination block.
527 /// 3. If this block ends with a conditional branch and it falls through to a
528 /// successor block, it sets TBB to be the branch destination block and a
529 /// list of operands that evaluate the condition. These operands can be
530 /// passed to other TargetInstrInfo methods to create new branches.
531 /// 4. If this block ends with a conditional branch followed by an
532 /// unconditional branch, it returns the 'true' destination in TBB, the
533 /// 'false' destination in FBB, and a list of operands that evaluate the
534 /// condition. These operands can be passed to other TargetInstrInfo
535 /// methods to create new branches.
537 /// Note that removeBranch and insertBranch must be implemented to support
538 /// cases where this method returns success.
540 /// If AllowModify is true, then this routine is allowed to modify the basic
541 /// block (e.g. delete instructions after the unconditional branch).
543 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
544 /// before calling this function.
545 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
546 MachineBasicBlock *&FBB,
547 SmallVectorImpl<MachineOperand> &Cond,
548 bool AllowModify = false) const {
552 /// Represents a predicate at the MachineFunction level. The control flow a
553 /// MachineBranchPredicate represents is:
555 /// Reg <def>= LHS `Predicate` RHS == ConditionDef
556 /// if Reg then goto TrueDest else goto FalseDest
558 struct MachineBranchPredicate {
559 enum ComparePredicate {
560 PRED_EQ, // True if two values are equal
561 PRED_NE, // True if two values are not equal
562 PRED_INVALID // Sentinel value
565 ComparePredicate Predicate = PRED_INVALID;
566 MachineOperand LHS = MachineOperand::CreateImm(0);
567 MachineOperand RHS = MachineOperand::CreateImm(0);
568 MachineBasicBlock *TrueDest = nullptr;
569 MachineBasicBlock *FalseDest = nullptr;
570 MachineInstr *ConditionDef = nullptr;
572 /// SingleUseCondition is true if ConditionDef is dead except for the
573 /// branch(es) at the end of the basic block.
575 bool SingleUseCondition = false;
577 explicit MachineBranchPredicate() = default;
580 /// Analyze the branching code at the end of MBB and parse it into the
581 /// MachineBranchPredicate structure if possible. Returns false on success
582 /// and true on failure.
584 /// If AllowModify is true, then this routine is allowed to modify the basic
585 /// block (e.g. delete instructions after the unconditional branch).
587 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
588 MachineBranchPredicate &MBP,
589 bool AllowModify = false) const {
593 /// Remove the branching code at the end of the specific MBB.
594 /// This is only invoked in cases where AnalyzeBranch returns success. It
595 /// returns the number of instructions that were removed.
596 /// If \p BytesRemoved is non-null, report the change in code size from the
597 /// removed instructions.
598 virtual unsigned removeBranch(MachineBasicBlock &MBB,
599 int *BytesRemoved = nullptr) const {
600 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
603 /// Insert branch code into the end of the specified MachineBasicBlock. The
604 /// operands to this method are the same as those returned by AnalyzeBranch.
605 /// This is only invoked in cases where AnalyzeBranch returns success. It
606 /// returns the number of instructions inserted. If \p BytesAdded is non-null,
607 /// report the change in code size from the added instructions.
609 /// It is also invoked by tail merging to add unconditional branches in
610 /// cases where AnalyzeBranch doesn't apply because there was no original
611 /// branch to analyze. At least this much must be implemented, else tail
612 /// merging needs to be disabled.
614 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
615 /// before calling this function.
616 virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
617 MachineBasicBlock *FBB,
618 ArrayRef<MachineOperand> Cond,
620 int *BytesAdded = nullptr) const {
621 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
624 unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
625 MachineBasicBlock *DestBB,
627 int *BytesAdded = nullptr) const {
628 return insertBranch(MBB, DestBB, nullptr,
629 ArrayRef<MachineOperand>(), DL, BytesAdded);
632 /// Analyze the loop code, return true if it cannot be understoo. Upon
633 /// success, this function returns false and returns information about the
634 /// induction variable and compare instruction used at the end.
635 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
636 MachineInstr *&CmpInst) const {
640 /// Generate code to reduce the loop iteration by one and check if the loop is
641 /// finished. Return the value/register of the the new loop count. We need
642 /// this function when peeling off one or more iterations of a loop. This
643 /// function assumes the nth iteration is peeled first.
644 virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
645 MachineInstr *IndVar, MachineInstr &Cmp,
646 SmallVectorImpl<MachineOperand> &Cond,
647 SmallVectorImpl<MachineInstr *> &PrevInsts,
648 unsigned Iter, unsigned MaxIter) const {
649 llvm_unreachable("Target didn't implement ReduceLoopCount");
652 /// Delete the instruction OldInst and everything after it, replacing it with
653 /// an unconditional branch to NewDest. This is used by the tail merging pass.
654 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
655 MachineBasicBlock *NewDest) const;
657 /// Return true if it's legal to split the given basic
658 /// block at the specified instruction (i.e. instruction would be the start
659 /// of a new basic block).
660 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
661 MachineBasicBlock::iterator MBBI) const {
665 /// Return true if it's profitable to predicate
666 /// instructions with accumulated instruction latency of "NumCycles"
667 /// of the specified basic block, where the probability of the instructions
668 /// being executed is given by Probability, and Confidence is a measure
669 /// of our confidence that it will be properly predicted.
671 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
672 unsigned ExtraPredCycles,
673 BranchProbability Probability) const {
677 /// Second variant of isProfitableToIfCvt. This one
678 /// checks for the case where two basic blocks from true and false path
679 /// of a if-then-else (diamond) are predicated on mutally exclusive
680 /// predicates, where the probability of the true path being taken is given
681 /// by Probability, and Confidence is a measure of our confidence that it
682 /// will be properly predicted.
684 isProfitableToIfCvt(MachineBasicBlock &TMBB,
685 unsigned NumTCycles, unsigned ExtraTCycles,
686 MachineBasicBlock &FMBB,
687 unsigned NumFCycles, unsigned ExtraFCycles,
688 BranchProbability Probability) const {
692 /// Return true if it's profitable for if-converter to duplicate instructions
693 /// of specified accumulated instruction latencies in the specified MBB to
694 /// enable if-conversion.
695 /// The probability of the instructions being executed is given by
696 /// Probability, and Confidence is a measure of our confidence that it
697 /// will be properly predicted.
699 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
700 BranchProbability Probability) const {
704 /// Return true if it's profitable to unpredicate
705 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
706 /// exclusive predicates.
714 /// This may be profitable is conditional instructions are always executed.
715 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
716 MachineBasicBlock &FMBB) const {
720 /// Return true if it is possible to insert a select
721 /// instruction that chooses between TrueReg and FalseReg based on the
722 /// condition code in Cond.
724 /// When successful, also return the latency in cycles from TrueReg,
725 /// FalseReg, and Cond to the destination register. In most cases, a select
726 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
728 /// Some x86 implementations have 2-cycle cmov instructions.
730 /// @param MBB Block where select instruction would be inserted.
731 /// @param Cond Condition returned by AnalyzeBranch.
732 /// @param TrueReg Virtual register to select when Cond is true.
733 /// @param FalseReg Virtual register to select when Cond is false.
734 /// @param CondCycles Latency from Cond+Branch to select output.
735 /// @param TrueCycles Latency from TrueReg to select output.
736 /// @param FalseCycles Latency from FalseReg to select output.
737 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
738 ArrayRef<MachineOperand> Cond,
739 unsigned TrueReg, unsigned FalseReg,
741 int &TrueCycles, int &FalseCycles) const {
745 /// Insert a select instruction into MBB before I that will copy TrueReg to
746 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
748 /// This function can only be called after canInsertSelect() returned true.
749 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
750 /// that the same flags or registers required by Cond are available at the
753 /// @param MBB Block where select instruction should be inserted.
754 /// @param I Insertion point.
755 /// @param DL Source location for debugging.
756 /// @param DstReg Virtual register to be defined by select instruction.
757 /// @param Cond Condition as computed by AnalyzeBranch.
758 /// @param TrueReg Virtual register to copy when Cond is true.
759 /// @param FalseReg Virtual register to copy when Cons is false.
760 virtual void insertSelect(MachineBasicBlock &MBB,
761 MachineBasicBlock::iterator I, const DebugLoc &DL,
762 unsigned DstReg, ArrayRef<MachineOperand> Cond,
763 unsigned TrueReg, unsigned FalseReg) const {
764 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
767 /// Analyze the given select instruction, returning true if
768 /// it cannot be understood. It is assumed that MI->isSelect() is true.
770 /// When successful, return the controlling condition and the operands that
771 /// determine the true and false result values.
773 /// Result = SELECT Cond, TrueOp, FalseOp
775 /// Some targets can optimize select instructions, for example by predicating
776 /// the instruction defining one of the operands. Such targets should set
779 /// @param MI Select instruction to analyze.
780 /// @param Cond Condition controlling the select.
781 /// @param TrueOp Operand number of the value selected when Cond is true.
782 /// @param FalseOp Operand number of the value selected when Cond is false.
783 /// @param Optimizable Returned as true if MI is optimizable.
784 /// @returns False on success.
785 virtual bool analyzeSelect(const MachineInstr &MI,
786 SmallVectorImpl<MachineOperand> &Cond,
787 unsigned &TrueOp, unsigned &FalseOp,
788 bool &Optimizable) const {
789 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
793 /// Given a select instruction that was understood by
794 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
795 /// merging it with one of its operands. Returns NULL on failure.
797 /// When successful, returns the new select instruction. The client is
798 /// responsible for deleting MI.
800 /// If both sides of the select can be optimized, PreferFalse is used to pick
803 /// @param MI Optimizable select instruction.
804 /// @param NewMIs Set that record all MIs in the basic block up to \p
805 /// MI. Has to be updated with any newly created MI or deleted ones.
806 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
807 /// @returns Optimized instruction or NULL.
808 virtual MachineInstr *optimizeSelect(MachineInstr &MI,
809 SmallPtrSetImpl<MachineInstr *> &NewMIs,
810 bool PreferFalse = false) const {
811 // This function must be implemented if Optimizable is ever set.
812 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
815 /// Emit instructions to copy a pair of physical registers.
817 /// This function should support copies within any legal register class as
818 /// well as any cross-class copies created during instruction selection.
820 /// The source and destination registers may overlap, which may require a
821 /// careful implementation when multiple copy instructions are required for
822 /// large registers. See for example the ARM target.
823 virtual void copyPhysReg(MachineBasicBlock &MBB,
824 MachineBasicBlock::iterator MI, const DebugLoc &DL,
825 unsigned DestReg, unsigned SrcReg,
826 bool KillSrc) const {
827 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
830 /// Store the specified register of the given register class to the specified
831 /// stack frame index. The store instruction is to be added to the given
832 /// machine basic block before the specified machine instruction. If isKill
833 /// is true, the register operand is the last use and must be marked kill.
834 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
835 MachineBasicBlock::iterator MI,
836 unsigned SrcReg, bool isKill, int FrameIndex,
837 const TargetRegisterClass *RC,
838 const TargetRegisterInfo *TRI) const {
839 llvm_unreachable("Target didn't implement "
840 "TargetInstrInfo::storeRegToStackSlot!");
843 /// Load the specified register of the given register class from the specified
844 /// stack frame index. The load instruction is to be added to the given
845 /// machine basic block before the specified machine instruction.
846 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
847 MachineBasicBlock::iterator MI,
848 unsigned DestReg, int FrameIndex,
849 const TargetRegisterClass *RC,
850 const TargetRegisterInfo *TRI) const {
851 llvm_unreachable("Target didn't implement "
852 "TargetInstrInfo::loadRegFromStackSlot!");
855 /// This function is called for all pseudo instructions
856 /// that remain after register allocation. Many pseudo instructions are
857 /// created to help register allocation. This is the place to convert them
858 /// into real instructions. The target can edit MI in place, or it can insert
859 /// new instructions and erase MI. The function should return true if
860 /// anything was changed.
861 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
863 /// Check whether the target can fold a load that feeds a subreg operand
864 /// (or a subreg operand that feeds a store).
865 /// For example, X86 may want to return true if it can fold
866 /// movl (%esp), %eax
871 /// Ideally, we'd like the target implementation of foldMemoryOperand() to
872 /// reject subregs - but since this behavior used to be enforced in the
873 /// target-independent code, moving this responsibility to the targets
874 /// has the potential of causing nasty silent breakage in out-of-tree targets.
875 virtual bool isSubregFoldable() const { return false; }
877 /// Attempt to fold a load or store of the specified stack
878 /// slot into the specified machine instruction for the specified operand(s).
879 /// If this is possible, a new instruction is returned with the specified
880 /// operand folded, otherwise NULL is returned.
881 /// The new instruction is inserted before MI, and the client is responsible
882 /// for removing the old instruction.
883 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
885 LiveIntervals *LIS = nullptr) const;
887 /// Same as the previous version except it allows folding of any load and
888 /// store from / to any address, not just from a specific stack slot.
889 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
890 MachineInstr &LoadMI,
891 LiveIntervals *LIS = nullptr) const;
893 /// Return true when there is potentially a faster code sequence
894 /// for an instruction chain ending in \p Root. All potential patterns are
895 /// returned in the \p Pattern vector. Pattern should be sorted in priority
896 /// order since the pattern evaluator stops checking as soon as it finds a
898 /// \param Root - Instruction that could be combined with one of its operands
899 /// \param Patterns - Vector of possible combination patterns
900 virtual bool getMachineCombinerPatterns(
902 SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
904 /// Return true when a code sequence can improve throughput. It
905 /// should be called only for instructions in loops.
906 /// \param Pattern - combiner pattern
907 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
909 /// Return true if the input \P Inst is part of a chain of dependent ops
910 /// that are suitable for reassociation, otherwise return false.
911 /// If the instruction's operands must be commuted to have a previous
912 /// instruction of the same type define the first source operand, \P Commuted
913 /// will be set to true.
914 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
916 /// Return true when \P Inst is both associative and commutative.
917 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
921 /// Return true when \P Inst has reassociable operands in the same \P MBB.
922 virtual bool hasReassociableOperands(const MachineInstr &Inst,
923 const MachineBasicBlock *MBB) const;
925 /// Return true when \P Inst has reassociable sibling.
926 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
928 /// When getMachineCombinerPatterns() finds patterns, this function generates
929 /// the instructions that could replace the original code sequence. The client
930 /// has to decide whether the actual replacement is beneficial or not.
931 /// \param Root - Instruction that could be combined with one of its operands
932 /// \param Pattern - Combination pattern for Root
933 /// \param InsInstrs - Vector of new instructions that implement P
934 /// \param DelInstrs - Old instructions, including Root, that could be
935 /// replaced by InsInstr
936 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
937 /// InsInstr that defines it
938 virtual void genAlternativeCodeSequence(
939 MachineInstr &Root, MachineCombinerPattern Pattern,
940 SmallVectorImpl<MachineInstr *> &InsInstrs,
941 SmallVectorImpl<MachineInstr *> &DelInstrs,
942 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
944 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
945 /// reduce critical path length.
946 void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
947 MachineCombinerPattern Pattern,
948 SmallVectorImpl<MachineInstr *> &InsInstrs,
949 SmallVectorImpl<MachineInstr *> &DelInstrs,
950 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
952 /// This is an architecture-specific helper function of reassociateOps.
953 /// Set special operand attributes for new instructions after reassociation.
954 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
955 MachineInstr &NewMI1,
956 MachineInstr &NewMI2) const {
959 /// Return true when a target supports MachineCombiner.
960 virtual bool useMachineCombiner() const { return false; }
963 /// Target-dependent implementation for foldMemoryOperand.
964 /// Target-independent code in foldMemoryOperand will
965 /// take care of adding a MachineMemOperand to the newly created instruction.
966 /// The instruction and any auxiliary instructions necessary will be inserted
968 virtual MachineInstr *
969 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
970 ArrayRef<unsigned> Ops,
971 MachineBasicBlock::iterator InsertPt, int FrameIndex,
972 LiveIntervals *LIS = nullptr) const {
976 /// Target-dependent implementation for foldMemoryOperand.
977 /// Target-independent code in foldMemoryOperand will
978 /// take care of adding a MachineMemOperand to the newly created instruction.
979 /// The instruction and any auxiliary instructions necessary will be inserted
981 virtual MachineInstr *foldMemoryOperandImpl(
982 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
983 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
984 LiveIntervals *LIS = nullptr) const {
988 /// \brief Target-dependent implementation of getRegSequenceInputs.
990 /// \returns true if it is possible to build the equivalent
991 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
993 /// \pre MI.isRegSequenceLike().
995 /// \see TargetInstrInfo::getRegSequenceInputs.
996 virtual bool getRegSequenceLikeInputs(
997 const MachineInstr &MI, unsigned DefIdx,
998 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1002 /// \brief Target-dependent implementation of getExtractSubregInputs.
1004 /// \returns true if it is possible to build the equivalent
1005 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1007 /// \pre MI.isExtractSubregLike().
1009 /// \see TargetInstrInfo::getExtractSubregInputs.
1010 virtual bool getExtractSubregLikeInputs(
1011 const MachineInstr &MI, unsigned DefIdx,
1012 RegSubRegPairAndIdx &InputReg) const {
1016 /// \brief Target-dependent implementation of getInsertSubregInputs.
1018 /// \returns true if it is possible to build the equivalent
1019 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1021 /// \pre MI.isInsertSubregLike().
1023 /// \see TargetInstrInfo::getInsertSubregInputs.
1025 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1026 RegSubRegPair &BaseReg,
1027 RegSubRegPairAndIdx &InsertedReg) const {
1032 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1033 /// a store or a load and a store into two or more instruction. If this is
1034 /// possible, returns true as well as the new instructions by reference.
1036 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1037 bool UnfoldLoad, bool UnfoldStore,
1038 SmallVectorImpl<MachineInstr *> &NewMIs) const {
1042 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1043 SmallVectorImpl<SDNode*> &NewNodes) const {
1047 /// Returns the opcode of the would be new
1048 /// instruction after load / store are unfolded from an instruction of the
1049 /// specified opcode. It returns zero if the specified unfolding is not
1050 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1051 /// index of the operand which will hold the register holding the loaded
1053 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
1054 bool UnfoldLoad, bool UnfoldStore,
1055 unsigned *LoadRegIndex = nullptr) const {
1059 /// This is used by the pre-regalloc scheduler to determine if two loads are
1060 /// loading from the same base address. It should only return true if the base
1061 /// pointers are the same and the only differences between the two addresses
1062 /// are the offset. It also returns the offsets by reference.
1063 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1064 int64_t &Offset1, int64_t &Offset2) const {
1068 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1069 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1070 /// On some targets if two loads are loading from
1071 /// addresses in the same cache line, it's better if they are scheduled
1072 /// together. This function takes two integers that represent the load offsets
1073 /// from the common base address. It returns true if it decides it's desirable
1074 /// to schedule the two loads together. "NumLoads" is the number of loads that
1075 /// have already been scheduled after Load1.
1076 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1077 int64_t Offset1, int64_t Offset2,
1078 unsigned NumLoads) const {
1082 /// Get the base register and byte offset of an instruction that reads/writes
1084 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1086 const TargetRegisterInfo *TRI) const {
1090 /// Return true if the instruction contains a base register and offset. If
1091 /// true, the function also sets the operand position in the instruction
1092 /// for the base register and offset.
1093 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1095 unsigned &OffsetPos) const {
1099 /// If the instruction is an increment of a constant value, return the amount.
1100 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1104 /// Returns true if the two given memory operations should be scheduled
1105 /// adjacent. Note that you have to add:
1106 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1108 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1109 /// to TargetPassConfig::createMachineScheduler() to have an effect.
1110 virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt,
1111 MachineInstr &SecondLdSt,
1112 unsigned NumLoads) const {
1113 llvm_unreachable("target did not implement shouldClusterMemOps()");
1116 /// Reverses the branch condition of the specified condition list,
1117 /// returning false on success and true if it cannot be reversed.
1119 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1123 /// Insert a noop into the instruction stream at the specified point.
1124 virtual void insertNoop(MachineBasicBlock &MBB,
1125 MachineBasicBlock::iterator MI) const;
1127 /// Return the noop instruction to use for a noop.
1128 virtual void getNoop(MCInst &NopInst) const;
1130 /// Return true for post-incremented instructions.
1131 virtual bool isPostIncrement(const MachineInstr &MI) const {
1135 /// Returns true if the instruction is already predicated.
1136 virtual bool isPredicated(const MachineInstr &MI) const {
1140 /// Returns true if the instruction is a
1141 /// terminator instruction that has not been predicated.
1142 virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1144 /// Returns true if MI is an unconditional tail call.
1145 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1149 /// Returns true if the tail call can be made conditional on BranchCond.
1151 canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
1152 const MachineInstr &TailCall) const {
1156 /// Replace the conditional branch in MBB with a conditional tail call.
1157 virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1158 SmallVectorImpl<MachineOperand> &Cond,
1159 const MachineInstr &TailCall) const {
1160 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1163 /// Convert the instruction into a predicated instruction.
1164 /// It returns true if the operation was successful.
1165 virtual bool PredicateInstruction(MachineInstr &MI,
1166 ArrayRef<MachineOperand> Pred) const;
1168 /// Returns true if the first specified predicate
1169 /// subsumes the second, e.g. GE subsumes GT.
1171 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1172 ArrayRef<MachineOperand> Pred2) const {
1176 /// If the specified instruction defines any predicate
1177 /// or condition code register(s) used for predication, returns true as well
1178 /// as the definition predicate(s) by reference.
1179 virtual bool DefinesPredicate(MachineInstr &MI,
1180 std::vector<MachineOperand> &Pred) const {
1184 /// Return true if the specified instruction can be predicated.
1185 /// By default, this returns true for every instruction with a
1186 /// PredicateOperand.
1187 virtual bool isPredicable(const MachineInstr &MI) const {
1188 return MI.getDesc().isPredicable();
1191 /// Return true if it's safe to move a machine
1192 /// instruction that defines the specified register class.
1193 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1197 /// Test if the given instruction should be considered a scheduling boundary.
1198 /// This primarily includes labels and terminators.
1199 virtual bool isSchedulingBoundary(const MachineInstr &MI,
1200 const MachineBasicBlock *MBB,
1201 const MachineFunction &MF) const;
1203 /// Measure the specified inline asm to determine an approximation of its
1205 virtual unsigned getInlineAsmLength(const char *Str,
1206 const MCAsmInfo &MAI) const;
1208 /// Allocate and return a hazard recognizer to use for this target when
1209 /// scheduling the machine instructions before register allocation.
1210 virtual ScheduleHazardRecognizer*
1211 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1212 const ScheduleDAG *DAG) const;
1214 /// Allocate and return a hazard recognizer to use for this target when
1215 /// scheduling the machine instructions before register allocation.
1216 virtual ScheduleHazardRecognizer*
1217 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
1218 const ScheduleDAG *DAG) const;
1220 /// Allocate and return a hazard recognizer to use for this target when
1221 /// scheduling the machine instructions after register allocation.
1222 virtual ScheduleHazardRecognizer*
1223 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
1224 const ScheduleDAG *DAG) const;
1226 /// Allocate and return a hazard recognizer to use for by non-scheduling
1228 virtual ScheduleHazardRecognizer*
1229 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1233 /// Provide a global flag for disabling the PreRA hazard recognizer that
1234 /// targets may choose to honor.
1235 bool usePreRAHazardRecognizer() const;
1237 /// For a comparison instruction, return the source registers
1238 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1239 /// compares against in CmpValue. Return true if the comparison instruction
1240 /// can be analyzed.
1241 virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1242 unsigned &SrcReg2, int &Mask, int &Value) const {
1246 /// See if the comparison instruction can be converted
1247 /// into something more efficient. E.g., on ARM most instructions can set the
1248 /// flags register, obviating the need for a separate CMP.
1249 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1250 unsigned SrcReg2, int Mask, int Value,
1251 const MachineRegisterInfo *MRI) const {
1254 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1256 /// Try to remove the load by folding it to a register operand at the use.
1257 /// We fold the load instructions if and only if the
1258 /// def and use are in the same BB. We only look at one load and see
1259 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1260 /// defined by the load we are trying to fold. DefMI returns the machine
1261 /// instruction that defines FoldAsLoadDefReg, and the function returns
1262 /// the machine instruction generated due to folding.
1263 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1264 const MachineRegisterInfo *MRI,
1265 unsigned &FoldAsLoadDefReg,
1266 MachineInstr *&DefMI) const {
1270 /// 'Reg' is known to be defined by a move immediate instruction,
1271 /// try to fold the immediate into the use instruction.
1272 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1273 /// then the caller may assume that DefMI has been erased from its parent
1274 /// block. The caller may assume that it will not be erased by this
1275 /// function otherwise.
1276 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1277 unsigned Reg, MachineRegisterInfo *MRI) const {
1281 /// Return the number of u-operations the given machine
1282 /// instruction will be decoded to on the target cpu. The itinerary's
1283 /// IssueWidth is the number of microops that can be dispatched each
1284 /// cycle. An instruction with zero microops takes no dispatch resources.
1285 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1286 const MachineInstr &MI) const;
1288 /// Return true for pseudo instructions that don't consume any
1289 /// machine resources in their current form. These are common cases that the
1290 /// scheduler should consider free, rather than conservatively handling them
1291 /// as instructions with no itinerary.
1292 bool isZeroCost(unsigned Opcode) const {
1293 return Opcode <= TargetOpcode::COPY;
1296 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1297 SDNode *DefNode, unsigned DefIdx,
1298 SDNode *UseNode, unsigned UseIdx) const;
1300 /// Compute and return the use operand latency of a given pair of def and use.
1301 /// In most cases, the static scheduling itinerary was enough to determine the
1302 /// operand latency. But it may not be possible for instructions with variable
1303 /// number of defs / uses.
1305 /// This is a raw interface to the itinerary that may be directly overridden
1306 /// by a target. Use computeOperandLatency to get the best estimate of
1308 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1309 const MachineInstr &DefMI, unsigned DefIdx,
1310 const MachineInstr &UseMI,
1311 unsigned UseIdx) const;
1313 /// Compute the instruction latency of a given instruction.
1314 /// If the instruction has higher cost when predicated, it's returned via
1316 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1317 const MachineInstr &MI,
1318 unsigned *PredCost = nullptr) const;
1320 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1322 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1323 SDNode *Node) const;
1325 /// Return the default expected latency for a def based on its opcode.
1326 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1327 const MachineInstr &DefMI) const;
1329 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1330 const MachineInstr &DefMI) const;
1332 /// Return true if this opcode has high latency to its result.
1333 virtual bool isHighLatencyDef(int opc) const { return false; }
1335 /// Compute operand latency between a def of 'Reg'
1336 /// and a use in the current loop. Return true if the target considered
1337 /// it 'high'. This is used by optimization passes such as machine LICM to
1338 /// determine whether it makes sense to hoist an instruction out even in a
1339 /// high register pressure situation.
1340 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1341 const MachineRegisterInfo *MRI,
1342 const MachineInstr &DefMI, unsigned DefIdx,
1343 const MachineInstr &UseMI,
1344 unsigned UseIdx) const {
1348 /// Compute operand latency of a def of 'Reg'. Return true
1349 /// if the target considered it 'low'.
1350 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1351 const MachineInstr &DefMI,
1352 unsigned DefIdx) const;
1354 /// Perform target-specific instruction verification.
1355 virtual bool verifyInstruction(const MachineInstr &MI,
1356 StringRef &ErrInfo) const {
1360 /// Return the current execution domain and bit mask of
1361 /// possible domains for instruction.
1363 /// Some micro-architectures have multiple execution domains, and multiple
1364 /// opcodes that perform the same operation in different domains. For
1365 /// example, the x86 architecture provides the por, orps, and orpd
1366 /// instructions that all do the same thing. There is a latency penalty if a
1367 /// register is written in one domain and read in another.
1369 /// This function returns a pair (domain, mask) containing the execution
1370 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1371 /// function can be used to change the opcode to one of the domains in the
1372 /// bit mask. Instructions whose execution domain can't be changed should
1373 /// return a 0 mask.
1375 /// The execution domain numbers don't have any special meaning except domain
1376 /// 0 is used for instructions that are not associated with any interesting
1377 /// execution domain.
1379 virtual std::pair<uint16_t, uint16_t>
1380 getExecutionDomain(const MachineInstr &MI) const {
1381 return std::make_pair(0, 0);
1384 /// Change the opcode of MI to execute in Domain.
1386 /// The bit (1 << Domain) must be set in the mask returned from
1387 /// getExecutionDomain(MI).
1388 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1390 /// Returns the preferred minimum clearance
1391 /// before an instruction with an unwanted partial register update.
1393 /// Some instructions only write part of a register, and implicitly need to
1394 /// read the other parts of the register. This may cause unwanted stalls
1395 /// preventing otherwise unrelated instructions from executing in parallel in
1396 /// an out-of-order CPU.
1398 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1399 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1400 /// the instruction needs to wait for the old value of the register to become
1403 /// addps %xmm1, %xmm0
1404 /// movaps %xmm0, (%rax)
1405 /// cvtsi2ss %rbx, %xmm0
1407 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1408 /// instruction before it can issue, even though the high bits of %xmm0
1409 /// probably aren't needed.
1411 /// This hook returns the preferred clearance before MI, measured in
1412 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1413 /// instructions before MI. It should only return a positive value for
1414 /// unwanted dependencies. If the old bits of the defined register have
1415 /// useful values, or if MI is determined to otherwise read the dependency,
1416 /// the hook should return 0.
1418 /// The unwanted dependency may be handled by:
1420 /// 1. Allocating the same register for an MI def and use. That makes the
1421 /// unwanted dependency identical to a required dependency.
1423 /// 2. Allocating a register for the def that has no defs in the previous N
1426 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1427 /// allows the target to insert a dependency breaking instruction.
1430 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1431 const TargetRegisterInfo *TRI) const {
1432 // The default implementation returns 0 for no partial register dependency.
1436 /// \brief Return the minimum clearance before an instruction that reads an
1437 /// unused register.
1439 /// For example, AVX instructions may copy part of a register operand into
1440 /// the unused high bits of the destination register.
1442 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1444 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1445 /// false dependence on any previous write to %xmm0.
1447 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1448 /// does not take an operand index. Instead sets \p OpNum to the index of the
1449 /// unused register.
1450 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1451 const TargetRegisterInfo *TRI) const {
1452 // The default implementation returns 0 for no undef register dependency.
1456 /// Insert a dependency-breaking instruction
1457 /// before MI to eliminate an unwanted dependency on OpNum.
1459 /// If it wasn't possible to avoid a def in the last N instructions before MI
1460 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1461 /// unwanted dependency.
1463 /// On x86, an xorps instruction can be used as a dependency breaker:
1465 /// addps %xmm1, %xmm0
1466 /// movaps %xmm0, (%rax)
1467 /// xorps %xmm0, %xmm0
1468 /// cvtsi2ss %rbx, %xmm0
1470 /// An <imp-kill> operand should be added to MI if an instruction was
1471 /// inserted. This ties the instructions together in the post-ra scheduler.
1473 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1474 const TargetRegisterInfo *TRI) const {}
1476 /// Create machine specific model for scheduling.
1477 virtual DFAPacketizer *
1478 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1482 /// Sometimes, it is possible for the target
1483 /// to tell, even without aliasing information, that two MIs access different
1484 /// memory addresses. This function returns true if two MIs access different
1485 /// memory addresses and false otherwise.
1487 /// Assumes any physical registers used to compute addresses have the same
1488 /// value for both instructions. (This is the most useful assumption for
1489 /// post-RA scheduling.)
1491 /// See also MachineInstr::mayAlias, which is implemented on top of this
1494 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1495 AliasAnalysis *AA = nullptr) const {
1496 assert((MIa.mayLoad() || MIa.mayStore()) &&
1497 "MIa must load from or modify a memory location");
1498 assert((MIb.mayLoad() || MIb.mayStore()) &&
1499 "MIb must load from or modify a memory location");
1503 /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1504 /// which is a heuristic used for CSE'ing phys reg defs.
1505 virtual unsigned getMachineCSELookAheadLimit () const {
1506 // The default lookahead is small to prevent unprofitable quadratic
1511 /// Return an array that contains the ids of the target indices (used for the
1512 /// TargetIndex machine operand) and their names.
1514 /// MIR Serialization is able to serialize only the target indices that are
1515 /// defined by this method.
1516 virtual ArrayRef<std::pair<int, const char *>>
1517 getSerializableTargetIndices() const {
1521 /// Decompose the machine operand's target flags into two values - the direct
1522 /// target flag value and any of bit flags that are applied.
1523 virtual std::pair<unsigned, unsigned>
1524 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1525 return std::make_pair(0u, 0u);
1528 /// Return an array that contains the direct target flag values and their
1531 /// MIR Serialization is able to serialize only the target flags that are
1532 /// defined by this method.
1533 virtual ArrayRef<std::pair<unsigned, const char *>>
1534 getSerializableDirectMachineOperandTargetFlags() const {
1538 /// Return an array that contains the bitmask target flag values and their
1541 /// MIR Serialization is able to serialize only the target flags that are
1542 /// defined by this method.
1543 virtual ArrayRef<std::pair<unsigned, const char *>>
1544 getSerializableBitmaskMachineOperandTargetFlags() const {
1548 /// Return an array that contains the MMO target flag values and their
1551 /// MIR Serialization is able to serialize only the MMO target flags that are
1552 /// defined by this method.
1553 virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
1554 getSerializableMachineMemOperandTargetFlags() const {
1558 /// Determines whether \p Inst is a tail call instruction. Override this
1559 /// method on targets that do not properly set MCID::Return and MCID::Call on
1560 /// tail call instructions."
1561 virtual bool isTailCall(const MachineInstr &Inst) const {
1562 return Inst.isReturn() && Inst.isCall();
1565 /// True if the instruction is bound to the top of its basic block and no
1566 /// other instructions shall be inserted before it. This can be implemented
1567 /// to prevent register allocator to insert spills before such instructions.
1568 virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1572 /// \brief Return how many instructions would be saved by outlining a
1573 /// sequence containing \p SequenceSize instructions that appears
1574 /// \p Occurrences times in a module.
1575 virtual unsigned getOutliningBenefit(size_t SequenceSize, size_t Occurrences,
1576 bool CanBeTailCall) const {
1578 "Target didn't implement TargetInstrInfo::getOutliningBenefit!");
1581 /// Represents how an instruction should be mapped by the outliner.
1582 /// \p Legal instructions are those which are safe to outline.
1583 /// \p Illegal instructions are those which cannot be outlined.
1584 /// \p Invisible instructions are instructions which can be outlined, but
1585 /// shouldn't actually impact the outlining result.
1586 enum MachineOutlinerInstrType {Legal, Illegal, Invisible};
1588 /// Returns how or if \p MI should be outlined.
1589 virtual MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const {
1591 "Target didn't implement TargetInstrInfo::getOutliningType!");
1594 /// Insert a custom epilogue for outlined functions.
1595 /// This may be empty, in which case no epilogue or return statement will be
1597 virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB,
1598 MachineFunction &MF,
1599 bool IsTailCall) const {
1601 "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!");
1604 /// Insert a call to an outlined function into the program.
1605 /// Returns an iterator to the spot where we inserted the call. This must be
1606 /// implemented by the target.
1607 virtual MachineBasicBlock::iterator
1608 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
1609 MachineBasicBlock::iterator &It, MachineFunction &MF,
1610 bool IsTailCall) const {
1612 "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1615 /// Insert a custom prologue for outlined functions.
1616 /// This may be empty, in which case no prologue will be emitted.
1617 virtual void insertOutlinerPrologue(MachineBasicBlock &MBB,
1618 MachineFunction &MF,
1619 bool IsTailCall) const {
1621 "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!");
1624 /// Return true if the function can safely be outlined from.
1625 /// By default, this means that the function has no red zone.
1626 virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF) const {
1627 llvm_unreachable("Target didn't implement "
1628 "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1632 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1633 unsigned CatchRetOpcode;
1634 unsigned ReturnOpcode;
1637 /// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1639 struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
1640 using RegInfo = DenseMapInfo<unsigned>;
1642 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1643 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1644 RegInfo::getEmptyKey());
1647 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1648 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1649 RegInfo::getTombstoneKey());
1652 /// \brief Reuse getHashValue implementation from
1653 /// std::pair<unsigned, unsigned>.
1654 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1655 std::pair<unsigned, unsigned> PairVal =
1656 std::make_pair(Val.Reg, Val.SubReg);
1657 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1660 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1661 const TargetInstrInfo::RegSubRegPair &RHS) {
1662 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1663 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1667 } // end namespace llvm
1669 #endif // LLVM_TARGET_TARGETINSTRINFO_H