1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
44 class BranchProbability;
49 class FunctionLoweringInfo;
50 class ImmutableCallSite;
52 class MachineBasicBlock;
53 class MachineFunction;
55 class MachineJumpTableInfo;
57 class MachineRegisterInfo;
62 template<typename T> class SmallVectorImpl;
64 class TargetRegisterClass;
65 class TargetLibraryInfo;
66 class TargetLoweringObjectFile;
71 None, // No preference
72 Source, // Follow source order.
73 RegPressure, // Scheduling for lowest register pressure.
74 Hybrid, // Scheduling for both latency and register pressure.
75 ILP, // Scheduling for ILP in low register pressure mode.
76 VLIW // Scheduling for VLIW targets.
80 /// This base class for TargetLowering contains the SelectionDAG-independent
81 /// parts that can be used from the rest of CodeGen.
82 class TargetLoweringBase {
83 TargetLoweringBase(const TargetLoweringBase&) = delete;
84 void operator=(const TargetLoweringBase&) = delete;
87 /// This enum indicates whether operations are valid for a target, and if not,
88 /// what action should be used to make them valid.
89 enum LegalizeAction : uint8_t {
90 Legal, // The target natively supports this operation.
91 Promote, // This operation should be executed in a larger type.
92 Expand, // Try to expand this to other ops, otherwise use a libcall.
93 LibCall, // Don't try to expand this to other ops, always use a libcall.
94 Custom // Use the LowerOperation hook to implement custom lowering.
97 /// This enum indicates whether a types are legal for a target, and if not,
98 /// what action should be used to make them valid.
99 enum LegalizeTypeAction : uint8_t {
100 TypeLegal, // The target natively supports this type.
101 TypePromoteInteger, // Replace this integer with a larger one.
102 TypeExpandInteger, // Split this integer into two of half the size.
103 TypeSoftenFloat, // Convert this float to a same size integer type,
104 // if an operation is not supported in target HW.
105 TypeExpandFloat, // Split this float into two of half the size.
106 TypeScalarizeVector, // Replace this one-element vector with its element.
107 TypeSplitVector, // Split this vector into two of half the size.
108 TypeWidenVector, // This vector should be widened into a larger vector.
109 TypePromoteFloat // Replace this float with a larger one.
112 /// LegalizeKind holds the legalization kind that needs to happen to EVT
113 /// in order to type-legalize it.
114 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
116 /// Enum that describes how the target represents true/false values.
117 enum BooleanContent {
118 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
119 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
120 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
123 /// Enum that describes what type of support for selects the target has.
124 enum SelectSupportKind {
125 ScalarValSelect, // The target supports scalar selects (ex: cmov).
126 ScalarCondVectorVal, // The target supports selects with a scalar condition
127 // and vector values (ex: cmov).
128 VectorMaskSelect // The target supports vector selects with a vector
129 // mask (ex: x86 blends).
132 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
133 /// to, if at all. Exists because different targets have different levels of
134 /// support for these atomic instructions, and also have different options
135 /// w.r.t. what they should expand to.
136 enum class AtomicExpansionKind {
137 None, // Don't expand the instruction.
138 LLSC, // Expand the instruction into loadlinked/storeconditional; used
140 LLOnly, // Expand the (load) instruction into just a load-linked, which has
141 // greater atomic guarantees than a normal load.
142 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
145 static ISD::NodeType getExtendForContent(BooleanContent Content) {
147 case UndefinedBooleanContent:
148 // Extend by adding rubbish bits.
149 return ISD::ANY_EXTEND;
150 case ZeroOrOneBooleanContent:
151 // Extend by adding zero bits.
152 return ISD::ZERO_EXTEND;
153 case ZeroOrNegativeOneBooleanContent:
154 // Extend by copying the sign bit.
155 return ISD::SIGN_EXTEND;
157 llvm_unreachable("Invalid content kind");
160 /// NOTE: The TargetMachine owns TLOF.
161 explicit TargetLoweringBase(const TargetMachine &TM);
162 virtual ~TargetLoweringBase() {}
165 /// \brief Initialize all of the actions to default values.
169 const TargetMachine &getTargetMachine() const { return TM; }
171 virtual bool useSoftFloat() const { return false; }
173 /// Return the pointer type for the given address space, defaults to
174 /// the pointer type from the data layout.
175 /// FIXME: The default needs to be removed once all the code is updated.
176 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
177 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
180 /// EVT is not used in-tree, but is used by out-of-tree target.
181 /// A documentation for this function would be nice...
182 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
184 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
186 /// Returns the type to be used for the index operand of:
187 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
188 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
189 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
190 return getPointerTy(DL);
193 /// Return true if the select operation is expensive for this target.
194 bool isSelectExpensive() const { return SelectIsExpensive; }
196 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
200 /// Return true if multiple condition registers are available.
201 bool hasMultipleConditionRegisters() const {
202 return HasMultipleConditionRegisters;
205 /// Return true if the target has BitExtract instructions.
206 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
208 /// Return the preferred vector type legalization action.
209 virtual TargetLoweringBase::LegalizeTypeAction
210 getPreferredVectorAction(EVT VT) const {
211 // The default action for one element vectors is to scalarize
212 if (VT.getVectorNumElements() == 1)
213 return TypeScalarizeVector;
214 // The default action for other vectors is to promote
215 return TypePromoteInteger;
218 // There are two general methods for expanding a BUILD_VECTOR node:
219 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
221 // 2. Build the vector on the stack and then load it.
222 // If this function returns true, then method (1) will be used, subject to
223 // the constraint that all of the necessary shuffles are legal (as determined
224 // by isShuffleMaskLegal). If this function returns false, then method (2) is
225 // always used. The vector type, and the number of defined values, are
228 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
229 unsigned DefinedValues) const {
230 return DefinedValues < 3;
233 /// Return true if integer divide is usually cheaper than a sequence of
234 /// several shifts, adds, and multiplies for this target.
235 /// The definition of "cheaper" may depend on whether we're optimizing
236 /// for speed or for size.
237 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const {
241 /// Return true if the target can handle a standalone remainder operation.
242 virtual bool hasStandaloneRem(EVT VT) const {
246 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
247 bool isFsqrtCheap() const {
251 /// Returns true if target has indicated at least one type should be bypassed.
252 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
254 /// Returns map of slow types for division or remainder with corresponding
256 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
257 return BypassSlowDivWidths;
260 /// Return true if Flow Control is an expensive operation that should be
262 bool isJumpExpensive() const { return JumpIsExpensive; }
264 /// Return true if selects are only cheaper than branches if the branch is
265 /// unlikely to be predicted right.
266 bool isPredictableSelectExpensive() const {
267 return PredictableSelectIsExpensive;
270 /// If a branch or a select condition is skewed in one direction by more than
271 /// this factor, it is very likely to be predicted correctly.
272 virtual BranchProbability getPredictableBranchThreshold() const;
274 /// Return true if the following transform is beneficial:
275 /// fold (conv (load x)) -> (load (conv*)x)
276 /// On architectures that don't natively support some vector loads
277 /// efficiently, casting the load to a smaller vector of larger types and
278 /// loading is more efficient, however, this can be undone by optimizations in
280 virtual bool isLoadBitCastBeneficial(EVT LoadVT,
281 EVT BitcastVT) const {
282 // Don't do if we could do an indexed load on the original type, but not on
284 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
287 MVT LoadMVT = LoadVT.getSimpleVT();
289 // Don't bother doing this if it's just going to be promoted again later, as
290 // doing so might interfere with other combines.
291 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
292 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
298 /// Return true if the following transform is beneficial:
299 /// (store (y (conv x)), y*)) -> (store x, (x*))
300 virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
301 // Default to the same logic as loads.
302 return isLoadBitCastBeneficial(StoreVT, BitcastVT);
305 /// Return true if it is expected to be cheaper to do a store of a non-zero
306 /// vector constant with the given size and type for the address space than to
307 /// store the individual scalar element constants.
308 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
310 unsigned AddrSpace) const {
314 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
315 virtual bool isCheapToSpeculateCttz() const {
319 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
320 virtual bool isCheapToSpeculateCtlz() const {
324 /// Return true if it is safe to transform an integer-domain bitwise operation
325 /// into the equivalent floating-point operation. This should be set to true
326 /// if the target has IEEE-754-compliant fabs/fneg operations for the input
328 virtual bool hasBitPreservingFPLogic(EVT VT) const {
332 /// \brief Return if the target supports combining a
335 /// %andResult = and %val1, #imm-with-one-bit-set;
336 /// %icmpResult = icmp %andResult, 0
337 /// br i1 %icmpResult, label %dest1, label %dest2
339 /// into a single machine instruction of a form like:
341 /// brOnBitSet %register, #bitNumber, dest
343 bool isMaskAndBranchFoldingLegal() const {
344 return MaskAndBranchFoldingIsLegal;
347 /// Return true if the target should transform:
348 /// (X & Y) == Y ---> (~X & Y) == 0
349 /// (X & Y) != Y ---> (~X & Y) != 0
351 /// This may be profitable if the target has a bitwise and-not operation that
352 /// sets comparison flags. A target may want to limit the transformation based
353 /// on the type of Y or if Y is a constant.
355 /// Note that the transform will not occur if Y is known to be a power-of-2
356 /// because a mask and compare of a single bit can be handled by inverting the
357 /// predicate, for example:
358 /// (X & 8) == 8 ---> (X & 8) != 0
359 virtual bool hasAndNotCompare(SDValue Y) const {
363 /// \brief Return true if the target wants to use the optimization that
364 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
365 /// promotedInst1(...(promotedInstN(ext(load)))).
366 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
368 /// Return true if the target can combine store(extractelement VectorTy,
370 /// \p Cost[out] gives the cost of that transformation when this is true.
371 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
372 unsigned &Cost) const {
376 /// Return true if target supports floating point exceptions.
377 bool hasFloatingPointExceptions() const {
378 return HasFloatingPointExceptions;
381 /// Return true if target always beneficiates from combining into FMA for a
382 /// given value type. This must typically return false on targets where FMA
383 /// takes more cycles to execute than FADD.
384 virtual bool enableAggressiveFMAFusion(EVT VT) const {
388 /// Return the ValueType of the result of SETCC operations.
389 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
392 /// Return the ValueType for comparison libcalls. Comparions libcalls include
393 /// floating point comparion calls, and Ordered/Unordered check calls on
394 /// floating point numbers.
396 MVT::SimpleValueType getCmpLibcallReturnType() const;
398 /// For targets without i1 registers, this gives the nature of the high-bits
399 /// of boolean values held in types wider than i1.
401 /// "Boolean values" are special true/false values produced by nodes like
402 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
403 /// Not to be confused with general values promoted from i1. Some cpus
404 /// distinguish between vectors of boolean and scalars; the isVec parameter
405 /// selects between the two kinds. For example on X86 a scalar boolean should
406 /// be zero extended from i1, while the elements of a vector of booleans
407 /// should be sign extended from i1.
409 /// Some cpus also treat floating point types the same way as they treat
410 /// vectors instead of the way they treat scalars.
411 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
413 return BooleanVectorContents;
414 return isFloat ? BooleanFloatContents : BooleanContents;
417 BooleanContent getBooleanContents(EVT Type) const {
418 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
421 /// Return target scheduling preference.
422 Sched::Preference getSchedulingPreference() const {
423 return SchedPreferenceInfo;
426 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
427 /// for different nodes. This function returns the preference (or none) for
429 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
433 /// Return the register class that should be used for the specified value
435 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
436 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
437 assert(RC && "This value type is not natively supported!");
441 /// Return the 'representative' register class for the specified value
444 /// The 'representative' register class is the largest legal super-reg
445 /// register class for the register class of the value type. For example, on
446 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
447 /// register class is GR64 on x86_64.
448 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
449 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
453 /// Return the cost of the 'representative' register class for the specified
455 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
456 return RepRegClassCostForVT[VT.SimpleTy];
459 /// Return true if the target has native support for the specified value type.
460 /// This means that it has a register that directly holds it without
461 /// promotions or expansions.
462 bool isTypeLegal(EVT VT) const {
463 assert(!VT.isSimple() ||
464 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
465 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
468 class ValueTypeActionImpl {
469 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
470 /// that indicates how instruction selection should deal with the type.
471 LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
474 ValueTypeActionImpl() {
475 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
479 LegalizeTypeAction getTypeAction(MVT VT) const {
480 return ValueTypeActions[VT.SimpleTy];
483 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
484 ValueTypeActions[VT.SimpleTy] = Action;
488 const ValueTypeActionImpl &getValueTypeActions() const {
489 return ValueTypeActions;
492 /// Return how we should legalize values of this type, either it is already
493 /// legal (return 'Legal') or we need to promote it to a larger type (return
494 /// 'Promote'), or we need to expand it into multiple registers of smaller
495 /// integer type (return 'Expand'). 'Custom' is not an option.
496 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
497 return getTypeConversion(Context, VT).first;
499 LegalizeTypeAction getTypeAction(MVT VT) const {
500 return ValueTypeActions.getTypeAction(VT);
503 /// For types supported by the target, this is an identity function. For
504 /// types that must be promoted to larger types, this returns the larger type
505 /// to promote to. For integer types that are larger than the largest integer
506 /// register, this contains one step in the expansion to get to the smaller
507 /// register. For illegal floating point types, this returns the integer type
509 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
510 return getTypeConversion(Context, VT).second;
513 /// For types supported by the target, this is an identity function. For
514 /// types that must be expanded (i.e. integer types that are larger than the
515 /// largest integer register or illegal floating point types), this returns
516 /// the largest legal type it will be expanded to.
517 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
518 assert(!VT.isVector());
520 switch (getTypeAction(Context, VT)) {
523 case TypeExpandInteger:
524 VT = getTypeToTransformTo(Context, VT);
527 llvm_unreachable("Type is not legal nor is it to be expanded!");
532 /// Vector types are broken down into some number of legal first class types.
533 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
534 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
535 /// turns into 4 EVT::i32 values with both PPC and X86.
537 /// This method returns the number of registers needed, and the VT for each
538 /// register. It also returns the VT and quantity of the intermediate values
539 /// before they are promoted/expanded.
540 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
542 unsigned &NumIntermediates,
543 MVT &RegisterVT) const;
545 struct IntrinsicInfo {
546 unsigned opc; // target opcode
547 EVT memVT; // memory VT
548 const Value* ptrVal; // value representing memory location
549 int offset; // offset off of ptrVal
550 unsigned size; // the size of the memory location
551 // (taken from memVT if zero)
552 unsigned align; // alignment
553 bool vol; // is volatile?
554 bool readMem; // reads memory?
555 bool writeMem; // writes memory?
557 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
558 vol(false), readMem(false), writeMem(false) {}
561 /// Given an intrinsic, checks if on the target the intrinsic will need to map
562 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
563 /// true and store the intrinsic information into the IntrinsicInfo that was
564 /// passed to the function.
565 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
566 unsigned /*Intrinsic*/) const {
570 /// Returns true if the target can instruction select the specified FP
571 /// immediate natively. If false, the legalizer will materialize the FP
572 /// immediate as a load from a constant pool.
573 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
577 /// Targets can use this to indicate that they only support *some*
578 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
579 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
581 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
586 /// Returns true if the operation can trap for the value type.
588 /// VT must be a legal type. By default, we optimistically assume most
589 /// operations don't trap except for divide and remainder.
590 virtual bool canOpTrap(unsigned Op, EVT VT) const;
592 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
593 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
594 /// a VAND with a constant pool entry.
595 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
600 /// Return how this operation should be treated: either it is legal, needs to
601 /// be promoted to a larger size, needs to be expanded to some other code
602 /// sequence, or the target has a custom expander for it.
603 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
604 if (VT.isExtended()) return Expand;
605 // If a target-specific SDNode requires legalization, require the target
606 // to provide custom legalization for it.
607 if (Op > array_lengthof(OpActions[0])) return Custom;
608 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
611 /// Return true if the specified operation is legal on this target or can be
612 /// made legal with custom lowering. This is used to help guide high-level
613 /// lowering decisions.
614 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
615 return (VT == MVT::Other || isTypeLegal(VT)) &&
616 (getOperationAction(Op, VT) == Legal ||
617 getOperationAction(Op, VT) == Custom);
620 /// Return true if the specified operation is legal on this target or can be
621 /// made legal using promotion. This is used to help guide high-level lowering
623 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
624 return (VT == MVT::Other || isTypeLegal(VT)) &&
625 (getOperationAction(Op, VT) == Legal ||
626 getOperationAction(Op, VT) == Promote);
629 /// Return true if the specified operation is legal on this target or can be
630 /// made legal with custom lowering or using promotion. This is used to help
631 /// guide high-level lowering decisions.
632 bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
633 return (VT == MVT::Other || isTypeLegal(VT)) &&
634 (getOperationAction(Op, VT) == Legal ||
635 getOperationAction(Op, VT) == Custom ||
636 getOperationAction(Op, VT) == Promote);
639 /// Return true if the specified operation is illegal but has a custom lowering
640 /// on that type. This is used to help guide high-level lowering
642 bool isOperationCustom(unsigned Op, EVT VT) const {
643 return (!isTypeLegal(VT) && getOperationAction(Op, VT) == Custom);
646 /// Return true if the specified operation is illegal on this target or
647 /// unlikely to be made legal with custom lowering. This is used to help guide
648 /// high-level lowering decisions.
649 bool isOperationExpand(unsigned Op, EVT VT) const {
650 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
653 /// Return true if the specified operation is legal on this target.
654 bool isOperationLegal(unsigned Op, EVT VT) const {
655 return (VT == MVT::Other || isTypeLegal(VT)) &&
656 getOperationAction(Op, VT) == Legal;
659 /// Return how this load with extension should be treated: either it is legal,
660 /// needs to be promoted to a larger size, needs to be expanded to some other
661 /// code sequence, or the target has a custom expander for it.
662 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
664 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
665 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
666 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
667 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
668 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
669 unsigned Shift = 4 * ExtType;
670 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
673 /// Return true if the specified load with extension is legal on this target.
674 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
675 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
678 /// Return true if the specified load with extension is legal or custom
680 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
681 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
682 getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
685 /// Return how this store with truncation should be treated: either it is
686 /// legal, needs to be promoted to a larger size, needs to be expanded to some
687 /// other code sequence, or the target has a custom expander for it.
688 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
689 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
690 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
691 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
692 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
693 "Table isn't big enough!");
694 return TruncStoreActions[ValI][MemI];
697 /// Return true if the specified store with truncation is legal on this
699 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
700 return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
703 /// Return true if the specified store with truncation has solution on this
705 bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
706 return isTypeLegal(ValVT) &&
707 (getTruncStoreAction(ValVT, MemVT) == Legal ||
708 getTruncStoreAction(ValVT, MemVT) == Custom);
711 /// Return how the indexed load should be treated: either it is legal, needs
712 /// to be promoted to a larger size, needs to be expanded to some other code
713 /// sequence, or the target has a custom expander for it.
715 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
716 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
717 "Table isn't big enough!");
718 unsigned Ty = (unsigned)VT.SimpleTy;
719 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
722 /// Return true if the specified indexed load is legal on this target.
723 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
724 return VT.isSimple() &&
725 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
726 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
729 /// Return how the indexed store should be treated: either it is legal, needs
730 /// to be promoted to a larger size, needs to be expanded to some other code
731 /// sequence, or the target has a custom expander for it.
733 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
734 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
735 "Table isn't big enough!");
736 unsigned Ty = (unsigned)VT.SimpleTy;
737 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
740 /// Return true if the specified indexed load is legal on this target.
741 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
742 return VT.isSimple() &&
743 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
744 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
747 /// Return how the condition code should be treated: either it is legal, needs
748 /// to be expanded to some other code sequence, or the target has a custom
751 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
752 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
753 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
754 "Table isn't big enough!");
755 // See setCondCodeAction for how this is encoded.
756 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
757 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
758 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
759 assert(Action != Promote && "Can't promote condition code!");
763 /// Return true if the specified condition code is legal on this target.
764 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
766 getCondCodeAction(CC, VT) == Legal ||
767 getCondCodeAction(CC, VT) == Custom;
771 /// If the action for this operation is to promote, this method returns the
772 /// ValueType to promote to.
773 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
774 assert(getOperationAction(Op, VT) == Promote &&
775 "This operation isn't promoted!");
777 // See if this has an explicit type specified.
778 std::map<std::pair<unsigned, MVT::SimpleValueType>,
779 MVT::SimpleValueType>::const_iterator PTTI =
780 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
781 if (PTTI != PromoteToType.end()) return PTTI->second;
783 assert((VT.isInteger() || VT.isFloatingPoint()) &&
784 "Cannot autopromote this type, add it with AddPromotedToType.");
788 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
789 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
790 "Didn't find type to promote to!");
791 } while (!isTypeLegal(NVT) ||
792 getOperationAction(Op, NVT) == Promote);
796 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
797 /// operations except for the pointer size. If AllowUnknown is true, this
798 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
799 /// otherwise it will assert.
800 EVT getValueType(const DataLayout &DL, Type *Ty,
801 bool AllowUnknown = false) const {
802 // Lower scalar pointers to native pointer types.
803 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
804 return getPointerTy(DL, PTy->getAddressSpace());
806 if (Ty->isVectorTy()) {
807 VectorType *VTy = cast<VectorType>(Ty);
808 Type *Elm = VTy->getElementType();
809 // Lower vectors of pointers to native pointer types.
810 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
811 EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
812 Elm = PointerTy.getTypeForEVT(Ty->getContext());
815 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
816 VTy->getNumElements());
818 return EVT::getEVT(Ty, AllowUnknown);
821 /// Return the MVT corresponding to this LLVM type. See getValueType.
822 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
823 bool AllowUnknown = false) const {
824 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
827 /// Return the desired alignment for ByVal or InAlloca aggregate function
828 /// arguments in the caller parameter area. This is the actual alignment, not
830 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
832 /// Return the type of registers that this ValueType will eventually require.
833 MVT getRegisterType(MVT VT) const {
834 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
835 return RegisterTypeForVT[VT.SimpleTy];
838 /// Return the type of registers that this ValueType will eventually require.
839 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
841 assert((unsigned)VT.getSimpleVT().SimpleTy <
842 array_lengthof(RegisterTypeForVT));
843 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
848 unsigned NumIntermediates;
849 (void)getVectorTypeBreakdown(Context, VT, VT1,
850 NumIntermediates, RegisterVT);
853 if (VT.isInteger()) {
854 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
856 llvm_unreachable("Unsupported extended type!");
859 /// Return the number of registers that this ValueType will eventually
862 /// This is one for any types promoted to live in larger registers, but may be
863 /// more than one for types (like i64) that are split into pieces. For types
864 /// like i140, which are first promoted then expanded, it is the number of
865 /// registers needed to hold all the bits of the original type. For an i140
866 /// on a 32 bit machine this means 5 registers.
867 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
869 assert((unsigned)VT.getSimpleVT().SimpleTy <
870 array_lengthof(NumRegistersForVT));
871 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
876 unsigned NumIntermediates;
877 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
879 if (VT.isInteger()) {
880 unsigned BitWidth = VT.getSizeInBits();
881 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
882 return (BitWidth + RegWidth - 1) / RegWidth;
884 llvm_unreachable("Unsupported extended type!");
887 /// If true, then instruction selection should seek to shrink the FP constant
888 /// of the specified type to a smaller type in order to save space and / or
890 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
892 // Return true if it is profitable to reduce the given load node to a smaller
895 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
896 virtual bool shouldReduceLoadWidth(SDNode *Load,
897 ISD::LoadExtType ExtTy,
902 /// When splitting a value of the specified type into parts, does the Lo
903 /// or Hi part come first? This usually follows the endianness, except
904 /// for ppcf128, where the Hi part always comes first.
905 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
906 return DL.isBigEndian() || VT == MVT::ppcf128;
909 /// If true, the target has custom DAG combine transformations that it can
910 /// perform for the specified node.
911 bool hasTargetDAGCombine(ISD::NodeType NT) const {
912 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
913 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
916 unsigned getGatherAllAliasesMaxDepth() const {
917 return GatherAllAliasesMaxDepth;
920 /// \brief Get maximum # of store operations permitted for llvm.memset
922 /// This function returns the maximum number of store operations permitted
923 /// to replace a call to llvm.memset. The value is set by the target at the
924 /// performance threshold for such a replacement. If OptSize is true,
925 /// return the limit for functions that have OptSize attribute.
926 unsigned getMaxStoresPerMemset(bool OptSize) const {
927 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
930 /// \brief Get maximum # of store operations permitted for llvm.memcpy
932 /// This function returns the maximum number of store operations permitted
933 /// to replace a call to llvm.memcpy. The value is set by the target at the
934 /// performance threshold for such a replacement. If OptSize is true,
935 /// return the limit for functions that have OptSize attribute.
936 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
937 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
940 /// \brief Get maximum # of store operations permitted for llvm.memmove
942 /// This function returns the maximum number of store operations permitted
943 /// to replace a call to llvm.memmove. The value is set by the target at the
944 /// performance threshold for such a replacement. If OptSize is true,
945 /// return the limit for functions that have OptSize attribute.
946 unsigned getMaxStoresPerMemmove(bool OptSize) const {
947 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
950 /// \brief Determine if the target supports unaligned memory accesses.
952 /// This function returns true if the target allows unaligned memory accesses
953 /// of the specified type in the given address space. If true, it also returns
954 /// whether the unaligned memory access is "fast" in the last argument by
955 /// reference. This is used, for example, in situations where an array
956 /// copy/move/set is converted to a sequence of store operations. Its use
957 /// helps to ensure that such replacements don't generate code that causes an
958 /// alignment error (trap) on the target machine.
959 virtual bool allowsMisalignedMemoryAccesses(EVT,
960 unsigned AddrSpace = 0,
962 bool * /*Fast*/ = nullptr) const {
966 /// Return true if the target supports a memory access of this type for the
967 /// given address space and alignment. If the access is allowed, the optional
968 /// final parameter returns if the access is also fast (as defined by the
970 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
971 unsigned AddrSpace = 0, unsigned Alignment = 1,
972 bool *Fast = nullptr) const;
974 /// Returns the target specific optimal type for load and store operations as
975 /// a result of memset, memcpy, and memmove lowering.
977 /// If DstAlign is zero that means it's safe to destination alignment can
978 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
979 /// a need to check it against alignment requirement, probably because the
980 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
981 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
982 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
983 /// does not need to be loaded. It returns EVT::Other if the type should be
984 /// determined using generic target-independent logic.
985 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
986 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
989 bool /*MemcpyStrSrc*/,
990 MachineFunction &/*MF*/) const {
994 /// Returns true if it's safe to use load / store of the specified type to
995 /// expand memcpy / memset inline.
997 /// This is mostly true for all types except for some special cases. For
998 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
999 /// fstpl which also does type conversion. Note the specified type doesn't
1000 /// have to be legal as the hook is used before type legalization.
1001 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1003 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1004 bool usesUnderscoreSetJmp() const {
1005 return UseUnderscoreSetJmp;
1008 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1009 bool usesUnderscoreLongJmp() const {
1010 return UseUnderscoreLongJmp;
1013 /// Return integer threshold on number of blocks to use jump tables rather
1014 /// than if sequence.
1015 int getMinimumJumpTableEntries() const {
1016 return MinimumJumpTableEntries;
1019 /// If a physical register, this specifies the register that
1020 /// llvm.savestack/llvm.restorestack should save and restore.
1021 unsigned getStackPointerRegisterToSaveRestore() const {
1022 return StackPointerRegisterToSaveRestore;
1025 /// If a physical register, this returns the register that receives the
1026 /// exception address on entry to an EH pad.
1028 getExceptionPointerRegister(const Constant *PersonalityFn) const {
1029 // 0 is guaranteed to be the NoRegister value on all targets
1033 /// If a physical register, this returns the register that receives the
1034 /// exception typeid on entry to a landing pad.
1036 getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1037 // 0 is guaranteed to be the NoRegister value on all targets
1041 virtual bool needsFixedCatchObjects() const {
1042 report_fatal_error("Funclet EH is not implemented for this target");
1045 /// Returns the target's jmp_buf size in bytes (if never set, the default is
1047 unsigned getJumpBufSize() const {
1051 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1053 unsigned getJumpBufAlignment() const {
1054 return JumpBufAlignment;
1057 /// Return the minimum stack alignment of an argument.
1058 unsigned getMinStackArgumentAlignment() const {
1059 return MinStackArgumentAlignment;
1062 /// Return the minimum function alignment.
1063 unsigned getMinFunctionAlignment() const {
1064 return MinFunctionAlignment;
1067 /// Return the preferred function alignment.
1068 unsigned getPrefFunctionAlignment() const {
1069 return PrefFunctionAlignment;
1072 /// Return the preferred loop alignment.
1073 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1074 return PrefLoopAlignment;
1077 /// If the target has a standard location for the stack protector guard,
1078 /// returns the address of that location. Otherwise, returns nullptr.
1079 /// DEPRECATED: please override useLoadStackGuardNode and customize
1080 /// LOAD_STACK_GUARD, or customize @llvm.stackguard().
1081 virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1083 /// Inserts necessary declarations for SSP (stack protection) purpose.
1084 /// Should be used only when getIRStackGuard returns nullptr.
1085 virtual void insertSSPDeclarations(Module &M) const;
1087 /// Return the variable that's previously inserted by insertSSPDeclarations,
1088 /// if any, otherwise return nullptr. Should be used only when
1089 /// getIRStackGuard returns nullptr.
1090 virtual Value *getSDagStackGuard(const Module &M) const;
1092 /// If the target has a standard stack protection check function that
1093 /// performs validation and error handling, returns the function. Otherwise,
1094 /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1095 /// Should be used only when getIRStackGuard returns nullptr.
1096 virtual Value *getSSPStackGuardCheck(const Module &M) const;
1098 /// If the target has a standard location for the unsafe stack pointer,
1099 /// returns the address of that location. Otherwise, returns nullptr.
1100 virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1102 /// Returns true if a cast between SrcAS and DestAS is a noop.
1103 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1107 /// Return true if the pointer arguments to CI should be aligned by aligning
1108 /// the object whose address is being passed. If so then MinSize is set to the
1109 /// minimum size the object must be to be aligned and PrefAlign is set to the
1110 /// preferred alignment.
1111 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1112 unsigned & /*PrefAlign*/) const {
1116 //===--------------------------------------------------------------------===//
1117 /// \name Helpers for TargetTransformInfo implementations
1120 /// Get the ISD node that corresponds to the Instruction class opcode.
1121 int InstructionOpcodeToISD(unsigned Opcode) const;
1123 /// Estimate the cost of type-legalization and the legalized type.
1124 std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1129 //===--------------------------------------------------------------------===//
1130 /// \name Helpers for atomic expansion.
1133 /// Returns the maximum atomic operation size (in bits) supported by
1134 /// the backend. Atomic operations greater than this size (as well
1135 /// as ones that are not naturally aligned), will be expanded by
1136 /// AtomicExpandPass into an __atomic_* library call.
1137 unsigned getMaxAtomicSizeInBitsSupported() const {
1138 return MaxAtomicSizeInBitsSupported;
1141 /// Returns the size of the smallest cmpxchg or ll/sc instruction
1142 /// the backend supports. Any smaller operations are widened in
1143 /// AtomicExpandPass.
1145 /// Note that *unlike* operations above the maximum size, atomic ops
1146 /// are still natively supported below the minimum; they just
1147 /// require a more complex expansion.
1148 unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1150 /// Whether AtomicExpandPass should automatically insert fences and reduce
1151 /// ordering for this atomic. This should be true for most architectures with
1152 /// weak memory ordering. Defaults to false.
1153 virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1157 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1158 /// corresponding pointee type. This may entail some non-trivial operations to
1159 /// truncate or reconstruct types that will be illegal in the backend. See
1160 /// ARMISelLowering for an example implementation.
1161 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1162 AtomicOrdering Ord) const {
1163 llvm_unreachable("Load linked unimplemented on this target");
1166 /// Perform a store-conditional operation to Addr. Return the status of the
1167 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1168 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1169 Value *Addr, AtomicOrdering Ord) const {
1170 llvm_unreachable("Store conditional unimplemented on this target");
1173 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1174 /// It is called by AtomicExpandPass before expanding an
1175 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1176 /// if shouldInsertFencesForAtomic returns true.
1177 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1178 /// This function should either return a nullptr, or a pointer to an IR-level
1179 /// Instruction*. Even complex fence sequences can be represented by a
1180 /// single Instruction* through an intrinsic to be lowered later.
1181 /// Backends should override this method to produce target-specific intrinsic
1182 /// for their fences.
1183 /// FIXME: Please note that the default implementation here in terms of
1184 /// IR-level fences exists for historical/compatibility reasons and is
1185 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1186 /// consistency. For example, consider the following example:
1187 /// atomic<int> x = y = 0;
1188 /// int r1, r2, r3, r4;
1199 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1200 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1201 /// IR-level fences can prevent it.
1203 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder,
1204 AtomicOrdering Ord, bool IsStore,
1205 bool IsLoad) const {
1206 if (isReleaseOrStronger(Ord) && IsStore)
1207 return Builder.CreateFence(Ord);
1212 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1213 AtomicOrdering Ord, bool IsStore,
1214 bool IsLoad) const {
1215 if (isAcquireOrStronger(Ord))
1216 return Builder.CreateFence(Ord);
1222 // Emits code that executes when the comparison result in the ll/sc
1223 // expansion of a cmpxchg instruction is such that the store-conditional will
1224 // not execute. This makes it possible to balance out the load-linked with
1225 // a dedicated instruction, if desired.
1226 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1227 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1228 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1230 /// Returns true if the given (atomic) store should be expanded by the
1231 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1232 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1236 /// Returns true if arguments should be sign-extended in lib calls.
1237 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1241 /// Returns how the given (atomic) load should be expanded by the
1242 /// IR-level AtomicExpand pass.
1243 virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1244 return AtomicExpansionKind::None;
1247 /// Returns true if the given atomic cmpxchg should be expanded by the
1248 /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1249 /// (through emitLoadLinked() and emitStoreConditional()).
1250 virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1254 /// Returns how the IR-level AtomicExpand pass should expand the given
1255 /// AtomicRMW, if at all. Default is to never expand.
1256 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1257 return AtomicExpansionKind::None;
1260 /// On some platforms, an AtomicRMW that never actually modifies the value
1261 /// (such as fetch_add of 0) can be turned into a fence followed by an
1262 /// atomic load. This may sound useless, but it makes it possible for the
1263 /// processor to keep the cacheline shared, dramatically improving
1264 /// performance. And such idempotent RMWs are useful for implementing some
1265 /// kinds of locks, see for example (justification + benchmarks):
1266 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1267 /// This method tries doing that transformation, returning the atomic load if
1268 /// it succeeds, and nullptr otherwise.
1269 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1270 /// another round of expansion.
1272 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1276 /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1277 /// SIGN_EXTEND, or ANY_EXTEND).
1278 virtual ISD::NodeType getExtendForAtomicOps() const {
1279 return ISD::ZERO_EXTEND;
1284 /// Returns true if we should normalize
1285 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1286 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1287 /// that it saves us from materializing N0 and N1 in an integer register.
1288 /// Targets that are able to perform and/or on flags should return false here.
1289 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1291 // If a target has multiple condition registers, then it likely has logical
1292 // operations on those registers.
1293 if (hasMultipleConditionRegisters())
1295 // Only do the transform if the value won't be split into multiple
1297 LegalizeTypeAction Action = getTypeAction(Context, VT);
1298 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1299 Action != TypeSplitVector;
1302 //===--------------------------------------------------------------------===//
1303 // TargetLowering Configuration Methods - These methods should be invoked by
1304 // the derived class constructor to configure this object for the target.
1307 /// Specify how the target extends the result of integer and floating point
1308 /// boolean values from i1 to a wider type. See getBooleanContents.
1309 void setBooleanContents(BooleanContent Ty) {
1310 BooleanContents = Ty;
1311 BooleanFloatContents = Ty;
1314 /// Specify how the target extends the result of integer and floating point
1315 /// boolean values from i1 to a wider type. See getBooleanContents.
1316 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1317 BooleanContents = IntTy;
1318 BooleanFloatContents = FloatTy;
1321 /// Specify how the target extends the result of a vector boolean value from a
1322 /// vector of i1 to a wider type. See getBooleanContents.
1323 void setBooleanVectorContents(BooleanContent Ty) {
1324 BooleanVectorContents = Ty;
1327 /// Specify the target scheduling preference.
1328 void setSchedulingPreference(Sched::Preference Pref) {
1329 SchedPreferenceInfo = Pref;
1332 /// Indicate whether this target prefers to use _setjmp to implement
1333 /// llvm.setjmp or the version without _. Defaults to false.
1334 void setUseUnderscoreSetJmp(bool Val) {
1335 UseUnderscoreSetJmp = Val;
1338 /// Indicate whether this target prefers to use _longjmp to implement
1339 /// llvm.longjmp or the version without _. Defaults to false.
1340 void setUseUnderscoreLongJmp(bool Val) {
1341 UseUnderscoreLongJmp = Val;
1344 /// Indicate the number of blocks to generate jump tables rather than if
1346 void setMinimumJumpTableEntries(int Val) {
1347 MinimumJumpTableEntries = Val;
1350 /// If set to a physical register, this specifies the register that
1351 /// llvm.savestack/llvm.restorestack should save and restore.
1352 void setStackPointerRegisterToSaveRestore(unsigned R) {
1353 StackPointerRegisterToSaveRestore = R;
1356 /// Tells the code generator not to expand operations into sequences that use
1357 /// the select operations if possible.
1358 void setSelectIsExpensive(bool isExpensive = true) {
1359 SelectIsExpensive = isExpensive;
1362 /// Tells the code generator that the target has multiple (allocatable)
1363 /// condition registers that can be used to store the results of comparisons
1364 /// for use by selects and conditional branches. With multiple condition
1365 /// registers, the code generator will not aggressively sink comparisons into
1366 /// the blocks of their users.
1367 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1368 HasMultipleConditionRegisters = hasManyRegs;
1371 /// Tells the code generator that the target has BitExtract instructions.
1372 /// The code generator will aggressively sink "shift"s into the blocks of
1373 /// their users if the users will generate "and" instructions which can be
1374 /// combined with "shift" to BitExtract instructions.
1375 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1376 HasExtractBitsInsn = hasExtractInsn;
1379 /// Tells the code generator not to expand logic operations on comparison
1380 /// predicates into separate sequences that increase the amount of flow
1382 void setJumpIsExpensive(bool isExpensive = true);
1384 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1385 /// with an alternative sequence of instructions.
1386 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1388 /// Tells the code generator that this target supports floating point
1389 /// exceptions and cares about preserving floating point exception behavior.
1390 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1391 HasFloatingPointExceptions = FPExceptions;
1394 /// Tells the code generator which bitwidths to bypass.
1395 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1396 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1399 /// Add the specified register class as an available regclass for the
1400 /// specified value type. This indicates the selector can handle values of
1401 /// that class natively.
1402 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1403 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1404 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1405 RegClassForVT[VT.SimpleTy] = RC;
1408 /// Remove all register classes.
1409 void clearRegisterClasses() {
1410 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
1412 AvailableRegClasses.clear();
1415 /// \brief Remove all operation actions.
1416 void clearOperationActions() {
1419 /// Return the largest legal super-reg register class of the register class
1420 /// for the specified type and its associated "cost".
1421 virtual std::pair<const TargetRegisterClass *, uint8_t>
1422 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1424 /// Once all of the register classes are added, this allows us to compute
1425 /// derived properties we expose.
1426 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1428 /// Indicate that the specified operation does not work with the specified
1429 /// type and indicate what to do about it.
1430 void setOperationAction(unsigned Op, MVT VT,
1431 LegalizeAction Action) {
1432 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1433 OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1436 /// Indicate that the specified load with extension does not work with the
1437 /// specified type and indicate what to do about it.
1438 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1439 LegalizeAction Action) {
1440 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1441 MemVT.isValid() && "Table isn't big enough!");
1442 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1443 unsigned Shift = 4 * ExtType;
1444 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1445 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1448 /// Indicate that the specified truncating store does not work with the
1449 /// specified type and indicate what to do about it.
1450 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1451 LegalizeAction Action) {
1452 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1453 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1456 /// Indicate that the specified indexed load does or does not work with the
1457 /// specified type and indicate what to do abort it.
1459 /// NOTE: All indexed mode loads are initialized to Expand in
1460 /// TargetLowering.cpp
1461 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1462 LegalizeAction Action) {
1463 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1464 (unsigned)Action < 0xf && "Table isn't big enough!");
1465 // Load action are kept in the upper half.
1466 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1467 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1470 /// Indicate that the specified indexed store does or does not work with the
1471 /// specified type and indicate what to do about it.
1473 /// NOTE: All indexed mode stores are initialized to Expand in
1474 /// TargetLowering.cpp
1475 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1476 LegalizeAction Action) {
1477 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1478 (unsigned)Action < 0xf && "Table isn't big enough!");
1479 // Store action are kept in the lower half.
1480 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1481 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1484 /// Indicate that the specified condition code is or isn't supported on the
1485 /// target and indicate what to do about it.
1486 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1487 LegalizeAction Action) {
1488 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1489 "Table isn't big enough!");
1490 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1491 /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1492 /// value and the upper 29 bits index into the second dimension of the array
1493 /// to select what 32-bit value to use.
1494 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1495 CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1496 CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1499 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1500 /// to trying a larger integer/fp until it can find one that works. If that
1501 /// default is insufficient, this method can be used by the target to override
1503 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1504 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1507 /// Convenience method to set an operation to Promote and specify the type
1508 /// in a single call.
1509 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1510 setOperationAction(Opc, OrigVT, Promote);
1511 AddPromotedToType(Opc, OrigVT, DestVT);
1514 /// Targets should invoke this method for each target independent node that
1515 /// they want to provide a custom DAG combiner for by implementing the
1516 /// PerformDAGCombine virtual method.
1517 void setTargetDAGCombine(ISD::NodeType NT) {
1518 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1519 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1522 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1523 void setJumpBufSize(unsigned Size) {
1527 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1529 void setJumpBufAlignment(unsigned Align) {
1530 JumpBufAlignment = Align;
1533 /// Set the target's minimum function alignment (in log2(bytes))
1534 void setMinFunctionAlignment(unsigned Align) {
1535 MinFunctionAlignment = Align;
1538 /// Set the target's preferred function alignment. This should be set if
1539 /// there is a performance benefit to higher-than-minimum alignment (in
1541 void setPrefFunctionAlignment(unsigned Align) {
1542 PrefFunctionAlignment = Align;
1545 /// Set the target's preferred loop alignment. Default alignment is zero, it
1546 /// means the target does not care about loop alignment. The alignment is
1547 /// specified in log2(bytes). The target may also override
1548 /// getPrefLoopAlignment to provide per-loop values.
1549 void setPrefLoopAlignment(unsigned Align) {
1550 PrefLoopAlignment = Align;
1553 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1554 void setMinStackArgumentAlignment(unsigned Align) {
1555 MinStackArgumentAlignment = Align;
1558 /// Set the maximum atomic operation size supported by the
1559 /// backend. Atomic operations greater than this size (as well as
1560 /// ones that are not naturally aligned), will be expanded by
1561 /// AtomicExpandPass into an __atomic_* library call.
1562 void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1563 MaxAtomicSizeInBitsSupported = SizeInBits;
1566 // Sets the minimum cmpxchg or ll/sc size supported by the backend.
1567 void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1568 MinCmpXchgSizeInBits = SizeInBits;
1572 //===--------------------------------------------------------------------===//
1573 // Addressing mode description hooks (used by LSR etc).
1576 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1577 /// instructions reading the address. This allows as much computation as
1578 /// possible to be done in the address mode for that operand. This hook lets
1579 /// targets also pass back when this should be done on intrinsics which
1581 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1582 SmallVectorImpl<Value*> &/*Ops*/,
1583 Type *&/*AccessTy*/,
1584 unsigned AddrSpace = 0) const {
1588 /// This represents an addressing mode of:
1589 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1590 /// If BaseGV is null, there is no BaseGV.
1591 /// If BaseOffs is zero, there is no base offset.
1592 /// If HasBaseReg is false, there is no base register.
1593 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1596 GlobalValue *BaseGV;
1600 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1603 /// Return true if the addressing mode represented by AM is legal for this
1604 /// target, for a load/store of the specified type.
1606 /// The type may be VoidTy, in which case only return true if the addressing
1607 /// mode is legal for a load/store of any legal type. TODO: Handle
1608 /// pre/postinc as well.
1610 /// If the address space cannot be determined, it will be -1.
1612 /// TODO: Remove default argument
1613 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1614 Type *Ty, unsigned AddrSpace) const;
1616 /// \brief Return the cost of the scaling factor used in the addressing mode
1617 /// represented by AM for this target, for a load/store of the specified type.
1619 /// If the AM is supported, the return value must be >= 0.
1620 /// If the AM is not supported, it returns a negative value.
1621 /// TODO: Handle pre/postinc as well.
1622 /// TODO: Remove default argument
1623 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1624 Type *Ty, unsigned AS = 0) const {
1625 // Default: assume that any scaling factor used in a legal AM is free.
1626 if (isLegalAddressingMode(DL, AM, Ty, AS))
1631 /// Return true if the specified immediate is legal icmp immediate, that is
1632 /// the target has icmp instructions which can compare a register against the
1633 /// immediate without having to materialize the immediate into a register.
1634 virtual bool isLegalICmpImmediate(int64_t) const {
1638 /// Return true if the specified immediate is legal add immediate, that is the
1639 /// target has add instructions which can add a register with the immediate
1640 /// without having to materialize the immediate into a register.
1641 virtual bool isLegalAddImmediate(int64_t) const {
1645 /// Return true if it's significantly cheaper to shift a vector by a uniform
1646 /// scalar than by an amount which will vary across each lane. On x86, for
1647 /// example, there is a "psllw" instruction for the former case, but no simple
1648 /// instruction for a general "a << b" operation on vectors.
1649 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1653 /// Return true if it's free to truncate a value of type FromTy to type
1654 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1655 /// by referencing its sub-register AX.
1656 /// Targets must return false when FromTy <= ToTy.
1657 virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
1661 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
1662 /// whether a call is in tail position. Typically this means that both results
1663 /// would be assigned to the same register or stack slot, but it could mean
1664 /// the target performs adequate checks of its own before proceeding with the
1665 /// tail call. Targets must return false when FromTy <= ToTy.
1666 virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
1670 virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
1674 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1676 /// Return true if the extension represented by \p I is free.
1677 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1678 /// this method can use the context provided by \p I to decide
1679 /// whether or not \p I is free.
1680 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1681 /// In other words, if is[Z|FP]Free returns true, then this method
1682 /// returns true as well. The converse is not true.
1683 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1684 /// \pre \p I must be a sign, zero, or fp extension.
1685 bool isExtFree(const Instruction *I) const {
1686 switch (I->getOpcode()) {
1687 case Instruction::FPExt:
1688 if (isFPExtFree(EVT::getEVT(I->getType())))
1691 case Instruction::ZExt:
1692 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1695 case Instruction::SExt:
1698 llvm_unreachable("Instruction is not an extension");
1700 return isExtFreeImpl(I);
1703 /// Return true if any actual instruction that defines a value of type FromTy
1704 /// implicitly zero-extends the value to ToTy in the result register.
1706 /// The function should return true when it is likely that the truncate can
1707 /// be freely folded with an instruction defining a value of FromTy. If
1708 /// the defining instruction is unknown (because you're looking at a
1709 /// function argument, PHI, etc.) then the target may require an
1710 /// explicit truncate, which is not necessarily free, but this function
1711 /// does not deal with those cases.
1712 /// Targets must return false when FromTy >= ToTy.
1713 virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
1717 virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
1721 /// Return true if the target supplies and combines to a paired load
1722 /// two loaded values of type LoadedType next to each other in memory.
1723 /// RequiredAlignment gives the minimal alignment constraints that must be met
1724 /// to be able to select this paired load.
1726 /// This information is *not* used to generate actual paired loads, but it is
1727 /// used to generate a sequence of loads that is easier to combine into a
1729 /// For instance, something like this:
1730 /// a = load i64* addr
1731 /// b = trunc i64 a to i32
1732 /// c = lshr i64 a, 32
1733 /// d = trunc i64 c to i32
1734 /// will be optimized into:
1735 /// b = load i32* addr1
1736 /// d = load i32* addr2
1737 /// Where addr1 = addr2 +/- sizeof(i32).
1739 /// In other words, unless the target performs a post-isel load combining,
1740 /// this information should not be provided because it will generate more
1742 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1743 unsigned & /*RequiredAligment*/) const {
1747 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1748 unsigned & /*RequiredAligment*/) const {
1752 /// \brief Get the maximum supported factor for interleaved memory accesses.
1753 /// Default to be the minimum interleave factor: 2.
1754 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
1756 /// \brief Lower an interleaved load to target specific intrinsics. Return
1757 /// true on success.
1759 /// \p LI is the vector load instruction.
1760 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
1761 /// \p Indices is the corresponding indices for each shufflevector.
1762 /// \p Factor is the interleave factor.
1763 virtual bool lowerInterleavedLoad(LoadInst *LI,
1764 ArrayRef<ShuffleVectorInst *> Shuffles,
1765 ArrayRef<unsigned> Indices,
1766 unsigned Factor) const {
1770 /// \brief Lower an interleaved store to target specific intrinsics. Return
1771 /// true on success.
1773 /// \p SI is the vector store instruction.
1774 /// \p SVI is the shufflevector to RE-interleave the stored vector.
1775 /// \p Factor is the interleave factor.
1776 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1777 unsigned Factor) const {
1781 /// Return true if zero-extending the specific node Val to type VT2 is free
1782 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1783 /// because it's folded such as X86 zero-extending loads).
1784 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1785 return isZExtFree(Val.getValueType(), VT2);
1788 /// Return true if an fpext operation is free (for instance, because
1789 /// single-precision floating-point numbers are implicitly extended to
1790 /// double-precision).
1791 virtual bool isFPExtFree(EVT VT) const {
1792 assert(VT.isFloatingPoint());
1796 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1797 /// extend node) is profitable.
1798 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1800 /// Return true if an fneg operation is free to the point where it is never
1801 /// worthwhile to replace it with a bitwise operation.
1802 virtual bool isFNegFree(EVT VT) const {
1803 assert(VT.isFloatingPoint());
1807 /// Return true if an fabs operation is free to the point where it is never
1808 /// worthwhile to replace it with a bitwise operation.
1809 virtual bool isFAbsFree(EVT VT) const {
1810 assert(VT.isFloatingPoint());
1814 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1815 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1816 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1818 /// NOTE: This may be called before legalization on types for which FMAs are
1819 /// not legal, but should return true if those types will eventually legalize
1820 /// to types that support FMAs. After legalization, it will only be called on
1821 /// types that support FMAs (via Legal or Custom actions)
1822 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1826 /// Return true if it's profitable to narrow operations of type VT1 to
1827 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1829 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1833 /// \brief Return true if it is beneficial to convert a load of a constant to
1834 /// just the constant itself.
1835 /// On some targets it might be more efficient to use a combination of
1836 /// arithmetic instructions to materialize the constant instead of loading it
1837 /// from a constant pool.
1838 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1843 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1844 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1845 /// has custom lowering that depends on the index of the first element,
1846 /// and only the target knows which lowering is cheap.
1847 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1851 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
1852 // even if the vector itself has multiple uses.
1853 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
1857 //===--------------------------------------------------------------------===//
1858 // Runtime Library hooks
1861 /// Rename the default libcall routine name for the specified libcall.
1862 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1863 LibcallRoutineNames[Call] = Name;
1866 /// Get the libcall routine name for the specified libcall.
1867 const char *getLibcallName(RTLIB::Libcall Call) const {
1868 return LibcallRoutineNames[Call];
1871 /// Override the default CondCode to be used to test the result of the
1872 /// comparison libcall against zero.
1873 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1874 CmpLibcallCCs[Call] = CC;
1877 /// Get the CondCode that's to be used to test the result of the comparison
1878 /// libcall against zero.
1879 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1880 return CmpLibcallCCs[Call];
1883 /// Set the CallingConv that should be used for the specified libcall.
1884 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1885 LibcallCallingConvs[Call] = CC;
1888 /// Get the CallingConv that should be used for the specified libcall.
1889 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1890 return LibcallCallingConvs[Call];
1894 const TargetMachine &TM;
1896 /// Tells the code generator not to expand operations into sequences that use
1897 /// the select operations if possible.
1898 bool SelectIsExpensive;
1900 /// Tells the code generator that the target has multiple (allocatable)
1901 /// condition registers that can be used to store the results of comparisons
1902 /// for use by selects and conditional branches. With multiple condition
1903 /// registers, the code generator will not aggressively sink comparisons into
1904 /// the blocks of their users.
1905 bool HasMultipleConditionRegisters;
1907 /// Tells the code generator that the target has BitExtract instructions.
1908 /// The code generator will aggressively sink "shift"s into the blocks of
1909 /// their users if the users will generate "and" instructions which can be
1910 /// combined with "shift" to BitExtract instructions.
1911 bool HasExtractBitsInsn;
1913 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1916 /// Tells the code generator to bypass slow divide or remainder
1917 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1918 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1919 /// div/rem when the operands are positive and less than 256.
1920 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1922 /// Tells the code generator that it shouldn't generate extra flow control
1923 /// instructions and should attempt to combine flow control instructions via
1925 bool JumpIsExpensive;
1927 /// Whether the target supports or cares about preserving floating point
1928 /// exception behavior.
1929 bool HasFloatingPointExceptions;
1931 /// This target prefers to use _setjmp to implement llvm.setjmp.
1933 /// Defaults to false.
1934 bool UseUnderscoreSetJmp;
1936 /// This target prefers to use _longjmp to implement llvm.longjmp.
1938 /// Defaults to false.
1939 bool UseUnderscoreLongJmp;
1941 /// Number of blocks threshold to use jump tables.
1942 int MinimumJumpTableEntries;
1944 /// Information about the contents of the high-bits in boolean values held in
1945 /// a type wider than i1. See getBooleanContents.
1946 BooleanContent BooleanContents;
1948 /// Information about the contents of the high-bits in boolean values held in
1949 /// a type wider than i1. See getBooleanContents.
1950 BooleanContent BooleanFloatContents;
1952 /// Information about the contents of the high-bits in boolean vector values
1953 /// when the element type is wider than i1. See getBooleanContents.
1954 BooleanContent BooleanVectorContents;
1956 /// The target scheduling preference: shortest possible total cycles or lowest
1958 Sched::Preference SchedPreferenceInfo;
1960 /// The size, in bytes, of the target's jmp_buf buffers
1961 unsigned JumpBufSize;
1963 /// The alignment, in bytes, of the target's jmp_buf buffers
1964 unsigned JumpBufAlignment;
1966 /// The minimum alignment that any argument on the stack needs to have.
1967 unsigned MinStackArgumentAlignment;
1969 /// The minimum function alignment (used when optimizing for size, and to
1970 /// prevent explicitly provided alignment from leading to incorrect code).
1971 unsigned MinFunctionAlignment;
1973 /// The preferred function alignment (used when alignment unspecified and
1974 /// optimizing for speed).
1975 unsigned PrefFunctionAlignment;
1977 /// The preferred loop alignment.
1978 unsigned PrefLoopAlignment;
1980 /// Size in bits of the maximum atomics size the backend supports.
1981 /// Accesses larger than this will be expanded by AtomicExpandPass.
1982 unsigned MaxAtomicSizeInBitsSupported;
1984 /// Size in bits of the minimum cmpxchg or ll/sc operation the
1985 /// backend supports.
1986 unsigned MinCmpXchgSizeInBits;
1988 /// If set to a physical register, this specifies the register that
1989 /// llvm.savestack/llvm.restorestack should save and restore.
1990 unsigned StackPointerRegisterToSaveRestore;
1992 /// This indicates the default register class to use for each ValueType the
1993 /// target supports natively.
1994 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1995 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1996 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1998 /// This indicates the "representative" register class to use for each
1999 /// ValueType the target supports natively. This information is used by the
2000 /// scheduler to track register pressure. By default, the representative
2001 /// register class is the largest legal super-reg register class of the
2002 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2003 /// representative class would be GR32.
2004 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2006 /// This indicates the "cost" of the "representative" register class for each
2007 /// ValueType. The cost is used by the scheduler to approximate register
2009 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2011 /// For any value types we are promoting or expanding, this contains the value
2012 /// type that we are changing to. For Expanded types, this contains one step
2013 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2014 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2015 /// the same type (e.g. i32 -> i32).
2016 MVT TransformToType[MVT::LAST_VALUETYPE];
2018 /// For each operation and each value type, keep a LegalizeAction that
2019 /// indicates how instruction selection should deal with the operation. Most
2020 /// operations are Legal (aka, supported natively by the target), but
2021 /// operations that are not should be described. Note that operations on
2022 /// non-legal value types are not described here.
2023 LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2025 /// For each load extension type and each value type, keep a LegalizeAction
2026 /// that indicates how instruction selection should deal with a load of a
2027 /// specific value type and extension type. Uses 4-bits to store the action
2028 /// for each of the 4 load ext types.
2029 uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2031 /// For each value type pair keep a LegalizeAction that indicates whether a
2032 /// truncating store of a specific value type and truncating type is legal.
2033 LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2035 /// For each indexed mode and each value type, keep a pair of LegalizeAction
2036 /// that indicates how instruction selection should deal with the load /
2039 /// The first dimension is the value_type for the reference. The second
2040 /// dimension represents the various modes for load store.
2041 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2043 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2044 /// indicates how instruction selection should deal with the condition code.
2046 /// Because each CC action takes up 4 bits, we need to have the array size be
2047 /// large enough to fit all of the value types. This can be done by rounding
2048 /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2049 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2052 ValueTypeActionImpl ValueTypeActions;
2055 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2058 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
2060 /// Targets can specify ISD nodes that they would like PerformDAGCombine
2061 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2064 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2066 /// For operations that must be promoted to a specific type, this holds the
2067 /// destination type. This map should be sparse, so don't hold it as an
2070 /// Targets add entries to this map with AddPromotedToType(..), clients access
2071 /// this with getTypeToPromoteTo(..).
2072 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2075 /// Stores the name each libcall.
2076 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
2078 /// The ISD::CondCode that should be used to test the result of each of the
2079 /// comparison libcall against zero.
2080 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2082 /// Stores the CallingConv that should be used for each libcall.
2083 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2086 /// Return true if the extension represented by \p I is free.
2087 /// \pre \p I is a sign, zero, or fp extension and
2088 /// is[Z|FP]ExtFree of the related types is not true.
2089 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2091 /// Depth that GatherAllAliases should should continue looking for chain
2092 /// dependencies when trying to find a more preferrable chain. As an
2093 /// approximation, this should be more than the number of consecutive stores
2094 /// expected to be merged.
2095 unsigned GatherAllAliasesMaxDepth;
2097 /// \brief Specify maximum number of store instructions per memset call.
2099 /// When lowering \@llvm.memset this field specifies the maximum number of
2100 /// store operations that may be substituted for the call to memset. Targets
2101 /// must set this value based on the cost threshold for that target. Targets
2102 /// should assume that the memset will be done using as many of the largest
2103 /// store operations first, followed by smaller ones, if necessary, per
2104 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2105 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2106 /// store. This only applies to setting a constant array of a constant size.
2107 unsigned MaxStoresPerMemset;
2109 /// Maximum number of stores operations that may be substituted for the call
2110 /// to memset, used for functions with OptSize attribute.
2111 unsigned MaxStoresPerMemsetOptSize;
2113 /// \brief Specify maximum bytes of store instructions per memcpy call.
2115 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2116 /// store operations that may be substituted for a call to memcpy. Targets
2117 /// must set this value based on the cost threshold for that target. Targets
2118 /// should assume that the memcpy will be done using as many of the largest
2119 /// store operations first, followed by smaller ones, if necessary, per
2120 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2121 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2122 /// and one 1-byte store. This only applies to copying a constant array of
2124 unsigned MaxStoresPerMemcpy;
2126 /// Maximum number of store operations that may be substituted for a call to
2127 /// memcpy, used for functions with OptSize attribute.
2128 unsigned MaxStoresPerMemcpyOptSize;
2130 /// \brief Specify maximum bytes of store instructions per memmove call.
2132 /// When lowering \@llvm.memmove this field specifies the maximum number of
2133 /// store instructions that may be substituted for a call to memmove. Targets
2134 /// must set this value based on the cost threshold for that target. Targets
2135 /// should assume that the memmove will be done using as many of the largest
2136 /// store operations first, followed by smaller ones, if necessary, per
2137 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2138 /// with 8-bit alignment would result in nine 1-byte stores. This only
2139 /// applies to copying a constant array of constant size.
2140 unsigned MaxStoresPerMemmove;
2142 /// Maximum number of store instructions that may be substituted for a call to
2143 /// memmove, used for functions with OptSize attribute.
2144 unsigned MaxStoresPerMemmoveOptSize;
2146 /// Tells the code generator that select is more expensive than a branch if
2147 /// the branch is usually predicted right.
2148 bool PredictableSelectIsExpensive;
2150 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
2151 /// a mask of a single bit, a compare, and a branch into a single instruction.
2152 bool MaskAndBranchFoldingIsLegal;
2154 /// \see enableExtLdPromotion.
2155 bool EnableExtLdPromotion;
2158 /// Return true if the value types that can be represented by the specified
2159 /// register class are all legal.
2160 bool isLegalRC(const TargetRegisterClass *RC) const;
2162 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2163 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2164 MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2165 MachineBasicBlock *MBB) const;
2168 /// This class defines information used to lower LLVM code to legal SelectionDAG
2169 /// operators that the target instruction selector can accept natively.
2171 /// This class also defines callbacks that targets must implement to lower
2172 /// target-specific constructs to SelectionDAG operators.
2173 class TargetLowering : public TargetLoweringBase {
2174 TargetLowering(const TargetLowering&) = delete;
2175 void operator=(const TargetLowering&) = delete;
2178 /// NOTE: The TargetMachine owns TLOF.
2179 explicit TargetLowering(const TargetMachine &TM);
2181 bool isPositionIndependent() const;
2183 /// Returns true by value, base pointer and offset pointer and addressing mode
2184 /// by reference if the node's address can be legally represented as
2185 /// pre-indexed load / store address.
2186 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2187 SDValue &/*Offset*/,
2188 ISD::MemIndexedMode &/*AM*/,
2189 SelectionDAG &/*DAG*/) const {
2193 /// Returns true by value, base pointer and offset pointer and addressing mode
2194 /// by reference if this node can be combined with a load / store to form a
2195 /// post-indexed load / store.
2196 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2198 SDValue &/*Offset*/,
2199 ISD::MemIndexedMode &/*AM*/,
2200 SelectionDAG &/*DAG*/) const {
2204 /// Return the entry encoding for a jump table in the current function. The
2205 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2206 virtual unsigned getJumpTableEncoding() const;
2208 virtual const MCExpr *
2209 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2210 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2211 MCContext &/*Ctx*/) const {
2212 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2215 /// Returns relocation base for the given PIC jumptable.
2216 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2217 SelectionDAG &DAG) const;
2219 /// This returns the relocation base for the given PIC jumptable, the same as
2220 /// getPICJumpTableRelocBase, but as an MCExpr.
2221 virtual const MCExpr *
2222 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2223 unsigned JTI, MCContext &Ctx) const;
2225 /// Return true if folding a constant offset with the given GlobalAddress is
2226 /// legal. It is frequently not legal in PIC relocation models.
2227 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2229 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2230 SDValue &Chain) const;
2232 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2233 SDValue &NewRHS, ISD::CondCode &CCCode,
2234 const SDLoc &DL) const;
2236 /// Returns a pair of (return value, chain).
2237 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2238 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2239 EVT RetVT, ArrayRef<SDValue> Ops,
2240 bool isSigned, const SDLoc &dl,
2241 bool doesNotReturn = false,
2242 bool isReturnValueUsed = true) const;
2244 /// Check whether parameters to a call that are passed in callee saved
2245 /// registers are the same as from the calling function. This needs to be
2246 /// checked for tail call eligibility.
2247 bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2248 const uint32_t *CallerPreservedMask,
2249 const SmallVectorImpl<CCValAssign> &ArgLocs,
2250 const SmallVectorImpl<SDValue> &OutVals) const;
2252 //===--------------------------------------------------------------------===//
2253 // TargetLowering Optimization Methods
2256 /// A convenience struct that encapsulates a DAG, and two SDValues for
2257 /// returning information from TargetLowering to its clients that want to
2259 struct TargetLoweringOpt {
2266 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2268 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2270 bool LegalTypes() const { return LegalTys; }
2271 bool LegalOperations() const { return LegalOps; }
2273 bool CombineTo(SDValue O, SDValue N) {
2279 /// Check to see if the specified operand of the specified instruction is a
2280 /// constant integer. If so, check to see if there are any bits set in the
2281 /// constant that are not demanded. If so, shrink the constant and return
2283 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2285 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2286 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2287 /// generalized for targets with other types of implicit widening casts.
2288 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2292 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2293 /// result of Op are ever used downstream. If we can use this information to
2294 /// simplify Op, create a new simplified DAG node and return true, returning
2295 /// the original and new nodes in Old and New. Otherwise, analyze the
2296 /// expression and return a mask of KnownOne and KnownZero bits for the
2297 /// expression (used to simplify the caller). The KnownZero/One bits may only
2298 /// be accurate for those bits in the DemandedMask.
2299 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2300 APInt &KnownZero, APInt &KnownOne,
2301 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2303 /// Determine which of the bits specified in Mask are known to be either zero
2304 /// or one and return them in the KnownZero/KnownOne bitsets.
2305 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2308 const SelectionDAG &DAG,
2309 unsigned Depth = 0) const;
2311 /// This method can be implemented by targets that want to expose additional
2312 /// information about sign bits to the DAG Combiner.
2313 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2314 const SelectionDAG &DAG,
2315 unsigned Depth = 0) const;
2317 struct DAGCombinerInfo {
2318 void *DC; // The DAG Combiner object.
2320 bool CalledByLegalizer;
2324 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2325 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2327 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2328 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2329 bool isAfterLegalizeVectorOps() const {
2330 return Level == AfterLegalizeDAG;
2332 CombineLevel getDAGCombineLevel() { return Level; }
2333 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2335 void AddToWorklist(SDNode *N);
2336 void RemoveFromWorklist(SDNode *N);
2337 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2338 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2339 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2341 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2344 /// Return if the N is a constant or constant vector equal to the true value
2345 /// from getBooleanContents().
2346 bool isConstTrueVal(const SDNode *N) const;
2348 /// Return if the N is a constant or constant vector equal to the false value
2349 /// from getBooleanContents().
2350 bool isConstFalseVal(const SDNode *N) const;
2352 /// Return a constant of type VT that contains a true value that respects
2353 /// getBooleanContents()
2354 SDValue getConstTrueVal(SelectionDAG &DAG, EVT VT, const SDLoc &DL) const;
2356 /// Return if \p N is a True value when extended to \p VT.
2357 bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
2359 /// Try to simplify a setcc built with the specified operands and cc. If it is
2360 /// unable to simplify it, return a null SDValue.
2361 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2362 bool foldBooleans, DAGCombinerInfo &DCI,
2363 const SDLoc &dl) const;
2365 /// Returns true (and the GlobalValue and the offset) if the node is a
2366 /// GlobalAddress + offset.
2368 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2370 /// This method will be invoked for all target nodes and for any
2371 /// target-independent nodes that the target has registered with invoke it
2374 /// The semantics are as follows:
2376 /// SDValue.Val == 0 - No change was made
2377 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2378 /// otherwise - N should be replaced by the returned Operand.
2380 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2381 /// more complex transformations.
2383 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2385 /// Return true if it is profitable to move a following shift through this
2386 // node, adjusting any immediate operands as necessary to preserve semantics.
2387 // This transformation may not be desirable if it disrupts a particularly
2388 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2389 // By default, it returns true.
2390 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2394 /// Return true if the target has native support for the specified value type
2395 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2396 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2397 /// and some i16 instructions are slow.
2398 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2399 // By default, assume all legal types are desirable.
2400 return isTypeLegal(VT);
2403 /// Return true if it is profitable for dag combiner to transform a floating
2404 /// point op of specified opcode to a equivalent op of an integer
2405 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2406 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2411 /// This method query the target whether it is beneficial for dag combiner to
2412 /// promote the specified node. If true, it should return the desired
2413 /// promotion type by reference.
2414 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2418 /// Return true if the target supports swifterror attribute. It optimizes
2419 /// loads and stores to reading and writing a specific register.
2420 virtual bool supportSwiftError() const {
2424 /// Return true if the target supports that a subset of CSRs for the given
2425 /// machine function is handled explicitly via copies.
2426 virtual bool supportSplitCSR(MachineFunction *MF) const {
2430 /// Return true if the MachineFunction contains a COPY which would imply
2431 /// HasCopyImplyingStackAdjustment.
2432 virtual bool hasCopyImplyingStackAdjustment(MachineFunction *MF) const {
2436 /// Perform necessary initialization to handle a subset of CSRs explicitly
2437 /// via copies. This function is called at the beginning of instruction
2439 virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
2440 llvm_unreachable("Not Implemented");
2443 /// Insert explicit copies in entry and exit blocks. We copy a subset of
2444 /// CSRs to virtual registers in the entry block, and copy them back to
2445 /// physical registers in the exit blocks. This function is called at the end
2446 /// of instruction selection.
2447 virtual void insertCopiesSplitCSR(
2448 MachineBasicBlock *Entry,
2449 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2450 llvm_unreachable("Not Implemented");
2453 //===--------------------------------------------------------------------===//
2454 // Lowering methods - These methods must be implemented by targets so that
2455 // the SelectionDAGBuilder code knows how to lower these.
2458 /// This hook must be implemented to lower the incoming (formal) arguments,
2459 /// described by the Ins array, into the specified DAG. The implementation
2460 /// should fill in the InVals array with legal-type argument values, and
2461 /// return the resulting token chain value.
2463 virtual SDValue LowerFormalArguments(
2464 SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
2465 const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
2466 SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
2467 llvm_unreachable("Not Implemented");
2470 struct ArgListEntry {
2479 bool isInAlloca : 1;
2480 bool isReturned : 1;
2481 bool isSwiftSelf : 1;
2482 bool isSwiftError : 1;
2485 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2486 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2487 isReturned(false), isSwiftSelf(false), isSwiftError(false),
2490 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2492 typedef std::vector<ArgListEntry> ArgListTy;
2494 /// This structure contains all information that is necessary for lowering
2495 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2496 /// needs to lower a call, and targets will see this struct in their LowerCall
2498 struct CallLoweringInfo {
2505 bool DoesNotReturn : 1;
2506 bool IsReturnValueUsed : 1;
2507 bool IsConvergent : 1;
2509 // IsTailCall should be modified by implementations of
2510 // TargetLowering::LowerCall that perform tail call conversions.
2513 unsigned NumFixedArgs;
2514 CallingConv::ID CallConv;
2519 ImmutableCallSite *CS;
2521 SmallVector<ISD::OutputArg, 32> Outs;
2522 SmallVector<SDValue, 32> OutVals;
2523 SmallVector<ISD::InputArg, 32> Ins;
2524 SmallVector<SDValue, 4> InVals;
2526 CallLoweringInfo(SelectionDAG &DAG)
2527 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2528 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2529 IsConvergent(false), IsTailCall(false), NumFixedArgs(-1),
2530 CallConv(CallingConv::C), DAG(DAG), CS(nullptr), IsPatchPoint(false) {
2533 CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
2538 CallLoweringInfo &setChain(SDValue InChain) {
2543 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2544 SDValue Target, ArgListTy &&ArgsList) {
2548 NumFixedArgs = Args.size();
2549 Args = std::move(ArgsList);
2553 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2554 SDValue Target, ArgListTy &&ArgsList,
2555 ImmutableCallSite &Call) {
2558 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2560 Call.doesNotReturn() ||
2561 (!Call.isInvoke() &&
2562 isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
2563 IsVarArg = FTy->isVarArg();
2564 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2565 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2566 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2570 CallConv = Call.getCallingConv();
2571 NumFixedArgs = FTy->getNumParams();
2572 Args = std::move(ArgsList);
2579 CallLoweringInfo &setInRegister(bool Value = true) {
2584 CallLoweringInfo &setNoReturn(bool Value = true) {
2585 DoesNotReturn = Value;
2589 CallLoweringInfo &setVarArg(bool Value = true) {
2594 CallLoweringInfo &setTailCall(bool Value = true) {
2599 CallLoweringInfo &setDiscardResult(bool Value = true) {
2600 IsReturnValueUsed = !Value;
2604 CallLoweringInfo &setConvergent(bool Value = true) {
2605 IsConvergent = Value;
2609 CallLoweringInfo &setSExtResult(bool Value = true) {
2614 CallLoweringInfo &setZExtResult(bool Value = true) {
2619 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2620 IsPatchPoint = Value;
2624 ArgListTy &getArgs() {
2630 /// This function lowers an abstract call to a function into an actual call.
2631 /// This returns a pair of operands. The first element is the return value
2632 /// for the function (if RetTy is not VoidTy). The second element is the
2633 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2634 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2636 /// This hook must be implemented to lower calls into the specified
2637 /// DAG. The outgoing arguments to the call are described by the Outs array,
2638 /// and the values to be returned by the call are described by the Ins
2639 /// array. The implementation should fill in the InVals array with legal-type
2640 /// return values from the call, and return the resulting token chain value.
2642 LowerCall(CallLoweringInfo &/*CLI*/,
2643 SmallVectorImpl<SDValue> &/*InVals*/) const {
2644 llvm_unreachable("Not Implemented");
2647 /// Target-specific cleanup for formal ByVal parameters.
2648 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2650 /// This hook should be implemented to check whether the return values
2651 /// described by the Outs array can fit into the return registers. If false
2652 /// is returned, an sret-demotion is performed.
2653 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2654 MachineFunction &/*MF*/, bool /*isVarArg*/,
2655 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2656 LLVMContext &/*Context*/) const
2658 // Return true by default to get preexisting behavior.
2662 /// This hook must be implemented to lower outgoing return values, described
2663 /// by the Outs array, into the specified DAG. The implementation should
2664 /// return the resulting token chain value.
2665 virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2667 const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
2668 const SmallVectorImpl<SDValue> & /*OutVals*/,
2669 const SDLoc & /*dl*/,
2670 SelectionDAG & /*DAG*/) const {
2671 llvm_unreachable("Not Implemented");
2674 /// Return true if result of the specified node is used by a return node
2675 /// only. It also compute and return the input chain for the tail call.
2677 /// This is used to determine whether it is possible to codegen a libcall as
2678 /// tail call at legalization time.
2679 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2683 /// Return true if the target may be able emit the call instruction as a tail
2684 /// call. This is used by optimization passes to determine if it's profitable
2685 /// to duplicate return instructions to enable tailcall optimization.
2686 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2690 /// Return the builtin name for the __builtin___clear_cache intrinsic
2691 /// Default is to invoke the clear cache library call
2692 virtual const char * getClearCacheBuiltinName() const {
2693 return "__clear_cache";
2696 /// Return the register ID of the name passed in. Used by named register
2697 /// global variables extension. There is no target-independent behaviour
2698 /// so the default action is to bail.
2699 virtual unsigned getRegisterByName(const char* RegName, EVT VT,
2700 SelectionDAG &DAG) const {
2701 report_fatal_error("Named registers not implemented for this target");
2704 /// Return the type that should be used to zero or sign extend a
2705 /// zeroext/signext integer return value. FIXME: Some C calling conventions
2706 /// require the return type to be promoted, but this is not true all the time,
2707 /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
2708 /// conventions. The frontend should handle this and include all of the
2709 /// necessary information.
2710 virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
2711 ISD::NodeType /*ExtendKind*/) const {
2712 EVT MinVT = getRegisterType(Context, MVT::i32);
2713 return VT.bitsLT(MinVT) ? MinVT : VT;
2716 /// For some targets, an LLVM struct type must be broken down into multiple
2717 /// simple types, but the calling convention specifies that the entire struct
2718 /// must be passed in a block of consecutive registers.
2720 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2721 bool isVarArg) const {
2725 /// Returns a 0 terminated array of registers that can be safely used as
2726 /// scratch registers.
2727 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2731 /// This callback is used to prepare for a volatile or atomic load.
2732 /// It takes a chain node as input and returns the chain for the load itself.
2734 /// Having a callback like this is necessary for targets like SystemZ,
2735 /// which allows a CPU to reuse the result of a previous load indefinitely,
2736 /// even if a cache-coherent store is performed by another CPU. The default
2737 /// implementation does nothing.
2738 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
2739 SelectionDAG &DAG) const {
2743 /// This callback is invoked by the type legalizer to legalize nodes with an
2744 /// illegal operand type but legal result types. It replaces the
2745 /// LowerOperation callback in the type Legalizer. The reason we can not do
2746 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2747 /// use this callback.
2749 /// TODO: Consider merging with ReplaceNodeResults.
2751 /// The target places new result values for the node in Results (their number
2752 /// and types must exactly match those of the original return values of
2753 /// the node), or leaves Results empty, which indicates that the node is not
2754 /// to be custom lowered after all.
2755 /// The default implementation calls LowerOperation.
2756 virtual void LowerOperationWrapper(SDNode *N,
2757 SmallVectorImpl<SDValue> &Results,
2758 SelectionDAG &DAG) const;
2760 /// This callback is invoked for operations that are unsupported by the
2761 /// target, which are registered to use 'custom' lowering, and whose defined
2762 /// values are all legal. If the target has no operations that require custom
2763 /// lowering, it need not implement this. The default implementation of this
2765 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2767 /// This callback is invoked when a node result type is illegal for the
2768 /// target, and the operation was registered to use 'custom' lowering for that
2769 /// result type. The target places new result values for the node in Results
2770 /// (their number and types must exactly match those of the original return
2771 /// values of the node), or leaves Results empty, which indicates that the
2772 /// node is not to be custom lowered after all.
2774 /// If the target has no operations that require custom lowering, it need not
2775 /// implement this. The default implementation aborts.
2776 virtual void ReplaceNodeResults(SDNode * /*N*/,
2777 SmallVectorImpl<SDValue> &/*Results*/,
2778 SelectionDAG &/*DAG*/) const {
2779 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2782 /// This method returns the name of a target specific DAG node.
2783 virtual const char *getTargetNodeName(unsigned Opcode) const;
2785 /// This method returns a target specific FastISel object, or null if the
2786 /// target does not support "fast" ISel.
2787 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2788 const TargetLibraryInfo *) const {
2793 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2794 SelectionDAG &DAG) const;
2796 //===--------------------------------------------------------------------===//
2797 // Inline Asm Support hooks
2800 /// This hook allows the target to expand an inline asm call to be explicit
2801 /// llvm code if it wants to. This is useful for turning simple inline asms
2802 /// into LLVM intrinsics, which gives the compiler more information about the
2803 /// behavior of the code.
2804 virtual bool ExpandInlineAsm(CallInst *) const {
2808 enum ConstraintType {
2809 C_Register, // Constraint represents specific register(s).
2810 C_RegisterClass, // Constraint represents any of register(s) in class.
2811 C_Memory, // Memory constraint.
2812 C_Other, // Something else.
2813 C_Unknown // Unsupported constraint.
2816 enum ConstraintWeight {
2818 CW_Invalid = -1, // No match.
2819 CW_Okay = 0, // Acceptable.
2820 CW_Good = 1, // Good weight.
2821 CW_Better = 2, // Better weight.
2822 CW_Best = 3, // Best weight.
2824 // Well-known weights.
2825 CW_SpecificReg = CW_Okay, // Specific register operands.
2826 CW_Register = CW_Good, // Register operands.
2827 CW_Memory = CW_Better, // Memory operands.
2828 CW_Constant = CW_Best, // Constant operand.
2829 CW_Default = CW_Okay // Default or don't know type.
2832 /// This contains information for each constraint that we are lowering.
2833 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2834 /// This contains the actual string for the code, like "m". TargetLowering
2835 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2836 /// matches the operand.
2837 std::string ConstraintCode;
2839 /// Information about the constraint code, e.g. Register, RegisterClass,
2840 /// Memory, Other, Unknown.
2841 TargetLowering::ConstraintType ConstraintType;
2843 /// If this is the result output operand or a clobber, this is null,
2844 /// otherwise it is the incoming operand to the CallInst. This gets
2845 /// modified as the asm is processed.
2846 Value *CallOperandVal;
2848 /// The ValueType for the operand value.
2851 /// Return true of this is an input operand that is a matching constraint
2853 bool isMatchingInputConstraint() const;
2855 /// If this is an input matching constraint, this method returns the output
2856 /// operand it matches.
2857 unsigned getMatchedOperand() const;
2859 /// Copy constructor for copying from a ConstraintInfo.
2860 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2861 : InlineAsm::ConstraintInfo(std::move(Info)),
2862 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2863 ConstraintVT(MVT::Other) {}
2866 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2868 /// Split up the constraint string from the inline assembly value into the
2869 /// specific constraints and their prefixes, and also tie in the associated
2870 /// operand values. If this returns an empty vector, and if the constraint
2871 /// string itself isn't empty, there was an error parsing.
2872 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
2873 const TargetRegisterInfo *TRI,
2874 ImmutableCallSite CS) const;
2876 /// Examine constraint type and operand type and determine a weight value.
2877 /// The operand object must already have been set up with the operand type.
2878 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2879 AsmOperandInfo &info, int maIndex) const;
2881 /// Examine constraint string and operand type and determine a weight value.
2882 /// The operand object must already have been set up with the operand type.
2883 virtual ConstraintWeight getSingleConstraintMatchWeight(
2884 AsmOperandInfo &info, const char *constraint) const;
2886 /// Determines the constraint code and constraint type to use for the specific
2887 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2888 /// If the actual operand being passed in is available, it can be passed in as
2889 /// Op, otherwise an empty SDValue can be passed.
2890 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2892 SelectionDAG *DAG = nullptr) const;
2894 /// Given a constraint, return the type of constraint it is for this target.
2895 virtual ConstraintType getConstraintType(StringRef Constraint) const;
2897 /// Given a physical register constraint (e.g. {edx}), return the register
2898 /// number and the register class for the register.
2900 /// Given a register class constraint, like 'r', if this corresponds directly
2901 /// to an LLVM register class, return a register of 0 and the register class
2904 /// This should only be used for C_Register constraints. On error, this
2905 /// returns a register number of 0 and a null register class pointer.
2906 virtual std::pair<unsigned, const TargetRegisterClass *>
2907 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2908 StringRef Constraint, MVT VT) const;
2910 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2911 if (ConstraintCode == "i")
2912 return InlineAsm::Constraint_i;
2913 else if (ConstraintCode == "m")
2914 return InlineAsm::Constraint_m;
2915 return InlineAsm::Constraint_Unknown;
2918 /// Try to replace an X constraint, which matches anything, with another that
2919 /// has more specific requirements based on the type of the corresponding
2920 /// operand. This returns null if there is no replacement to make.
2921 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2923 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2924 /// add anything to Ops.
2925 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2926 std::vector<SDValue> &Ops,
2927 SelectionDAG &DAG) const;
2929 //===--------------------------------------------------------------------===//
2930 // Div utility functions
2932 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2933 bool IsAfterLegalization,
2934 std::vector<SDNode *> *Created) const;
2935 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2936 bool IsAfterLegalization,
2937 std::vector<SDNode *> *Created) const;
2939 /// Targets may override this function to provide custom SDIV lowering for
2940 /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
2941 /// assumes SDIV is expensive and replaces it with a series of other integer
2943 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2945 std::vector<SDNode *> *Created) const;
2947 /// Indicate whether this target prefers to combine FDIVs with the same
2948 /// divisor. If the transform should never be done, return zero. If the
2949 /// transform should be done, return the minimum number of divisor uses
2950 /// that must exist.
2951 virtual unsigned combineRepeatedFPDivisors() const {
2955 /// Hooks for building estimates in place of slower divisions and square
2958 /// Return a reciprocal square root estimate value for the input operand.
2959 /// The RefinementSteps output is the number of Newton-Raphson refinement
2960 /// iterations required to generate a sufficient (though not necessarily
2961 /// IEEE-754 compliant) estimate for the value type.
2962 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2963 /// algorithm implementation that uses one constant or two constants.
2964 /// A target may choose to implement its own refinement within this function.
2965 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2966 /// any further refinement of the estimate.
2967 /// An empty SDValue return means no estimate sequence can be created.
2968 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2969 unsigned &RefinementSteps,
2970 bool &UseOneConstNR) const {
2974 /// Return a reciprocal estimate value for the input operand.
2975 /// The RefinementSteps output is the number of Newton-Raphson refinement
2976 /// iterations required to generate a sufficient (though not necessarily
2977 /// IEEE-754 compliant) estimate for the value type.
2978 /// A target may choose to implement its own refinement within this function.
2979 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2980 /// any further refinement of the estimate.
2981 /// An empty SDValue return means no estimate sequence can be created.
2982 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2983 unsigned &RefinementSteps) const {
2987 //===--------------------------------------------------------------------===//
2988 // Legalization utility functions
2991 /// Expand a MUL into two nodes. One that computes the high bits of
2992 /// the result and one that computes the low bits.
2993 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2994 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2995 /// if you want to control how low bits are extracted from the LHS.
2996 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2997 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2998 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2999 /// \returns true if the node has been expanded. false if it has not
3000 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3001 SelectionDAG &DAG, SDValue LL = SDValue(),
3002 SDValue LH = SDValue(), SDValue RL = SDValue(),
3003 SDValue RH = SDValue()) const;
3005 /// Expand float(f32) to SINT(i64) conversion
3006 /// \param N Node to expand
3007 /// \param Result output after conversion
3008 /// \returns True, if the expansion was successful, false otherwise
3009 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3011 /// Turn load of vector type into a load of the individual elements.
3012 /// \param LD load to expand
3013 /// \returns MERGE_VALUEs of the scalar loads with their chains.
3014 SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3016 // Turn a store of a vector type into stores of the individual elements.
3017 /// \param ST Store with a vector value type
3018 /// \returns MERGE_VALUs of the individual store chains.
3019 SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3021 /// Expands an unaligned load to 2 half-size loads for an integer, and
3022 /// possibly more for vectors.
3023 std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3024 SelectionDAG &DAG) const;
3026 /// Expands an unaligned store to 2 half-size stores for integer values, and
3027 /// possibly more for vectors.
3028 SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3030 //===--------------------------------------------------------------------===//
3031 // Instruction Emitting Hooks
3034 /// This method should be implemented by targets that mark instructions with
3035 /// the 'usesCustomInserter' flag. These instructions are special in various
3036 /// ways, which require special support to insert. The specified MachineInstr
3037 /// is created but not inserted into any basic blocks, and this method is
3038 /// called to expand it into a sequence of instructions, potentially also
3039 /// creating new basic blocks and control flow.
3040 /// As long as the returned basic block is different (i.e., we created a new
3041 /// one), the custom inserter is free to modify the rest of \p MBB.
3042 virtual MachineBasicBlock *
3043 EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3045 /// This method should be implemented by targets that mark instructions with
3046 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3047 /// instruction selection by target hooks. e.g. To fill in optional defs for
3048 /// ARM 's' setting instructions.
3049 virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3050 SDNode *Node) const;
3052 /// If this function returns true, SelectionDAGBuilder emits a
3053 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3054 virtual bool useLoadStackGuardNode() const {
3058 /// Lower TLS global address SDNode for target independent emulated TLS model.
3059 virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3060 SelectionDAG &DAG) const;
3063 SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3064 ISD::CondCode Cond, DAGCombinerInfo &DCI,
3065 const SDLoc &DL) const;
3068 /// Given an LLVM IR type and return type attributes, compute the return value
3069 /// EVTs and flags, and optionally also the offsets, if the return value is
3070 /// being lowered to memory.
3071 void GetReturnInfo(Type *ReturnType, AttributeSet attr,
3072 SmallVectorImpl<ISD::OutputArg> &Outs,
3073 const TargetLowering &TLI, const DataLayout &DL);
3075 } // end llvm namespace