1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Pass.h"
21 #include "llvm/Support/CodeGen.h"
22 #include "llvm/Target/TargetOptions.h"
29 class MachineModuleInfo;
35 class MCSubtargetInfo;
37 class raw_pwrite_stream;
38 class PassManagerBuilder;
40 class TargetIntrinsicInfo;
41 class TargetIRAnalysis;
42 class TargetTransformInfo;
43 class TargetLoweringObjectFile;
44 class TargetPassConfig;
45 class TargetSubtargetInfo;
47 // The old pass manager infrastructure is hidden in a legacy namespace now.
49 class PassManagerBase;
51 using legacy::PassManagerBase;
53 //===----------------------------------------------------------------------===//
55 /// Primary interface to the complete machine description for the target
56 /// machine. All target-specific information should be accessible through this
60 protected: // Can only create subclasses.
61 TargetMachine(const Target &T, StringRef DataLayoutString,
62 const Triple &TargetTriple, StringRef CPU, StringRef FS,
63 const TargetOptions &Options);
65 /// The Target that this machine was created for.
66 const Target &TheTarget;
68 /// DataLayout for the target: keep ABI type size and alignment.
70 /// The DataLayout is created based on the string representation provided
71 /// during construction. It is kept here only to avoid reparsing the string
72 /// but should not really be used during compilation, because it has an
73 /// internal cache that is context specific.
76 /// Triple string, CPU name, and target feature strings the TargetMachine
77 /// instance is created with.
79 std::string TargetCPU;
82 Reloc::Model RM = Reloc::Static;
83 CodeModel::Model CMModel = CodeModel::Small;
84 CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
86 /// Contains target specific asm information.
87 const MCAsmInfo *AsmInfo;
89 const MCRegisterInfo *MRI;
90 const MCInstrInfo *MII;
91 const MCSubtargetInfo *STI;
93 unsigned RequireStructuredCFG : 1;
94 unsigned O0WantsFastISel : 1;
97 const TargetOptions DefaultOptions;
98 mutable TargetOptions Options;
100 TargetMachine(const TargetMachine &) = delete;
101 void operator=(const TargetMachine &) = delete;
102 virtual ~TargetMachine();
104 const Target &getTarget() const { return TheTarget; }
106 const Triple &getTargetTriple() const { return TargetTriple; }
107 StringRef getTargetCPU() const { return TargetCPU; }
108 StringRef getTargetFeatureString() const { return TargetFS; }
110 /// Virtual method implemented by subclasses that returns a reference to that
111 /// target's TargetSubtargetInfo-derived member variable.
112 virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const {
115 virtual TargetLoweringObjectFile *getObjFileLowering() const {
119 /// This method returns a pointer to the specified type of
120 /// TargetSubtargetInfo. In debug builds, it verifies that the object being
121 /// returned is of the correct type.
122 template <typename STC> const STC &getSubtarget(const Function &F) const {
123 return *static_cast<const STC*>(getSubtargetImpl(F));
126 /// Create a DataLayout.
127 const DataLayout createDataLayout() const { return DL; }
129 /// Test if a DataLayout if compatible with the CodeGen for this target.
131 /// The LLVM Module owns a DataLayout that is used for the target independent
132 /// optimizations and code generation. This hook provides a target specific
133 /// check on the validity of this DataLayout.
134 bool isCompatibleDataLayout(const DataLayout &Candidate) const {
135 return DL == Candidate;
138 /// Get the pointer size for this target.
140 /// This is the only time the DataLayout in the TargetMachine is used.
141 unsigned getPointerSize() const { return DL.getPointerSize(); }
143 /// \brief Reset the target options based on the function's attributes.
144 // FIXME: Remove TargetOptions that affect per-function code generation
145 // from TargetMachine.
146 void resetTargetOptions(const Function &F) const;
148 /// Return target specific asm information.
149 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
151 const MCRegisterInfo *getMCRegisterInfo() const { return MRI; }
152 const MCInstrInfo *getMCInstrInfo() const { return MII; }
153 const MCSubtargetInfo *getMCSubtargetInfo() const { return STI; }
155 /// If intrinsic information is available, return it. If not, return null.
156 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const {
160 bool requiresStructuredCFG() const { return RequireStructuredCFG; }
161 void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
163 /// Returns the code generation relocation model. The choices are static, PIC,
164 /// and dynamic-no-pic, and target default.
165 Reloc::Model getRelocationModel() const;
167 /// Returns the code model. The choices are small, kernel, medium, large, and
169 CodeModel::Model getCodeModel() const;
171 bool isPositionIndependent() const;
173 bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const;
175 /// Returns the TLS model which should be used for the given global variable.
176 TLSModel::Model getTLSModel(const GlobalValue *GV) const;
178 /// Returns the optimization level: None, Less, Default, or Aggressive.
179 CodeGenOpt::Level getOptLevel() const;
181 /// \brief Overrides the optimization level.
182 void setOptLevel(CodeGenOpt::Level Level);
184 void setFastISel(bool Enable) { Options.EnableFastISel = Enable; }
185 bool getO0WantsFastISel() { return O0WantsFastISel; }
186 void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; }
188 bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
190 bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
192 /// Return true if data objects should be emitted into their own section,
193 /// corresponds to -fdata-sections.
194 bool getDataSections() const {
195 return Options.DataSections;
198 /// Return true if functions should be emitted into their own section,
199 /// corresponding to -ffunction-sections.
200 bool getFunctionSections() const {
201 return Options.FunctionSections;
204 /// \brief Get a \c TargetIRAnalysis appropriate for the target.
206 /// This is used to construct the new pass manager's target IR analysis pass,
207 /// set up appropriately for this target machine. Even the old pass manager
208 /// uses this to answer queries about the IR.
209 TargetIRAnalysis getTargetIRAnalysis();
211 /// \brief Return a TargetTransformInfo for a given function.
213 /// The returned TargetTransformInfo is specialized to the subtarget
214 /// corresponding to \p F.
215 virtual TargetTransformInfo getTargetTransformInfo(const Function &F);
217 /// Allow the target to modify the pass manager, e.g. by calling
218 /// PassManagerBuilder::addExtension.
219 virtual void adjustPassManager(PassManagerBuilder &) {}
221 /// These enums are meant to be passed into addPassesToEmitFile to indicate
222 /// what type of file to emit, and returned by it to indicate what type of
223 /// file could actually be made.
224 enum CodeGenFileType {
227 CGFT_Null // Do not emit any output.
230 /// Add passes to the specified pass manager to get the specified file
231 /// emitted. Typically this will involve several steps of code generation.
232 /// This method should return true if emission of this file type is not
233 /// supported, or false on success.
234 /// \p MMI is an optional parameter that, if set to non-nullptr,
235 /// will be used to set the MachineModuloInfo for this PM.
236 virtual bool addPassesToEmitFile(PassManagerBase &, raw_pwrite_stream &,
238 bool /*DisableVerify*/ = true,
239 MachineModuleInfo *MMI = nullptr) {
243 /// Add passes to the specified pass manager to get machine code emitted with
244 /// the MCJIT. This method returns true if machine code is not supported. It
245 /// fills the MCContext Ctx pointer which can be used to build custom
248 virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&,
250 bool /*DisableVerify*/ = true) {
254 /// True if subtarget inserts the final scheduling pass on its own.
256 /// Branch relaxation, which must happen after block placement, can
257 /// on some targets (e.g. SystemZ) expose additional post-RA
258 /// scheduling opportunities.
259 virtual bool targetSchedulesPostRAScheduling() const { return false; };
261 void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
262 Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
263 MCSymbol *getSymbol(const GlobalValue *GV) const;
265 /// True if the target uses physical regs at Prolog/Epilog insertion
266 /// time. If true (most machines), all vregs must be allocated before
267 /// PEI. If false (virtual-register machines), then callee-save register
268 /// spilling and scavenging are not needed or used.
269 virtual bool usesPhysRegsForPEI() const { return true; }
271 /// True if the target wants to use interprocedural register allocation by
272 /// default. The -enable-ipra flag can be used to override this.
273 virtual bool useIPRA() const {
278 /// This class describes a target machine that is implemented with the LLVM
279 /// target-independent code generator.
281 class LLVMTargetMachine : public TargetMachine {
282 protected: // Can only create subclasses.
283 LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
284 const Triple &TargetTriple, StringRef CPU, StringRef FS,
285 const TargetOptions &Options, Reloc::Model RM,
286 CodeModel::Model CM, CodeGenOpt::Level OL);
291 /// \brief Get a TargetTransformInfo implementation for the target.
293 /// The TTI returned uses the common code generator to answer queries about
295 TargetTransformInfo getTargetTransformInfo(const Function &F) override;
297 /// Create a pass configuration object to be used by addPassToEmitX methods
298 /// for generating a pipeline of CodeGen passes.
299 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
301 /// Add passes to the specified pass manager to get the specified file
302 /// emitted. Typically this will involve several steps of code generation.
303 /// \p MMI is an optional parameter that, if set to non-nullptr,
304 /// will be used to set the MachineModuloInfofor this PM.
305 bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
306 CodeGenFileType FileType, bool DisableVerify = true,
307 MachineModuleInfo *MMI = nullptr) override;
309 /// Add passes to the specified pass manager to get machine code emitted with
310 /// the MCJIT. This method returns true if machine code is not supported. It
311 /// fills the MCContext Ctx pointer which can be used to build custom
313 bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
314 raw_pwrite_stream &OS,
315 bool DisableVerify = true) override;
317 /// Returns true if the target is expected to pass all machine verifier
318 /// checks. This is a stopgap measure to fix targets one by one. We will
319 /// remove this at some point and always enable the verifier when
320 /// EXPENSIVE_CHECKS is enabled.
321 virtual bool isMachineVerifierClean() const { return true; }
323 /// \brief Adds an AsmPrinter pass to the pipeline that prints assembly or
324 /// machine code from the MI representation.
325 bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
326 CodeGenFileType FileTYpe, MCContext &Context);
329 } // end namespace llvm
331 #endif // LLVM_TARGET_TARGETMACHINE_H