1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineValueType.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Printable.h"
31 class MachineFunction;
33 template<class T> class SmallVectorImpl;
38 /// A bitmask representing the covering of a register with sub-registers.
40 /// This is typically used to track liveness at sub-register granularity.
41 /// Lane masks for sub-register indices are similar to register units for
42 /// physical registers. The individual bits in a lane mask can't be assigned
43 /// any specific meaning. They can be used to check if two sub-register
46 /// Iff the target has a register such that:
48 /// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
52 /// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0
53 typedef unsigned LaneBitmask;
55 class TargetRegisterClass {
57 typedef const MCPhysReg* iterator;
58 typedef const MCPhysReg* const_iterator;
59 typedef const MVT::SimpleValueType* vt_iterator;
60 typedef const TargetRegisterClass* const * sc_iterator;
62 // Instance variables filled by tablegen, do not use!
63 const MCRegisterClass *MC;
64 const vt_iterator VTs;
65 const uint32_t *SubClassMask;
66 const uint16_t *SuperRegIndices;
67 const LaneBitmask LaneMask;
68 /// Classes with a higher priority value are assigned first by register
69 /// allocators using a greedy heuristic. The value is in the range [0,63].
70 const uint8_t AllocationPriority;
71 /// Whether the class supports two (or more) disjunct subregister indices.
72 const bool HasDisjunctSubRegs;
73 /// Whether a combination of subregisters can cover every register in the
74 /// class. See also the CoveredBySubRegs description in Target.td.
75 const bool CoveredBySubRegs;
76 const sc_iterator SuperClasses;
77 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
79 /// Return the register class ID number.
80 unsigned getID() const { return MC->getID(); }
82 /// begin/end - Return all of the registers in this class.
84 iterator begin() const { return MC->begin(); }
85 iterator end() const { return MC->end(); }
87 /// Return the number of registers in this class.
88 unsigned getNumRegs() const { return MC->getNumRegs(); }
90 /// Return the specified register in the class.
91 unsigned getRegister(unsigned i) const {
92 return MC->getRegister(i);
95 /// Return true if the specified register is included in this register class.
96 /// This does not include virtual registers.
97 bool contains(unsigned Reg) const {
98 return MC->contains(Reg);
101 /// Return true if both registers are in this class.
102 bool contains(unsigned Reg1, unsigned Reg2) const {
103 return MC->contains(Reg1, Reg2);
106 /// Return the size of the register in bytes, which is also the size
107 /// of a stack slot allocated to hold a spilled copy of this register.
108 unsigned getSize() const { return MC->getSize(); }
110 /// Return the minimum required alignment for a register of this class.
111 unsigned getAlignment() const { return MC->getAlignment(); }
113 /// Return the cost of copying a value between two registers in this class.
114 /// A negative number means the register class is very expensive
115 /// to copy e.g. status flag register classes.
116 int getCopyCost() const { return MC->getCopyCost(); }
118 /// Return true if this register class may be used to create virtual
120 bool isAllocatable() const { return MC->isAllocatable(); }
122 /// Return true if this TargetRegisterClass has the ValueType vt.
123 bool hasType(MVT vt) const {
124 for(int i = 0; VTs[i] != MVT::Other; ++i)
125 if (MVT(VTs[i]) == vt)
130 /// vt_begin / vt_end - Loop over all of the value types that can be
131 /// represented by values in this register class.
132 vt_iterator vt_begin() const {
136 vt_iterator vt_end() const {
138 while (*I != MVT::Other) ++I;
142 /// Return true if the specified TargetRegisterClass
143 /// is a proper sub-class of this TargetRegisterClass.
144 bool hasSubClass(const TargetRegisterClass *RC) const {
145 return RC != this && hasSubClassEq(RC);
148 /// Returns true if RC is a sub-class of or equal to this class.
149 bool hasSubClassEq(const TargetRegisterClass *RC) const {
150 unsigned ID = RC->getID();
151 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
154 /// Return true if the specified TargetRegisterClass is a
155 /// proper super-class of this TargetRegisterClass.
156 bool hasSuperClass(const TargetRegisterClass *RC) const {
157 return RC->hasSubClass(this);
160 /// Returns true if RC is a super-class of or equal to this class.
161 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
162 return RC->hasSubClassEq(this);
165 /// Returns a bit vector of subclasses, including this one.
166 /// The vector is indexed by class IDs.
168 /// To use it, consider the returned array as a chunk of memory that
169 /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
170 /// contains a bitset of the ID of the subclasses in big-endian style.
172 /// I.e., the representation of the memory from left to right at the
173 /// bit level looks like:
174 /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
175 /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
176 /// Where the number represents the class ID and XXX bits that
177 /// should be ignored.
179 /// See the implementation of hasSubClassEq for an example of how it
181 const uint32_t *getSubClassMask() const {
185 /// Returns a 0-terminated list of sub-register indices that project some
186 /// super-register class into this register class. The list has an entry for
187 /// each Idx such that:
189 /// There exists SuperRC where:
190 /// For all Reg in SuperRC:
191 /// this->contains(Reg:Idx)
193 const uint16_t *getSuperRegIndices() const {
194 return SuperRegIndices;
197 /// Returns a NULL-terminated list of super-classes. The
198 /// classes are ordered by ID which is also a topological ordering from large
199 /// to small classes. The list does NOT include the current class.
200 sc_iterator getSuperClasses() const {
204 /// Return true if this TargetRegisterClass is a subset
205 /// class of at least one other TargetRegisterClass.
206 bool isASubClass() const {
207 return SuperClasses[0] != nullptr;
210 /// Returns the preferred order for allocating registers from this register
211 /// class in MF. The raw order comes directly from the .td file and may
212 /// include reserved registers that are not allocatable.
213 /// Register allocators should also make sure to allocate
214 /// callee-saved registers only after all the volatiles are used. The
215 /// RegisterClassInfo class provides filtered allocation orders with
216 /// callee-saved registers moved to the end.
218 /// The MachineFunction argument can be used to tune the allocatable
219 /// registers based on the characteristics of the function, subtarget, or
222 /// By default, this method returns all registers in the class.
224 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
225 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
228 /// Returns the combination of all lane masks of register in this class.
229 /// The lane masks of the registers are the combination of all lane masks
230 /// of their subregisters. Returns 1 if there are no subregisters.
231 LaneBitmask getLaneMask() const {
236 /// Extra information, not in MCRegisterDesc, about registers.
237 /// These are used by codegen, not by MC.
238 struct TargetRegisterInfoDesc {
239 unsigned CostPerUse; // Extra cost of instructions using register.
240 bool inAllocatableClass; // Register belongs to an allocatable regclass.
243 /// Each TargetRegisterClass has a per register weight, and weight
244 /// limit which must be less than the limits of its pressure sets.
245 struct RegClassWeight {
247 unsigned WeightLimit;
250 /// TargetRegisterInfo base class - We assume that the target defines a static
251 /// array of TargetRegisterDesc objects that represent all of the machine
252 /// registers that the target has. As such, we simply have to track a pointer
253 /// to this array so that we can turn register number into a register
256 class TargetRegisterInfo : public MCRegisterInfo {
258 typedef const TargetRegisterClass * const * regclass_iterator;
260 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
261 const char *const *SubRegIndexNames; // Names of subreg indexes.
262 // Pointer to array of lane masks, one per sub-reg index.
263 const LaneBitmask *SubRegIndexLaneMasks;
265 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
266 unsigned CoveringLanes;
269 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
270 regclass_iterator RegClassBegin,
271 regclass_iterator RegClassEnd,
272 const char *const *SRINames,
273 const LaneBitmask *SRILaneMasks,
274 unsigned CoveringLanes);
275 virtual ~TargetRegisterInfo();
278 // Register numbers can represent physical registers, virtual registers, and
279 // sometimes stack slots. The unsigned values are divided into these ranges:
281 // 0 Not a register, can be used as a sentinel.
282 // [1;2^30) Physical registers assigned by TableGen.
283 // [2^30;2^31) Stack slots. (Rarely used.)
284 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
286 // Further sentinels can be allocated from the small negative integers.
287 // DenseMapInfo<unsigned> uses -1u and -2u.
289 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
290 /// frame index in a variable that normally holds a register. isStackSlot()
291 /// returns true if Reg is in the range used for stack slots.
293 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
294 /// slots, so if a variable may contains a stack slot, always check
295 /// isStackSlot() first.
297 static bool isStackSlot(unsigned Reg) {
298 return int(Reg) >= (1 << 30);
301 /// Compute the frame index from a register value representing a stack slot.
302 static int stackSlot2Index(unsigned Reg) {
303 assert(isStackSlot(Reg) && "Not a stack slot");
304 return int(Reg - (1u << 30));
307 /// Convert a non-negative frame index to a stack slot register value.
308 static unsigned index2StackSlot(int FI) {
309 assert(FI >= 0 && "Cannot hold a negative frame index.");
310 return FI + (1u << 30);
313 /// Return true if the specified register number is in
314 /// the physical register namespace.
315 static bool isPhysicalRegister(unsigned Reg) {
316 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
320 /// Return true if the specified register number is in
321 /// the virtual register namespace.
322 static bool isVirtualRegister(unsigned Reg) {
323 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
327 /// Convert a virtual register number to a 0-based index.
328 /// The first virtual register in a function will get the index 0.
329 static unsigned virtReg2Index(unsigned Reg) {
330 assert(isVirtualRegister(Reg) && "Not a virtual register");
331 return Reg & ~(1u << 31);
334 /// Convert a 0-based index to a virtual register number.
335 /// This is the inverse operation of VirtReg2IndexFunctor below.
336 static unsigned index2VirtReg(unsigned Index) {
337 return Index | (1u << 31);
340 /// Returns the Register Class of a physical register of the given type,
341 /// picking the most sub register class of the right type that contains this
343 const TargetRegisterClass *
344 getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
346 /// Return the maximal subclass of the given register class that is
347 /// allocatable or NULL.
348 const TargetRegisterClass *
349 getAllocatableClass(const TargetRegisterClass *RC) const;
351 /// Returns a bitset indexed by register number indicating if a register is
352 /// allocatable or not. If a register class is specified, returns the subset
354 BitVector getAllocatableSet(const MachineFunction &MF,
355 const TargetRegisterClass *RC = nullptr) const;
357 /// Return the additional cost of using this register instead
358 /// of other registers in its class.
359 unsigned getCostPerUse(unsigned RegNo) const {
360 return InfoDesc[RegNo].CostPerUse;
363 /// Return true if the register is in the allocation of any register class.
364 bool isInAllocatableClass(unsigned RegNo) const {
365 return InfoDesc[RegNo].inAllocatableClass;
368 /// Return the human-readable symbolic target-specific
369 /// name for the specified SubRegIndex.
370 const char *getSubRegIndexName(unsigned SubIdx) const {
371 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
372 "This is not a subregister index");
373 return SubRegIndexNames[SubIdx-1];
376 /// Return a bitmask representing the parts of a register that are covered by
377 /// SubIdx \see LaneBitmask.
379 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
381 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
382 return SubRegIndexLaneMasks[SubIdx];
385 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
386 /// used to determine if sub-registers overlap - they can't be used to
387 /// determine if a set of sub-registers completely cover another
390 /// The X86 general purpose registers have two lanes corresponding to the
391 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
392 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
393 /// sub_32bit sub-register.
395 /// On the other hand, the ARM NEON lanes fully cover their registers: The
396 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
397 /// This is related to the CoveredBySubRegs property on register definitions.
399 /// This function returns a bit mask of lanes that completely cover their
400 /// sub-registers. More precisely, given:
402 /// Covering = getCoveringLanes();
403 /// MaskA = getSubRegIndexLaneMask(SubA);
404 /// MaskB = getSubRegIndexLaneMask(SubB);
406 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
408 LaneBitmask getCoveringLanes() const { return CoveringLanes; }
410 /// Returns true if the two registers are equal or alias each other.
411 /// The registers may be virtual registers.
412 bool regsOverlap(unsigned regA, unsigned regB) const {
413 if (regA == regB) return true;
414 if (isVirtualRegister(regA) || isVirtualRegister(regB))
417 // Regunits are numerically ordered. Find a common unit.
418 MCRegUnitIterator RUA(regA, this);
419 MCRegUnitIterator RUB(regB, this);
421 if (*RUA == *RUB) return true;
422 if (*RUA < *RUB) ++RUA;
424 } while (RUA.isValid() && RUB.isValid());
428 /// Returns true if Reg contains RegUnit.
429 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
430 for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
431 if (*Units == RegUnit)
436 /// Return a null-terminated list of all of the callee-saved registers on
437 /// this target. The register should be in the order of desired callee-save
438 /// stack frame offset. The first register is closest to the incoming stack
439 /// pointer if stack grows down, and vice versa.
441 virtual const MCPhysReg*
442 getCalleeSavedRegs(const MachineFunction *MF) const = 0;
444 virtual const MCPhysReg*
445 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
449 /// Return a mask of call-preserved registers for the given calling convention
450 /// on the current function. The mask should include all call-preserved
451 /// aliases. This is used by the register allocator to determine which
452 /// registers can be live across a call.
454 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
455 /// A set bit indicates that all bits of the corresponding register are
456 /// preserved across the function call. The bit mask is expected to be
457 /// sub-register complete, i.e. if A is preserved, so are all its
460 /// Bits are numbered from the LSB, so the bit for physical register Reg can
461 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
463 /// A NULL pointer means that no register mask will be used, and call
464 /// instructions should use implicit-def operands to indicate call clobbered
467 virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
468 CallingConv::ID) const {
469 // The default mask clobbers everything. All targets should override.
473 /// Return a register mask that clobbers everything.
474 virtual const uint32_t *getNoPreservedMask() const {
475 llvm_unreachable("target does not provide no preserved mask");
478 /// Return true if all bits that are set in mask \p mask0 are also set in
480 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
482 /// Return all the call-preserved register masks defined for this target.
483 virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
484 virtual ArrayRef<const char *> getRegMaskNames() const = 0;
486 /// Returns a bitset indexed by physical register number indicating if a
487 /// register is a special register that has particular uses and should be
488 /// considered unavailable at all times, e.g. SP, RA. This is
489 /// used by register scavenger to determine what registers are free.
490 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
492 /// Prior to adding the live-out mask to a stackmap or patchpoint
493 /// instruction, provide the target the opportunity to adjust it (mainly to
494 /// remove pseudo-registers that should be ignored).
495 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const { }
497 /// Return a super-register of the specified register
498 /// Reg so its sub-register of index SubIdx is Reg.
499 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
500 const TargetRegisterClass *RC) const {
501 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
504 /// Return a subclass of the specified register
505 /// class A so that each register in it has a sub-register of the
506 /// specified sub-register index which is in the specified register class B.
508 /// TableGen will synthesize missing A sub-classes.
509 virtual const TargetRegisterClass *
510 getMatchingSuperRegClass(const TargetRegisterClass *A,
511 const TargetRegisterClass *B, unsigned Idx) const;
513 // For a copy-like instruction that defines a register of class DefRC with
514 // subreg index DefSubReg, reading from another source with class SrcRC and
515 // subregister SrcSubReg return true if this is a preferrable copy
516 // instruction or an earlier use should be used.
517 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
519 const TargetRegisterClass *SrcRC,
520 unsigned SrcSubReg) const;
522 /// Returns the largest legal sub-class of RC that
523 /// supports the sub-register index Idx.
524 /// If no such sub-class exists, return NULL.
525 /// If all registers in RC already have an Idx sub-register, return RC.
527 /// TableGen generates a version of this function that is good enough in most
528 /// cases. Targets can override if they have constraints that TableGen
529 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
530 /// supported by the full GR32 register class in 64-bit mode, but only by the
531 /// GR32_ABCD regiister class in 32-bit mode.
533 /// TableGen will synthesize missing RC sub-classes.
534 virtual const TargetRegisterClass *
535 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
536 assert(Idx == 0 && "Target has no sub-registers");
540 /// Return the subregister index you get from composing
541 /// two subregister indices.
543 /// The special null sub-register index composes as the identity.
545 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
546 /// returns c. Note that composeSubRegIndices does not tell you about illegal
547 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
548 /// b, composeSubRegIndices doesn't tell you.
550 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
551 /// ssub_0:S0 - ssub_3:S3 subregs.
552 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
554 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
557 return composeSubRegIndicesImpl(a, b);
560 /// Transforms a LaneMask computed for one subregister to the lanemask that
561 /// would have been computed when composing the subsubregisters with IdxA
562 /// first. @sa composeSubRegIndices()
563 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
564 LaneBitmask Mask) const {
567 return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
570 /// Transform a lanemask given for a virtual register to the corresponding
571 /// lanemask before using subregister with index \p IdxA.
572 /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
573 /// valie lane mask (no invalid bits set) the following holds:
574 /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
575 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
577 LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
578 LaneBitmask LaneMask) const {
581 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
584 /// Debugging helper: dump register in human readable form to dbgs() stream.
585 static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
586 const TargetRegisterInfo* TRI = nullptr);
589 /// Overridden by TableGen in targets that have sub-registers.
590 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
591 llvm_unreachable("Target has no sub-registers");
594 /// Overridden by TableGen in targets that have sub-registers.
596 composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
597 llvm_unreachable("Target has no sub-registers");
600 virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
602 llvm_unreachable("Target has no sub-registers");
606 /// Find a common super-register class if it exists.
608 /// Find a register class, SuperRC and two sub-register indices, PreA and
611 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
613 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
615 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
617 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
618 /// requirements, and there is no register class with a smaller spill size
619 /// that satisfies the requirements.
621 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
623 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
624 /// that case, the returned register class will be a sub-class of the
625 /// corresponding argument register class.
627 /// The function returns NULL if no register class can be found.
629 const TargetRegisterClass*
630 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
631 const TargetRegisterClass *RCB, unsigned SubB,
632 unsigned &PreA, unsigned &PreB) const;
634 //===--------------------------------------------------------------------===//
635 // Register Class Information
638 /// Register class iterators
640 regclass_iterator regclass_begin() const { return RegClassBegin; }
641 regclass_iterator regclass_end() const { return RegClassEnd; }
643 unsigned getNumRegClasses() const {
644 return (unsigned)(regclass_end()-regclass_begin());
647 /// Returns the register class associated with the enumeration value.
648 /// See class MCOperandInfo.
649 const TargetRegisterClass *getRegClass(unsigned i) const {
650 assert(i < getNumRegClasses() && "Register Class ID out of range");
651 return RegClassBegin[i];
654 /// Returns the name of the register class.
655 const char *getRegClassName(const TargetRegisterClass *Class) const {
656 return MCRegisterInfo::getRegClassName(Class->MC);
659 /// Find the largest common subclass of A and B.
660 /// Return NULL if there is no common subclass.
661 /// The common subclass should contain
662 /// simple value type SVT if it is not the Any type.
663 const TargetRegisterClass *
664 getCommonSubClass(const TargetRegisterClass *A,
665 const TargetRegisterClass *B,
666 const MVT::SimpleValueType SVT =
667 MVT::SimpleValueType::Any) const;
669 /// Returns a TargetRegisterClass used for pointer values.
670 /// If a target supports multiple different pointer register classes,
671 /// kind specifies which one is indicated.
672 virtual const TargetRegisterClass *
673 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
674 llvm_unreachable("Target didn't implement getPointerRegClass!");
677 /// Returns a legal register class to copy a register in the specified class
678 /// to or from. If it is possible to copy the register directly without using
679 /// a cross register class copy, return the specified RC. Returns NULL if it
680 /// is not possible to copy between two registers of the specified class.
681 virtual const TargetRegisterClass *
682 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
686 /// Returns the largest super class of RC that is legal to use in the current
687 /// sub-target and has the same spill size.
688 /// The returned register class can be used to create virtual registers which
689 /// means that all its registers can be copied and spilled.
690 virtual const TargetRegisterClass *
691 getLargestLegalSuperClass(const TargetRegisterClass *RC,
692 const MachineFunction &) const {
693 /// The default implementation is very conservative and doesn't allow the
694 /// register allocator to inflate register classes.
698 /// Return the register pressure "high water mark" for the specific register
699 /// class. The scheduler is in high register pressure mode (for the specific
700 /// register class) if it goes over the limit.
702 /// Note: this is the old register pressure model that relies on a manually
703 /// specified representative register class per value type.
704 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
705 MachineFunction &MF) const {
709 /// Return a heuristic for the machine scheduler to compare the profitability
710 /// of increasing one register pressure set versus another. The scheduler
711 /// will prefer increasing the register pressure of the set which returns
712 /// the largest value for this function.
713 virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
714 unsigned PSetID) const {
718 /// Get the weight in units of pressure for this register class.
719 virtual const RegClassWeight &getRegClassWeight(
720 const TargetRegisterClass *RC) const = 0;
722 /// Get the weight in units of pressure for this register unit.
723 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
725 /// Get the number of dimensions of register pressure.
726 virtual unsigned getNumRegPressureSets() const = 0;
728 /// Get the name of this register unit pressure set.
729 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
731 /// Get the register unit pressure limit for this dimension.
732 /// This limit must be adjusted dynamically for reserved registers.
733 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
734 unsigned Idx) const = 0;
736 /// Get the dimensions of register pressure impacted by this register class.
737 /// Returns a -1 terminated array of pressure set IDs.
738 virtual const int *getRegClassPressureSets(
739 const TargetRegisterClass *RC) const = 0;
741 /// Get the dimensions of register pressure impacted by this register unit.
742 /// Returns a -1 terminated array of pressure set IDs.
743 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
745 /// Get a list of 'hint' registers that the register allocator should try
746 /// first when allocating a physical register for the virtual register
747 /// VirtReg. These registers are effectively moved to the front of the
748 /// allocation order.
750 /// The Order argument is the allocation order for VirtReg's register class
751 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
752 /// come from Order, and they must not be reserved.
754 /// The default implementation of this function can resolve
755 /// target-independent hints provided to MRI::setRegAllocationHint with
756 /// HintType == 0. Targets that override this function should defer to the
757 /// default implementation if they have no reason to change the allocation
758 /// order for VirtReg. There may be target-independent hints.
759 virtual void getRegAllocationHints(unsigned VirtReg,
760 ArrayRef<MCPhysReg> Order,
761 SmallVectorImpl<MCPhysReg> &Hints,
762 const MachineFunction &MF,
763 const VirtRegMap *VRM = nullptr,
764 const LiveRegMatrix *Matrix = nullptr)
767 /// A callback to allow target a chance to update register allocation hints
768 /// when a register is "changed" (e.g. coalesced) to another register.
769 /// e.g. On ARM, some virtual registers should target register pairs,
770 /// if one of pair is coalesced to another register, the allocation hint of
771 /// the other half of the pair should be changed to point to the new register.
772 virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
773 MachineFunction &MF) const {
777 /// Allow the target to reverse allocation order of local live ranges. This
778 /// will generally allocate shorter local live ranges first. For targets with
779 /// many registers, this could reduce regalloc compile time by a large
780 /// factor. It is disabled by default for three reasons:
781 /// (1) Top-down allocation is simpler and easier to debug for targets that
782 /// don't benefit from reversing the order.
783 /// (2) Bottom-up allocation could result in poor evicition decisions on some
784 /// targets affecting the performance of compiled code.
785 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
786 virtual bool reverseLocalAssignment() const { return false; }
788 /// Allow the target to override the cost of using a callee-saved register for
789 /// the first time. Default value of 0 means we will use a callee-saved
790 /// register if it is available.
791 virtual unsigned getCSRFirstUseCost() const { return 0; }
793 /// Returns true if the target requires (and can make use of) the register
795 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
799 /// Returns true if the target wants to use frame pointer based accesses to
800 /// spill to the scavenger emergency spill slot.
801 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
805 /// Returns true if the target requires post PEI scavenging of registers for
806 /// materializing frame index constants.
807 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
811 /// Returns true if the target wants the LocalStackAllocation pass to be run
812 /// and virtual base registers used for more efficient stack access.
813 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
817 /// Return true if target has reserved a spill slot in the stack frame of
818 /// the given function for the specified register. e.g. On x86, if the frame
819 /// register is required, the first fixed stack object is reserved as its
820 /// spill slot. This tells PEI not to create a new stack frame
821 /// object for the given register. It should be called only after
822 /// determineCalleeSaves().
823 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
824 int &FrameIdx) const {
828 /// Returns true if the live-ins should be tracked after register allocation.
829 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
833 /// True if the stack can be realigned for the target.
834 virtual bool canRealignStack(const MachineFunction &MF) const;
836 /// True if storage within the function requires the stack pointer to be
837 /// aligned more than the normal calling convention calls for.
838 /// This cannot be overriden by the target, but canRealignStack can be
840 bool needsStackRealignment(const MachineFunction &MF) const;
842 /// Get the offset from the referenced frame index in the instruction,
844 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
849 /// Returns true if the instruction's frame index reference would be better
850 /// served by a base register other than FP or SP.
851 /// Used by LocalStackFrameAllocation to determine which frame index
852 /// references it should create new base registers for.
853 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
857 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
858 /// before insertion point I.
859 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
860 unsigned BaseReg, int FrameIdx,
861 int64_t Offset) const {
862 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
866 /// Resolve a frame index operand of an instruction
867 /// to reference the indicated base register plus offset instead.
868 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
869 int64_t Offset) const {
870 llvm_unreachable("resolveFrameIndex does not exist on this target");
873 /// Determine whether a given base register plus offset immediate is
874 /// encodable to resolve a frame index.
875 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
876 int64_t Offset) const {
877 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
880 /// Spill the register so it can be used by the register scavenger.
881 /// Return true if the register was spilled, false otherwise.
882 /// If this function does not spill the register, the scavenger
883 /// will instead spill it to the emergency spill slot.
885 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
886 MachineBasicBlock::iterator I,
887 MachineBasicBlock::iterator &UseMI,
888 const TargetRegisterClass *RC,
889 unsigned Reg) const {
893 /// This method must be overriden to eliminate abstract frame indices from
894 /// instructions which may use them. The instruction referenced by the
895 /// iterator contains an MO_FrameIndex operand which must be eliminated by
896 /// this method. This method may modify or replace the specified instruction,
897 /// as long as it keeps the iterator pointing at the finished product.
898 /// SPAdj is the SP adjustment due to call frame setup instruction.
899 /// FIOperandNum is the FI operand number.
900 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
901 int SPAdj, unsigned FIOperandNum,
902 RegScavenger *RS = nullptr) const = 0;
904 /// Return the assembly name for \p Reg.
905 virtual StringRef getRegAsmName(unsigned Reg) const {
906 // FIXME: We are assuming that the assembly name is equal to the TableGen
907 // name converted to lower case
909 // The TableGen name is the name of the definition for this register in the
910 // target's tablegen files. For example, the TableGen name of
911 // def EAX : Register <...>; is "EAX"
912 return StringRef(getName(Reg));
915 //===--------------------------------------------------------------------===//
918 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
919 virtual bool shouldCoalesce(MachineInstr *MI,
920 const TargetRegisterClass *SrcRC,
922 const TargetRegisterClass *DstRC,
924 const TargetRegisterClass *NewRC) const
927 //===--------------------------------------------------------------------===//
928 /// Debug information queries.
930 /// getFrameRegister - This method should return the register used as a base
931 /// for values allocated in the current stack frame.
932 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
936 //===----------------------------------------------------------------------===//
937 // SuperRegClassIterator
938 //===----------------------------------------------------------------------===//
940 // Iterate over the possible super-registers for a given register class. The
941 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
942 // possible classes of super-registers.
944 // Each bit mask will have at least one set bit, and each set bit in Mask
945 // corresponds to a SuperRC such that:
947 // For all Reg in SuperRC: Reg:Idx is in RC.
949 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
950 // also satisfies the above requirement, assuming Reg:0 == Reg.
952 class SuperRegClassIterator {
953 const unsigned RCMaskWords;
956 const uint32_t *Mask;
959 /// Create a SuperRegClassIterator that visits all the super-register classes
960 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
961 SuperRegClassIterator(const TargetRegisterClass *RC,
962 const TargetRegisterInfo *TRI,
963 bool IncludeSelf = false)
964 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
966 Idx(RC->getSuperRegIndices()),
967 Mask(RC->getSubClassMask()) {
972 /// Returns true if this iterator is still pointing at a valid entry.
973 bool isValid() const { return Idx; }
975 /// Returns the current sub-register index.
976 unsigned getSubReg() const { return SubReg; }
978 /// Returns the bit mask of register classes that getSubReg() projects into
980 /// See TargetRegisterClass::getSubClassMask() for how to use it.
981 const uint32_t *getMask() const { return Mask; }
983 /// Advance iterator to the next entry.
985 assert(isValid() && "Cannot move iterator past end.");
993 //===----------------------------------------------------------------------===//
994 // BitMaskClassIterator
995 //===----------------------------------------------------------------------===//
996 /// This class encapuslates the logic to iterate over bitmask returned by
997 /// the various RegClass related APIs.
998 /// E.g., this class can be used to iterate over the subclasses provided by
999 /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1000 class BitMaskClassIterator {
1001 /// Total number of register classes.
1002 const unsigned NumRegClasses;
1003 /// Base index of CurrentChunk.
1004 /// In other words, the number of bit we read to get at the
1005 /// beginning of that chunck.
1007 /// Adjust base index of CurrentChunk.
1008 /// Base index + how many bit we read within CurrentChunk.
1010 /// Current register class ID.
1012 /// Mask we are iterating over.
1013 const uint32_t *Mask;
1014 /// Current chunk of the Mask we are traversing.
1015 uint32_t CurrentChunk;
1017 /// Move ID to the next set bit.
1018 void moveToNextID() {
1019 // If the current chunk of memory is empty, move to the next one,
1020 // while making sure we do not go pass the number of register
1022 while (!CurrentChunk) {
1023 // Move to the next chunk.
1025 if (Base >= NumRegClasses) {
1029 CurrentChunk = *++Mask;
1032 // Otherwise look for the first bit set from the right
1033 // (representation of the class ID is big endian).
1034 // See getSubClassMask for more details on the representation.
1035 unsigned Offset = countTrailingZeros(CurrentChunk);
1036 // Add the Offset to the adjusted base number of this chunk: Idx.
1037 // This is the ID of the register class.
1040 // Consume the zeros, if any, and the bit we just read
1041 // so that we are at the right spot for the next call.
1042 // Do not do Offset + 1 because Offset may be 31 and 32
1043 // will be UB for the shift, though in that case we could
1044 // have make the chunk being equal to 0, but that would
1045 // have introduced a if statement.
1050 /// Move \p NumBits Bits forward in CurrentChunk.
1051 void moveNBits(unsigned NumBits) {
1052 assert(NumBits < 32 && "Undefined behavior spotted!");
1053 // Consume the bit we read for the next call.
1054 CurrentChunk >>= NumBits;
1055 // Adjust the base for the chunk.
1060 /// Create a BitMaskClassIterator that visits all the register classes
1061 /// represented by \p Mask.
1063 /// \pre \p Mask != nullptr
1064 BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
1065 : NumRegClasses(TRI.getNumRegClasses()), Base(0), Idx(0), ID(0),
1066 Mask(Mask), CurrentChunk(*Mask) {
1067 // Move to the first ID.
1071 /// Returns true if this iterator is still pointing at a valid entry.
1072 bool isValid() const { return getID() != NumRegClasses; }
1074 /// Returns the current register class ID.
1075 unsigned getID() const { return ID; }
1077 /// Advance iterator to the next entry.
1079 assert(isValid() && "Cannot move iterator past end.");
1084 // This is useful when building IndexedMaps keyed on virtual registers
1085 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
1086 unsigned operator()(unsigned Reg) const {
1087 return TargetRegisterInfo::virtReg2Index(Reg);
1091 /// Prints virtual and physical registers with or without a TRI instance.
1094 /// %noreg - NoRegister
1095 /// %vreg5 - a virtual register.
1096 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
1097 /// %EAX - a physical register
1098 /// %physreg17 - a physical register when no TRI instance given.
1100 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
1101 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
1102 unsigned SubRegIdx = 0);
1104 /// Create Printable object to print register units on a \ref raw_ostream.
1106 /// Register units are named after their root registers:
1108 /// AL - Single root.
1109 /// FP0~ST7 - Dual roots.
1111 /// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
1112 Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1114 /// \brief Create Printable object to print virtual registers and physical
1115 /// registers on a \ref raw_ostream.
1116 Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1118 /// Create Printable object to print LaneBitmasks on a \ref raw_ostream.
1119 Printable PrintLaneMask(LaneBitmask LaneMask);
1121 } // End llvm namespace