1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 //===----------------------------------------------------------------------===//
72 // Selection DAG Type Profile definitions.
74 // These use the constraints defined above to describe the type requirements of
75 // the various nodes. These are not hard coded into tblgen, allowing targets to
76 // add their own if needed.
79 // SDTypeProfile - This profile describes the type requirements of a Selection
81 class SDTypeProfile<int numresults, int numoperands,
82 list<SDTypeConstraint> constraints> {
83 int NumResults = numresults;
84 int NumOperands = numoperands;
85 list<SDTypeConstraint> Constraints = constraints;
89 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
90 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
91 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
92 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
93 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
94 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
96 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
99 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
102 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
109 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
112 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
116 SDTCisSameAs<0, 1>, SDTCisInt<0>
118 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
124 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
125 SDTCisSameAs<0, 1>, SDTCisFP<0>
127 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
130 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
134 SDTCisFP<0>, SDTCisInt<1>
136 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
137 SDTCisInt<0>, SDTCisFP<1>
139 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
141 SDTCisVTSmallerThanOp<2, 1>
144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
148 def SDTSelect : SDTypeProfile<1, 3, [ // select
149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
152 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
153 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
156 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
157 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
161 def SDTBr : SDTypeProfile<0, 1, [ // br
165 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc
166 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
169 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
170 SDTCisInt<0>, SDTCisVT<1, OtherVT>
173 def SDTBrind : SDTypeProfile<0, 1, [ // brind
177 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
179 def SDTLoad : SDTypeProfile<1, 1, [ // load
183 def SDTStore : SDTypeProfile<0, 2, [ // store
187 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
188 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
191 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store
192 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>
195 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load
196 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>
199 def SDTVecShuffle : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
202 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
203 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
205 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
206 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
209 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
210 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
212 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
213 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
216 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
217 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
220 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier
221 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
224 def SDTAtomicFence : SDTypeProfile<0, 2, [
225 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
227 def SDTAtomic3 : SDTypeProfile<1, 3, [
228 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
230 def SDTAtomic2 : SDTypeProfile<1, 2, [
231 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
233 def SDTAtomicStore : SDTypeProfile<0, 2, [
234 SDTCisPtrTy<0>, SDTCisInt<1>
236 def SDTAtomicLoad : SDTypeProfile<1, 1, [
237 SDTCisInt<0>, SDTCisPtrTy<1>
240 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
241 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
244 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
245 SDTypeProfile<0, 1, constraints>;
246 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
247 SDTypeProfile<0, 2, constraints>;
249 //===----------------------------------------------------------------------===//
250 // Selection DAG Node Properties.
252 // Note: These are hard coded into tblgen.
254 class SDNodeProperty;
255 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
256 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
257 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
258 def SDNPOutGlue : SDNodeProperty; // Write a flag result
259 def SDNPInGlue : SDNodeProperty; // Read a flag operand
260 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
261 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
262 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
263 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
264 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
265 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
266 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
267 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
269 //===----------------------------------------------------------------------===//
270 // Selection DAG Pattern Operations
271 class SDPatternOperator;
273 //===----------------------------------------------------------------------===//
274 // Selection DAG Node definitions.
276 class SDNode<string opcode, SDTypeProfile typeprof,
277 list<SDNodeProperty> props = [], string sdclass = "SDNode">
278 : SDPatternOperator {
279 string Opcode = opcode;
280 string SDClass = sdclass;
281 list<SDNodeProperty> Properties = props;
282 SDTypeProfile TypeProfile = typeprof;
285 // Special TableGen-recognized dag nodes
291 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
292 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
293 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
294 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
295 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
296 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
297 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
298 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
299 "GlobalAddressSDNode">;
300 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
301 "GlobalAddressSDNode">;
302 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
303 "GlobalAddressSDNode">;
304 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
305 "GlobalAddressSDNode">;
306 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
307 "ConstantPoolSDNode">;
308 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
309 "ConstantPoolSDNode">;
310 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
312 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
314 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
316 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
318 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
319 "ExternalSymbolSDNode">;
320 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
321 "ExternalSymbolSDNode">;
322 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
323 "BlockAddressSDNode">;
324 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
325 "BlockAddressSDNode">;
327 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
328 [SDNPCommutative, SDNPAssociative]>;
329 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
330 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
331 [SDNPCommutative, SDNPAssociative]>;
332 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
333 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
334 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
335 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
336 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
337 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
338 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
339 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
340 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
341 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
342 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
343 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
344 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
345 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
346 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
347 def and : SDNode<"ISD::AND" , SDTIntBinOp,
348 [SDNPCommutative, SDNPAssociative]>;
349 def or : SDNode<"ISD::OR" , SDTIntBinOp,
350 [SDNPCommutative, SDNPAssociative]>;
351 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
352 [SDNPCommutative, SDNPAssociative]>;
353 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
354 [SDNPCommutative, SDNPOutGlue]>;
355 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
356 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
357 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
359 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
360 [SDNPOutGlue, SDNPInGlue]>;
362 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
363 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
364 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
365 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
366 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
367 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
368 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
369 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
370 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
371 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
372 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
373 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
374 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
375 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
377 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
378 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
379 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
380 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
381 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
382 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
383 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
384 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
385 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp>;
386 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
387 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
388 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
389 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
390 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
391 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
392 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
393 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
394 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
395 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
396 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
397 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
398 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
399 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
401 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
402 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
403 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
405 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
406 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
407 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
408 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
409 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
410 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
412 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
413 def select : SDNode<"ISD::SELECT" , SDTSelect>;
414 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
415 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
417 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
418 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
419 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
420 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
421 def trap : SDNode<"ISD::TRAP" , SDTNone,
422 [SDNPHasChain, SDNPSideEffect]>;
423 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
424 [SDNPHasChain, SDNPSideEffect]>;
426 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
427 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
430 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
431 [SDNPHasChain, SDNPSideEffect]>;
433 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
434 [SDNPHasChain, SDNPSideEffect]>;
436 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
437 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
438 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
439 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
440 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
441 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
442 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
443 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
444 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
445 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
446 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
447 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
448 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
449 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
450 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
451 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
452 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
453 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
454 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
455 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
456 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
457 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
458 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
459 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
460 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
461 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
462 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
463 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
465 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore,
466 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
467 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
468 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
470 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
471 // and truncst (see below).
472 def ld : SDNode<"ISD::LOAD" , SDTLoad,
473 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
474 def st : SDNode<"ISD::STORE" , SDTStore,
475 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
476 def ist : SDNode<"ISD::STORE" , SDTIStore,
477 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
479 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
480 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
481 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
483 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
484 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
485 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
486 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
487 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
488 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
490 // This operator does not do subvector type checking. The ARM
491 // backend, at least, needs it.
492 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
493 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
496 // This operator does subvector type checking.
497 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
498 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
500 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
501 // these internally. Don't reference these directly.
502 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
503 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
505 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
506 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
508 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
509 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
511 // Do not use cvt directly. Use cvt forms below
512 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
514 def SDT_assertext : SDTypeProfile<1, 1,
515 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
516 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
517 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
520 //===----------------------------------------------------------------------===//
521 // Selection DAG Condition Codes
523 class CondCode; // ISD::CondCode enums
524 def SETOEQ : CondCode; def SETOGT : CondCode;
525 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
526 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
527 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
528 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
530 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
531 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
534 //===----------------------------------------------------------------------===//
535 // Selection DAG Node Transformation Functions.
537 // This mechanism allows targets to manipulate nodes in the output DAG once a
538 // match has been formed. This is typically used to manipulate immediate
541 class SDNodeXForm<SDNode opc, code xformFunction> {
543 code XFormFunction = xformFunction;
546 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
548 //===----------------------------------------------------------------------===//
549 // PatPred Subclasses.
551 // These allow specifying different sorts of predicates that control whether a
556 class CodePatPred<code predicate> : PatPred {
557 code PredicateCode = predicate;
561 //===----------------------------------------------------------------------===//
562 // Selection DAG Pattern Fragments.
564 // Pattern fragments are reusable chunks of dags that match specific things.
565 // They can take arguments and have C++ predicates that control whether they
566 // match. They are intended to make the patterns for common instructions more
567 // compact and readable.
570 /// PatFrag - Represents a pattern fragment. This can match something on the
571 /// DAG, from a single node to multiple nested other fragments.
573 class PatFrag<dag ops, dag frag, code pred = [{}],
574 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
577 code PredicateCode = pred;
578 code ImmediateCode = [{}];
579 SDNodeXForm OperandTransform = xform;
582 // OutPatFrag is a pattern fragment that is used as part of an output pattern
583 // (not an input pattern). These do not have predicates or transforms, but are
584 // used to avoid repeated subexpressions in output patterns.
585 class OutPatFrag<dag ops, dag frag>
586 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
588 // PatLeaf's are pattern fragments that have no operands. This is just a helper
589 // to define immediates and other common things concisely.
590 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
591 : PatFrag<(ops), frag, pred, xform>;
594 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
595 // constraint is a function that is run on the immediate (always with the value
596 // sign extended out to an int64_t) as Imm. For example:
598 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
600 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
601 // is preferred over using PatLeaf because it allows the code generator to
602 // reason more about the constraint.
604 // If FastIsel should ignore all instructions that have an operand of this type,
605 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
606 // the code size of the generated fast instruction selector.
607 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
608 : PatFrag<(ops), (vt imm), [{}], xform> {
609 let ImmediateCode = pred;
610 bit FastIselShouldIgnore = 0;
616 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
617 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
619 def immAllOnesV: PatLeaf<(build_vector), [{
620 return ISD::isBuildVectorAllOnes(N);
622 def immAllZerosV: PatLeaf<(build_vector), [{
623 return ISD::isBuildVectorAllZeros(N);
628 // Other helper fragments.
629 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
630 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
631 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
633 // null_frag - The null pattern operator is used in multiclass instantiations
634 // which accept an SDPatternOperator for use in matching patterns for internal
635 // definitions. When expanding a pattern, if the null fragment is referenced
636 // in the expansion, the pattern is discarded and it is as-if '[]' had been
637 // specified. This allows multiclasses to have the isel patterns be optional.
638 def null_frag : SDPatternOperator;
641 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
642 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
644 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
645 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
648 // extending load fragments.
649 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
650 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
652 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
653 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
655 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
656 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
659 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
660 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
662 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
663 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
665 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
666 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
668 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
669 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
671 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
672 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
674 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
675 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
678 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
679 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
681 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
682 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
684 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
685 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
687 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
688 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
691 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
692 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
694 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
695 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
697 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
698 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
700 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
701 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
704 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
705 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
707 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
708 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
710 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
711 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
713 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
714 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
716 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
717 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
719 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
720 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
723 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
724 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
726 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
727 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
729 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
730 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
732 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
733 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
736 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
737 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
739 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
740 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
742 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
743 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
745 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
746 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
750 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
751 (st node:$val, node:$ptr), [{
752 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
754 def store : PatFrag<(ops node:$val, node:$ptr),
755 (unindexedstore node:$val, node:$ptr), [{
756 return !cast<StoreSDNode>(N)->isTruncatingStore();
759 // truncstore fragments.
760 def truncstore : PatFrag<(ops node:$val, node:$ptr),
761 (unindexedstore node:$val, node:$ptr), [{
762 return cast<StoreSDNode>(N)->isTruncatingStore();
764 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
765 (truncstore node:$val, node:$ptr), [{
766 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
768 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
769 (truncstore node:$val, node:$ptr), [{
770 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
772 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
773 (truncstore node:$val, node:$ptr), [{
774 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
776 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
777 (truncstore node:$val, node:$ptr), [{
778 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
780 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
781 (truncstore node:$val, node:$ptr), [{
782 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
785 // indexed store fragments.
786 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
787 (ist node:$val, node:$base, node:$offset), [{
788 return !cast<StoreSDNode>(N)->isTruncatingStore();
791 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
792 (istore node:$val, node:$base, node:$offset), [{
793 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
794 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
797 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
798 (ist node:$val, node:$base, node:$offset), [{
799 return cast<StoreSDNode>(N)->isTruncatingStore();
801 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
802 (itruncstore node:$val, node:$base, node:$offset), [{
803 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
804 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
806 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
807 (pre_truncst node:$val, node:$base, node:$offset), [{
808 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
810 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
811 (pre_truncst node:$val, node:$base, node:$offset), [{
812 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
814 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
815 (pre_truncst node:$val, node:$base, node:$offset), [{
816 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
818 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
819 (pre_truncst node:$val, node:$base, node:$offset), [{
820 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
822 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
823 (pre_truncst node:$val, node:$base, node:$offset), [{
824 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
827 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
828 (istore node:$val, node:$ptr, node:$offset), [{
829 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
830 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
833 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
834 (itruncstore node:$val, node:$base, node:$offset), [{
835 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
836 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
838 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
839 (post_truncst node:$val, node:$base, node:$offset), [{
840 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
842 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
843 (post_truncst node:$val, node:$base, node:$offset), [{
844 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
846 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
847 (post_truncst node:$val, node:$base, node:$offset), [{
848 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
850 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
851 (post_truncst node:$val, node:$base, node:$offset), [{
852 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
854 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
855 (post_truncst node:$val, node:$base, node:$offset), [{
856 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
859 // setcc convenience fragments.
860 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
861 (setcc node:$lhs, node:$rhs, SETOEQ)>;
862 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
863 (setcc node:$lhs, node:$rhs, SETOGT)>;
864 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
865 (setcc node:$lhs, node:$rhs, SETOGE)>;
866 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
867 (setcc node:$lhs, node:$rhs, SETOLT)>;
868 def setole : PatFrag<(ops node:$lhs, node:$rhs),
869 (setcc node:$lhs, node:$rhs, SETOLE)>;
870 def setone : PatFrag<(ops node:$lhs, node:$rhs),
871 (setcc node:$lhs, node:$rhs, SETONE)>;
872 def seto : PatFrag<(ops node:$lhs, node:$rhs),
873 (setcc node:$lhs, node:$rhs, SETO)>;
874 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
875 (setcc node:$lhs, node:$rhs, SETUO)>;
876 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
877 (setcc node:$lhs, node:$rhs, SETUEQ)>;
878 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
879 (setcc node:$lhs, node:$rhs, SETUGT)>;
880 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
881 (setcc node:$lhs, node:$rhs, SETUGE)>;
882 def setult : PatFrag<(ops node:$lhs, node:$rhs),
883 (setcc node:$lhs, node:$rhs, SETULT)>;
884 def setule : PatFrag<(ops node:$lhs, node:$rhs),
885 (setcc node:$lhs, node:$rhs, SETULE)>;
886 def setune : PatFrag<(ops node:$lhs, node:$rhs),
887 (setcc node:$lhs, node:$rhs, SETUNE)>;
888 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
889 (setcc node:$lhs, node:$rhs, SETEQ)>;
890 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
891 (setcc node:$lhs, node:$rhs, SETGT)>;
892 def setge : PatFrag<(ops node:$lhs, node:$rhs),
893 (setcc node:$lhs, node:$rhs, SETGE)>;
894 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
895 (setcc node:$lhs, node:$rhs, SETLT)>;
896 def setle : PatFrag<(ops node:$lhs, node:$rhs),
897 (setcc node:$lhs, node:$rhs, SETLE)>;
898 def setne : PatFrag<(ops node:$lhs, node:$rhs),
899 (setcc node:$lhs, node:$rhs, SETNE)>;
901 def atomic_cmp_swap_8 :
902 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
903 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
904 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
906 def atomic_cmp_swap_16 :
907 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
908 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
909 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
911 def atomic_cmp_swap_32 :
912 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
913 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
914 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
916 def atomic_cmp_swap_64 :
917 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
918 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
919 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
922 multiclass binary_atomic_op<SDNode atomic_op> {
923 def _8 : PatFrag<(ops node:$ptr, node:$val),
924 (atomic_op node:$ptr, node:$val), [{
925 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
927 def _16 : PatFrag<(ops node:$ptr, node:$val),
928 (atomic_op node:$ptr, node:$val), [{
929 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
931 def _32 : PatFrag<(ops node:$ptr, node:$val),
932 (atomic_op node:$ptr, node:$val), [{
933 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
935 def _64 : PatFrag<(ops node:$ptr, node:$val),
936 (atomic_op node:$ptr, node:$val), [{
937 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
941 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
942 defm atomic_swap : binary_atomic_op<atomic_swap>;
943 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
944 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
945 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
946 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
947 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
948 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
949 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
950 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
951 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
952 defm atomic_store : binary_atomic_op<atomic_store>;
955 PatFrag<(ops node:$ptr),
956 (atomic_load node:$ptr), [{
957 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
960 PatFrag<(ops node:$ptr),
961 (atomic_load node:$ptr), [{
962 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
965 PatFrag<(ops node:$ptr),
966 (atomic_load node:$ptr), [{
967 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
970 PatFrag<(ops node:$ptr),
971 (atomic_load node:$ptr), [{
972 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
975 //===----------------------------------------------------------------------===//
976 // Selection DAG CONVERT_RNDSAT patterns
978 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
979 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
980 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
983 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
984 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
985 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
988 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
989 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
990 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
993 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
994 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
995 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
998 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
999 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1000 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
1003 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1004 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1005 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
1008 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1009 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1010 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
1013 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1014 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1015 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
1018 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1019 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1020 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
1023 //===----------------------------------------------------------------------===//
1024 // Selection DAG Pattern Support.
1026 // Patterns are what are actually matched against by the target-flavored
1027 // instruction selection DAG. Instructions defined by the target implicitly
1028 // define patterns in most cases, but patterns can also be explicitly added when
1029 // an operation is defined by a sequence of instructions (e.g. loading a large
1030 // immediate value on RISC targets that do not support immediates as large as
1034 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1035 dag PatternToMatch = patternToMatch;
1036 list<dag> ResultInstrs = resultInstrs;
1037 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1038 int AddedComplexity = 0; // See class Instruction in Target.td.
1041 // Pat - A simple (but common) form of a pattern, which produces a simple result
1042 // not needing a full list.
1043 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1045 //===----------------------------------------------------------------------===//
1046 // Complex pattern definitions.
1049 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1050 // in C++. NumOperands is the number of operands returned by the select function;
1051 // SelectFunc is the name of the function used to pattern match the max. pattern;
1052 // RootNodes are the list of possible root nodes of the sub-dags to match.
1053 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1055 class ComplexPattern<ValueType ty, int numops, string fn,
1056 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
1058 int NumOperands = numops;
1059 string SelectFunc = fn;
1060 list<SDNode> RootNodes = roots;
1061 list<SDNodeProperty> Properties = props;