1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 // SDTCVecEltisVT - The specified operand is vector type with element type
73 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
77 // SDTCisSameNumEltsAs - The two specified operands have identical number
79 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
80 int OtherOperandNum = OtherOp;
83 // SDTCisSameSizeAs - The two specified operands have identical size.
84 class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
85 int OtherOperandNum = OtherOp;
88 //===----------------------------------------------------------------------===//
89 // Selection DAG Type Profile definitions.
91 // These use the constraints defined above to describe the type requirements of
92 // the various nodes. These are not hard coded into tblgen, allowing targets to
93 // add their own if needed.
96 // SDTypeProfile - This profile describes the type requirements of a Selection
98 class SDTypeProfile<int numresults, int numoperands,
99 list<SDTypeConstraint> constraints> {
100 int NumResults = numresults;
101 int NumOperands = numoperands;
102 list<SDTypeConstraint> Constraints = constraints;
106 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
107 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
108 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
109 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
110 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
111 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
113 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
114 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
116 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
117 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
119 def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift
120 SDTCisSameAs<0, 1>, SDTCisInt<2>
122 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
123 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
126 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
127 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
129 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
130 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
132 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
133 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
135 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz, cttz
136 SDTCisSameAs<0, 1>, SDTCisInt<0>
138 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
139 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>
141 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
142 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>
144 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
145 SDTCisSameAs<0, 1>, SDTCisFP<0>
147 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
148 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>
150 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
151 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>
153 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
154 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>
156 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
157 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>
159 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
160 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
161 SDTCisVTSmallerThanOp<2, 1>
163 def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec
164 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>,
165 SDTCisOpSmallerThanOp<1, 0>, SDTCisSameSizeAs<0,1>
168 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
169 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
172 def SDTSelect : SDTypeProfile<1, 3, [ // select
173 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
176 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
177 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1>
180 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
181 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
185 def SDTBr : SDTypeProfile<0, 1, [ // br
189 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc
190 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
193 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
194 SDTCisInt<0>, SDTCisVT<1, OtherVT>
197 def SDTBrind : SDTypeProfile<0, 1, [ // brind
201 def SDTCatchret : SDTypeProfile<0, 2, [ // catchret
202 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>
205 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
207 def SDTLoad : SDTypeProfile<1, 1, [ // load
211 def SDTStore : SDTypeProfile<0, 2, [ // store
215 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
216 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
219 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store
220 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2>
223 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load
224 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>,
225 SDTCisSameNumEltsAs<0, 2>
228 def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather
229 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
230 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1>
233 def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter
234 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>,
235 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3>
238 def SDTVecShuffle : SDTypeProfile<1, 2, [
239 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
241 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
242 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
244 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
245 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
248 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
249 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
251 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
252 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
255 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
256 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
259 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier
260 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
263 def SDTAtomicFence : SDTypeProfile<0, 2, [
264 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
266 def SDTAtomic3 : SDTypeProfile<1, 3, [
267 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
269 def SDTAtomic2 : SDTypeProfile<1, 2, [
270 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
272 def SDTAtomicStore : SDTypeProfile<0, 2, [
273 SDTCisPtrTy<0>, SDTCisInt<1>
275 def SDTAtomicLoad : SDTypeProfile<1, 1, [
276 SDTCisInt<0>, SDTCisPtrTy<1>
279 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
280 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
283 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
284 SDTypeProfile<0, 2, constraints>;
285 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
286 SDTypeProfile<0, 2, constraints>;
288 //===----------------------------------------------------------------------===//
289 // Selection DAG Node Properties.
291 // Note: These are hard coded into tblgen.
293 class SDNodeProperty;
294 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
295 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
296 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
297 def SDNPOutGlue : SDNodeProperty; // Write a flag result
298 def SDNPInGlue : SDNodeProperty; // Read a flag operand
299 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
300 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
301 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
302 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
303 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
304 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
305 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
306 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
308 //===----------------------------------------------------------------------===//
309 // Selection DAG Pattern Operations
310 class SDPatternOperator {
311 list<SDNodeProperty> Properties = [];
314 //===----------------------------------------------------------------------===//
315 // Selection DAG Node definitions.
317 class SDNode<string opcode, SDTypeProfile typeprof,
318 list<SDNodeProperty> props = [], string sdclass = "SDNode">
319 : SDPatternOperator {
320 string Opcode = opcode;
321 string SDClass = sdclass;
322 let Properties = props;
323 SDTypeProfile TypeProfile = typeprof;
326 // Special TableGen-recognized dag nodes
332 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
333 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
334 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
335 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
336 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
337 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
338 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
339 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
340 "GlobalAddressSDNode">;
341 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
342 "GlobalAddressSDNode">;
343 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
344 "GlobalAddressSDNode">;
345 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
346 "GlobalAddressSDNode">;
347 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
348 "ConstantPoolSDNode">;
349 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
350 "ConstantPoolSDNode">;
351 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
353 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
355 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
357 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
359 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
360 "ExternalSymbolSDNode">;
361 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
362 "ExternalSymbolSDNode">;
363 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">;
364 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
365 "BlockAddressSDNode">;
366 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
367 "BlockAddressSDNode">;
369 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
370 [SDNPCommutative, SDNPAssociative]>;
371 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
372 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
373 [SDNPCommutative, SDNPAssociative]>;
374 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
375 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
376 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
377 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
378 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
379 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
380 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
381 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
382 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
383 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
384 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
385 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
386 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
387 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
388 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
389 def and : SDNode<"ISD::AND" , SDTIntBinOp,
390 [SDNPCommutative, SDNPAssociative]>;
391 def or : SDNode<"ISD::OR" , SDTIntBinOp,
392 [SDNPCommutative, SDNPAssociative]>;
393 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
394 [SDNPCommutative, SDNPAssociative]>;
395 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
396 [SDNPCommutative, SDNPOutGlue]>;
397 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
398 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
399 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
401 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
402 [SDNPOutGlue, SDNPInGlue]>;
403 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp,
404 [SDNPCommutative, SDNPAssociative]>;
405 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp,
406 [SDNPCommutative, SDNPAssociative]>;
407 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp,
408 [SDNPCommutative, SDNPAssociative]>;
409 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
410 [SDNPCommutative, SDNPAssociative]>;
412 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
413 def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>;
414 def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>;
416 def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>;
417 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>;
418 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
419 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
420 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
421 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
422 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
423 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
424 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
425 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
426 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
427 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
428 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
429 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>;
430 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
431 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
433 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
434 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
435 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
436 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
437 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
438 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
439 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
440 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
441 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp,
442 [SDNPCommutative, SDNPAssociative]>;
443 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp,
444 [SDNPCommutative, SDNPAssociative]>;
445 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
446 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>;
447 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
448 def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>;
449 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
450 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
451 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
452 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
453 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
454 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
455 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
456 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
457 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
458 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
459 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
460 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
461 def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
463 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
464 def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
465 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
467 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
468 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
469 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
470 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
471 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
472 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
474 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
475 def select : SDNode<"ISD::SELECT" , SDTSelect>;
476 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
477 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
479 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
480 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
481 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
482 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
483 def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret,
484 [SDNPHasChain, SDNPSideEffect]>;
485 def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>;
486 def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone,
487 [SDNPHasChain, SDNPSideEffect]>;
489 def trap : SDNode<"ISD::TRAP" , SDTNone,
490 [SDNPHasChain, SDNPSideEffect]>;
491 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
492 [SDNPHasChain, SDNPSideEffect]>;
494 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
495 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
498 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
499 [SDNPHasChain, SDNPSideEffect]>;
501 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
502 [SDNPHasChain, SDNPSideEffect]>;
504 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
505 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
506 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
507 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
508 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
509 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
510 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
511 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
512 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
513 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
514 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
515 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
516 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
517 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
518 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
519 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
520 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
521 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
522 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
523 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
524 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
525 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
526 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
527 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
528 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
529 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
530 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
531 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
533 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore,
534 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
535 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
536 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
537 def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter,
538 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
539 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather,
540 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
542 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
543 // and truncst (see below).
544 def ld : SDNode<"ISD::LOAD" , SDTLoad,
545 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
546 def st : SDNode<"ISD::STORE" , SDTStore,
547 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
548 def ist : SDNode<"ISD::STORE" , SDTIStore,
549 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
551 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
552 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
553 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
556 // vector_extract/vector_insert are deprecated. extractelt/insertelt
558 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
559 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
560 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
561 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
562 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
563 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
565 // This operator does not do subvector type checking. The ARM
566 // backend, at least, needs it.
567 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
568 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
571 // This operator does subvector type checking.
572 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
573 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
575 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
576 // these internally. Don't reference these directly.
577 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
578 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
580 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
581 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
583 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
584 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
586 def SDT_assertext : SDTypeProfile<1, 1,
587 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
588 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
589 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
592 //===----------------------------------------------------------------------===//
593 // Selection DAG Condition Codes
595 class CondCode; // ISD::CondCode enums
596 def SETOEQ : CondCode; def SETOGT : CondCode;
597 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
598 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
599 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
600 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
602 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
603 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
606 //===----------------------------------------------------------------------===//
607 // Selection DAG Node Transformation Functions.
609 // This mechanism allows targets to manipulate nodes in the output DAG once a
610 // match has been formed. This is typically used to manipulate immediate
613 class SDNodeXForm<SDNode opc, code xformFunction> {
615 code XFormFunction = xformFunction;
618 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
620 //===----------------------------------------------------------------------===//
621 // PatPred Subclasses.
623 // These allow specifying different sorts of predicates that control whether a
628 class CodePatPred<code predicate> : PatPred {
629 code PredicateCode = predicate;
633 //===----------------------------------------------------------------------===//
634 // Selection DAG Pattern Fragments.
636 // Pattern fragments are reusable chunks of dags that match specific things.
637 // They can take arguments and have C++ predicates that control whether they
638 // match. They are intended to make the patterns for common instructions more
639 // compact and readable.
642 /// PatFrag - Represents a pattern fragment. This can match something on the
643 /// DAG, from a single node to multiple nested other fragments.
645 class PatFrag<dag ops, dag frag, code pred = [{}],
646 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
649 code PredicateCode = pred;
650 code ImmediateCode = [{}];
651 SDNodeXForm OperandTransform = xform;
653 // Define a few pre-packaged predicates. This helps GlobalISel import
654 // existing rules from SelectionDAG for many common cases.
655 // They will be tested prior to the code in pred and must not be used in
656 // ImmLeaf and its subclasses.
658 // Is the desired pre-packaged predicate for a load?
660 // Is the desired pre-packaged predicate for a store?
662 // Is the desired pre-packaged predicate for an atomic?
665 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
666 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
669 // cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD
670 bit IsNonExtLoad = ?;
671 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
672 bit IsAnyExtLoad = ?;
673 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
674 bit IsSignExtLoad = ?;
675 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
676 bit IsZeroExtLoad = ?;
677 // !cast<StoreSDNode>(N)->isTruncatingStore();
678 // cast<StoreSDNode>(N)->isTruncatingStore();
679 bit IsTruncStore = ?;
681 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic
682 bit IsAtomicOrderingMonotonic = ?;
683 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire
684 bit IsAtomicOrderingAcquire = ?;
685 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release
686 bit IsAtomicOrderingRelease = ?;
687 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease
688 bit IsAtomicOrderingAcquireRelease = ?;
689 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent
690 bit IsAtomicOrderingSequentiallyConsistent = ?;
692 // isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering())
693 // !isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering())
694 bit IsAtomicOrderingAcquireOrStronger = ?;
696 // isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering())
697 // !isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering())
698 bit IsAtomicOrderingReleaseOrStronger = ?;
700 // cast<LoadSDNode>(N)->getMemoryVT() == MVT::<VT>;
701 // cast<StoreSDNode>(N)->getMemoryVT() == MVT::<VT>;
702 ValueType MemoryVT = ?;
703 // cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>;
704 // cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>;
705 ValueType ScalarMemoryVT = ?;
708 // OutPatFrag is a pattern fragment that is used as part of an output pattern
709 // (not an input pattern). These do not have predicates or transforms, but are
710 // used to avoid repeated subexpressions in output patterns.
711 class OutPatFrag<dag ops, dag frag>
712 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
714 // PatLeaf's are pattern fragments that have no operands. This is just a helper
715 // to define immediates and other common things concisely.
716 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
717 : PatFrag<(ops), frag, pred, xform>;
720 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
721 // constraint is a function that is run on the immediate (always with the value
722 // sign extended out to an int64_t) as Imm. For example:
724 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
726 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
727 // is preferred over using PatLeaf because it allows the code generator to
728 // reason more about the constraint.
730 // If FastIsel should ignore all instructions that have an operand of this type,
731 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
732 // the code size of the generated fast instruction selector.
733 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm,
734 SDNode ImmNode = imm>
735 : PatFrag<(ops), (vt ImmNode), [{}], xform> {
736 let ImmediateCode = pred;
737 bit FastIselShouldIgnore = 0;
739 // Is the data type of the immediate an APInt?
742 // Is the data type of the immediate an APFloat?
746 // An ImmLeaf except that Imm is an APInt. This is useful when you need to
747 // zero-extend the immediate instead of sign-extend it.
749 // Note that FastISel does not currently understand IntImmLeaf and will not
750 // generate code for rules that make use of it. As such, it does not make sense
751 // to replace ImmLeaf with IntImmLeaf. However, replacing PatLeaf with an
752 // IntImmLeaf will allow GlobalISel to import the rule.
753 class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
754 : ImmLeaf<vt, pred, xform> {
756 let FastIselShouldIgnore = 1;
759 // An ImmLeaf except that Imm is an APFloat.
761 // Note that FastISel does not currently understand FPImmLeaf and will not
762 // generate code for rules that make use of it.
763 class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
764 : ImmLeaf<vt, pred, xform, fpimm> {
766 let FastIselShouldIgnore = 1;
771 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
772 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
774 def immAllOnesV: PatLeaf<(build_vector), [{
775 return ISD::isBuildVectorAllOnes(N);
777 def immAllZerosV: PatLeaf<(build_vector), [{
778 return ISD::isBuildVectorAllZeros(N);
783 // Other helper fragments.
784 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
785 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
786 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
788 // null_frag - The null pattern operator is used in multiclass instantiations
789 // which accept an SDPatternOperator for use in matching patterns for internal
790 // definitions. When expanding a pattern, if the null fragment is referenced
791 // in the expansion, the pattern is discarded and it is as-if '[]' had been
792 // specified. This allows multiclasses to have the isel patterns be optional.
793 def null_frag : SDPatternOperator;
796 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> {
800 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
802 let IsNonExtLoad = 1;
805 // extending load fragments.
806 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
808 let IsAnyExtLoad = 1;
810 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
812 let IsSignExtLoad = 1;
814 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
816 let IsZeroExtLoad = 1;
819 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
823 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
827 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
831 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
835 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
839 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
844 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
848 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
852 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
856 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
861 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
865 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
869 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
873 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
878 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
880 let ScalarMemoryVT = i1;
882 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
884 let ScalarMemoryVT = i8;
886 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
888 let ScalarMemoryVT = i16;
890 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
892 let ScalarMemoryVT = i32;
894 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
896 let ScalarMemoryVT = f32;
898 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
900 let ScalarMemoryVT = f64;
903 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
905 let ScalarMemoryVT = i1;
907 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
909 let ScalarMemoryVT = i8;
911 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
913 let ScalarMemoryVT = i16;
915 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
917 let ScalarMemoryVT = i32;
920 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
922 let ScalarMemoryVT = i1;
924 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
926 let ScalarMemoryVT = i8;
928 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
930 let ScalarMemoryVT = i16;
932 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
934 let ScalarMemoryVT = i32;
938 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
939 (st node:$val, node:$ptr)> {
943 def store : PatFrag<(ops node:$val, node:$ptr),
944 (unindexedstore node:$val, node:$ptr)> {
946 let IsTruncStore = 0;
949 // truncstore fragments.
950 def truncstore : PatFrag<(ops node:$val, node:$ptr),
951 (unindexedstore node:$val, node:$ptr)> {
953 let IsTruncStore = 1;
955 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
956 (truncstore node:$val, node:$ptr)> {
960 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
961 (truncstore node:$val, node:$ptr)> {
965 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
966 (truncstore node:$val, node:$ptr)> {
970 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
971 (truncstore node:$val, node:$ptr)> {
975 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
976 (truncstore node:$val, node:$ptr)> {
981 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr),
982 (truncstore node:$val, node:$ptr)> {
984 let ScalarMemoryVT = i8;
987 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr),
988 (truncstore node:$val, node:$ptr)> {
990 let ScalarMemoryVT = i16;
993 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr),
994 (truncstore node:$val, node:$ptr)> {
996 let ScalarMemoryVT = i32;
999 // indexed store fragments.
1000 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
1001 (ist node:$val, node:$base, node:$offset)> {
1003 let IsTruncStore = 0;
1006 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
1007 (istore node:$val, node:$base, node:$offset), [{
1008 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1009 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1012 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
1013 (ist node:$val, node:$base, node:$offset)> {
1015 let IsTruncStore = 1;
1017 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
1018 (itruncstore node:$val, node:$base, node:$offset), [{
1019 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1020 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1022 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
1023 (pre_truncst node:$val, node:$base, node:$offset)> {
1027 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
1028 (pre_truncst node:$val, node:$base, node:$offset)> {
1032 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
1033 (pre_truncst node:$val, node:$base, node:$offset)> {
1037 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
1038 (pre_truncst node:$val, node:$base, node:$offset)> {
1042 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
1043 (pre_truncst node:$val, node:$base, node:$offset)> {
1048 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
1049 (istore node:$val, node:$ptr, node:$offset), [{
1050 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1051 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
1054 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
1055 (itruncstore node:$val, node:$base, node:$offset), [{
1056 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1057 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
1059 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
1060 (post_truncst node:$val, node:$base, node:$offset)> {
1064 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
1065 (post_truncst node:$val, node:$base, node:$offset)> {
1069 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
1070 (post_truncst node:$val, node:$base, node:$offset)> {
1074 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
1075 (post_truncst node:$val, node:$base, node:$offset)> {
1079 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
1080 (post_truncst node:$val, node:$base, node:$offset)> {
1085 // nontemporal store fragments.
1086 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
1087 (store node:$val, node:$ptr), [{
1088 return cast<StoreSDNode>(N)->isNonTemporal();
1091 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
1092 (nontemporalstore node:$val, node:$ptr), [{
1093 StoreSDNode *St = cast<StoreSDNode>(N);
1094 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
1097 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
1098 (nontemporalstore node:$val, node:$ptr), [{
1099 StoreSDNode *St = cast<StoreSDNode>(N);
1100 return St->getAlignment() < St->getMemoryVT().getStoreSize();
1103 // nontemporal load fragments.
1104 def nontemporalload : PatFrag<(ops node:$ptr),
1105 (load node:$ptr), [{
1106 return cast<LoadSDNode>(N)->isNonTemporal();
1109 def alignednontemporalload : PatFrag<(ops node:$ptr),
1110 (nontemporalload node:$ptr), [{
1111 LoadSDNode *Ld = cast<LoadSDNode>(N);
1112 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
1115 // setcc convenience fragments.
1116 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
1117 (setcc node:$lhs, node:$rhs, SETOEQ)>;
1118 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
1119 (setcc node:$lhs, node:$rhs, SETOGT)>;
1120 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
1121 (setcc node:$lhs, node:$rhs, SETOGE)>;
1122 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
1123 (setcc node:$lhs, node:$rhs, SETOLT)>;
1124 def setole : PatFrag<(ops node:$lhs, node:$rhs),
1125 (setcc node:$lhs, node:$rhs, SETOLE)>;
1126 def setone : PatFrag<(ops node:$lhs, node:$rhs),
1127 (setcc node:$lhs, node:$rhs, SETONE)>;
1128 def seto : PatFrag<(ops node:$lhs, node:$rhs),
1129 (setcc node:$lhs, node:$rhs, SETO)>;
1130 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
1131 (setcc node:$lhs, node:$rhs, SETUO)>;
1132 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
1133 (setcc node:$lhs, node:$rhs, SETUEQ)>;
1134 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
1135 (setcc node:$lhs, node:$rhs, SETUGT)>;
1136 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
1137 (setcc node:$lhs, node:$rhs, SETUGE)>;
1138 def setult : PatFrag<(ops node:$lhs, node:$rhs),
1139 (setcc node:$lhs, node:$rhs, SETULT)>;
1140 def setule : PatFrag<(ops node:$lhs, node:$rhs),
1141 (setcc node:$lhs, node:$rhs, SETULE)>;
1142 def setune : PatFrag<(ops node:$lhs, node:$rhs),
1143 (setcc node:$lhs, node:$rhs, SETUNE)>;
1144 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
1145 (setcc node:$lhs, node:$rhs, SETEQ)>;
1146 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
1147 (setcc node:$lhs, node:$rhs, SETGT)>;
1148 def setge : PatFrag<(ops node:$lhs, node:$rhs),
1149 (setcc node:$lhs, node:$rhs, SETGE)>;
1150 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
1151 (setcc node:$lhs, node:$rhs, SETLT)>;
1152 def setle : PatFrag<(ops node:$lhs, node:$rhs),
1153 (setcc node:$lhs, node:$rhs, SETLE)>;
1154 def setne : PatFrag<(ops node:$lhs, node:$rhs),
1155 (setcc node:$lhs, node:$rhs, SETNE)>;
1157 multiclass binary_atomic_op_ord<SDNode atomic_op> {
1158 def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),
1159 (!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
1161 let IsAtomicOrderingMonotonic = 1;
1163 def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$val),
1164 (!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
1166 let IsAtomicOrderingAcquire = 1;
1168 def #NAME#_release : PatFrag<(ops node:$ptr, node:$val),
1169 (!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
1171 let IsAtomicOrderingRelease = 1;
1173 def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val),
1174 (!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
1176 let IsAtomicOrderingAcquireRelease = 1;
1178 def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val),
1179 (!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
1181 let IsAtomicOrderingSequentiallyConsistent = 1;
1185 multiclass ternary_atomic_op_ord<SDNode atomic_op> {
1186 def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1187 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1189 let IsAtomicOrderingMonotonic = 1;
1191 def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1192 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1194 let IsAtomicOrderingAcquire = 1;
1196 def #NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1197 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1199 let IsAtomicOrderingRelease = 1;
1201 def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1202 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1204 let IsAtomicOrderingAcquireRelease = 1;
1206 def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1207 (!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1209 let IsAtomicOrderingSequentiallyConsistent = 1;
1213 multiclass binary_atomic_op<SDNode atomic_op> {
1214 def _8 : PatFrag<(ops node:$ptr, node:$val),
1215 (atomic_op node:$ptr, node:$val)> {
1219 def _16 : PatFrag<(ops node:$ptr, node:$val),
1220 (atomic_op node:$ptr, node:$val)> {
1224 def _32 : PatFrag<(ops node:$ptr, node:$val),
1225 (atomic_op node:$ptr, node:$val)> {
1229 def _64 : PatFrag<(ops node:$ptr, node:$val),
1230 (atomic_op node:$ptr, node:$val)> {
1235 defm NAME#_8 : binary_atomic_op_ord<atomic_op>;
1236 defm NAME#_16 : binary_atomic_op_ord<atomic_op>;
1237 defm NAME#_32 : binary_atomic_op_ord<atomic_op>;
1238 defm NAME#_64 : binary_atomic_op_ord<atomic_op>;
1241 multiclass ternary_atomic_op<SDNode atomic_op> {
1242 def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1243 (atomic_op node:$ptr, node:$cmp, node:$val)> {
1247 def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1248 (atomic_op node:$ptr, node:$cmp, node:$val)> {
1252 def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1253 (atomic_op node:$ptr, node:$cmp, node:$val)> {
1257 def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1258 (atomic_op node:$ptr, node:$cmp, node:$val)> {
1263 defm NAME#_8 : ternary_atomic_op_ord<atomic_op>;
1264 defm NAME#_16 : ternary_atomic_op_ord<atomic_op>;
1265 defm NAME#_32 : ternary_atomic_op_ord<atomic_op>;
1266 defm NAME#_64 : ternary_atomic_op_ord<atomic_op>;
1269 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
1270 defm atomic_swap : binary_atomic_op<atomic_swap>;
1271 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
1272 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
1273 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
1274 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
1275 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
1276 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
1277 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
1278 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
1279 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
1280 defm atomic_store : binary_atomic_op<atomic_store>;
1281 defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>;
1284 PatFrag<(ops node:$ptr),
1285 (atomic_load node:$ptr)> {
1289 def atomic_load_16 :
1290 PatFrag<(ops node:$ptr),
1291 (atomic_load node:$ptr)> {
1295 def atomic_load_32 :
1296 PatFrag<(ops node:$ptr),
1297 (atomic_load node:$ptr)> {
1301 def atomic_load_64 :
1302 PatFrag<(ops node:$ptr),
1303 (atomic_load node:$ptr)> {
1308 //===----------------------------------------------------------------------===//
1309 // Selection DAG Pattern Support.
1311 // Patterns are what are actually matched against by the target-flavored
1312 // instruction selection DAG. Instructions defined by the target implicitly
1313 // define patterns in most cases, but patterns can also be explicitly added when
1314 // an operation is defined by a sequence of instructions (e.g. loading a large
1315 // immediate value on RISC targets that do not support immediates as large as
1319 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1320 dag PatternToMatch = patternToMatch;
1321 list<dag> ResultInstrs = resultInstrs;
1322 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1323 int AddedComplexity = 0; // See class Instruction in Target.td.
1326 // Pat - A simple (but common) form of a pattern, which produces a simple result
1327 // not needing a full list.
1328 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1330 //===----------------------------------------------------------------------===//
1331 // Complex pattern definitions.
1334 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1335 // in C++. NumOperands is the number of operands returned by the select function;
1336 // SelectFunc is the name of the function used to pattern match the max. pattern;
1337 // RootNodes are the list of possible root nodes of the sub-dags to match.
1338 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1340 class ComplexPattern<ValueType ty, int numops, string fn,
1341 list<SDNode> roots = [], list<SDNodeProperty> props = [],
1342 int complexity = -1> {
1344 int NumOperands = numops;
1345 string SelectFunc = fn;
1346 list<SDNode> RootNodes = roots;
1347 list<SDNodeProperty> Properties = props;
1348 int Complexity = complexity;